2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
29 #include "common/gen_l3_config.h"
30 #include "genxml/gen_macros.h"
31 #include "genxml/genX_pack.h"
34 emit_lrm(struct anv_batch
*batch
,
35 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
37 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
38 lrm
.RegisterAddress
= reg
;
39 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
44 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
46 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
47 lri
.RegisterOffset
= reg
;
53 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
55 struct anv_device
*device
= cmd_buffer
->device
;
57 /* XXX: Do we need this on more than just BDW? */
59 /* Emit a render target cache flush.
61 * This isn't documented anywhere in the PRM. However, it seems to be
62 * necessary prior to changing the surface state base adress. Without
63 * this, we get GPU hangs when using multi-level command buffers which
64 * clear depth, reset state base address, and then go render stuff.
66 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
67 pc
.RenderTargetCacheFlushEnable
= true;
71 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
72 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
73 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
74 sba
.GeneralStateBaseAddressModifyEnable
= true;
76 sba
.SurfaceStateBaseAddress
=
77 anv_cmd_buffer_surface_base_address(cmd_buffer
);
78 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
79 sba
.SurfaceStateBaseAddressModifyEnable
= true;
81 sba
.DynamicStateBaseAddress
=
82 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
83 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
),
84 sba
.DynamicStateBaseAddressModifyEnable
= true,
86 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
87 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
88 sba
.IndirectObjectBaseAddressModifyEnable
= true;
90 sba
.InstructionBaseAddress
=
91 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
92 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
93 sba
.InstructionBaseAddressModifyEnable
= true;
96 /* Broadwell requires that we specify a buffer size for a bunch of
97 * these fields. However, since we will be growing the BO's live, we
98 * just set them all to the maximum.
100 sba
.GeneralStateBufferSize
= 0xfffff;
101 sba
.GeneralStateBufferSizeModifyEnable
= true;
102 sba
.DynamicStateBufferSize
= 0xfffff;
103 sba
.DynamicStateBufferSizeModifyEnable
= true;
104 sba
.IndirectObjectBufferSize
= 0xfffff;
105 sba
.IndirectObjectBufferSizeModifyEnable
= true;
106 sba
.InstructionBufferSize
= 0xfffff;
107 sba
.InstructionBuffersizeModifyEnable
= true;
111 /* After re-setting the surface state base address, we have to do some
112 * cache flusing so that the sampler engine will pick up the new
113 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
114 * Shared Function > 3D Sampler > State > State Caching (page 96):
116 * Coherency with system memory in the state cache, like the texture
117 * cache is handled partially by software. It is expected that the
118 * command stream or shader will issue Cache Flush operation or
119 * Cache_Flush sampler message to ensure that the L1 cache remains
120 * coherent with system memory.
124 * Whenever the value of the Dynamic_State_Base_Addr,
125 * Surface_State_Base_Addr are altered, the L1 state cache must be
126 * invalidated to ensure the new surface or sampler state is fetched
127 * from system memory.
129 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
130 * which, according the PIPE_CONTROL instruction documentation in the
133 * Setting this bit is independent of any other bit in this packet.
134 * This bit controls the invalidation of the L1 and L2 state caches
135 * at the top of the pipe i.e. at the parsing time.
137 * Unfortunately, experimentation seems to indicate that state cache
138 * invalidation through a PIPE_CONTROL does nothing whatsoever in
139 * regards to surface state and binding tables. In stead, it seems that
140 * invalidating the texture cache is what is actually needed.
142 * XXX: As far as we have been able to determine through
143 * experimentation, shows that flush the texture cache appears to be
144 * sufficient. The theory here is that all of the sampling/rendering
145 * units cache the binding table in the texture cache. However, we have
146 * yet to be able to actually confirm this.
148 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
149 pc
.TextureCacheInvalidationEnable
= true;
153 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
154 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
155 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
158 * Program the hardware to use the specified L3 configuration.
161 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
162 const struct gen_l3_config
*cfg
)
165 if (cfg
== cmd_buffer
->state
.current_l3_config
)
168 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
169 fprintf(stderr
, "L3 config transition: ");
170 gen_dump_l3_config(cfg
, stderr
);
173 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
175 /* According to the hardware docs, the L3 partitioning can only be changed
176 * while the pipeline is completely drained and the caches are flushed,
177 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
179 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
180 pc
.DCFlushEnable
= true;
181 pc
.PostSyncOperation
= NoWrite
;
182 pc
.CommandStreamerStallEnable
= true;
185 /* ...followed by a second pipelined PIPE_CONTROL that initiates
186 * invalidation of the relevant caches. Note that because RO invalidation
187 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
188 * command is processed by the CS) we cannot combine it with the previous
189 * stalling flush as the hardware documentation suggests, because that
190 * would cause the CS to stall on previous rendering *after* RO
191 * invalidation and wouldn't prevent the RO caches from being polluted by
192 * concurrent rendering before the stall completes. This intentionally
193 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
194 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
195 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
196 * already guarantee that there is no concurrent GPGPU kernel execution
197 * (see SKL HSD 2132585).
199 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
200 pc
.TextureCacheInvalidationEnable
= true;
201 pc
.ConstantCacheInvalidationEnable
= true;
202 pc
.InstructionCacheInvalidateEnable
= true;
203 pc
.StateCacheInvalidationEnable
= true;
204 pc
.PostSyncOperation
= NoWrite
;
207 /* Now send a third stalling flush to make sure that invalidation is
208 * complete when the L3 configuration registers are modified.
210 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
211 pc
.DCFlushEnable
= true;
212 pc
.PostSyncOperation
= NoWrite
;
213 pc
.CommandStreamerStallEnable
= true;
218 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
221 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
222 .SLMEnable
= has_slm
,
223 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
224 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
225 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
226 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
228 /* Set up the L3 partitioning. */
229 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
233 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
234 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
236 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
238 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
241 assert(!cfg
->n
[GEN_L3P_ALL
]);
243 /* When enabled SLM only uses a portion of the L3 on half of the banks,
244 * the matching space on the remaining banks has to be allocated to a
245 * client (URB for all validated configurations) set to the
246 * lower-bandwidth 2-bank address hashing mode.
248 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
249 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
250 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
252 /* Minimum number of ways that can be allocated to the URB. */
253 const unsigned n0_urb
= (devinfo
->is_baytrail
? 32 : 0);
254 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
256 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
257 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
258 .ConvertDC_UC
= !has_dc
,
259 .ConvertIS_UC
= !has_is
,
260 .ConvertC_UC
= !has_c
,
261 .ConvertT_UC
= !has_t
);
263 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
264 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
265 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
267 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
268 .SLMEnable
= has_slm
,
269 .URBLowBandwidth
= urb_low_bw
,
270 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
272 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
274 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
275 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
277 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
278 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
280 .CAllocation
= cfg
->n
[GEN_L3P_C
],
282 .TAllocation
= cfg
->n
[GEN_L3P_T
],
285 /* Set up the L3 partitioning. */
286 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
287 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
288 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
291 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
292 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
293 * them disabled to avoid crashing the system hard.
295 uint32_t scratch1
, chicken3
;
296 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
297 .L3AtomicDisable
= !has_dc
);
298 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
299 .L3AtomicDisable
= !has_dc
);
300 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
301 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
307 cmd_buffer
->state
.current_l3_config
= cfg
;
311 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
313 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
315 /* Flushes are pipelined while invalidations are handled immediately.
316 * Therefore, if we're flushing anything then we need to schedule a stall
317 * before any invalidations can happen.
319 if (bits
& ANV_PIPE_FLUSH_BITS
)
320 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
322 /* If we're going to do an invalidate and we have a pending CS stall that
323 * has yet to be resolved, we do the CS stall now.
325 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
326 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
327 bits
|= ANV_PIPE_CS_STALL_BIT
;
328 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
331 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
332 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
333 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
334 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
335 pipe
.RenderTargetCacheFlushEnable
=
336 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
338 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
339 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
340 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
343 * According to the Broadwell documentation, any PIPE_CONTROL with the
344 * "Command Streamer Stall" bit set must also have another bit set,
345 * with five different options:
347 * - Render Target Cache Flush
348 * - Depth Cache Flush
349 * - Stall at Pixel Scoreboard
350 * - Post-Sync Operation
354 * I chose "Stall at Pixel Scoreboard" since that's what we use in
355 * mesa and it seems to work fine. The choice is fairly arbitrary.
357 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
358 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
359 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
360 pipe
.StallAtPixelScoreboard
= true;
363 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
366 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
367 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
368 pipe
.StateCacheInvalidationEnable
=
369 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
370 pipe
.ConstantCacheInvalidationEnable
=
371 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
372 pipe
.VFCacheInvalidationEnable
=
373 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
374 pipe
.TextureCacheInvalidationEnable
=
375 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
376 pipe
.InstructionCacheInvalidateEnable
=
377 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
380 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
383 cmd_buffer
->state
.pending_pipe_bits
= bits
;
386 void genX(CmdPipelineBarrier
)(
387 VkCommandBuffer commandBuffer
,
388 VkPipelineStageFlags srcStageMask
,
389 VkPipelineStageFlags destStageMask
,
391 uint32_t memoryBarrierCount
,
392 const VkMemoryBarrier
* pMemoryBarriers
,
393 uint32_t bufferMemoryBarrierCount
,
394 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
395 uint32_t imageMemoryBarrierCount
,
396 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
398 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
401 /* XXX: Right now, we're really dumb and just flush whatever categories
402 * the app asks for. One of these days we may make this a bit better
403 * but right now that's all the hardware allows for in most areas.
405 VkAccessFlags src_flags
= 0;
406 VkAccessFlags dst_flags
= 0;
408 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
409 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
410 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
413 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
414 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
415 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
418 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
419 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
420 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
423 enum anv_pipe_bits pipe_bits
= 0;
425 for_each_bit(b
, src_flags
) {
426 switch ((VkAccessFlagBits
)(1 << b
)) {
427 case VK_ACCESS_SHADER_WRITE_BIT
:
428 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
430 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
431 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
433 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
434 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
436 case VK_ACCESS_TRANSFER_WRITE_BIT
:
437 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
438 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
441 break; /* Nothing to do */
445 for_each_bit(b
, dst_flags
) {
446 switch ((VkAccessFlagBits
)(1 << b
)) {
447 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
448 case VK_ACCESS_INDEX_READ_BIT
:
449 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
450 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
452 case VK_ACCESS_UNIFORM_READ_BIT
:
453 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
454 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
456 case VK_ACCESS_SHADER_READ_BIT
:
457 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
458 case VK_ACCESS_TRANSFER_READ_BIT
:
459 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
462 break; /* Nothing to do */
466 cmd_buffer
->state
.pending_pipe_bits
|= pipe_bits
;
470 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
472 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
474 /* In order to avoid thrash, we assume that vertex and fragment stages
475 * always exist. In the rare case where one is missing *and* the other
476 * uses push concstants, this may be suboptimal. However, avoiding stalls
477 * seems more important.
479 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
481 if (stages
== cmd_buffer
->state
.push_constant_stages
)
485 const unsigned push_constant_kb
= 32;
487 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
489 const unsigned push_constant_kb
= 16;
492 const unsigned num_stages
=
493 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
494 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
496 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
497 * units of 2KB. Incidentally, these are the same platforms that have
498 * 32KB worth of push constant space.
500 if (push_constant_kb
== 32)
501 size_per_stage
&= ~1u;
503 uint32_t kb_used
= 0;
504 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
505 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
506 anv_batch_emit(&cmd_buffer
->batch
,
507 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
508 alloc
._3DCommandSubOpcode
= 18 + i
;
509 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
510 alloc
.ConstantBufferSize
= push_size
;
512 kb_used
+= push_size
;
515 anv_batch_emit(&cmd_buffer
->batch
,
516 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
517 alloc
.ConstantBufferOffset
= kb_used
;
518 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
521 cmd_buffer
->state
.push_constant_stages
= stages
;
523 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
525 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
526 * the next 3DPRIMITIVE command after programming the
527 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
529 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
530 * pipeline setup, we need to dirty push constants.
532 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
536 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
539 static const uint32_t sampler_state_opcodes
[] = {
540 [MESA_SHADER_VERTEX
] = 43,
541 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
542 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
543 [MESA_SHADER_GEOMETRY
] = 46,
544 [MESA_SHADER_FRAGMENT
] = 47,
545 [MESA_SHADER_COMPUTE
] = 0,
548 static const uint32_t binding_table_opcodes
[] = {
549 [MESA_SHADER_VERTEX
] = 38,
550 [MESA_SHADER_TESS_CTRL
] = 39,
551 [MESA_SHADER_TESS_EVAL
] = 40,
552 [MESA_SHADER_GEOMETRY
] = 41,
553 [MESA_SHADER_FRAGMENT
] = 42,
554 [MESA_SHADER_COMPUTE
] = 0,
557 anv_foreach_stage(s
, stages
) {
558 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
559 anv_batch_emit(&cmd_buffer
->batch
,
560 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
561 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
562 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
566 /* Always emit binding table pointers if we're asked to, since on SKL
567 * this is what flushes push constants. */
568 anv_batch_emit(&cmd_buffer
->batch
,
569 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
570 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
571 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
577 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
579 static const uint32_t push_constant_opcodes
[] = {
580 [MESA_SHADER_VERTEX
] = 21,
581 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
582 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
583 [MESA_SHADER_GEOMETRY
] = 22,
584 [MESA_SHADER_FRAGMENT
] = 23,
585 [MESA_SHADER_COMPUTE
] = 0,
588 VkShaderStageFlags flushed
= 0;
590 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
591 if (stage
== MESA_SHADER_COMPUTE
)
594 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
596 if (state
.offset
== 0) {
597 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
598 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
600 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
601 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
602 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
604 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
605 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
607 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
608 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
614 flushed
|= mesa_to_vk_shader_stage(stage
);
617 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
623 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
625 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
628 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
630 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
632 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
634 genX(flush_pipeline_select_3d
)(cmd_buffer
);
637 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
638 const uint32_t num_dwords
= 1 + num_buffers
* 4;
640 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
641 GENX(3DSTATE_VERTEX_BUFFERS
));
643 for_each_bit(vb
, vb_emit
) {
644 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
645 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
647 struct GENX(VERTEX_BUFFER_STATE
) state
= {
648 .VertexBufferIndex
= vb
,
651 .MemoryObjectControlState
= GENX(MOCS
),
653 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
654 .InstanceDataStepRate
= 1,
655 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
658 .AddressModifyEnable
= true,
659 .BufferPitch
= pipeline
->binding_stride
[vb
],
660 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
663 .BufferSize
= buffer
->size
- offset
665 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
669 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
674 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
676 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
677 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
679 /* The exact descriptor layout is pulled from the pipeline, so we need
680 * to re-emit binding tables on every pipeline change.
682 cmd_buffer
->state
.descriptors_dirty
|=
683 cmd_buffer
->state
.pipeline
->active_stages
;
685 /* If the pipeline changed, we may need to re-allocate push constant
688 cmd_buffer_alloc_push_constants(cmd_buffer
);
692 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
693 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
694 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
696 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
697 * stall needs to be sent just prior to any 3DSTATE_VS,
698 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
699 * 3DSTATE_BINDING_TABLE_POINTER_VS,
700 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
701 * PIPE_CONTROL needs to be sent before any combination of VS
702 * associated 3DSTATE."
704 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
705 pc
.DepthStallEnable
= true;
706 pc
.PostSyncOperation
= WriteImmediateData
;
708 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
713 /* We emit the binding tables and sampler tables first, then emit push
714 * constants and then finally emit binding table and sampler table
715 * pointers. It has to happen in this order, since emitting the binding
716 * tables may change the push constants (in case of storage images). After
717 * emitting push constants, on SKL+ we have to emit the corresponding
718 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
721 if (cmd_buffer
->state
.descriptors_dirty
)
722 dirty
= anv_cmd_buffer_flush_descriptor_sets(cmd_buffer
);
724 if (cmd_buffer
->state
.push_constants_dirty
) {
726 /* On Sky Lake and later, the binding table pointers commands are
727 * what actually flush the changes to push constant state so we need
728 * to dirty them so they get re-emitted below.
730 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
732 cmd_buffer_flush_push_constants(cmd_buffer
);
737 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
739 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
740 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
742 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
743 ANV_CMD_DIRTY_PIPELINE
)) {
744 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
745 pipeline
->depth_clamp_enable
);
748 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
749 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
751 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
753 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
757 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
758 struct anv_bo
*bo
, uint32_t offset
)
760 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
761 GENX(3DSTATE_VERTEX_BUFFERS
));
763 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
764 &(struct GENX(VERTEX_BUFFER_STATE
)) {
765 .VertexBufferIndex
= 32, /* Reserved for this */
766 .AddressModifyEnable
= true,
769 .MemoryObjectControlState
= GENX(MOCS
),
770 .BufferStartingAddress
= { bo
, offset
},
773 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
774 .BufferStartingAddress
= { bo
, offset
},
775 .EndAddress
= { bo
, offset
+ 8 },
781 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
782 uint32_t base_vertex
, uint32_t base_instance
)
784 struct anv_state id_state
=
785 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
787 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
788 ((uint32_t *)id_state
.map
)[1] = base_instance
;
790 if (!cmd_buffer
->device
->info
.has_llc
)
791 anv_state_clflush(id_state
);
793 emit_base_vertex_instance_bo(cmd_buffer
,
794 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
798 VkCommandBuffer commandBuffer
,
799 uint32_t vertexCount
,
800 uint32_t instanceCount
,
801 uint32_t firstVertex
,
802 uint32_t firstInstance
)
804 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
805 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
806 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
808 genX(cmd_buffer_flush_state
)(cmd_buffer
);
810 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
811 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
813 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
814 prim
.VertexAccessType
= SEQUENTIAL
;
815 prim
.PrimitiveTopologyType
= pipeline
->topology
;
816 prim
.VertexCountPerInstance
= vertexCount
;
817 prim
.StartVertexLocation
= firstVertex
;
818 prim
.InstanceCount
= instanceCount
;
819 prim
.StartInstanceLocation
= firstInstance
;
820 prim
.BaseVertexLocation
= 0;
824 void genX(CmdDrawIndexed
)(
825 VkCommandBuffer commandBuffer
,
827 uint32_t instanceCount
,
829 int32_t vertexOffset
,
830 uint32_t firstInstance
)
832 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
833 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
834 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
836 genX(cmd_buffer_flush_state
)(cmd_buffer
);
838 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
839 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
841 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
842 prim
.VertexAccessType
= RANDOM
;
843 prim
.PrimitiveTopologyType
= pipeline
->topology
;
844 prim
.VertexCountPerInstance
= indexCount
;
845 prim
.StartVertexLocation
= firstIndex
;
846 prim
.InstanceCount
= instanceCount
;
847 prim
.StartInstanceLocation
= firstInstance
;
848 prim
.BaseVertexLocation
= vertexOffset
;
852 /* Auto-Draw / Indirect Registers */
853 #define GEN7_3DPRIM_END_OFFSET 0x2420
854 #define GEN7_3DPRIM_START_VERTEX 0x2430
855 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
856 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
857 #define GEN7_3DPRIM_START_INSTANCE 0x243C
858 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
860 void genX(CmdDrawIndirect
)(
861 VkCommandBuffer commandBuffer
,
867 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
868 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
869 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
870 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
871 struct anv_bo
*bo
= buffer
->bo
;
872 uint32_t bo_offset
= buffer
->offset
+ offset
;
874 genX(cmd_buffer_flush_state
)(cmd_buffer
);
876 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
877 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
879 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
880 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
881 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
882 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
883 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
885 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
886 prim
.IndirectParameterEnable
= true;
887 prim
.VertexAccessType
= SEQUENTIAL
;
888 prim
.PrimitiveTopologyType
= pipeline
->topology
;
892 void genX(CmdDrawIndexedIndirect
)(
893 VkCommandBuffer commandBuffer
,
899 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
900 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
901 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
902 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
903 struct anv_bo
*bo
= buffer
->bo
;
904 uint32_t bo_offset
= buffer
->offset
+ offset
;
906 genX(cmd_buffer_flush_state
)(cmd_buffer
);
908 /* TODO: We need to stomp base vertex to 0 somehow */
909 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
910 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
912 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
913 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
914 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
915 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
916 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
918 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
919 prim
.IndirectParameterEnable
= true;
920 prim
.VertexAccessType
= RANDOM
;
921 prim
.PrimitiveTopologyType
= pipeline
->topology
;
928 verify_cmd_parser(const struct anv_device
*device
,
929 int required_version
,
930 const char *function
)
932 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
933 vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
934 "cmd parser version %d is required for %s",
935 required_version
, function
);
944 void genX(CmdDispatch
)(
945 VkCommandBuffer commandBuffer
,
950 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
951 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
952 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
954 if (prog_data
->uses_num_work_groups
) {
955 struct anv_state state
=
956 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
957 uint32_t *sizes
= state
.map
;
961 if (!cmd_buffer
->device
->info
.has_llc
)
962 anv_state_clflush(state
);
963 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
964 cmd_buffer
->state
.num_workgroups_bo
=
965 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
968 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
970 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
971 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
972 ggw
.ThreadDepthCounterMaximum
= 0;
973 ggw
.ThreadHeightCounterMaximum
= 0;
974 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
975 ggw
.ThreadGroupIDXDimension
= x
;
976 ggw
.ThreadGroupIDYDimension
= y
;
977 ggw
.ThreadGroupIDZDimension
= z
;
978 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
979 ggw
.BottomExecutionMask
= 0xffffffff;
982 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
985 #define GPGPU_DISPATCHDIMX 0x2500
986 #define GPGPU_DISPATCHDIMY 0x2504
987 #define GPGPU_DISPATCHDIMZ 0x2508
989 #define MI_PREDICATE_SRC0 0x2400
990 #define MI_PREDICATE_SRC1 0x2408
992 void genX(CmdDispatchIndirect
)(
993 VkCommandBuffer commandBuffer
,
997 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
998 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
999 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1000 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1001 struct anv_bo
*bo
= buffer
->bo
;
1002 uint32_t bo_offset
= buffer
->offset
+ offset
;
1003 struct anv_batch
*batch
= &cmd_buffer
->batch
;
1006 /* Linux 4.4 added command parser version 5 which allows the GPGPU
1007 * indirect dispatch registers to be written.
1009 if (!verify_cmd_parser(cmd_buffer
->device
, 5, "vkCmdDispatchIndirect"))
1013 if (prog_data
->uses_num_work_groups
) {
1014 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
1015 cmd_buffer
->state
.num_workgroups_bo
= bo
;
1018 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1020 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
1021 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
1022 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
1025 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
1026 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
1027 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
1028 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
1030 /* Load compute_dispatch_indirect_x_size into SRC0 */
1031 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
1033 /* predicate = (compute_dispatch_indirect_x_size == 0); */
1034 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1035 mip
.LoadOperation
= LOAD_LOAD
;
1036 mip
.CombineOperation
= COMBINE_SET
;
1037 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1040 /* Load compute_dispatch_indirect_y_size into SRC0 */
1041 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
1043 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
1044 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1045 mip
.LoadOperation
= LOAD_LOAD
;
1046 mip
.CombineOperation
= COMBINE_OR
;
1047 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1050 /* Load compute_dispatch_indirect_z_size into SRC0 */
1051 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
1053 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
1054 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1055 mip
.LoadOperation
= LOAD_LOAD
;
1056 mip
.CombineOperation
= COMBINE_OR
;
1057 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1060 /* predicate = !predicate; */
1061 #define COMPARE_FALSE 1
1062 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1063 mip
.LoadOperation
= LOAD_LOADINV
;
1064 mip
.CombineOperation
= COMBINE_OR
;
1065 mip
.CompareOperation
= COMPARE_FALSE
;
1069 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
1070 ggw
.IndirectParameterEnable
= true;
1071 ggw
.PredicateEnable
= GEN_GEN
<= 7;
1072 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1073 ggw
.ThreadDepthCounterMaximum
= 0;
1074 ggw
.ThreadHeightCounterMaximum
= 0;
1075 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1076 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1077 ggw
.BottomExecutionMask
= 0xffffffff;
1080 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1084 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
1087 #if GEN_GEN >= 8 && GEN_GEN < 10
1088 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
1090 * Software must clear the COLOR_CALC_STATE Valid field in
1091 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
1092 * with Pipeline Select set to GPGPU.
1094 * The internal hardware docs recommend the same workaround for Gen9
1097 if (pipeline
== GPGPU
)
1098 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
1100 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
1101 * PIPELINE_SELECT [DevBWR+]":
1105 * Software must ensure all the write caches are flushed through a
1106 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
1107 * command to invalidate read only caches prior to programming
1108 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
1110 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1111 pc
.RenderTargetCacheFlushEnable
= true;
1112 pc
.DepthCacheFlushEnable
= true;
1113 pc
.DCFlushEnable
= true;
1114 pc
.PostSyncOperation
= NoWrite
;
1115 pc
.CommandStreamerStallEnable
= true;
1118 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1119 pc
.TextureCacheInvalidationEnable
= true;
1120 pc
.ConstantCacheInvalidationEnable
= true;
1121 pc
.StateCacheInvalidationEnable
= true;
1122 pc
.InstructionCacheInvalidateEnable
= true;
1123 pc
.PostSyncOperation
= NoWrite
;
1129 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
1131 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
1132 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
1134 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
1138 ps
.PipelineSelection
= _3D
;
1141 cmd_buffer
->state
.current_pipeline
= _3D
;
1146 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
1148 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
1149 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
1151 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
1155 ps
.PipelineSelection
= GPGPU
;
1158 cmd_buffer
->state
.current_pipeline
= GPGPU
;
1163 genX(cmd_buffer_alloc_null_surface_state
)(struct anv_cmd_buffer
*cmd_buffer
,
1164 struct anv_framebuffer
*fb
)
1166 struct anv_state state
=
1167 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
1169 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
1170 .SurfaceType
= SURFTYPE_NULL
,
1171 .SurfaceArray
= fb
->layers
> 0,
1172 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1176 .TiledSurface
= true,
1178 .Width
= fb
->width
- 1,
1179 .Height
= fb
->height
- 1,
1180 .Depth
= fb
->layers
- 1,
1181 .RenderTargetViewExtent
= fb
->layers
- 1,
1184 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
.map
, &null_ss
);
1186 if (!cmd_buffer
->device
->info
.has_llc
)
1187 anv_state_clflush(state
);
1193 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
1195 struct anv_device
*device
= cmd_buffer
->device
;
1196 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1197 const struct anv_image_view
*iview
=
1198 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1199 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
1200 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1201 const bool has_stencil
=
1202 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1204 /* FIXME: Implement the PMA stall W/A */
1205 /* FIXME: Width and Height are wrong */
1207 /* Emit 3DSTATE_DEPTH_BUFFER */
1209 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
1210 db
.SurfaceType
= SURFTYPE_2D
;
1211 db
.DepthWriteEnable
= true;
1212 db
.StencilWriteEnable
= has_stencil
;
1213 db
.HierarchicalDepthBufferEnable
= false;
1215 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
1216 &image
->depth_surface
.isl
);
1218 db
.SurfaceBaseAddress
= (struct anv_address
) {
1220 .offset
= image
->offset
+ image
->depth_surface
.offset
,
1222 db
.DepthBufferObjectControlState
= GENX(MOCS
),
1224 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
1225 db
.Height
= image
->extent
.height
- 1;
1226 db
.Width
= image
->extent
.width
- 1;
1227 db
.LOD
= iview
->base_mip
;
1228 db
.Depth
= image
->array_size
- 1; /* FIXME: 3-D */
1229 db
.MinimumArrayElement
= iview
->base_layer
;
1233 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2,
1235 db
.RenderTargetViewExtent
= 1 - 1;
1238 /* Even when no depth buffer is present, the hardware requires that
1239 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
1241 * If a null depth buffer is bound, the driver must instead bind depth as:
1242 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
1243 * 3DSTATE_DEPTH.Width = 1
1244 * 3DSTATE_DEPTH.Height = 1
1245 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
1246 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
1247 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
1248 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
1249 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
1251 * The PRM is wrong, though. The width and height must be programmed to
1252 * actual framebuffer's width and height, even when neither depth buffer
1253 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
1254 * be combined with a stencil buffer so we use D32_FLOAT instead.
1256 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
1257 db
.SurfaceType
= SURFTYPE_2D
;
1258 db
.SurfaceFormat
= D32_FLOAT
;
1259 db
.Width
= fb
->width
- 1;
1260 db
.Height
= fb
->height
- 1;
1261 db
.StencilWriteEnable
= has_stencil
;
1265 /* Emit 3DSTATE_STENCIL_BUFFER */
1267 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
1268 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1269 sb
.StencilBufferEnable
= true,
1271 sb
.StencilBufferObjectControlState
= GENX(MOCS
),
1273 sb
.SurfacePitch
= image
->stencil_surface
.isl
.row_pitch
- 1,
1276 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2,
1278 sb
.SurfaceBaseAddress
= (struct anv_address
) {
1280 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
1284 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
1287 /* Disable hierarchial depth buffers. */
1288 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hz
);
1290 /* Clear the clear params. */
1291 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
);
1295 * @see anv_cmd_buffer_set_subpass()
1298 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
1299 struct anv_subpass
*subpass
)
1301 cmd_buffer
->state
.subpass
= subpass
;
1303 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1305 cmd_buffer_emit_depth_stencil(cmd_buffer
);
1308 void genX(CmdBeginRenderPass
)(
1309 VkCommandBuffer commandBuffer
,
1310 const VkRenderPassBeginInfo
* pRenderPassBegin
,
1311 VkSubpassContents contents
)
1313 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1314 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
1315 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
1317 cmd_buffer
->state
.framebuffer
= framebuffer
;
1318 cmd_buffer
->state
.pass
= pass
;
1319 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
1320 anv_cmd_state_setup_attachments(cmd_buffer
, pRenderPassBegin
);
1322 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1324 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
1325 anv_cmd_buffer_clear_subpass(cmd_buffer
);
1328 void genX(CmdNextSubpass
)(
1329 VkCommandBuffer commandBuffer
,
1330 VkSubpassContents contents
)
1332 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1334 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1336 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
1337 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
1338 anv_cmd_buffer_clear_subpass(cmd_buffer
);
1341 void genX(CmdEndRenderPass
)(
1342 VkCommandBuffer commandBuffer
)
1344 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1346 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
1349 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
1354 emit_ps_depth_count(struct anv_batch
*batch
,
1355 struct anv_bo
*bo
, uint32_t offset
)
1357 anv_batch_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1358 pc
.DestinationAddressType
= DAT_PPGTT
;
1359 pc
.PostSyncOperation
= WritePSDepthCount
;
1360 pc
.DepthStallEnable
= true;
1361 pc
.Address
= (struct anv_address
) { bo
, offset
};
1366 emit_query_availability(struct anv_batch
*batch
,
1367 struct anv_bo
*bo
, uint32_t offset
)
1369 anv_batch_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1370 pc
.DestinationAddressType
= DAT_PPGTT
;
1371 pc
.PostSyncOperation
= WriteImmediateData
;
1372 pc
.Address
= (struct anv_address
) { bo
, offset
};
1373 pc
.ImmediateData
= 1;
1377 void genX(CmdBeginQuery
)(
1378 VkCommandBuffer commandBuffer
,
1379 VkQueryPool queryPool
,
1381 VkQueryControlFlags flags
)
1383 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1384 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1386 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
1387 * that the pipelining of the depth write breaks. What we see is that
1388 * samples from the render pass clear leaks into the first query
1389 * immediately after the clear. Doing a pipecontrol with a post-sync
1390 * operation and DepthStallEnable seems to work around the issue.
1392 if (cmd_buffer
->state
.need_query_wa
) {
1393 cmd_buffer
->state
.need_query_wa
= false;
1394 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1395 pc
.DepthCacheFlushEnable
= true;
1396 pc
.DepthStallEnable
= true;
1400 switch (pool
->type
) {
1401 case VK_QUERY_TYPE_OCCLUSION
:
1402 emit_ps_depth_count(&cmd_buffer
->batch
, &pool
->bo
,
1403 query
* sizeof(struct anv_query_pool_slot
));
1406 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1412 void genX(CmdEndQuery
)(
1413 VkCommandBuffer commandBuffer
,
1414 VkQueryPool queryPool
,
1417 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1418 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1420 switch (pool
->type
) {
1421 case VK_QUERY_TYPE_OCCLUSION
:
1422 emit_ps_depth_count(&cmd_buffer
->batch
, &pool
->bo
,
1423 query
* sizeof(struct anv_query_pool_slot
) + 8);
1425 emit_query_availability(&cmd_buffer
->batch
, &pool
->bo
,
1426 query
* sizeof(struct anv_query_pool_slot
) + 16);
1429 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1435 #define TIMESTAMP 0x2358
1437 void genX(CmdWriteTimestamp
)(
1438 VkCommandBuffer commandBuffer
,
1439 VkPipelineStageFlagBits pipelineStage
,
1440 VkQueryPool queryPool
,
1443 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1444 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1445 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
1447 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
1449 switch (pipelineStage
) {
1450 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
1451 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
1452 srm
.RegisterAddress
= TIMESTAMP
;
1453 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
};
1455 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
1456 srm
.RegisterAddress
= TIMESTAMP
+ 4;
1457 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
+ 4 };
1462 /* Everything else is bottom-of-pipe */
1463 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1464 pc
.DestinationAddressType
= DAT_PPGTT
,
1465 pc
.PostSyncOperation
= WriteTimestamp
,
1466 pc
.Address
= (struct anv_address
) { &pool
->bo
, offset
};
1471 emit_query_availability(&cmd_buffer
->batch
, &pool
->bo
, query
+ 16);
1474 #if GEN_GEN > 7 || GEN_IS_HASWELL
1476 #define alu_opcode(v) __gen_uint((v), 20, 31)
1477 #define alu_operand1(v) __gen_uint((v), 10, 19)
1478 #define alu_operand2(v) __gen_uint((v), 0, 9)
1479 #define alu(opcode, operand1, operand2) \
1480 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
1482 #define OPCODE_NOOP 0x000
1483 #define OPCODE_LOAD 0x080
1484 #define OPCODE_LOADINV 0x480
1485 #define OPCODE_LOAD0 0x081
1486 #define OPCODE_LOAD1 0x481
1487 #define OPCODE_ADD 0x100
1488 #define OPCODE_SUB 0x101
1489 #define OPCODE_AND 0x102
1490 #define OPCODE_OR 0x103
1491 #define OPCODE_XOR 0x104
1492 #define OPCODE_STORE 0x180
1493 #define OPCODE_STOREINV 0x580
1495 #define OPERAND_R0 0x00
1496 #define OPERAND_R1 0x01
1497 #define OPERAND_R2 0x02
1498 #define OPERAND_R3 0x03
1499 #define OPERAND_R4 0x04
1500 #define OPERAND_SRCA 0x20
1501 #define OPERAND_SRCB 0x21
1502 #define OPERAND_ACCU 0x31
1503 #define OPERAND_ZF 0x32
1504 #define OPERAND_CF 0x33
1506 #define CS_GPR(n) (0x2600 + (n) * 8)
1509 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
1510 struct anv_bo
*bo
, uint32_t offset
)
1512 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
1513 lrm
.RegisterAddress
= reg
,
1514 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
1516 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
1517 lrm
.RegisterAddress
= reg
+ 4;
1518 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
1523 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
1524 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
1526 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
1527 srm
.RegisterAddress
= reg
;
1528 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
1531 if (flags
& VK_QUERY_RESULT_64_BIT
) {
1532 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
1533 srm
.RegisterAddress
= reg
+ 4;
1534 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
1539 void genX(CmdCopyQueryPoolResults
)(
1540 VkCommandBuffer commandBuffer
,
1541 VkQueryPool queryPool
,
1542 uint32_t firstQuery
,
1543 uint32_t queryCount
,
1544 VkBuffer destBuffer
,
1545 VkDeviceSize destOffset
,
1546 VkDeviceSize destStride
,
1547 VkQueryResultFlags flags
)
1549 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1550 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1551 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
1552 uint32_t slot_offset
, dst_offset
;
1554 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
1555 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1556 pc
.CommandStreamerStallEnable
= true;
1557 pc
.StallAtPixelScoreboard
= true;
1561 dst_offset
= buffer
->offset
+ destOffset
;
1562 for (uint32_t i
= 0; i
< queryCount
; i
++) {
1564 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
1565 switch (pool
->type
) {
1566 case VK_QUERY_TYPE_OCCLUSION
:
1567 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
1568 CS_GPR(0), &pool
->bo
, slot_offset
);
1569 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
1570 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
1572 /* FIXME: We need to clamp the result for 32 bit. */
1574 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
1575 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
1576 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
1577 dw
[3] = alu(OPCODE_SUB
, 0, 0);
1578 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
1581 case VK_QUERY_TYPE_TIMESTAMP
:
1582 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
1583 CS_GPR(2), &pool
->bo
, slot_offset
);
1587 unreachable("unhandled query type");
1590 store_query_result(&cmd_buffer
->batch
,
1591 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
1593 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
1594 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
1595 &pool
->bo
, slot_offset
+ 16);
1596 if (flags
& VK_QUERY_RESULT_64_BIT
)
1597 store_query_result(&cmd_buffer
->batch
,
1598 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
1600 store_query_result(&cmd_buffer
->batch
,
1601 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
1604 dst_offset
+= destStride
;
1609 void genX(CmdCopyQueryPoolResults
)(
1610 VkCommandBuffer commandBuffer
,
1611 VkQueryPool queryPool
,
1612 uint32_t firstQuery
,
1613 uint32_t queryCount
,
1614 VkBuffer destBuffer
,
1615 VkDeviceSize destOffset
,
1616 VkDeviceSize destStride
,
1617 VkQueryResultFlags flags
)
1619 anv_finishme("Queries not yet supported on Ivy Bridge");