2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_l3_config.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
36 /* We reserve GPR 14 and 15 for conditional rendering */
37 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
38 #define __gen_get_batch_dwords anv_batch_emit_dwords
39 #define __gen_address_offset anv_address_add
40 #include "common/gen_mi_builder.h"
43 emit_lrm(struct anv_batch
*batch
, uint32_t reg
, struct anv_address addr
)
45 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
46 lrm
.RegisterAddress
= reg
;
47 lrm
.MemoryAddress
= addr
;
52 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
54 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
55 lri
.RegisterOffset
= reg
;
60 #if GEN_IS_HASWELL || GEN_GEN >= 8
62 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
64 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
65 lrr
.SourceRegisterAddress
= src
;
66 lrr
.DestinationRegisterAddress
= dst
;
72 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
74 struct anv_device
*device
= cmd_buffer
->device
;
76 /* If we are emitting a new state base address we probably need to re-emit
79 cmd_buffer
->state
.descriptors_dirty
|= ~0;
81 /* Emit a render target cache flush.
83 * This isn't documented anywhere in the PRM. However, it seems to be
84 * necessary prior to changing the surface state base adress. Without
85 * this, we get GPU hangs when using multi-level command buffers which
86 * clear depth, reset state base address, and then go render stuff.
88 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
89 pc
.DCFlushEnable
= true;
90 pc
.RenderTargetCacheFlushEnable
= true;
91 pc
.CommandStreamerStallEnable
= true;
94 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
95 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
96 sba
.GeneralStateMOCS
= GENX(MOCS
);
97 sba
.GeneralStateBaseAddressModifyEnable
= true;
99 sba
.SurfaceStateBaseAddress
=
100 anv_cmd_buffer_surface_base_address(cmd_buffer
);
101 sba
.SurfaceStateMOCS
= GENX(MOCS
);
102 sba
.SurfaceStateBaseAddressModifyEnable
= true;
104 sba
.DynamicStateBaseAddress
=
105 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
106 sba
.DynamicStateMOCS
= GENX(MOCS
);
107 sba
.DynamicStateBaseAddressModifyEnable
= true;
109 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
110 sba
.IndirectObjectMOCS
= GENX(MOCS
);
111 sba
.IndirectObjectBaseAddressModifyEnable
= true;
113 sba
.InstructionBaseAddress
=
114 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
115 sba
.InstructionMOCS
= GENX(MOCS
);
116 sba
.InstructionBaseAddressModifyEnable
= true;
119 /* Broadwell requires that we specify a buffer size for a bunch of
120 * these fields. However, since we will be growing the BO's live, we
121 * just set them all to the maximum.
123 sba
.GeneralStateBufferSize
= 0xfffff;
124 sba
.GeneralStateBufferSizeModifyEnable
= true;
125 sba
.DynamicStateBufferSize
= 0xfffff;
126 sba
.DynamicStateBufferSizeModifyEnable
= true;
127 sba
.IndirectObjectBufferSize
= 0xfffff;
128 sba
.IndirectObjectBufferSizeModifyEnable
= true;
129 sba
.InstructionBufferSize
= 0xfffff;
130 sba
.InstructionBuffersizeModifyEnable
= true;
133 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
134 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
135 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
136 sba
.BindlessSurfaceStateSize
= 0;
139 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
140 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
141 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
142 sba
.BindlessSamplerStateBufferSize
= 0;
146 /* After re-setting the surface state base address, we have to do some
147 * cache flusing so that the sampler engine will pick up the new
148 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
149 * Shared Function > 3D Sampler > State > State Caching (page 96):
151 * Coherency with system memory in the state cache, like the texture
152 * cache is handled partially by software. It is expected that the
153 * command stream or shader will issue Cache Flush operation or
154 * Cache_Flush sampler message to ensure that the L1 cache remains
155 * coherent with system memory.
159 * Whenever the value of the Dynamic_State_Base_Addr,
160 * Surface_State_Base_Addr are altered, the L1 state cache must be
161 * invalidated to ensure the new surface or sampler state is fetched
162 * from system memory.
164 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
165 * which, according the PIPE_CONTROL instruction documentation in the
168 * Setting this bit is independent of any other bit in this packet.
169 * This bit controls the invalidation of the L1 and L2 state caches
170 * at the top of the pipe i.e. at the parsing time.
172 * Unfortunately, experimentation seems to indicate that state cache
173 * invalidation through a PIPE_CONTROL does nothing whatsoever in
174 * regards to surface state and binding tables. In stead, it seems that
175 * invalidating the texture cache is what is actually needed.
177 * XXX: As far as we have been able to determine through
178 * experimentation, shows that flush the texture cache appears to be
179 * sufficient. The theory here is that all of the sampling/rendering
180 * units cache the binding table in the texture cache. However, we have
181 * yet to be able to actually confirm this.
183 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
184 pc
.TextureCacheInvalidationEnable
= true;
185 pc
.ConstantCacheInvalidationEnable
= true;
186 pc
.StateCacheInvalidationEnable
= true;
191 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
192 struct anv_state state
, struct anv_address addr
)
194 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
197 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
198 state
.offset
+ isl_dev
->ss
.addr_offset
,
199 addr
.bo
, addr
.offset
);
200 if (result
!= VK_SUCCESS
)
201 anv_batch_set_error(&cmd_buffer
->batch
, result
);
205 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
206 struct anv_surface_state state
)
208 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
210 assert(!anv_address_is_null(state
.address
));
211 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
213 if (!anv_address_is_null(state
.aux_address
)) {
215 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
216 &cmd_buffer
->pool
->alloc
,
217 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
218 state
.aux_address
.bo
, state
.aux_address
.offset
);
219 if (result
!= VK_SUCCESS
)
220 anv_batch_set_error(&cmd_buffer
->batch
, result
);
223 if (!anv_address_is_null(state
.clear_address
)) {
225 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
226 &cmd_buffer
->pool
->alloc
,
228 isl_dev
->ss
.clear_color_state_offset
,
229 state
.clear_address
.bo
, state
.clear_address
.offset
);
230 if (result
!= VK_SUCCESS
)
231 anv_batch_set_error(&cmd_buffer
->batch
, result
);
236 color_attachment_compute_aux_usage(struct anv_device
* device
,
237 struct anv_cmd_state
* cmd_state
,
238 uint32_t att
, VkRect2D render_area
,
239 union isl_color_value
*fast_clear_color
)
241 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
242 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
244 assert(iview
->n_planes
== 1);
246 if (iview
->planes
[0].isl
.base_array_layer
>=
247 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
248 iview
->planes
[0].isl
.base_level
)) {
249 /* There is no aux buffer which corresponds to the level and layer(s)
252 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
253 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
254 att_state
->fast_clear
= false;
258 att_state
->aux_usage
=
259 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
260 VK_IMAGE_ASPECT_COLOR_BIT
,
261 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
263 /* If we don't have aux, then we should have returned early in the layer
264 * check above. If we got here, we must have something.
266 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
268 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
269 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
270 att_state
->input_aux_usage
= att_state
->aux_usage
;
272 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
274 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
275 * setting is only allowed if Surface Format supported for Fast
276 * Clear. In addition, if the surface is bound to the sampling
277 * engine, Surface Format must be supported for Render Target
278 * Compression for surfaces bound to the sampling engine."
280 * In other words, we can only sample from a fast-cleared image if it
281 * also supports color compression.
283 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
284 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
286 /* While fast-clear resolves and partial resolves are fairly cheap in the
287 * case where you render to most of the pixels, full resolves are not
288 * because they potentially involve reading and writing the entire
289 * framebuffer. If we can't texture with CCS_E, we should leave it off and
290 * limit ourselves to fast clears.
292 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
293 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
294 anv_perf_warn(device
->instance
, iview
->image
,
295 "Not temporarily enabling CCS_E.");
298 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
302 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
303 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
305 union isl_color_value clear_color
= {};
306 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
308 att_state
->clear_color_is_zero_one
=
309 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
310 att_state
->clear_color_is_zero
=
311 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
313 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
314 /* Start by getting the fast clear type. We use the first subpass
315 * layout here because we don't want to fast-clear if the first subpass
316 * to use the attachment can't handle fast-clears.
318 enum anv_fast_clear_type fast_clear_type
=
319 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
320 VK_IMAGE_ASPECT_COLOR_BIT
,
321 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
322 switch (fast_clear_type
) {
323 case ANV_FAST_CLEAR_NONE
:
324 att_state
->fast_clear
= false;
326 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
327 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
329 case ANV_FAST_CLEAR_ANY
:
330 att_state
->fast_clear
= true;
334 /* Potentially, we could do partial fast-clears but doing so has crazy
335 * alignment restrictions. It's easier to just restrict to full size
336 * fast clears for now.
338 if (render_area
.offset
.x
!= 0 ||
339 render_area
.offset
.y
!= 0 ||
340 render_area
.extent
.width
!= iview
->extent
.width
||
341 render_area
.extent
.height
!= iview
->extent
.height
)
342 att_state
->fast_clear
= false;
344 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
345 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
346 att_state
->fast_clear
= false;
348 /* We only allow fast clears to the first slice of an image (level 0,
349 * layer 0) and only for the entire slice. This guarantees us that, at
350 * any given time, there is only one clear color on any given image at
351 * any given time. At the time of our testing (Jan 17, 2018), there
352 * were no known applications which would benefit from fast-clearing
353 * more than just the first slice.
355 if (att_state
->fast_clear
&&
356 (iview
->planes
[0].isl
.base_level
> 0 ||
357 iview
->planes
[0].isl
.base_array_layer
> 0)) {
358 anv_perf_warn(device
->instance
, iview
->image
,
359 "Rendering with multi-lod or multi-layer framebuffer "
360 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
361 "baseArrayLayer > 0. Not fast clearing.");
362 att_state
->fast_clear
= false;
363 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
364 anv_perf_warn(device
->instance
, iview
->image
,
365 "Rendering to a multi-layer framebuffer with "
366 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
369 if (att_state
->fast_clear
)
370 *fast_clear_color
= clear_color
;
372 att_state
->fast_clear
= false;
377 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
378 struct anv_cmd_state
*cmd_state
,
379 uint32_t att
, VkRect2D render_area
)
381 struct anv_render_pass_attachment
*pass_att
=
382 &cmd_state
->pass
->attachments
[att
];
383 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
384 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
386 /* These will be initialized after the first subpass transition. */
387 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
388 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
391 /* We don't do any HiZ or depth fast-clears on gen7 yet */
392 att_state
->fast_clear
= false;
396 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
397 /* If we're just clearing stencil, we can always HiZ clear */
398 att_state
->fast_clear
= true;
402 /* Default to false for now */
403 att_state
->fast_clear
= false;
405 /* We must have depth in order to have HiZ */
406 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
409 const enum isl_aux_usage first_subpass_aux_usage
=
410 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
411 VK_IMAGE_ASPECT_DEPTH_BIT
,
412 pass_att
->first_subpass_layout
);
413 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
416 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
417 iview
->planes
[0].isl
.format
,
418 iview
->image
->samples
,
419 render_area
.offset
.x
,
420 render_area
.offset
.y
,
421 render_area
.offset
.x
+
422 render_area
.extent
.width
,
423 render_area
.offset
.y
+
424 render_area
.extent
.height
))
427 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
430 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
431 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
432 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
433 * only supports returning 0.0f. Gens prior to gen8 do not support this
439 /* If we got here, then we can fast clear */
440 att_state
->fast_clear
= true;
444 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
446 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
449 /* We only allocate input attachment states for color surfaces. Compression
450 * is not yet enabled for depth textures and stencil doesn't allow
451 * compression so we can just use the texture surface state from the view.
453 return vk_format_is_color(att
->format
);
456 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
457 * the initial layout is undefined, the HiZ buffer and depth buffer will
458 * represent the same data at the end of this operation.
461 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
462 const struct anv_image
*image
,
463 VkImageLayout initial_layout
,
464 VkImageLayout final_layout
)
466 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
467 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
468 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
469 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
470 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
471 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
473 enum isl_aux_op hiz_op
;
474 if (hiz_enabled
&& !enable_hiz
) {
475 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
476 } else if (!hiz_enabled
&& enable_hiz
) {
477 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
479 assert(hiz_enabled
== enable_hiz
);
480 /* If the same buffer will be used, no resolves are necessary. */
481 hiz_op
= ISL_AUX_OP_NONE
;
484 if (hiz_op
!= ISL_AUX_OP_NONE
)
485 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
489 #define MI_PREDICATE_SRC0 0x2400
490 #define MI_PREDICATE_SRC1 0x2408
491 #define MI_PREDICATE_RESULT 0x2418
494 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
495 const struct anv_image
*image
,
496 VkImageAspectFlagBits aspect
,
498 uint32_t base_layer
, uint32_t layer_count
,
501 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
503 /* We only have compression tracking for CCS_E */
504 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
507 for (uint32_t a
= 0; a
< layer_count
; a
++) {
508 uint32_t layer
= base_layer
+ a
;
509 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
510 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
513 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
519 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
520 const struct anv_image
*image
,
521 VkImageAspectFlagBits aspect
,
522 enum anv_fast_clear_type fast_clear
)
524 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
525 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
527 sdi
.ImmediateData
= fast_clear
;
530 /* Whenever we have fast-clear, we consider that slice to be compressed.
531 * This makes building predicates much easier.
533 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
534 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
537 #if GEN_IS_HASWELL || GEN_GEN >= 8
538 static inline uint32_t
539 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
541 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
543 .Operand1
= operand1
,
544 .Operand2
= operand2
,
548 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
554 #define CS_GPR(n) (0x2600 + (n) * 8)
556 /* This is only really practical on haswell and above because it requires
557 * MI math in order to get it correct.
559 #if GEN_GEN >= 8 || GEN_IS_HASWELL
561 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
562 const struct anv_image
*image
,
563 VkImageAspectFlagBits aspect
,
564 uint32_t level
, uint32_t array_layer
,
565 enum isl_aux_op resolve_op
,
566 enum anv_fast_clear_type fast_clear_supported
)
568 struct anv_address fast_clear_type_addr
=
569 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
571 /* Name some registers */
572 const int image_fc_reg
= MI_ALU_REG0
;
573 const int fc_imm_reg
= MI_ALU_REG1
;
574 const int pred_reg
= MI_ALU_REG2
;
578 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
579 /* In this case, we're doing a full resolve which means we want the
580 * resolve to happen if any compression (including fast-clears) is
583 * In order to simplify the logic a bit, we make the assumption that,
584 * if the first slice has been fast-cleared, it is also marked as
585 * compressed. See also set_image_fast_clear_state.
587 struct anv_address compression_state_addr
=
588 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
589 aspect
, level
, array_layer
);
590 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
591 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
592 lrm
.MemoryAddress
= compression_state_addr
;
594 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
595 sdi
.Address
= compression_state_addr
;
596 sdi
.ImmediateData
= 0;
599 if (level
== 0 && array_layer
== 0) {
600 /* If the predicate is true, we want to write 0 to the fast clear type
601 * and, if it's false, leave it alone. We can do this by writing
603 * clear_type = clear_type & ~predicate;
605 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
606 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
607 lrm
.MemoryAddress
= fast_clear_type_addr
;
609 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
610 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
611 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
614 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
615 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
616 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
617 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
618 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
620 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
621 srm
.MemoryAddress
= fast_clear_type_addr
;
622 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
625 } else if (level
== 0 && array_layer
== 0) {
626 /* In this case, we are doing a partial resolve to get rid of fast-clear
627 * colors. We don't care about the compression state but we do care
628 * about how much fast clear is allowed by the final layout.
630 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
631 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
633 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
634 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
635 lrm
.MemoryAddress
= fast_clear_type_addr
;
637 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
639 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
640 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
642 /* We need to compute (fast_clear_supported < image->fast_clear).
643 * We do this by subtracting and storing the carry bit.
645 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
646 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
647 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
648 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
649 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
651 /* Store the predicate */
652 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
654 /* If the predicate is true, we want to write 0 to the fast clear type
655 * and, if it's false, leave it alone. We can do this by writing
657 * clear_type = clear_type & ~predicate;
659 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
660 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
661 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
662 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
663 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
665 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
666 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
667 srm
.MemoryAddress
= fast_clear_type_addr
;
670 /* In this case, we're trying to do a partial resolve on a slice that
671 * doesn't have clear color. There's nothing to do.
673 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
677 /* We use the first half of src0 for the actual predicate. Set the second
678 * half of src0 and all of src1 to 0 as the predicate operation will be
679 * doing an implicit src0 != src1.
681 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
682 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
683 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
685 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
686 mip
.LoadOperation
= LOAD_LOADINV
;
687 mip
.CombineOperation
= COMBINE_SET
;
688 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
691 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
695 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
696 const struct anv_image
*image
,
697 VkImageAspectFlagBits aspect
,
698 uint32_t level
, uint32_t array_layer
,
699 enum isl_aux_op resolve_op
,
700 enum anv_fast_clear_type fast_clear_supported
)
702 struct anv_address fast_clear_type_addr
=
703 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
705 /* This only works for partial resolves and only when the clear color is
706 * all or nothing. On the upside, this emits less command streamer code
707 * and works on Ivybridge and Bay Trail.
709 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
710 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
712 /* We don't support fast clears on anything other than the first slice. */
713 if (level
> 0 || array_layer
> 0)
716 /* On gen8, we don't have a concept of default clear colors because we
717 * can't sample from CCS surfaces. It's enough to just load the fast clear
718 * state into the predicate register.
720 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
721 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
722 lrm
.MemoryAddress
= fast_clear_type_addr
;
724 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
725 sdi
.Address
= fast_clear_type_addr
;
726 sdi
.ImmediateData
= 0;
729 /* We use the first half of src0 for the actual predicate. Set the second
730 * half of src0 and all of src1 to 0 as the predicate operation will be
731 * doing an implicit src0 != src1.
733 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
734 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
735 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
737 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
738 mip
.LoadOperation
= LOAD_LOADINV
;
739 mip
.CombineOperation
= COMBINE_SET
;
740 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
743 #endif /* GEN_GEN <= 8 */
746 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
747 const struct anv_image
*image
,
748 enum isl_format format
,
749 VkImageAspectFlagBits aspect
,
750 uint32_t level
, uint32_t array_layer
,
751 enum isl_aux_op resolve_op
,
752 enum anv_fast_clear_type fast_clear_supported
)
754 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
757 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
758 aspect
, level
, array_layer
,
759 resolve_op
, fast_clear_supported
);
760 #else /* GEN_GEN <= 8 */
761 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
762 aspect
, level
, array_layer
,
763 resolve_op
, fast_clear_supported
);
766 /* CCS_D only supports full resolves and BLORP will assert on us if we try
767 * to do a partial resolve on a CCS_D surface.
769 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
770 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
771 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
773 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
774 array_layer
, 1, resolve_op
, NULL
, true);
778 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
779 const struct anv_image
*image
,
780 enum isl_format format
,
781 VkImageAspectFlagBits aspect
,
782 uint32_t array_layer
,
783 enum isl_aux_op resolve_op
,
784 enum anv_fast_clear_type fast_clear_supported
)
786 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
787 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
789 #if GEN_GEN >= 8 || GEN_IS_HASWELL
790 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
791 aspect
, 0, array_layer
,
792 resolve_op
, fast_clear_supported
);
794 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
795 array_layer
, 1, resolve_op
, NULL
, true);
797 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
802 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
803 const struct anv_image
*image
,
804 VkImageAspectFlagBits aspect
,
805 enum isl_aux_usage aux_usage
,
808 uint32_t layer_count
)
810 /* The aspect must be exactly one of the image aspects. */
811 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
813 /* The only compression types with more than just fast-clears are MCS,
814 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
815 * track the current fast-clear and compression state. This leaves us
816 * with just MCS and CCS_E.
818 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
819 aux_usage
!= ISL_AUX_USAGE_MCS
)
822 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
823 level
, base_layer
, layer_count
, true);
827 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
828 const struct anv_image
*image
,
829 VkImageAspectFlagBits aspect
)
831 assert(cmd_buffer
&& image
);
832 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
834 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
835 ANV_FAST_CLEAR_NONE
);
837 /* The fast clear value dword(s) will be copied into a surface state object.
838 * Ensure that the restrictions of the fields in the dword(s) are followed.
840 * CCS buffers on SKL+ can have any value set for the clear colors.
842 if (image
->samples
== 1 && GEN_GEN
>= 9)
845 /* Other combinations of auxiliary buffers and platforms require specific
846 * values in the clear value dword(s).
848 struct anv_address addr
=
849 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
852 for (unsigned i
= 0; i
< 4; i
++) {
853 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
855 sdi
.Address
.offset
+= i
* 4;
856 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
857 assert(image
->samples
> 1);
858 sdi
.ImmediateData
= 0;
862 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
864 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
865 /* Pre-SKL, the dword containing the clear values also contains
866 * other fields, so we need to initialize those fields to match the
867 * values that would be in a color attachment.
869 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
870 ISL_CHANNEL_SELECT_GREEN
<< 22 |
871 ISL_CHANNEL_SELECT_BLUE
<< 19 |
872 ISL_CHANNEL_SELECT_ALPHA
<< 16;
873 } else if (GEN_GEN
== 7) {
874 /* On IVB, the dword containing the clear values also contains
875 * other fields that must be zero or can be zero.
877 sdi
.ImmediateData
= 0;
883 /* Copy the fast-clear value dword(s) between a surface state object and an
884 * image's fast clear state buffer.
887 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
888 struct anv_state surface_state
,
889 const struct anv_image
*image
,
890 VkImageAspectFlagBits aspect
,
891 bool copy_from_surface_state
)
893 assert(cmd_buffer
&& image
);
894 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
896 struct anv_address ss_clear_addr
= {
897 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
898 .offset
= surface_state
.offset
+
899 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
901 const struct anv_address entry_addr
=
902 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
903 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
905 if (copy_from_surface_state
) {
906 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
,
907 ss_clear_addr
, copy_size
);
909 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_clear_addr
,
910 entry_addr
, copy_size
);
912 /* Updating a surface state object may require that the state cache be
913 * invalidated. From the SKL PRM, Shared Functions -> State -> State
916 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
917 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
918 * modified [...], the L1 state cache must be invalidated to ensure
919 * the new surface or sampler state is fetched from system memory.
921 * In testing, SKL doesn't actually seem to need this, but HSW does.
923 cmd_buffer
->state
.pending_pipe_bits
|=
924 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
929 * @brief Transitions a color buffer from one layout to another.
931 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
934 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
935 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
936 * this represents the maximum layers to transition at each
937 * specified miplevel.
940 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
941 const struct anv_image
*image
,
942 VkImageAspectFlagBits aspect
,
943 const uint32_t base_level
, uint32_t level_count
,
944 uint32_t base_layer
, uint32_t layer_count
,
945 VkImageLayout initial_layout
,
946 VkImageLayout final_layout
)
948 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
949 /* Validate the inputs. */
951 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
952 /* These values aren't supported for simplicity's sake. */
953 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
954 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
955 /* Ensure the subresource range is valid. */
956 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
957 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
958 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
959 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
960 assert(last_level_num
<= image
->levels
);
961 /* The spec disallows these final layouts. */
962 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
963 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
965 /* No work is necessary if the layout stays the same or if this subresource
966 * range lacks auxiliary data.
968 if (initial_layout
== final_layout
)
971 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
973 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
974 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
975 /* This surface is a linear compressed image with a tiled shadow surface
976 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
977 * we need to ensure the shadow copy is up-to-date.
979 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
980 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
981 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
982 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
984 anv_image_copy_to_shadow(cmd_buffer
, image
,
985 base_level
, level_count
,
986 base_layer
, layer_count
);
989 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
992 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
994 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
995 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
996 /* A subresource in the undefined layout may have been aliased and
997 * populated with any arrangement of bits. Therefore, we must initialize
998 * the related aux buffer and clear buffer entry with desirable values.
999 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1000 * images with VK_IMAGE_TILING_OPTIMAL.
1002 * Initialize the relevant clear buffer entries.
1004 if (base_level
== 0 && base_layer
== 0)
1005 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1007 /* Initialize the aux buffers to enable correct rendering. In order to
1008 * ensure that things such as storage images work correctly, aux buffers
1009 * need to be initialized to valid data.
1011 * Having an aux buffer with invalid data is a problem for two reasons:
1013 * 1) Having an invalid value in the buffer can confuse the hardware.
1014 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1015 * invalid and leads to the hardware doing strange things. It
1016 * doesn't hang as far as we can tell but rendering corruption can
1019 * 2) If this transition is into the GENERAL layout and we then use the
1020 * image as a storage image, then we must have the aux buffer in the
1021 * pass-through state so that, if we then go to texture from the
1022 * image, we get the results of our storage image writes and not the
1023 * fast clear color or other random data.
1025 * For CCS both of the problems above are real demonstrable issues. In
1026 * that case, the only thing we can do is to perform an ambiguate to
1027 * transition the aux surface into the pass-through state.
1029 * For MCS, (2) is never an issue because we don't support multisampled
1030 * storage images. In theory, issue (1) is a problem with MCS but we've
1031 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1032 * theory, be interpreted as something but we don't know that all bit
1033 * patterns are actually valid. For 2x and 8x, you could easily end up
1034 * with the MCS referring to an invalid plane because not all bits of
1035 * the MCS value are actually used. Even though we've never seen issues
1036 * in the wild, it's best to play it safe and initialize the MCS. We
1037 * can use a fast-clear for MCS because we only ever touch from render
1038 * and texture (no image load store).
1040 if (image
->samples
== 1) {
1041 for (uint32_t l
= 0; l
< level_count
; l
++) {
1042 const uint32_t level
= base_level
+ l
;
1044 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1045 if (base_layer
>= aux_layers
)
1046 break; /* We will only get fewer layers as level increases */
1047 uint32_t level_layer_count
=
1048 MIN2(layer_count
, aux_layers
- base_layer
);
1050 anv_image_ccs_op(cmd_buffer
, image
,
1051 image
->planes
[plane
].surface
.isl
.format
,
1052 aspect
, level
, base_layer
, level_layer_count
,
1053 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1055 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1056 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1057 level
, base_layer
, level_layer_count
,
1062 if (image
->samples
== 4 || image
->samples
== 16) {
1063 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1064 "Doing a potentially unnecessary fast-clear to "
1065 "define an MCS buffer.");
1068 assert(base_level
== 0 && level_count
== 1);
1069 anv_image_mcs_op(cmd_buffer
, image
,
1070 image
->planes
[plane
].surface
.isl
.format
,
1071 aspect
, base_layer
, layer_count
,
1072 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1077 const enum isl_aux_usage initial_aux_usage
=
1078 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1079 const enum isl_aux_usage final_aux_usage
=
1080 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1082 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1083 * We can handle transitions between CCS_D/E to and from NONE. What we
1084 * don't yet handle is switching between CCS_E and CCS_D within a given
1085 * image. Doing so in a performant way requires more detailed aux state
1086 * tracking such as what is done in i965. For now, just assume that we
1087 * only have one type of compression.
1089 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1090 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1091 initial_aux_usage
== final_aux_usage
);
1093 /* If initial aux usage is NONE, there is nothing to resolve */
1094 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1097 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1099 /* If the initial layout supports more fast clear than the final layout
1100 * then we need at least a partial resolve.
1102 const enum anv_fast_clear_type initial_fast_clear
=
1103 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1104 const enum anv_fast_clear_type final_fast_clear
=
1105 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1106 if (final_fast_clear
< initial_fast_clear
)
1107 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1109 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1110 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1111 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1113 if (resolve_op
== ISL_AUX_OP_NONE
)
1116 /* Perform a resolve to synchronize data between the main and aux buffer.
1117 * Before we begin, we must satisfy the cache flushing requirement specified
1118 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1120 * Any transition from any value in {Clear, Render, Resolve} to a
1121 * different value in {Clear, Render, Resolve} requires end of pipe
1124 * We perform a flush of the write cache before and after the clear and
1125 * resolve operations to meet this requirement.
1127 * Unlike other drawing, fast clear operations are not properly
1128 * synchronized. The first PIPE_CONTROL here likely ensures that the
1129 * contents of the previous render or clear hit the render target before we
1130 * resolve and the second likely ensures that the resolve is complete before
1131 * we do any more rendering or clearing.
1133 cmd_buffer
->state
.pending_pipe_bits
|=
1134 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1136 for (uint32_t l
= 0; l
< level_count
; l
++) {
1137 uint32_t level
= base_level
+ l
;
1139 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1140 if (base_layer
>= aux_layers
)
1141 break; /* We will only get fewer layers as level increases */
1142 uint32_t level_layer_count
=
1143 MIN2(layer_count
, aux_layers
- base_layer
);
1145 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1146 uint32_t array_layer
= base_layer
+ a
;
1147 if (image
->samples
== 1) {
1148 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1149 image
->planes
[plane
].surface
.isl
.format
,
1150 aspect
, level
, array_layer
, resolve_op
,
1153 /* We only support fast-clear on the first layer so partial
1154 * resolves should not be used on other layers as they will use
1155 * the clear color stored in memory that is only valid for layer0.
1157 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1161 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1162 image
->planes
[plane
].surface
.isl
.format
,
1163 aspect
, array_layer
, resolve_op
,
1169 cmd_buffer
->state
.pending_pipe_bits
|=
1170 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1174 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1177 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1178 struct anv_render_pass
*pass
,
1179 const VkRenderPassBeginInfo
*begin
)
1181 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1182 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1184 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1186 if (pass
->attachment_count
> 0) {
1187 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1188 pass
->attachment_count
*
1189 sizeof(state
->attachments
[0]),
1190 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1191 if (state
->attachments
== NULL
) {
1192 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1193 return anv_batch_set_error(&cmd_buffer
->batch
,
1194 VK_ERROR_OUT_OF_HOST_MEMORY
);
1197 state
->attachments
= NULL
;
1200 /* Reserve one for the NULL state. */
1201 unsigned num_states
= 1;
1202 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1203 if (vk_format_is_color(pass
->attachments
[i
].format
))
1206 if (need_input_attachment_state(&pass
->attachments
[i
]))
1210 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1211 state
->render_pass_states
=
1212 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1213 num_states
* ss_stride
, isl_dev
->ss
.align
);
1215 struct anv_state next_state
= state
->render_pass_states
;
1216 next_state
.alloc_size
= isl_dev
->ss
.size
;
1218 state
->null_surface_state
= next_state
;
1219 next_state
.offset
+= ss_stride
;
1220 next_state
.map
+= ss_stride
;
1222 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1223 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1224 state
->attachments
[i
].color
.state
= next_state
;
1225 next_state
.offset
+= ss_stride
;
1226 next_state
.map
+= ss_stride
;
1229 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1230 state
->attachments
[i
].input
.state
= next_state
;
1231 next_state
.offset
+= ss_stride
;
1232 next_state
.map
+= ss_stride
;
1235 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1236 state
->render_pass_states
.alloc_size
);
1239 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1240 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1242 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1243 isl_extent3d(framebuffer
->width
,
1244 framebuffer
->height
,
1245 framebuffer
->layers
));
1247 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1248 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1249 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1250 VkImageAspectFlags clear_aspects
= 0;
1251 VkImageAspectFlags load_aspects
= 0;
1253 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1254 /* color attachment */
1255 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1256 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1257 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1258 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1261 /* depthstencil attachment */
1262 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1263 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1264 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1265 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1266 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1269 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1270 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1271 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1272 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1273 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1278 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1279 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1280 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1282 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1284 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1285 anv_assert(iview
->vk_format
== att
->format
);
1287 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1288 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1290 union isl_color_value clear_color
= { .u32
= { 0, } };
1291 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1292 anv_assert(iview
->n_planes
== 1);
1293 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1294 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1295 state
, i
, begin
->renderArea
,
1298 anv_image_fill_surface_state(cmd_buffer
->device
,
1300 VK_IMAGE_ASPECT_COLOR_BIT
,
1301 &iview
->planes
[0].isl
,
1302 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1303 state
->attachments
[i
].aux_usage
,
1306 &state
->attachments
[i
].color
,
1309 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1311 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1316 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1317 anv_image_fill_surface_state(cmd_buffer
->device
,
1319 VK_IMAGE_ASPECT_COLOR_BIT
,
1320 &iview
->planes
[0].isl
,
1321 ISL_SURF_USAGE_TEXTURE_BIT
,
1322 state
->attachments
[i
].input_aux_usage
,
1325 &state
->attachments
[i
].input
,
1328 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1337 genX(BeginCommandBuffer
)(
1338 VkCommandBuffer commandBuffer
,
1339 const VkCommandBufferBeginInfo
* pBeginInfo
)
1341 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1343 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1344 * command buffer's state. Otherwise, we must *reset* its state. In both
1345 * cases we reset it.
1347 * From the Vulkan 1.0 spec:
1349 * If a command buffer is in the executable state and the command buffer
1350 * was allocated from a command pool with the
1351 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1352 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1353 * as if vkResetCommandBuffer had been called with
1354 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1355 * the command buffer in the recording state.
1357 anv_cmd_buffer_reset(cmd_buffer
);
1359 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1361 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1362 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1364 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1366 /* We sometimes store vertex data in the dynamic state buffer for blorp
1367 * operations and our dynamic state stream may re-use data from previous
1368 * command buffers. In order to prevent stale cache data, we flush the VF
1369 * cache. We could do this on every blorp call but that's not really
1370 * needed as all of the data will get written by the CPU prior to the GPU
1371 * executing anything. The chances are fairly high that they will use
1372 * blorp at least once per primary command buffer so it shouldn't be
1375 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1376 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1378 /* We send an "Indirect State Pointers Disable" packet at
1379 * EndCommandBuffer, so all push contant packets are ignored during a
1380 * context restore. Documentation says after that command, we need to
1381 * emit push constants again before any rendering operation. So we
1382 * flag them dirty here to make sure they get emitted.
1384 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1386 VkResult result
= VK_SUCCESS
;
1387 if (cmd_buffer
->usage_flags
&
1388 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1389 assert(pBeginInfo
->pInheritanceInfo
);
1390 cmd_buffer
->state
.pass
=
1391 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1392 cmd_buffer
->state
.subpass
=
1393 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1395 /* This is optional in the inheritance info. */
1396 cmd_buffer
->state
.framebuffer
=
1397 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1399 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1400 cmd_buffer
->state
.pass
, NULL
);
1402 /* Record that HiZ is enabled if we can. */
1403 if (cmd_buffer
->state
.framebuffer
) {
1404 const struct anv_image_view
* const iview
=
1405 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1408 VkImageLayout layout
=
1409 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1411 enum isl_aux_usage aux_usage
=
1412 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1413 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1415 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1419 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1422 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1423 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1424 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1425 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1427 /* If secondary buffer supports conditional rendering
1428 * we should emit commands as if conditional rendering is enabled.
1430 cmd_buffer
->state
.conditional_render_enabled
=
1431 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1438 /* From the PRM, Volume 2a:
1440 * "Indirect State Pointers Disable
1442 * At the completion of the post-sync operation associated with this pipe
1443 * control packet, the indirect state pointers in the hardware are
1444 * considered invalid; the indirect pointers are not saved in the context.
1445 * If any new indirect state commands are executed in the command stream
1446 * while the pipe control is pending, the new indirect state commands are
1449 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1450 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1451 * commands are only considered as Indirect State Pointers. Once ISP is
1452 * issued in a context, SW must initialize by programming push constant
1453 * commands for all the shaders (at least to zero length) before attempting
1454 * any rendering operation for the same context."
1456 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1457 * even though they point to a BO that has been already unreferenced at
1458 * the end of the previous batch buffer. This has been fine so far since
1459 * we are protected by these scratch page (every address not covered by
1460 * a BO should be pointing to the scratch page). But on CNL, it is
1461 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1464 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1465 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1466 * context restore, so the mentioned hang doesn't happen. However,
1467 * software must program push constant commands for all stages prior to
1468 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1470 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1471 * constants have been loaded into the EUs prior to disable the push constants
1472 * so that it doesn't hang a previous 3DPRIMITIVE.
1475 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1477 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1478 pc
.StallAtPixelScoreboard
= true;
1479 pc
.CommandStreamerStallEnable
= true;
1481 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1482 pc
.IndirectStatePointersDisable
= true;
1483 pc
.CommandStreamerStallEnable
= true;
1488 genX(EndCommandBuffer
)(
1489 VkCommandBuffer commandBuffer
)
1491 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1493 if (anv_batch_has_error(&cmd_buffer
->batch
))
1494 return cmd_buffer
->batch
.status
;
1496 /* We want every command buffer to start with the PMA fix in a known state,
1497 * so we disable it at the end of the command buffer.
1499 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1501 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1503 emit_isp_disable(cmd_buffer
);
1505 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1511 genX(CmdExecuteCommands
)(
1512 VkCommandBuffer commandBuffer
,
1513 uint32_t commandBufferCount
,
1514 const VkCommandBuffer
* pCmdBuffers
)
1516 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1518 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1520 if (anv_batch_has_error(&primary
->batch
))
1523 /* The secondary command buffers will assume that the PMA fix is disabled
1524 * when they begin executing. Make sure this is true.
1526 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1528 /* The secondary command buffer doesn't know which textures etc. have been
1529 * flushed prior to their execution. Apply those flushes now.
1531 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1533 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1534 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1536 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1537 assert(!anv_batch_has_error(&secondary
->batch
));
1539 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1540 if (secondary
->state
.conditional_render_enabled
) {
1541 if (!primary
->state
.conditional_render_enabled
) {
1542 /* Secondary buffer is constructed as if it will be executed
1543 * with conditional rendering, we should satisfy this dependency
1544 * regardless of conditional rendering being enabled in primary.
1546 emit_lri(&primary
->batch
, CS_GPR(ANV_PREDICATE_RESULT_REG
), UINT32_MAX
);
1547 emit_lri(&primary
->batch
, CS_GPR(ANV_PREDICATE_RESULT_REG
) + 4, UINT32_MAX
);
1552 if (secondary
->usage_flags
&
1553 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1554 /* If we're continuing a render pass from the primary, we need to
1555 * copy the surface states for the current subpass into the storage
1556 * we allocated for them in BeginCommandBuffer.
1558 struct anv_bo
*ss_bo
=
1559 primary
->device
->surface_state_pool
.block_pool
.bo
;
1560 struct anv_state src_state
= primary
->state
.render_pass_states
;
1561 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1562 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1564 genX(cmd_buffer_so_memcpy
)(primary
,
1565 (struct anv_address
) {
1567 .offset
= dst_state
.offset
,
1569 (struct anv_address
) {
1571 .offset
= src_state
.offset
,
1573 src_state
.alloc_size
);
1576 anv_cmd_buffer_add_secondary(primary
, secondary
);
1579 /* The secondary may have selected a different pipeline (3D or compute) and
1580 * may have changed the current L3$ configuration. Reset our tracking
1581 * variables to invalid values to ensure that we re-emit these in the case
1582 * where we do any draws or compute dispatches from the primary after the
1583 * secondary has returned.
1585 primary
->state
.current_pipeline
= UINT32_MAX
;
1586 primary
->state
.current_l3_config
= NULL
;
1588 /* Each of the secondary command buffers will use its own state base
1589 * address. We need to re-emit state base address for the primary after
1590 * all of the secondaries are done.
1592 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1595 genX(cmd_buffer_emit_state_base_address
)(primary
);
1598 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1599 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1600 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1603 * Program the hardware to use the specified L3 configuration.
1606 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1607 const struct gen_l3_config
*cfg
)
1610 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1613 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1614 intel_logd("L3 config transition: ");
1615 gen_dump_l3_config(cfg
, stderr
);
1618 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1620 /* According to the hardware docs, the L3 partitioning can only be changed
1621 * while the pipeline is completely drained and the caches are flushed,
1622 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1624 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1625 pc
.DCFlushEnable
= true;
1626 pc
.PostSyncOperation
= NoWrite
;
1627 pc
.CommandStreamerStallEnable
= true;
1630 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1631 * invalidation of the relevant caches. Note that because RO invalidation
1632 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1633 * command is processed by the CS) we cannot combine it with the previous
1634 * stalling flush as the hardware documentation suggests, because that
1635 * would cause the CS to stall on previous rendering *after* RO
1636 * invalidation and wouldn't prevent the RO caches from being polluted by
1637 * concurrent rendering before the stall completes. This intentionally
1638 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1639 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1640 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1641 * already guarantee that there is no concurrent GPGPU kernel execution
1642 * (see SKL HSD 2132585).
1644 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1645 pc
.TextureCacheInvalidationEnable
= true;
1646 pc
.ConstantCacheInvalidationEnable
= true;
1647 pc
.InstructionCacheInvalidateEnable
= true;
1648 pc
.StateCacheInvalidationEnable
= true;
1649 pc
.PostSyncOperation
= NoWrite
;
1652 /* Now send a third stalling flush to make sure that invalidation is
1653 * complete when the L3 configuration registers are modified.
1655 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1656 pc
.DCFlushEnable
= true;
1657 pc
.PostSyncOperation
= NoWrite
;
1658 pc
.CommandStreamerStallEnable
= true;
1663 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1666 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1667 .SLMEnable
= has_slm
,
1669 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1670 * in L3CNTLREG register. The default setting of the bit is not the
1671 * desirable behavior.
1673 .ErrorDetectionBehaviorControl
= true,
1674 .UseFullWays
= true,
1676 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1677 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1678 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1679 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1681 /* Set up the L3 partitioning. */
1682 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1686 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1687 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1688 cfg
->n
[GEN_L3P_ALL
];
1689 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1690 cfg
->n
[GEN_L3P_ALL
];
1691 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1692 cfg
->n
[GEN_L3P_ALL
];
1694 assert(!cfg
->n
[GEN_L3P_ALL
]);
1696 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1697 * the matching space on the remaining banks has to be allocated to a
1698 * client (URB for all validated configurations) set to the
1699 * lower-bandwidth 2-bank address hashing mode.
1701 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1702 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1703 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1705 /* Minimum number of ways that can be allocated to the URB. */
1706 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1707 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1709 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1710 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1711 .ConvertDC_UC
= !has_dc
,
1712 .ConvertIS_UC
= !has_is
,
1713 .ConvertC_UC
= !has_c
,
1714 .ConvertT_UC
= !has_t
);
1716 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1717 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1718 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1720 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1721 .SLMEnable
= has_slm
,
1722 .URBLowBandwidth
= urb_low_bw
,
1723 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1725 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1727 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1728 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1730 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1731 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1732 .ISLowBandwidth
= 0,
1733 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1735 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1736 .TLowBandwidth
= 0);
1738 /* Set up the L3 partitioning. */
1739 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1740 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1741 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1744 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1745 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1746 * them disabled to avoid crashing the system hard.
1748 uint32_t scratch1
, chicken3
;
1749 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1750 .L3AtomicDisable
= !has_dc
);
1751 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1752 .L3AtomicDisableMask
= true,
1753 .L3AtomicDisable
= !has_dc
);
1754 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1755 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1761 cmd_buffer
->state
.current_l3_config
= cfg
;
1765 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1767 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1769 /* Flushes are pipelined while invalidations are handled immediately.
1770 * Therefore, if we're flushing anything then we need to schedule a stall
1771 * before any invalidations can happen.
1773 if (bits
& ANV_PIPE_FLUSH_BITS
)
1774 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1776 /* If we're going to do an invalidate and we have a pending CS stall that
1777 * has yet to be resolved, we do the CS stall now.
1779 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1780 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1781 bits
|= ANV_PIPE_CS_STALL_BIT
;
1782 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1785 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1786 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1787 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1788 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1789 pipe
.RenderTargetCacheFlushEnable
=
1790 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1792 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1793 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1794 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1797 * According to the Broadwell documentation, any PIPE_CONTROL with the
1798 * "Command Streamer Stall" bit set must also have another bit set,
1799 * with five different options:
1801 * - Render Target Cache Flush
1802 * - Depth Cache Flush
1803 * - Stall at Pixel Scoreboard
1804 * - Post-Sync Operation
1808 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1809 * mesa and it seems to work fine. The choice is fairly arbitrary.
1811 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1812 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1813 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1814 pipe
.StallAtPixelScoreboard
= true;
1817 /* If a render target flush was emitted, then we can toggle off the bit
1818 * saying that render target writes are ongoing.
1820 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1821 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1823 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1826 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1827 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1829 * "If the VF Cache Invalidation Enable is set to a 1 in a
1830 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1831 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1832 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1835 * This appears to hang Broadwell, so we restrict it to just gen9.
1837 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1838 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1840 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1841 pipe
.StateCacheInvalidationEnable
=
1842 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1843 pipe
.ConstantCacheInvalidationEnable
=
1844 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1845 pipe
.VFCacheInvalidationEnable
=
1846 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1847 pipe
.TextureCacheInvalidationEnable
=
1848 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1849 pipe
.InstructionCacheInvalidateEnable
=
1850 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1852 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1854 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1855 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1856 * “Write Timestamp”.
1858 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1859 pipe
.PostSyncOperation
= WriteImmediateData
;
1861 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1865 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1868 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1871 void genX(CmdPipelineBarrier
)(
1872 VkCommandBuffer commandBuffer
,
1873 VkPipelineStageFlags srcStageMask
,
1874 VkPipelineStageFlags destStageMask
,
1876 uint32_t memoryBarrierCount
,
1877 const VkMemoryBarrier
* pMemoryBarriers
,
1878 uint32_t bufferMemoryBarrierCount
,
1879 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1880 uint32_t imageMemoryBarrierCount
,
1881 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1883 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1885 /* XXX: Right now, we're really dumb and just flush whatever categories
1886 * the app asks for. One of these days we may make this a bit better
1887 * but right now that's all the hardware allows for in most areas.
1889 VkAccessFlags src_flags
= 0;
1890 VkAccessFlags dst_flags
= 0;
1892 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1893 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1894 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1897 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1898 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1899 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1902 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1903 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1904 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1905 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1906 const VkImageSubresourceRange
*range
=
1907 &pImageMemoryBarriers
[i
].subresourceRange
;
1909 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1910 transition_depth_buffer(cmd_buffer
, image
,
1911 pImageMemoryBarriers
[i
].oldLayout
,
1912 pImageMemoryBarriers
[i
].newLayout
);
1913 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1914 VkImageAspectFlags color_aspects
=
1915 anv_image_expand_aspects(image
, range
->aspectMask
);
1916 uint32_t aspect_bit
;
1918 uint32_t base_layer
, layer_count
;
1919 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1921 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1923 base_layer
= range
->baseArrayLayer
;
1924 layer_count
= anv_get_layerCount(image
, range
);
1927 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1928 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1929 range
->baseMipLevel
,
1930 anv_get_levelCount(image
, range
),
1931 base_layer
, layer_count
,
1932 pImageMemoryBarriers
[i
].oldLayout
,
1933 pImageMemoryBarriers
[i
].newLayout
);
1938 cmd_buffer
->state
.pending_pipe_bits
|=
1939 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1940 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1944 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1946 VkShaderStageFlags stages
=
1947 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1949 /* In order to avoid thrash, we assume that vertex and fragment stages
1950 * always exist. In the rare case where one is missing *and* the other
1951 * uses push concstants, this may be suboptimal. However, avoiding stalls
1952 * seems more important.
1954 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1956 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1960 const unsigned push_constant_kb
= 32;
1961 #elif GEN_IS_HASWELL
1962 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1964 const unsigned push_constant_kb
= 16;
1967 const unsigned num_stages
=
1968 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1969 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1971 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1972 * units of 2KB. Incidentally, these are the same platforms that have
1973 * 32KB worth of push constant space.
1975 if (push_constant_kb
== 32)
1976 size_per_stage
&= ~1u;
1978 uint32_t kb_used
= 0;
1979 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1980 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1981 anv_batch_emit(&cmd_buffer
->batch
,
1982 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1983 alloc
._3DCommandSubOpcode
= 18 + i
;
1984 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1985 alloc
.ConstantBufferSize
= push_size
;
1987 kb_used
+= push_size
;
1990 anv_batch_emit(&cmd_buffer
->batch
,
1991 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1992 alloc
.ConstantBufferOffset
= kb_used
;
1993 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1996 cmd_buffer
->state
.push_constant_stages
= stages
;
1998 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2000 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2001 * the next 3DPRIMITIVE command after programming the
2002 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2004 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2005 * pipeline setup, we need to dirty push constants.
2007 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2010 static const struct anv_descriptor
*
2011 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2012 const struct anv_pipeline_binding
*binding
)
2014 assert(binding
->set
< MAX_SETS
);
2015 const struct anv_descriptor_set
*set
=
2016 pipe_state
->descriptors
[binding
->set
];
2017 const uint32_t offset
=
2018 set
->layout
->binding
[binding
->binding
].descriptor_index
;
2019 return &set
->descriptors
[offset
+ binding
->index
];
2023 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2024 const struct anv_pipeline_binding
*binding
)
2026 assert(binding
->set
< MAX_SETS
);
2027 const struct anv_descriptor_set
*set
=
2028 pipe_state
->descriptors
[binding
->set
];
2030 uint32_t dynamic_offset_idx
=
2031 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
2032 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
2035 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
2038 static struct anv_address
2039 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2040 struct anv_descriptor_set
*set
)
2043 /* This is a normal descriptor set */
2044 return (struct anv_address
) {
2045 .bo
= &set
->pool
->bo
,
2046 .offset
= set
->desc_mem
.offset
,
2049 /* This is a push descriptor set. We have to flag it as used on the GPU
2050 * so that the next time we push descriptors, we grab a new memory.
2052 struct anv_push_descriptor_set
*push_set
=
2053 (struct anv_push_descriptor_set
*)set
;
2054 push_set
->set_used_on_gpu
= true;
2056 return (struct anv_address
) {
2057 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2058 .offset
= set
->desc_mem
.offset
,
2064 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2065 gl_shader_stage stage
,
2066 struct anv_state
*bt_state
)
2068 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
2069 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2070 struct anv_cmd_pipeline_state
*pipe_state
;
2071 struct anv_pipeline
*pipeline
;
2072 uint32_t state_offset
;
2075 case MESA_SHADER_COMPUTE
:
2076 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2079 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2082 pipeline
= pipe_state
->pipeline
;
2084 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2085 *bt_state
= (struct anv_state
) { 0, };
2089 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2090 if (map
->surface_count
== 0) {
2091 *bt_state
= (struct anv_state
) { 0, };
2095 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2098 uint32_t *bt_map
= bt_state
->map
;
2100 if (bt_state
->map
== NULL
)
2101 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2103 /* We only use push constant space for images before gen9 */
2104 if (map
->image_param_count
> 0) {
2106 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
2107 if (result
!= VK_SUCCESS
)
2110 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
2114 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2115 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2117 struct anv_state surface_state
;
2119 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2120 /* Color attachment binding */
2121 assert(stage
== MESA_SHADER_FRAGMENT
);
2122 assert(binding
->binding
== 0);
2123 if (binding
->index
< subpass
->color_count
) {
2124 const unsigned att
=
2125 subpass
->color_attachments
[binding
->index
].attachment
;
2127 /* From the Vulkan 1.0.46 spec:
2129 * "If any color or depth/stencil attachments are
2130 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2133 if (att
== VK_ATTACHMENT_UNUSED
) {
2134 surface_state
= cmd_buffer
->state
.null_surface_state
;
2136 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2139 surface_state
= cmd_buffer
->state
.null_surface_state
;
2142 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2144 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2145 struct anv_state surface_state
=
2146 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2148 struct anv_address constant_data
= {
2149 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2150 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2152 unsigned constant_data_size
=
2153 pipeline
->shaders
[stage
]->constant_data_size
;
2155 const enum isl_format format
=
2156 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2157 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2158 surface_state
, format
,
2159 constant_data
, constant_data_size
, 1);
2161 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2162 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2164 } else if (binding
->set
== ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
) {
2165 /* This is always the first binding for compute shaders */
2166 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2167 if (!get_cs_prog_data(pipeline
)->uses_num_work_groups
)
2170 struct anv_state surface_state
=
2171 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2173 const enum isl_format format
=
2174 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2175 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2177 cmd_buffer
->state
.compute
.num_workgroups
,
2179 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2180 add_surface_reloc(cmd_buffer
, surface_state
,
2181 cmd_buffer
->state
.compute
.num_workgroups
);
2183 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2184 /* This is a descriptor set buffer so the set index is actually
2185 * given by binding->binding. (Yes, that's confusing.)
2187 struct anv_descriptor_set
*set
=
2188 pipe_state
->descriptors
[binding
->binding
];
2189 assert(set
->desc_mem
.alloc_size
);
2190 assert(set
->desc_surface_state
.alloc_size
);
2191 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2192 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2193 anv_descriptor_set_address(cmd_buffer
, set
));
2197 const struct anv_descriptor
*desc
=
2198 anv_descriptor_for_binding(pipe_state
, binding
);
2200 switch (desc
->type
) {
2201 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2202 /* Nothing for us to do here */
2205 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2206 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2207 struct anv_surface_state sstate
=
2208 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2209 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2210 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2211 surface_state
= sstate
.state
;
2212 assert(surface_state
.alloc_size
);
2213 add_surface_state_relocs(cmd_buffer
, sstate
);
2216 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2217 assert(stage
== MESA_SHADER_FRAGMENT
);
2218 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2219 /* For depth and stencil input attachments, we treat it like any
2220 * old texture that a user may have bound.
2222 struct anv_surface_state sstate
=
2223 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2224 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2225 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2226 surface_state
= sstate
.state
;
2227 assert(surface_state
.alloc_size
);
2228 add_surface_state_relocs(cmd_buffer
, sstate
);
2230 /* For color input attachments, we create the surface state at
2231 * vkBeginRenderPass time so that we can include aux and clear
2232 * color information.
2234 assert(binding
->input_attachment_index
< subpass
->input_count
);
2235 const unsigned subpass_att
= binding
->input_attachment_index
;
2236 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2237 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2241 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2242 struct anv_surface_state sstate
= (binding
->write_only
)
2243 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2244 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2245 surface_state
= sstate
.state
;
2246 assert(surface_state
.alloc_size
);
2247 add_surface_state_relocs(cmd_buffer
, sstate
);
2248 if (devinfo
->gen
< 9) {
2249 /* We only need the image params on gen8 and earlier. No image
2250 * workarounds that require tiling information are required on
2253 assert(image
< MAX_GEN8_IMAGES
);
2254 struct brw_image_param
*image_param
=
2255 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2258 desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2263 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2264 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2265 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2266 surface_state
= desc
->buffer_view
->surface_state
;
2267 assert(surface_state
.alloc_size
);
2268 add_surface_reloc(cmd_buffer
, surface_state
,
2269 desc
->buffer_view
->address
);
2272 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2273 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2274 /* Compute the offset within the buffer */
2275 uint32_t dynamic_offset
=
2276 dynamic_offset_for_binding(pipe_state
, binding
);
2277 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2278 /* Clamp to the buffer size */
2279 offset
= MIN2(offset
, desc
->buffer
->size
);
2280 /* Clamp the range to the buffer size */
2281 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2283 struct anv_address address
=
2284 anv_address_add(desc
->buffer
->address
, offset
);
2287 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2288 enum isl_format format
=
2289 anv_isl_format_for_descriptor_type(desc
->type
);
2291 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2292 format
, address
, range
, 1);
2293 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2297 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2298 surface_state
= (binding
->write_only
)
2299 ? desc
->buffer_view
->writeonly_storage_surface_state
2300 : desc
->buffer_view
->storage_surface_state
;
2301 assert(surface_state
.alloc_size
);
2302 add_surface_reloc(cmd_buffer
, surface_state
,
2303 desc
->buffer_view
->address
);
2304 if (devinfo
->gen
< 9) {
2305 assert(image
< MAX_GEN8_IMAGES
);
2306 struct brw_image_param
*image_param
=
2307 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2309 *image_param
= desc
->buffer_view
->storage_image_param
;
2314 assert(!"Invalid descriptor type");
2318 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2320 assert(image
== map
->image_param_count
);
2323 /* The PIPE_CONTROL command description says:
2325 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2326 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2327 * Target Cache Flush by enabling this bit. When render target flush
2328 * is set due to new association of BTI, PS Scoreboard Stall bit must
2329 * be set in this packet."
2331 * FINISHME: Currently we shuffle around the surface states in the binding
2332 * table based on if they are getting used or not. So, we've to do below
2333 * pipe control flush for every binding table upload. Make changes so
2334 * that we do it only when we modify render target surface states.
2336 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2337 pc
.RenderTargetCacheFlushEnable
= true;
2338 pc
.StallAtPixelScoreboard
= true;
2346 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2347 gl_shader_stage stage
,
2348 struct anv_state
*state
)
2350 struct anv_cmd_pipeline_state
*pipe_state
=
2351 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2352 &cmd_buffer
->state
.gfx
.base
;
2353 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2355 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2356 *state
= (struct anv_state
) { 0, };
2360 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2361 if (map
->sampler_count
== 0) {
2362 *state
= (struct anv_state
) { 0, };
2366 uint32_t size
= map
->sampler_count
* 16;
2367 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2369 if (state
->map
== NULL
)
2370 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2372 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2373 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2374 const struct anv_descriptor
*desc
=
2375 anv_descriptor_for_binding(pipe_state
, binding
);
2377 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2378 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2381 struct anv_sampler
*sampler
= desc
->sampler
;
2383 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2384 * happens to be zero.
2386 if (sampler
== NULL
)
2389 memcpy(state
->map
+ (s
* 16),
2390 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2397 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2399 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2401 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2402 pipeline
->active_stages
;
2404 VkResult result
= VK_SUCCESS
;
2405 anv_foreach_stage(s
, dirty
) {
2406 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2407 if (result
!= VK_SUCCESS
)
2409 result
= emit_binding_table(cmd_buffer
, s
,
2410 &cmd_buffer
->state
.binding_tables
[s
]);
2411 if (result
!= VK_SUCCESS
)
2415 if (result
!= VK_SUCCESS
) {
2416 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2418 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2419 if (result
!= VK_SUCCESS
)
2422 /* Re-emit state base addresses so we get the new surface state base
2423 * address before we start emitting binding tables etc.
2425 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2427 /* Re-emit all active binding tables */
2428 dirty
|= pipeline
->active_stages
;
2429 anv_foreach_stage(s
, dirty
) {
2430 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2431 if (result
!= VK_SUCCESS
) {
2432 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2435 result
= emit_binding_table(cmd_buffer
, s
,
2436 &cmd_buffer
->state
.binding_tables
[s
]);
2437 if (result
!= VK_SUCCESS
) {
2438 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2444 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2450 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2453 static const uint32_t sampler_state_opcodes
[] = {
2454 [MESA_SHADER_VERTEX
] = 43,
2455 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2456 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2457 [MESA_SHADER_GEOMETRY
] = 46,
2458 [MESA_SHADER_FRAGMENT
] = 47,
2459 [MESA_SHADER_COMPUTE
] = 0,
2462 static const uint32_t binding_table_opcodes
[] = {
2463 [MESA_SHADER_VERTEX
] = 38,
2464 [MESA_SHADER_TESS_CTRL
] = 39,
2465 [MESA_SHADER_TESS_EVAL
] = 40,
2466 [MESA_SHADER_GEOMETRY
] = 41,
2467 [MESA_SHADER_FRAGMENT
] = 42,
2468 [MESA_SHADER_COMPUTE
] = 0,
2471 anv_foreach_stage(s
, stages
) {
2472 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2473 assert(binding_table_opcodes
[s
] > 0);
2475 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2476 anv_batch_emit(&cmd_buffer
->batch
,
2477 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2478 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2479 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2483 /* Always emit binding table pointers if we're asked to, since on SKL
2484 * this is what flushes push constants. */
2485 anv_batch_emit(&cmd_buffer
->batch
,
2486 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2487 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2488 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2494 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2495 VkShaderStageFlags dirty_stages
)
2497 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2498 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2500 static const uint32_t push_constant_opcodes
[] = {
2501 [MESA_SHADER_VERTEX
] = 21,
2502 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2503 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2504 [MESA_SHADER_GEOMETRY
] = 22,
2505 [MESA_SHADER_FRAGMENT
] = 23,
2506 [MESA_SHADER_COMPUTE
] = 0,
2509 VkShaderStageFlags flushed
= 0;
2511 anv_foreach_stage(stage
, dirty_stages
) {
2512 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2513 assert(push_constant_opcodes
[stage
] > 0);
2515 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2516 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2518 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2519 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2520 const struct brw_stage_prog_data
*prog_data
=
2521 pipeline
->shaders
[stage
]->prog_data
;
2522 const struct anv_pipeline_bind_map
*bind_map
=
2523 &pipeline
->shaders
[stage
]->bind_map
;
2525 /* The Skylake PRM contains the following restriction:
2527 * "The driver must ensure The following case does not occur
2528 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2529 * buffer 3 read length equal to zero committed followed by a
2530 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2533 * To avoid this, we program the buffers in the highest slots.
2534 * This way, slot 0 is only used if slot 3 is also used.
2538 for (int i
= 3; i
>= 0; i
--) {
2539 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2540 if (range
->length
== 0)
2543 const unsigned surface
=
2544 prog_data
->binding_table
.ubo_start
+ range
->block
;
2546 assert(surface
<= bind_map
->surface_count
);
2547 const struct anv_pipeline_binding
*binding
=
2548 &bind_map
->surface_to_descriptor
[surface
];
2550 struct anv_address read_addr
;
2552 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2553 struct anv_address constant_data
= {
2554 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2555 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2557 unsigned constant_data_size
=
2558 pipeline
->shaders
[stage
]->constant_data_size
;
2560 read_len
= MIN2(range
->length
,
2561 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2562 read_addr
= anv_address_add(constant_data
,
2564 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2565 /* This is a descriptor set buffer so the set index is
2566 * actually given by binding->binding. (Yes, that's
2569 struct anv_descriptor_set
*set
=
2570 gfx_state
->base
.descriptors
[binding
->binding
];
2571 struct anv_address desc_buffer_addr
=
2572 anv_descriptor_set_address(cmd_buffer
, set
);
2573 const unsigned desc_buffer_size
= set
->desc_mem
.alloc_size
;
2575 read_len
= MIN2(range
->length
,
2576 DIV_ROUND_UP(desc_buffer_size
, 32) - range
->start
);
2577 read_addr
= anv_address_add(desc_buffer_addr
,
2580 const struct anv_descriptor
*desc
=
2581 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2583 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2584 read_len
= MIN2(range
->length
,
2585 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2586 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2589 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2591 uint32_t dynamic_offset
=
2592 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2593 uint32_t buf_offset
=
2594 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2595 uint32_t buf_range
=
2596 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2598 read_len
= MIN2(range
->length
,
2599 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2600 read_addr
= anv_address_add(desc
->buffer
->address
,
2601 buf_offset
+ range
->start
* 32);
2606 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2607 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2612 struct anv_state state
=
2613 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2615 if (state
.alloc_size
> 0) {
2616 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2617 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2618 .offset
= state
.offset
,
2620 c
.ConstantBody
.ReadLength
[n
] =
2621 DIV_ROUND_UP(state
.alloc_size
, 32);
2624 /* For Ivy Bridge, the push constants packets have a different
2625 * rule that would require us to iterate in the other direction
2626 * and possibly mess around with dynamic state base address.
2627 * Don't bother; just emit regular push constants at n = 0.
2629 struct anv_state state
=
2630 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2632 if (state
.alloc_size
> 0) {
2633 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2634 c
.ConstantBody
.ReadLength
[0] =
2635 DIV_ROUND_UP(state
.alloc_size
, 32);
2641 flushed
|= mesa_to_vk_shader_stage(stage
);
2644 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2648 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2650 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2653 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2654 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2655 vb_emit
|= pipeline
->vb_used
;
2657 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2659 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2661 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2664 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2665 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2667 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2668 GENX(3DSTATE_VERTEX_BUFFERS
));
2670 for_each_bit(vb
, vb_emit
) {
2671 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2672 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2674 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2675 .VertexBufferIndex
= vb
,
2677 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2679 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2680 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2683 .AddressModifyEnable
= true,
2684 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2685 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2688 .BufferSize
= buffer
->size
- offset
2690 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2694 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2699 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2702 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2703 /* We don't need any per-buffer dirty tracking because you're not
2704 * allowed to bind different XFB buffers while XFB is enabled.
2706 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2707 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2708 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2709 sob
.SOBufferIndex
= idx
;
2711 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2712 sob
.SOBufferEnable
= true;
2713 sob
.MOCS
= cmd_buffer
->device
->default_mocs
,
2714 sob
.StreamOffsetWriteEnable
= false;
2715 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2717 /* Size is in DWords - 1 */
2718 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2723 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2725 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2729 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2730 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2732 /* The exact descriptor layout is pulled from the pipeline, so we need
2733 * to re-emit binding tables on every pipeline change.
2735 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2737 /* If the pipeline changed, we may need to re-allocate push constant
2740 cmd_buffer_alloc_push_constants(cmd_buffer
);
2744 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2745 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2746 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2748 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2749 * stall needs to be sent just prior to any 3DSTATE_VS,
2750 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2751 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2752 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2753 * PIPE_CONTROL needs to be sent before any combination of VS
2754 * associated 3DSTATE."
2756 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2757 pc
.DepthStallEnable
= true;
2758 pc
.PostSyncOperation
= WriteImmediateData
;
2760 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2765 /* Render targets live in the same binding table as fragment descriptors */
2766 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2767 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2769 /* We emit the binding tables and sampler tables first, then emit push
2770 * constants and then finally emit binding table and sampler table
2771 * pointers. It has to happen in this order, since emitting the binding
2772 * tables may change the push constants (in case of storage images). After
2773 * emitting push constants, on SKL+ we have to emit the corresponding
2774 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2777 if (cmd_buffer
->state
.descriptors_dirty
)
2778 dirty
= flush_descriptor_sets(cmd_buffer
);
2780 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2781 /* Because we're pushing UBOs, we have to push whenever either
2782 * descriptors or push constants is dirty.
2784 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2785 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2786 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2790 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2792 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2793 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2795 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2796 ANV_CMD_DIRTY_PIPELINE
)) {
2797 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2798 pipeline
->depth_clamp_enable
);
2801 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2802 ANV_CMD_DIRTY_RENDER_TARGETS
))
2803 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2805 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2807 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2811 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2812 struct anv_address addr
,
2813 uint32_t size
, uint32_t index
)
2815 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2816 GENX(3DSTATE_VERTEX_BUFFERS
));
2818 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2819 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2820 .VertexBufferIndex
= index
,
2821 .AddressModifyEnable
= true,
2823 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2825 .BufferStartingAddress
= addr
,
2828 .BufferStartingAddress
= addr
,
2829 .EndAddress
= anv_address_add(addr
, size
),
2835 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2836 struct anv_address addr
)
2838 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2842 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2843 uint32_t base_vertex
, uint32_t base_instance
)
2845 struct anv_state id_state
=
2846 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2848 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2849 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2851 struct anv_address addr
= {
2852 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2853 .offset
= id_state
.offset
,
2856 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2860 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2862 struct anv_state state
=
2863 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2865 ((uint32_t *)state
.map
)[0] = draw_index
;
2867 struct anv_address addr
= {
2868 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2869 .offset
= state
.offset
,
2872 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2876 VkCommandBuffer commandBuffer
,
2877 uint32_t vertexCount
,
2878 uint32_t instanceCount
,
2879 uint32_t firstVertex
,
2880 uint32_t firstInstance
)
2882 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2883 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2884 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2886 if (anv_batch_has_error(&cmd_buffer
->batch
))
2889 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2891 if (cmd_buffer
->state
.conditional_render_enabled
)
2892 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2894 if (vs_prog_data
->uses_firstvertex
||
2895 vs_prog_data
->uses_baseinstance
)
2896 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2897 if (vs_prog_data
->uses_drawid
)
2898 emit_draw_index(cmd_buffer
, 0);
2900 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2901 * different views. We need to multiply instanceCount by the view count.
2903 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2905 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2906 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2907 prim
.VertexAccessType
= SEQUENTIAL
;
2908 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2909 prim
.VertexCountPerInstance
= vertexCount
;
2910 prim
.StartVertexLocation
= firstVertex
;
2911 prim
.InstanceCount
= instanceCount
;
2912 prim
.StartInstanceLocation
= firstInstance
;
2913 prim
.BaseVertexLocation
= 0;
2917 void genX(CmdDrawIndexed
)(
2918 VkCommandBuffer commandBuffer
,
2919 uint32_t indexCount
,
2920 uint32_t instanceCount
,
2921 uint32_t firstIndex
,
2922 int32_t vertexOffset
,
2923 uint32_t firstInstance
)
2925 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2926 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2927 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2929 if (anv_batch_has_error(&cmd_buffer
->batch
))
2932 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2934 if (cmd_buffer
->state
.conditional_render_enabled
)
2935 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2937 if (vs_prog_data
->uses_firstvertex
||
2938 vs_prog_data
->uses_baseinstance
)
2939 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2940 if (vs_prog_data
->uses_drawid
)
2941 emit_draw_index(cmd_buffer
, 0);
2943 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2944 * different views. We need to multiply instanceCount by the view count.
2946 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2948 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2949 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2950 prim
.VertexAccessType
= RANDOM
;
2951 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2952 prim
.VertexCountPerInstance
= indexCount
;
2953 prim
.StartVertexLocation
= firstIndex
;
2954 prim
.InstanceCount
= instanceCount
;
2955 prim
.StartInstanceLocation
= firstInstance
;
2956 prim
.BaseVertexLocation
= vertexOffset
;
2960 /* Auto-Draw / Indirect Registers */
2961 #define GEN7_3DPRIM_END_OFFSET 0x2420
2962 #define GEN7_3DPRIM_START_VERTEX 0x2430
2963 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2964 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2965 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2966 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2968 /* MI_MATH only exists on Haswell+ */
2969 #if GEN_IS_HASWELL || GEN_GEN >= 8
2971 /* Emit dwords to multiply GPR0 by N */
2973 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2975 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2977 #define append_alu(opcode, operand1, operand2) \
2978 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2981 unsigned top_bit
= 31 - __builtin_clz(N
);
2982 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2983 /* We get our initial data in GPR0 and we write the final data out to
2984 * GPR0 but we use GPR1 as our scratch register.
2986 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2987 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2989 /* Shift the current value left by 1 */
2990 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2991 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2992 append_alu(MI_ALU_ADD
, 0, 0);
2995 /* Store ACCU to R1 and add R0 to R1 */
2996 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2997 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2998 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2999 append_alu(MI_ALU_ADD
, 0, 0);
3002 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
3009 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
3011 uint32_t num_dwords
;
3012 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
3014 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
3015 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
3018 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3020 void genX(CmdDrawIndirectByteCountEXT
)(
3021 VkCommandBuffer commandBuffer
,
3022 uint32_t instanceCount
,
3023 uint32_t firstInstance
,
3024 VkBuffer counterBuffer
,
3025 VkDeviceSize counterBufferOffset
,
3026 uint32_t counterOffset
,
3027 uint32_t vertexStride
)
3029 #if GEN_IS_HASWELL || GEN_GEN >= 8
3030 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3031 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3032 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3033 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3035 /* firstVertex is always zero for this draw function */
3036 const uint32_t firstVertex
= 0;
3038 if (anv_batch_has_error(&cmd_buffer
->batch
))
3041 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3043 if (vs_prog_data
->uses_firstvertex
||
3044 vs_prog_data
->uses_baseinstance
)
3045 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3046 if (vs_prog_data
->uses_drawid
)
3047 emit_draw_index(cmd_buffer
, 0);
3049 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3050 * different views. We need to multiply instanceCount by the view count.
3052 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3054 struct gen_mi_builder b
;
3055 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3056 struct gen_mi_value count
=
3057 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3058 counterBufferOffset
));
3060 count
= gen_mi_iadd(&b
, count
, gen_mi_imm(-counterOffset
));
3061 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3062 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3064 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3065 gen_mi_imm(firstVertex
));
3066 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3067 gen_mi_imm(instanceCount
));
3068 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3069 gen_mi_imm(firstInstance
));
3070 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3072 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3073 prim
.IndirectParameterEnable
= true;
3074 prim
.VertexAccessType
= SEQUENTIAL
;
3075 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3077 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3081 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3082 struct anv_address addr
,
3085 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3087 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, anv_address_add(addr
, 0));
3089 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3090 if (view_count
> 1) {
3091 #if GEN_IS_HASWELL || GEN_GEN >= 8
3092 emit_lrm(batch
, CS_GPR(0), anv_address_add(addr
, 4));
3093 emit_mul_gpr0(batch
, view_count
);
3094 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
3096 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3097 "MI_MATH is not supported on Ivy Bridge");
3098 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
3101 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
3104 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, anv_address_add(addr
, 8));
3107 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, anv_address_add(addr
, 12));
3108 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 16));
3110 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 12));
3111 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
3115 void genX(CmdDrawIndirect
)(
3116 VkCommandBuffer commandBuffer
,
3118 VkDeviceSize offset
,
3122 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3123 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3124 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3125 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3127 if (anv_batch_has_error(&cmd_buffer
->batch
))
3130 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3132 if (cmd_buffer
->state
.conditional_render_enabled
)
3133 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3135 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3136 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3138 if (vs_prog_data
->uses_firstvertex
||
3139 vs_prog_data
->uses_baseinstance
)
3140 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3141 if (vs_prog_data
->uses_drawid
)
3142 emit_draw_index(cmd_buffer
, i
);
3144 load_indirect_parameters(cmd_buffer
, draw
, false);
3146 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3147 prim
.IndirectParameterEnable
= true;
3148 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3149 prim
.VertexAccessType
= SEQUENTIAL
;
3150 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3157 void genX(CmdDrawIndexedIndirect
)(
3158 VkCommandBuffer commandBuffer
,
3160 VkDeviceSize offset
,
3164 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3165 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3166 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3167 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3169 if (anv_batch_has_error(&cmd_buffer
->batch
))
3172 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3174 if (cmd_buffer
->state
.conditional_render_enabled
)
3175 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3177 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3178 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3180 /* TODO: We need to stomp base vertex to 0 somehow */
3181 if (vs_prog_data
->uses_firstvertex
||
3182 vs_prog_data
->uses_baseinstance
)
3183 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3184 if (vs_prog_data
->uses_drawid
)
3185 emit_draw_index(cmd_buffer
, i
);
3187 load_indirect_parameters(cmd_buffer
, draw
, true);
3189 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3190 prim
.IndirectParameterEnable
= true;
3191 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3192 prim
.VertexAccessType
= RANDOM
;
3193 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3200 #define TMP_DRAW_COUNT_REG MI_ALU_REG14
3203 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3204 struct anv_address count_address
,
3205 const bool conditional_render_enabled
)
3207 if (conditional_render_enabled
) {
3208 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3209 emit_lrm(&cmd_buffer
->batch
, CS_GPR(TMP_DRAW_COUNT_REG
), count_address
);
3210 emit_lri(&cmd_buffer
->batch
, CS_GPR(TMP_DRAW_COUNT_REG
) + 4, 0);
3213 /* Upload the current draw count from the draw parameters buffer to
3214 * MI_PREDICATE_SRC0.
3216 emit_lrm(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, count_address
);
3217 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
3219 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
3224 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3225 uint32_t draw_index
)
3227 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3228 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, draw_index
);
3230 if (draw_index
== 0) {
3231 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3232 mip
.LoadOperation
= LOAD_LOADINV
;
3233 mip
.CombineOperation
= COMBINE_SET
;
3234 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3237 /* While draw_index < draw_count the predicate's result will be
3238 * (draw_index == draw_count) ^ TRUE = TRUE
3239 * When draw_index == draw_count the result is
3240 * (TRUE) ^ TRUE = FALSE
3241 * After this all results will be:
3242 * (FALSE) ^ FALSE = FALSE
3244 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3245 mip
.LoadOperation
= LOAD_LOAD
;
3246 mip
.CombineOperation
= COMBINE_XOR
;
3247 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3252 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3254 emit_draw_count_predicate_with_conditional_render(
3255 struct anv_cmd_buffer
*cmd_buffer
,
3256 uint32_t draw_index
)
3258 const int draw_index_reg
= MI_ALU_REG0
;
3259 const int tmp_result_reg
= MI_ALU_REG1
;
3261 emit_lri(&cmd_buffer
->batch
, CS_GPR(draw_index_reg
), draw_index
);
3262 emit_lri(&cmd_buffer
->batch
, CS_GPR(draw_index_reg
) + 4, 0);
3265 /* Compute (draw_index < draw_count).
3266 * We do this by subtracting and storing the carry bit.
3268 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 9, GENX(MI_MATH
));
3269 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, draw_index_reg
);
3270 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, TMP_DRAW_COUNT_REG
);
3271 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
3272 dw
[4] = mi_alu(MI_ALU_STORE
, tmp_result_reg
, MI_ALU_CF
);
3274 dw
[5] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, tmp_result_reg
);
3275 dw
[6] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, ANV_PREDICATE_RESULT_REG
);
3276 dw
[7] = mi_alu(MI_ALU_AND
, 0, 0);
3277 dw
[8] = mi_alu(MI_ALU_STORE
, tmp_result_reg
, MI_ALU_ACCU
);
3280 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_RESULT
, CS_GPR(tmp_result_reg
));
3282 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3283 * so we emit MI_PREDICATE to set it.
3286 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(tmp_result_reg
));
3287 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
3288 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
3289 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
3291 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3292 mip
.LoadOperation
= LOAD_LOADINV
;
3293 mip
.CombineOperation
= COMBINE_SET
;
3294 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3300 void genX(CmdDrawIndirectCountKHR
)(
3301 VkCommandBuffer commandBuffer
,
3303 VkDeviceSize offset
,
3304 VkBuffer _countBuffer
,
3305 VkDeviceSize countBufferOffset
,
3306 uint32_t maxDrawCount
,
3309 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3310 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3311 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3312 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3313 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3314 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3316 if (anv_batch_has_error(&cmd_buffer
->batch
))
3319 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3321 struct anv_address count_address
=
3322 anv_address_add(count_buffer
->address
, countBufferOffset
);
3324 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3325 cmd_state
->conditional_render_enabled
);
3327 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3328 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3330 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3331 if (cmd_state
->conditional_render_enabled
) {
3332 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3334 emit_draw_count_predicate(cmd_buffer
, i
);
3337 emit_draw_count_predicate(cmd_buffer
, i
);
3340 if (vs_prog_data
->uses_firstvertex
||
3341 vs_prog_data
->uses_baseinstance
)
3342 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3343 if (vs_prog_data
->uses_drawid
)
3344 emit_draw_index(cmd_buffer
, i
);
3346 load_indirect_parameters(cmd_buffer
, draw
, false);
3348 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3349 prim
.IndirectParameterEnable
= true;
3350 prim
.PredicateEnable
= true;
3351 prim
.VertexAccessType
= SEQUENTIAL
;
3352 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3359 void genX(CmdDrawIndexedIndirectCountKHR
)(
3360 VkCommandBuffer commandBuffer
,
3362 VkDeviceSize offset
,
3363 VkBuffer _countBuffer
,
3364 VkDeviceSize countBufferOffset
,
3365 uint32_t maxDrawCount
,
3368 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3369 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3370 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3371 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3372 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3373 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3375 if (anv_batch_has_error(&cmd_buffer
->batch
))
3378 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3380 struct anv_address count_address
=
3381 anv_address_add(count_buffer
->address
, countBufferOffset
);
3383 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3384 cmd_state
->conditional_render_enabled
);
3386 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3387 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3389 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3390 if (cmd_state
->conditional_render_enabled
) {
3391 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3393 emit_draw_count_predicate(cmd_buffer
, i
);
3396 emit_draw_count_predicate(cmd_buffer
, i
);
3399 /* TODO: We need to stomp base vertex to 0 somehow */
3400 if (vs_prog_data
->uses_firstvertex
||
3401 vs_prog_data
->uses_baseinstance
)
3402 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3403 if (vs_prog_data
->uses_drawid
)
3404 emit_draw_index(cmd_buffer
, i
);
3406 load_indirect_parameters(cmd_buffer
, draw
, true);
3408 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3409 prim
.IndirectParameterEnable
= true;
3410 prim
.PredicateEnable
= true;
3411 prim
.VertexAccessType
= RANDOM
;
3412 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3419 void genX(CmdBeginTransformFeedbackEXT
)(
3420 VkCommandBuffer commandBuffer
,
3421 uint32_t firstCounterBuffer
,
3422 uint32_t counterBufferCount
,
3423 const VkBuffer
* pCounterBuffers
,
3424 const VkDeviceSize
* pCounterBufferOffsets
)
3426 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3428 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3429 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3430 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3432 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3434 * "Ssoftware must ensure that no HW stream output operations can be in
3435 * process or otherwise pending at the point that the MI_LOAD/STORE
3436 * commands are processed. This will likely require a pipeline flush."
3438 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3439 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3441 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3442 /* If we have a counter buffer, this is a resume so we need to load the
3443 * value into the streamout offset register. Otherwise, this is a begin
3444 * and we need to reset it to zero.
3446 if (pCounterBuffers
&&
3447 idx
>= firstCounterBuffer
&&
3448 idx
- firstCounterBuffer
< counterBufferCount
&&
3449 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3450 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3451 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3452 uint64_t offset
= pCounterBufferOffsets
?
3453 pCounterBufferOffsets
[cb_idx
] : 0;
3455 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3456 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3457 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3461 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3462 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3468 cmd_buffer
->state
.xfb_enabled
= true;
3469 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3472 void genX(CmdEndTransformFeedbackEXT
)(
3473 VkCommandBuffer commandBuffer
,
3474 uint32_t firstCounterBuffer
,
3475 uint32_t counterBufferCount
,
3476 const VkBuffer
* pCounterBuffers
,
3477 const VkDeviceSize
* pCounterBufferOffsets
)
3479 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3481 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3482 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3483 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3485 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3487 * "Ssoftware must ensure that no HW stream output operations can be in
3488 * process or otherwise pending at the point that the MI_LOAD/STORE
3489 * commands are processed. This will likely require a pipeline flush."
3491 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3492 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3494 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3495 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3497 /* If we have a counter buffer, this is a resume so we need to load the
3498 * value into the streamout offset register. Otherwise, this is a begin
3499 * and we need to reset it to zero.
3501 if (pCounterBuffers
&&
3502 cb_idx
< counterBufferCount
&&
3503 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3504 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3505 uint64_t offset
= pCounterBufferOffsets
?
3506 pCounterBufferOffsets
[cb_idx
] : 0;
3508 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3509 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3511 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3516 cmd_buffer
->state
.xfb_enabled
= false;
3517 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3521 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3523 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3524 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3527 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3528 if (result
!= VK_SUCCESS
) {
3529 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3531 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3532 if (result
!= VK_SUCCESS
)
3535 /* Re-emit state base addresses so we get the new surface state base
3536 * address before we start emitting binding tables etc.
3538 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3540 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3541 if (result
!= VK_SUCCESS
) {
3542 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3547 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3548 if (result
!= VK_SUCCESS
) {
3549 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3553 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3554 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3555 .BindingTablePointer
= surfaces
.offset
,
3556 .SamplerStatePointer
= samplers
.offset
,
3558 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3560 struct anv_state state
=
3561 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3562 pipeline
->interface_descriptor_data
,
3563 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3566 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3567 anv_batch_emit(&cmd_buffer
->batch
,
3568 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3569 mid
.InterfaceDescriptorTotalLength
= size
;
3570 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3577 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3579 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3580 MAYBE_UNUSED VkResult result
;
3582 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3584 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3586 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3588 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3589 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3591 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3592 * the only bits that are changed are scoreboard related: Scoreboard
3593 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3594 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3597 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3598 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3600 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3603 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3604 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3605 /* FIXME: figure out descriptors for gen7 */
3606 result
= flush_compute_descriptor_set(cmd_buffer
);
3607 if (result
!= VK_SUCCESS
)
3610 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3613 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3614 struct anv_state push_state
=
3615 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3617 if (push_state
.alloc_size
) {
3618 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3619 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3620 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3624 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3627 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3629 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3635 verify_cmd_parser(const struct anv_device
*device
,
3636 int required_version
,
3637 const char *function
)
3639 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3640 return vk_errorf(device
->instance
, device
->instance
,
3641 VK_ERROR_FEATURE_NOT_PRESENT
,
3642 "cmd parser version %d is required for %s",
3643 required_version
, function
);
3652 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3653 uint32_t baseGroupX
,
3654 uint32_t baseGroupY
,
3655 uint32_t baseGroupZ
)
3657 if (anv_batch_has_error(&cmd_buffer
->batch
))
3661 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3662 base_work_group_id
);
3663 if (result
!= VK_SUCCESS
) {
3664 cmd_buffer
->batch
.status
= result
;
3668 struct anv_push_constants
*push
=
3669 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3670 if (push
->base_work_group_id
[0] != baseGroupX
||
3671 push
->base_work_group_id
[1] != baseGroupY
||
3672 push
->base_work_group_id
[2] != baseGroupZ
) {
3673 push
->base_work_group_id
[0] = baseGroupX
;
3674 push
->base_work_group_id
[1] = baseGroupY
;
3675 push
->base_work_group_id
[2] = baseGroupZ
;
3677 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3681 void genX(CmdDispatch
)(
3682 VkCommandBuffer commandBuffer
,
3687 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3690 void genX(CmdDispatchBase
)(
3691 VkCommandBuffer commandBuffer
,
3692 uint32_t baseGroupX
,
3693 uint32_t baseGroupY
,
3694 uint32_t baseGroupZ
,
3695 uint32_t groupCountX
,
3696 uint32_t groupCountY
,
3697 uint32_t groupCountZ
)
3699 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3700 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3701 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3703 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3704 baseGroupY
, baseGroupZ
);
3706 if (anv_batch_has_error(&cmd_buffer
->batch
))
3709 if (prog_data
->uses_num_work_groups
) {
3710 struct anv_state state
=
3711 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3712 uint32_t *sizes
= state
.map
;
3713 sizes
[0] = groupCountX
;
3714 sizes
[1] = groupCountY
;
3715 sizes
[2] = groupCountZ
;
3716 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3717 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3718 .offset
= state
.offset
,
3722 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3724 if (cmd_buffer
->state
.conditional_render_enabled
)
3725 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3727 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3728 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3729 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3730 ggw
.ThreadDepthCounterMaximum
= 0;
3731 ggw
.ThreadHeightCounterMaximum
= 0;
3732 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3733 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3734 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3735 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3736 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3737 ggw
.BottomExecutionMask
= 0xffffffff;
3740 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3743 #define GPGPU_DISPATCHDIMX 0x2500
3744 #define GPGPU_DISPATCHDIMY 0x2504
3745 #define GPGPU_DISPATCHDIMZ 0x2508
3747 void genX(CmdDispatchIndirect
)(
3748 VkCommandBuffer commandBuffer
,
3750 VkDeviceSize offset
)
3752 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3753 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3754 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3755 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3756 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3757 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3759 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3762 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3763 * indirect dispatch registers to be written.
3765 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3766 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3770 if (prog_data
->uses_num_work_groups
)
3771 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3773 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3775 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, anv_address_add(addr
, 0));
3776 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, anv_address_add(addr
, 4));
3777 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, anv_address_add(addr
, 8));
3780 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3781 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3782 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3783 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3785 /* Load compute_dispatch_indirect_x_size into SRC0 */
3786 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 0));
3788 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3789 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3790 mip
.LoadOperation
= LOAD_LOAD
;
3791 mip
.CombineOperation
= COMBINE_SET
;
3792 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3795 /* Load compute_dispatch_indirect_y_size into SRC0 */
3796 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 4));
3798 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3799 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3800 mip
.LoadOperation
= LOAD_LOAD
;
3801 mip
.CombineOperation
= COMBINE_OR
;
3802 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3805 /* Load compute_dispatch_indirect_z_size into SRC0 */
3806 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 8));
3808 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3809 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3810 mip
.LoadOperation
= LOAD_LOAD
;
3811 mip
.CombineOperation
= COMBINE_OR
;
3812 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3815 /* predicate = !predicate; */
3816 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3817 mip
.LoadOperation
= LOAD_LOADINV
;
3818 mip
.CombineOperation
= COMBINE_OR
;
3819 mip
.CompareOperation
= COMPARE_FALSE
;
3823 if (cmd_buffer
->state
.conditional_render_enabled
) {
3824 emit_lrr(batch
, MI_PREDICATE_SRC0
, CS_GPR(ANV_PREDICATE_RESULT_REG
));
3825 /* predicate &= !(conditional_rendering_predicate == 0); */
3826 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3827 mip
.LoadOperation
= LOAD_LOADINV
;
3828 mip
.CombineOperation
= COMBINE_AND
;
3829 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3834 #else /* GEN_GEN > 7 */
3835 if (cmd_buffer
->state
.conditional_render_enabled
)
3836 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3839 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3840 ggw
.IndirectParameterEnable
= true;
3841 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3842 cmd_buffer
->state
.conditional_render_enabled
;
3843 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3844 ggw
.ThreadDepthCounterMaximum
= 0;
3845 ggw
.ThreadHeightCounterMaximum
= 0;
3846 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3847 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3848 ggw
.BottomExecutionMask
= 0xffffffff;
3851 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3855 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3858 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3860 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3863 #if GEN_GEN >= 8 && GEN_GEN < 10
3864 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3866 * Software must clear the COLOR_CALC_STATE Valid field in
3867 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3868 * with Pipeline Select set to GPGPU.
3870 * The internal hardware docs recommend the same workaround for Gen9
3873 if (pipeline
== GPGPU
)
3874 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3877 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3878 * PIPELINE_SELECT [DevBWR+]":
3882 * Software must ensure all the write caches are flushed through a
3883 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3884 * command to invalidate read only caches prior to programming
3885 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3887 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3888 pc
.RenderTargetCacheFlushEnable
= true;
3889 pc
.DepthCacheFlushEnable
= true;
3890 pc
.DCFlushEnable
= true;
3891 pc
.PostSyncOperation
= NoWrite
;
3892 pc
.CommandStreamerStallEnable
= true;
3895 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3896 pc
.TextureCacheInvalidationEnable
= true;
3897 pc
.ConstantCacheInvalidationEnable
= true;
3898 pc
.StateCacheInvalidationEnable
= true;
3899 pc
.InstructionCacheInvalidateEnable
= true;
3900 pc
.PostSyncOperation
= NoWrite
;
3903 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3907 ps
.PipelineSelection
= pipeline
;
3911 if (devinfo
->is_geminilake
) {
3914 * "This chicken bit works around a hardware issue with barrier logic
3915 * encountered when switching between GPGPU and 3D pipelines. To
3916 * workaround the issue, this mode bit should be set after a pipeline
3920 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3922 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3923 : GLK_BARRIER_MODE_3D_HULL
,
3924 .GLKBarrierModeMask
= 1);
3925 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3929 cmd_buffer
->state
.current_pipeline
= pipeline
;
3933 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3935 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3939 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3941 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3945 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3950 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3952 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3953 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3954 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3955 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3956 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3957 * Depth Flush Bit set, followed by another pipelined depth stall
3958 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3959 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3960 * via a preceding MI_FLUSH)."
3962 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3963 pipe
.DepthStallEnable
= true;
3965 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3966 pipe
.DepthCacheFlushEnable
= true;
3968 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3969 pipe
.DepthStallEnable
= true;
3974 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3976 struct anv_device
*device
= cmd_buffer
->device
;
3977 const struct anv_image_view
*iview
=
3978 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3979 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3981 /* FIXME: Width and Height are wrong */
3983 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3985 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3986 device
->isl_dev
.ds
.size
/ 4);
3990 struct isl_depth_stencil_hiz_emit_info info
= { };
3993 info
.view
= &iview
->planes
[0].isl
;
3995 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3996 uint32_t depth_plane
=
3997 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3998 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4000 info
.depth_surf
= &surface
->isl
;
4002 info
.depth_address
=
4003 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4004 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4005 image
->planes
[depth_plane
].address
.bo
,
4006 image
->planes
[depth_plane
].address
.offset
+
4009 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4012 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4013 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4014 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
4015 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4018 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4019 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4020 image
->planes
[depth_plane
].address
.bo
,
4021 image
->planes
[depth_plane
].address
.offset
+
4022 image
->planes
[depth_plane
].aux_surface
.offset
);
4024 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4028 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4029 uint32_t stencil_plane
=
4030 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4031 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4033 info
.stencil_surf
= &surface
->isl
;
4035 info
.stencil_address
=
4036 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4037 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4038 image
->planes
[stencil_plane
].address
.bo
,
4039 image
->planes
[stencil_plane
].address
.offset
+
4042 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4045 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4047 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
4051 * This ANDs the view mask of the current subpass with the pending clear
4052 * views in the attachment to get the mask of views active in the subpass
4053 * that still need to be cleared.
4055 static inline uint32_t
4056 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4057 const struct anv_attachment_state
*att_state
)
4059 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4063 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4064 const struct anv_attachment_state
*att_state
)
4066 if (!cmd_state
->subpass
->view_mask
)
4069 uint32_t pending_clear_mask
=
4070 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4072 return pending_clear_mask
& 1;
4076 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4079 const uint32_t last_subpass_idx
=
4080 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4081 const struct anv_subpass
*last_subpass
=
4082 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4083 return last_subpass
== cmd_state
->subpass
;
4087 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4088 uint32_t subpass_id
)
4090 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4091 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4092 cmd_state
->subpass
= subpass
;
4094 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4096 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4097 * different views. If the client asks for instancing, we need to use the
4098 * Instance Data Step Rate to ensure that we repeat the client's
4099 * per-instance data once for each view. Since this bit is in
4100 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4104 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4106 /* It is possible to start a render pass with an old pipeline. Because the
4107 * render pass and subpass index are both baked into the pipeline, this is
4108 * highly unlikely. In order to do so, it requires that you have a render
4109 * pass with a single subpass and that you use that render pass twice
4110 * back-to-back and use the same pipeline at the start of the second render
4111 * pass as at the end of the first. In order to avoid unpredictable issues
4112 * with this edge case, we just dirty the pipeline at the start of every
4115 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4117 /* Accumulate any subpass flushes that need to happen before the subpass */
4118 cmd_buffer
->state
.pending_pipe_bits
|=
4119 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4121 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4122 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4124 bool is_multiview
= subpass
->view_mask
!= 0;
4126 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4127 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4128 if (a
== VK_ATTACHMENT_UNUSED
)
4131 assert(a
< cmd_state
->pass
->attachment_count
);
4132 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4134 struct anv_image_view
*iview
= fb
->attachments
[a
];
4135 const struct anv_image
*image
= iview
->image
;
4137 /* A resolve is necessary before use as an input attachment if the clear
4138 * color or auxiliary buffer usage isn't supported by the sampler.
4140 const bool input_needs_resolve
=
4141 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4142 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4144 VkImageLayout target_layout
;
4145 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4146 !input_needs_resolve
) {
4147 /* Layout transitions before the final only help to enable sampling
4148 * as an input attachment. If the input attachment supports sampling
4149 * using the auxiliary surface, we can skip such transitions by
4150 * making the target layout one that is CCS-aware.
4152 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4154 target_layout
= subpass
->attachments
[i
].layout
;
4157 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4158 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4160 uint32_t base_layer
, layer_count
;
4161 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4163 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4164 iview
->planes
[0].isl
.base_level
);
4166 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4167 layer_count
= fb
->layers
;
4170 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4171 iview
->planes
[0].isl
.base_level
, 1,
4172 base_layer
, layer_count
,
4173 att_state
->current_layout
, target_layout
);
4174 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4175 transition_depth_buffer(cmd_buffer
, image
,
4176 att_state
->current_layout
, target_layout
);
4177 att_state
->aux_usage
=
4178 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4179 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4181 att_state
->current_layout
= target_layout
;
4183 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4184 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4186 /* Multi-planar images are not supported as attachments */
4187 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4188 assert(image
->n_planes
== 1);
4190 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4191 uint32_t clear_layer_count
= fb
->layers
;
4193 if (att_state
->fast_clear
&&
4194 do_first_layer_clear(cmd_state
, att_state
)) {
4195 /* We only support fast-clears on the first layer */
4196 assert(iview
->planes
[0].isl
.base_level
== 0);
4197 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4199 union isl_color_value clear_color
= {};
4200 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4201 if (iview
->image
->samples
== 1) {
4202 anv_image_ccs_op(cmd_buffer
, image
,
4203 iview
->planes
[0].isl
.format
,
4204 VK_IMAGE_ASPECT_COLOR_BIT
,
4205 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4209 anv_image_mcs_op(cmd_buffer
, image
,
4210 iview
->planes
[0].isl
.format
,
4211 VK_IMAGE_ASPECT_COLOR_BIT
,
4212 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4217 clear_layer_count
--;
4219 att_state
->pending_clear_views
&= ~1;
4221 if (att_state
->clear_color_is_zero
) {
4222 /* This image has the auxiliary buffer enabled. We can mark the
4223 * subresource as not needing a resolve because the clear color
4224 * will match what's in every RENDER_SURFACE_STATE object when
4225 * it's being used for sampling.
4227 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4228 VK_IMAGE_ASPECT_COLOR_BIT
,
4229 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4231 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4232 VK_IMAGE_ASPECT_COLOR_BIT
,
4233 ANV_FAST_CLEAR_ANY
);
4237 /* From the VkFramebufferCreateInfo spec:
4239 * "If the render pass uses multiview, then layers must be one and each
4240 * attachment requires a number of layers that is greater than the
4241 * maximum bit index set in the view mask in the subpasses in which it
4244 * So if multiview is active we ignore the number of layers in the
4245 * framebuffer and instead we honor the view mask from the subpass.
4248 assert(image
->n_planes
== 1);
4249 uint32_t pending_clear_mask
=
4250 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4253 for_each_bit(layer_idx
, pending_clear_mask
) {
4255 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4257 anv_image_clear_color(cmd_buffer
, image
,
4258 VK_IMAGE_ASPECT_COLOR_BIT
,
4259 att_state
->aux_usage
,
4260 iview
->planes
[0].isl
.format
,
4261 iview
->planes
[0].isl
.swizzle
,
4262 iview
->planes
[0].isl
.base_level
,
4265 vk_to_isl_color(att_state
->clear_value
.color
));
4268 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4269 } else if (clear_layer_count
> 0) {
4270 assert(image
->n_planes
== 1);
4271 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4272 att_state
->aux_usage
,
4273 iview
->planes
[0].isl
.format
,
4274 iview
->planes
[0].isl
.swizzle
,
4275 iview
->planes
[0].isl
.base_level
,
4276 base_clear_layer
, clear_layer_count
,
4278 vk_to_isl_color(att_state
->clear_value
.color
));
4280 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4281 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4282 if (att_state
->fast_clear
&& !is_multiview
) {
4283 /* We currently only support HiZ for single-layer images */
4284 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4285 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4286 assert(iview
->planes
[0].isl
.base_level
== 0);
4287 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4288 assert(fb
->layers
== 1);
4291 anv_image_hiz_clear(cmd_buffer
, image
,
4292 att_state
->pending_clear_aspects
,
4293 iview
->planes
[0].isl
.base_level
,
4294 iview
->planes
[0].isl
.base_array_layer
,
4295 fb
->layers
, render_area
,
4296 att_state
->clear_value
.depthStencil
.stencil
);
4297 } else if (is_multiview
) {
4298 uint32_t pending_clear_mask
=
4299 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4302 for_each_bit(layer_idx
, pending_clear_mask
) {
4304 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4306 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4307 att_state
->pending_clear_aspects
,
4308 att_state
->aux_usage
,
4309 iview
->planes
[0].isl
.base_level
,
4312 att_state
->clear_value
.depthStencil
.depth
,
4313 att_state
->clear_value
.depthStencil
.stencil
);
4316 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4318 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4319 att_state
->pending_clear_aspects
,
4320 att_state
->aux_usage
,
4321 iview
->planes
[0].isl
.base_level
,
4322 iview
->planes
[0].isl
.base_array_layer
,
4323 fb
->layers
, render_area
,
4324 att_state
->clear_value
.depthStencil
.depth
,
4325 att_state
->clear_value
.depthStencil
.stencil
);
4328 assert(att_state
->pending_clear_aspects
== 0);
4332 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4333 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4334 iview
->planes
[0].isl
.base_level
== 0 &&
4335 iview
->planes
[0].isl
.base_array_layer
== 0) {
4336 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4337 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4338 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4339 false /* copy to ss */);
4342 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4343 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4344 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4345 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4346 false /* copy to ss */);
4350 if (subpass
->attachments
[i
].usage
==
4351 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4352 /* We assume that if we're starting a subpass, we're going to do some
4353 * rendering so we may end up with compressed data.
4355 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4356 VK_IMAGE_ASPECT_COLOR_BIT
,
4357 att_state
->aux_usage
,
4358 iview
->planes
[0].isl
.base_level
,
4359 iview
->planes
[0].isl
.base_array_layer
,
4361 } else if (subpass
->attachments
[i
].usage
==
4362 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4363 /* We may be writing depth or stencil so we need to mark the surface.
4364 * Unfortunately, there's no way to know at this point whether the
4365 * depth or stencil tests used will actually write to the surface.
4367 * Even though stencil may be plane 1, it always shares a base_level
4370 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4371 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4372 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4373 VK_IMAGE_ASPECT_DEPTH_BIT
,
4374 att_state
->aux_usage
,
4375 ds_view
->base_level
,
4376 ds_view
->base_array_layer
,
4379 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4380 /* Even though stencil may be plane 1, it always shares a
4381 * base_level with depth.
4383 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4384 VK_IMAGE_ASPECT_STENCIL_BIT
,
4386 ds_view
->base_level
,
4387 ds_view
->base_array_layer
,
4392 /* If multiview is enabled, then we are only done clearing when we no
4393 * longer have pending layers to clear, or when we have processed the
4394 * last subpass that uses this attachment.
4396 if (!is_multiview
||
4397 att_state
->pending_clear_views
== 0 ||
4398 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4399 att_state
->pending_clear_aspects
= 0;
4402 att_state
->pending_load_aspects
= 0;
4405 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4408 static enum blorp_filter
4409 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4412 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4413 return BLORP_FILTER_SAMPLE_0
;
4414 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4415 return BLORP_FILTER_AVERAGE
;
4416 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4417 return BLORP_FILTER_MIN_SAMPLE
;
4418 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4419 return BLORP_FILTER_MAX_SAMPLE
;
4421 return BLORP_FILTER_NONE
;
4426 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4428 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4429 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4430 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4431 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4433 if (subpass
->has_color_resolve
) {
4434 /* We are about to do some MSAA resolves. We need to flush so that the
4435 * result of writes to the MSAA color attachments show up in the sampler
4436 * when we blit to the single-sampled resolve target.
4438 cmd_buffer
->state
.pending_pipe_bits
|=
4439 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4440 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4442 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4443 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4444 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4446 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4449 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4450 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4452 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4453 /* From the Vulkan 1.0 spec:
4455 * If the first use of an attachment in a render pass is as a
4456 * resolve attachment, then the loadOp is effectively ignored
4457 * as the resolve is guaranteed to overwrite all pixels in the
4460 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4463 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4464 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4466 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4468 enum isl_aux_usage src_aux_usage
=
4469 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4470 enum isl_aux_usage dst_aux_usage
=
4471 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4473 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4474 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4476 anv_image_msaa_resolve(cmd_buffer
,
4477 src_iview
->image
, src_aux_usage
,
4478 src_iview
->planes
[0].isl
.base_level
,
4479 src_iview
->planes
[0].isl
.base_array_layer
,
4480 dst_iview
->image
, dst_aux_usage
,
4481 dst_iview
->planes
[0].isl
.base_level
,
4482 dst_iview
->planes
[0].isl
.base_array_layer
,
4483 VK_IMAGE_ASPECT_COLOR_BIT
,
4484 render_area
.offset
.x
, render_area
.offset
.y
,
4485 render_area
.offset
.x
, render_area
.offset
.y
,
4486 render_area
.extent
.width
,
4487 render_area
.extent
.height
,
4488 fb
->layers
, BLORP_FILTER_NONE
);
4492 if (subpass
->ds_resolve_attachment
) {
4493 /* We are about to do some MSAA resolves. We need to flush so that the
4494 * result of writes to the MSAA depth attachments show up in the sampler
4495 * when we blit to the single-sampled resolve target.
4497 cmd_buffer
->state
.pending_pipe_bits
|=
4498 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4499 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4501 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4502 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4504 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4505 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4507 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4508 /* From the Vulkan 1.0 spec:
4510 * If the first use of an attachment in a render pass is as a
4511 * resolve attachment, then the loadOp is effectively ignored
4512 * as the resolve is guaranteed to overwrite all pixels in the
4515 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4518 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4519 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4521 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4523 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4524 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4526 struct anv_attachment_state
*src_state
=
4527 &cmd_state
->attachments
[src_att
];
4528 struct anv_attachment_state
*dst_state
=
4529 &cmd_state
->attachments
[dst_att
];
4531 /* MSAA resolves sample from the source attachment. Transition the
4532 * depth attachment first to get rid of any HiZ that we may not be
4535 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4536 src_state
->current_layout
,
4537 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4538 src_state
->aux_usage
=
4539 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4540 VK_IMAGE_ASPECT_DEPTH_BIT
,
4541 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4542 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4544 /* MSAA resolves write to the resolve attachment as if it were any
4545 * other transfer op. Transition the resolve attachment accordingly.
4547 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4549 /* If our render area is the entire size of the image, we're going to
4550 * blow it all away so we can claim the initial layout is UNDEFINED
4551 * and we'll get a HiZ ambiguate instead of a resolve.
4553 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4554 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4555 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4556 render_area
.extent
.height
== dst_iview
->extent
.height
)
4557 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4559 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4561 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4562 dst_state
->aux_usage
=
4563 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4564 VK_IMAGE_ASPECT_DEPTH_BIT
,
4565 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4566 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4568 enum blorp_filter filter
=
4569 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4571 anv_image_msaa_resolve(cmd_buffer
,
4572 src_iview
->image
, src_state
->aux_usage
,
4573 src_iview
->planes
[0].isl
.base_level
,
4574 src_iview
->planes
[0].isl
.base_array_layer
,
4575 dst_iview
->image
, dst_state
->aux_usage
,
4576 dst_iview
->planes
[0].isl
.base_level
,
4577 dst_iview
->planes
[0].isl
.base_array_layer
,
4578 VK_IMAGE_ASPECT_DEPTH_BIT
,
4579 render_area
.offset
.x
, render_area
.offset
.y
,
4580 render_area
.offset
.x
, render_area
.offset
.y
,
4581 render_area
.extent
.width
,
4582 render_area
.extent
.height
,
4583 fb
->layers
, filter
);
4586 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4587 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4589 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4590 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4592 enum blorp_filter filter
=
4593 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4595 anv_image_msaa_resolve(cmd_buffer
,
4596 src_iview
->image
, src_aux_usage
,
4597 src_iview
->planes
[0].isl
.base_level
,
4598 src_iview
->planes
[0].isl
.base_array_layer
,
4599 dst_iview
->image
, dst_aux_usage
,
4600 dst_iview
->planes
[0].isl
.base_level
,
4601 dst_iview
->planes
[0].isl
.base_array_layer
,
4602 VK_IMAGE_ASPECT_STENCIL_BIT
,
4603 render_area
.offset
.x
, render_area
.offset
.y
,
4604 render_area
.offset
.x
, render_area
.offset
.y
,
4605 render_area
.extent
.width
,
4606 render_area
.extent
.height
,
4607 fb
->layers
, filter
);
4611 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4612 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4613 if (a
== VK_ATTACHMENT_UNUSED
)
4616 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4619 assert(a
< cmd_state
->pass
->attachment_count
);
4620 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4621 struct anv_image_view
*iview
= fb
->attachments
[a
];
4622 const struct anv_image
*image
= iview
->image
;
4624 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4625 image
->vk_format
!= iview
->vk_format
) {
4626 enum anv_fast_clear_type fast_clear_type
=
4627 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4628 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4629 att_state
->current_layout
);
4631 /* If any clear color was used, flush it down the aux surfaces. If we
4632 * don't do it now using the view's format we might use the clear
4633 * color incorrectly in the following resolves (for example with an
4634 * SRGB view & a UNORM image).
4636 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4637 anv_perf_warn(cmd_buffer
->device
->instance
, fb
,
4638 "Doing a partial resolve to get rid of clear color at the "
4639 "end of a renderpass due to an image/view format mismatch");
4641 uint32_t base_layer
, layer_count
;
4642 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4644 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4645 iview
->planes
[0].isl
.base_level
);
4647 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4648 layer_count
= fb
->layers
;
4651 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4652 uint32_t array_layer
= base_layer
+ a
;
4653 if (image
->samples
== 1) {
4654 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4655 iview
->planes
[0].isl
.format
,
4656 VK_IMAGE_ASPECT_COLOR_BIT
,
4657 iview
->planes
[0].isl
.base_level
,
4659 ISL_AUX_OP_PARTIAL_RESOLVE
,
4660 ANV_FAST_CLEAR_NONE
);
4662 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4663 iview
->planes
[0].isl
.format
,
4664 VK_IMAGE_ASPECT_COLOR_BIT
,
4666 ISL_AUX_OP_PARTIAL_RESOLVE
,
4667 ANV_FAST_CLEAR_NONE
);
4673 /* Transition the image into the final layout for this render pass */
4674 VkImageLayout target_layout
=
4675 cmd_state
->pass
->attachments
[a
].final_layout
;
4677 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4678 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4680 uint32_t base_layer
, layer_count
;
4681 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4683 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4684 iview
->planes
[0].isl
.base_level
);
4686 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4687 layer_count
= fb
->layers
;
4690 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4691 iview
->planes
[0].isl
.base_level
, 1,
4692 base_layer
, layer_count
,
4693 att_state
->current_layout
, target_layout
);
4694 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4695 transition_depth_buffer(cmd_buffer
, image
,
4696 att_state
->current_layout
, target_layout
);
4700 /* Accumulate any subpass flushes that need to happen after the subpass.
4701 * Yes, they do get accumulated twice in the NextSubpass case but since
4702 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4703 * ORing the bits in twice so it's harmless.
4705 cmd_buffer
->state
.pending_pipe_bits
|=
4706 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4709 void genX(CmdBeginRenderPass
)(
4710 VkCommandBuffer commandBuffer
,
4711 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4712 VkSubpassContents contents
)
4714 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4715 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4716 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4718 cmd_buffer
->state
.framebuffer
= framebuffer
;
4719 cmd_buffer
->state
.pass
= pass
;
4720 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4722 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4724 /* If we failed to setup the attachments we should not try to go further */
4725 if (result
!= VK_SUCCESS
) {
4726 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4730 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4732 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4735 void genX(CmdBeginRenderPass2KHR
)(
4736 VkCommandBuffer commandBuffer
,
4737 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4738 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4740 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4741 pSubpassBeginInfo
->contents
);
4744 void genX(CmdNextSubpass
)(
4745 VkCommandBuffer commandBuffer
,
4746 VkSubpassContents contents
)
4748 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4750 if (anv_batch_has_error(&cmd_buffer
->batch
))
4753 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4755 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4756 cmd_buffer_end_subpass(cmd_buffer
);
4757 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4760 void genX(CmdNextSubpass2KHR
)(
4761 VkCommandBuffer commandBuffer
,
4762 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4763 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4765 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4768 void genX(CmdEndRenderPass
)(
4769 VkCommandBuffer commandBuffer
)
4771 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4773 if (anv_batch_has_error(&cmd_buffer
->batch
))
4776 cmd_buffer_end_subpass(cmd_buffer
);
4778 cmd_buffer
->state
.hiz_enabled
= false;
4781 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
4784 /* Remove references to render pass specific state. This enables us to
4785 * detect whether or not we're in a renderpass.
4787 cmd_buffer
->state
.framebuffer
= NULL
;
4788 cmd_buffer
->state
.pass
= NULL
;
4789 cmd_buffer
->state
.subpass
= NULL
;
4792 void genX(CmdEndRenderPass2KHR
)(
4793 VkCommandBuffer commandBuffer
,
4794 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4796 genX(CmdEndRenderPass
)(commandBuffer
);
4800 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
4802 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4803 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(ANV_PREDICATE_RESULT_REG
));
4804 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
4805 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
4806 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
4808 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
4809 mip
.LoadOperation
= LOAD_LOADINV
;
4810 mip
.CombineOperation
= COMBINE_SET
;
4811 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4816 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4817 void genX(CmdBeginConditionalRenderingEXT
)(
4818 VkCommandBuffer commandBuffer
,
4819 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4821 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4822 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4823 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4824 struct anv_address value_address
=
4825 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
4827 const bool isInverted
= pConditionalRenderingBegin
->flags
&
4828 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
4830 cmd_state
->conditional_render_enabled
= true;
4832 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4834 /* Section 19.4 of the Vulkan 1.1.85 spec says:
4836 * If the value of the predicate in buffer memory changes
4837 * while conditional rendering is active, the rendering commands
4838 * may be discarded in an implementation-dependent way.
4839 * Some implementations may latch the value of the predicate
4840 * upon beginning conditional rendering while others
4841 * may read it before every rendering command.
4843 * So it's perfectly fine to read a value from the buffer once.
4845 emit_lrm(&cmd_buffer
->batch
, CS_GPR(MI_ALU_REG0
), value_address
);
4846 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
4847 emit_lri(&cmd_buffer
->batch
, CS_GPR(MI_ALU_REG0
) + 4, 0);
4849 /* Precompute predicate result, it is necessary to support secondary
4850 * command buffers since it is unknown if conditional rendering is
4851 * inverted when populating them.
4853 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
4854 dw
[1] = mi_alu(MI_ALU_LOAD0
, MI_ALU_SRCA
, 0);
4855 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG0
);
4856 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
4857 dw
[4] = mi_alu(isInverted
? MI_ALU_STOREINV
: MI_ALU_STORE
,
4858 ANV_PREDICATE_RESULT_REG
, MI_ALU_CF
);
4861 void genX(CmdEndConditionalRenderingEXT
)(
4862 VkCommandBuffer commandBuffer
)
4864 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4865 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4867 cmd_state
->conditional_render_enabled
= false;