2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
,
37 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
39 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
40 lrm
.RegisterAddress
= reg
;
41 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
46 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
48 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
49 lri
.RegisterOffset
= reg
;
54 #if GEN_IS_HASWELL || GEN_GEN >= 8
56 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
58 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
59 lrr
.SourceRegisterAddress
= src
;
60 lrr
.DestinationRegisterAddress
= dst
;
66 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
68 struct anv_device
*device
= cmd_buffer
->device
;
70 /* Emit a render target cache flush.
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
77 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
78 pc
.DCFlushEnable
= true;
79 pc
.RenderTargetCacheFlushEnable
= true;
80 pc
.CommandStreamerStallEnable
= true;
83 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
84 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
85 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
86 sba
.GeneralStateBaseAddressModifyEnable
= true;
88 sba
.SurfaceStateBaseAddress
=
89 anv_cmd_buffer_surface_base_address(cmd_buffer
);
90 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
91 sba
.SurfaceStateBaseAddressModifyEnable
= true;
93 sba
.DynamicStateBaseAddress
=
94 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
95 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
96 sba
.DynamicStateBaseAddressModifyEnable
= true;
98 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
99 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
100 sba
.IndirectObjectBaseAddressModifyEnable
= true;
102 sba
.InstructionBaseAddress
=
103 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
104 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
105 sba
.InstructionBaseAddressModifyEnable
= true;
108 /* Broadwell requires that we specify a buffer size for a bunch of
109 * these fields. However, since we will be growing the BO's live, we
110 * just set them all to the maximum.
112 sba
.GeneralStateBufferSize
= 0xfffff;
113 sba
.GeneralStateBufferSizeModifyEnable
= true;
114 sba
.DynamicStateBufferSize
= 0xfffff;
115 sba
.DynamicStateBufferSizeModifyEnable
= true;
116 sba
.IndirectObjectBufferSize
= 0xfffff;
117 sba
.IndirectObjectBufferSizeModifyEnable
= true;
118 sba
.InstructionBufferSize
= 0xfffff;
119 sba
.InstructionBuffersizeModifyEnable
= true;
123 /* After re-setting the surface state base address, we have to do some
124 * cache flusing so that the sampler engine will pick up the new
125 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
126 * Shared Function > 3D Sampler > State > State Caching (page 96):
128 * Coherency with system memory in the state cache, like the texture
129 * cache is handled partially by software. It is expected that the
130 * command stream or shader will issue Cache Flush operation or
131 * Cache_Flush sampler message to ensure that the L1 cache remains
132 * coherent with system memory.
136 * Whenever the value of the Dynamic_State_Base_Addr,
137 * Surface_State_Base_Addr are altered, the L1 state cache must be
138 * invalidated to ensure the new surface or sampler state is fetched
139 * from system memory.
141 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
142 * which, according the PIPE_CONTROL instruction documentation in the
145 * Setting this bit is independent of any other bit in this packet.
146 * This bit controls the invalidation of the L1 and L2 state caches
147 * at the top of the pipe i.e. at the parsing time.
149 * Unfortunately, experimentation seems to indicate that state cache
150 * invalidation through a PIPE_CONTROL does nothing whatsoever in
151 * regards to surface state and binding tables. In stead, it seems that
152 * invalidating the texture cache is what is actually needed.
154 * XXX: As far as we have been able to determine through
155 * experimentation, shows that flush the texture cache appears to be
156 * sufficient. The theory here is that all of the sampling/rendering
157 * units cache the binding table in the texture cache. However, we have
158 * yet to be able to actually confirm this.
160 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
161 pc
.TextureCacheInvalidationEnable
= true;
162 pc
.ConstantCacheInvalidationEnable
= true;
163 pc
.StateCacheInvalidationEnable
= true;
168 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
169 struct anv_state state
,
170 struct anv_bo
*bo
, uint32_t offset
)
172 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
175 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
176 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
177 if (result
!= VK_SUCCESS
)
178 anv_batch_set_error(&cmd_buffer
->batch
, result
);
182 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
183 const struct anv_image_view
*image_view
,
184 const uint32_t plane
,
185 struct anv_surface_state state
)
187 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
188 const struct anv_image
*image
= image_view
->image
;
189 uint32_t image_plane
= image_view
->planes
[plane
].image_plane
;
191 add_surface_state_reloc(cmd_buffer
, state
.state
,
192 image
->planes
[image_plane
].bo
, state
.address
);
194 if (state
.aux_address
) {
196 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
197 &cmd_buffer
->pool
->alloc
,
198 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
199 image
->planes
[image_plane
].bo
, state
.aux_address
);
200 if (result
!= VK_SUCCESS
)
201 anv_batch_set_error(&cmd_buffer
->batch
, result
);
206 color_attachment_compute_aux_usage(struct anv_device
* device
,
207 struct anv_cmd_state
* cmd_state
,
208 uint32_t att
, VkRect2D render_area
,
209 union isl_color_value
*fast_clear_color
)
211 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
212 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
214 assert(iview
->n_planes
== 1);
216 if (iview
->planes
[0].isl
.base_array_layer
>=
217 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
218 iview
->planes
[0].isl
.base_level
)) {
219 /* There is no aux buffer which corresponds to the level and layer(s)
222 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
223 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
224 att_state
->fast_clear
= false;
226 } else if (iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_MCS
) {
227 att_state
->aux_usage
= ISL_AUX_USAGE_MCS
;
228 att_state
->input_aux_usage
= ISL_AUX_USAGE_MCS
;
229 att_state
->fast_clear
= false;
231 } else if (iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
232 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
233 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_E
;
235 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
236 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
238 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
239 * setting is only allowed if Surface Format supported for Fast
240 * Clear. In addition, if the surface is bound to the sampling
241 * engine, Surface Format must be supported for Render Target
242 * Compression for surfaces bound to the sampling engine."
244 * In other words, we can only sample from a fast-cleared image if it
245 * also supports color compression.
247 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
248 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
250 /* While fast-clear resolves and partial resolves are fairly cheap in the
251 * case where you render to most of the pixels, full resolves are not
252 * because they potentially involve reading and writing the entire
253 * framebuffer. If we can't texture with CCS_E, we should leave it off and
254 * limit ourselves to fast clears.
256 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
257 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
258 anv_perf_warn(device
->instance
, iview
->image
,
259 "Not temporarily enabling CCS_E.");
262 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
266 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
268 const struct isl_format_layout
*view_fmtl
=
269 isl_format_get_layout(iview
->planes
[0].isl
.format
);
270 union isl_color_value clear_color
= {};
272 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
273 if (view_fmtl->channels.c.bits) \
274 clear_color.u32[i] = att_state->clear_value.color.uint32[i]
276 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
277 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
278 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
279 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
281 #undef COPY_CLEAR_COLOR_CHANNEL
283 att_state
->clear_color_is_zero_one
=
284 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
285 att_state
->clear_color_is_zero
=
286 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
288 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
289 /* Start off assuming fast clears are possible */
290 att_state
->fast_clear
= true;
292 /* Potentially, we could do partial fast-clears but doing so has crazy
293 * alignment restrictions. It's easier to just restrict to full size
294 * fast clears for now.
296 if (render_area
.offset
.x
!= 0 ||
297 render_area
.offset
.y
!= 0 ||
298 render_area
.extent
.width
!= iview
->extent
.width
||
299 render_area
.extent
.height
!= iview
->extent
.height
)
300 att_state
->fast_clear
= false;
302 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
303 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
304 att_state
->fast_clear
= false;
306 /* We only allow fast clears in the GENERAL layout if the auxiliary
307 * buffer is always enabled and the fast-clear value is all 0's. See
308 * add_aux_state_tracking_buffer() for more information.
310 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
311 VK_IMAGE_LAYOUT_GENERAL
&&
312 (!att_state
->clear_color_is_zero
||
313 iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_NONE
)) {
314 att_state
->fast_clear
= false;
317 /* We only allow fast clears to the first slice of an image (level 0,
318 * layer 0) and only for the entire slice. This guarantees us that, at
319 * any given time, there is only one clear color on any given image at
320 * any given time. At the time of our testing (Jan 17, 2018), there
321 * were no known applications which would benefit from fast-clearing
322 * more than just the first slice.
324 if (att_state
->fast_clear
&&
325 (iview
->planes
[0].isl
.base_level
> 0 ||
326 iview
->planes
[0].isl
.base_array_layer
> 0)) {
327 anv_perf_warn(device
->instance
, iview
->image
,
328 "Rendering with multi-lod or multi-layer framebuffer "
329 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
330 "baseArrayLayer > 0. Not fast clearing.");
331 att_state
->fast_clear
= false;
332 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
333 anv_perf_warn(device
->instance
, iview
->image
,
334 "Rendering to a multi-layer framebuffer with "
335 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
338 if (att_state
->fast_clear
)
339 *fast_clear_color
= clear_color
;
341 att_state
->fast_clear
= false;
346 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
347 struct anv_cmd_state
*cmd_state
,
348 uint32_t att
, VkRect2D render_area
)
350 struct anv_render_pass_attachment
*pass_att
=
351 &cmd_state
->pass
->attachments
[att
];
352 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
353 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
355 /* These will be initialized after the first subpass transition. */
356 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
357 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
360 /* We don't do any HiZ or depth fast-clears on gen7 yet */
361 att_state
->fast_clear
= false;
365 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
366 /* If we're just clearing stencil, we can always HiZ clear */
367 att_state
->fast_clear
= true;
371 /* Default to false for now */
372 att_state
->fast_clear
= false;
374 /* We must have depth in order to have HiZ */
375 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
378 const enum isl_aux_usage first_subpass_aux_usage
=
379 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
380 VK_IMAGE_ASPECT_DEPTH_BIT
,
381 pass_att
->first_subpass_layout
);
382 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
385 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
386 iview
->planes
[0].isl
.format
,
387 iview
->image
->samples
,
388 render_area
.offset
.x
,
389 render_area
.offset
.y
,
390 render_area
.offset
.x
+
391 render_area
.extent
.width
,
392 render_area
.offset
.y
+
393 render_area
.extent
.height
))
396 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
399 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
400 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
401 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
402 * only supports returning 0.0f. Gens prior to gen8 do not support this
408 /* If we got here, then we can fast clear */
409 att_state
->fast_clear
= true;
413 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
415 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
418 /* We only allocate input attachment states for color surfaces. Compression
419 * is not yet enabled for depth textures and stencil doesn't allow
420 * compression so we can just use the texture surface state from the view.
422 return vk_format_is_color(att
->format
);
425 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
426 * the initial layout is undefined, the HiZ buffer and depth buffer will
427 * represent the same data at the end of this operation.
430 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
431 const struct anv_image
*image
,
432 VkImageLayout initial_layout
,
433 VkImageLayout final_layout
)
437 /* A transition is a no-op if HiZ is not enabled, or if the initial and
438 * final layouts are equal.
440 * The undefined layout indicates that the user doesn't care about the data
441 * that's currently in the buffer. Therefore, a data-preserving resolve
442 * operation is not needed.
444 if (image
->planes
[0].aux_usage
!= ISL_AUX_USAGE_HIZ
|| initial_layout
== final_layout
)
447 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
448 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
449 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
450 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
451 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
452 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
454 enum isl_aux_op hiz_op
;
455 if (hiz_enabled
&& !enable_hiz
) {
456 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
457 } else if (!hiz_enabled
&& enable_hiz
) {
458 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
460 assert(hiz_enabled
== enable_hiz
);
461 /* If the same buffer will be used, no resolves are necessary. */
462 hiz_op
= ISL_AUX_OP_NONE
;
465 if (hiz_op
!= ISL_AUX_OP_NONE
)
466 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
470 #define MI_PREDICATE_SRC0 0x2400
471 #define MI_PREDICATE_SRC1 0x2408
474 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
475 const struct anv_image
*image
,
476 VkImageAspectFlagBits aspect
,
478 uint32_t base_layer
, uint32_t layer_count
,
481 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
483 /* We only have compression tracking for CCS_E */
484 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
487 for (uint32_t a
= 0; a
< layer_count
; a
++) {
488 uint32_t layer
= base_layer
+ a
;
489 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
490 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
493 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
499 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
500 const struct anv_image
*image
,
501 VkImageAspectFlagBits aspect
,
502 enum anv_fast_clear_type fast_clear
)
504 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
505 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
507 sdi
.ImmediateData
= fast_clear
;
510 /* Whenever we have fast-clear, we consider that slice to be compressed.
511 * This makes building predicates much easier.
513 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
514 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
517 #if GEN_IS_HASWELL || GEN_GEN >= 8
518 static inline uint32_t
519 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
521 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
523 .Operand1
= operand1
,
524 .Operand2
= operand2
,
528 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
534 #define CS_GPR(n) (0x2600 + (n) * 8)
537 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
538 const struct anv_image
*image
,
539 VkImageAspectFlagBits aspect
,
540 uint32_t level
, uint32_t array_layer
,
541 enum isl_aux_op resolve_op
,
542 enum anv_fast_clear_type fast_clear_supported
)
544 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
545 struct anv_address fast_clear_type_addr
=
546 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
549 /* Name some registers */
550 const int image_fc_reg
= MI_ALU_REG0
;
551 const int fc_imm_reg
= MI_ALU_REG1
;
552 const int pred_reg
= MI_ALU_REG2
;
556 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
557 /* In this case, we're doing a full resolve which means we want the
558 * resolve to happen if any compression (including fast-clears) is
561 * In order to simplify the logic a bit, we make the assumption that,
562 * if the first slice has been fast-cleared, it is also marked as
563 * compressed. See also set_image_fast_clear_state.
565 struct anv_address compression_state_addr
=
566 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
567 aspect
, level
, array_layer
);
568 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
569 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
570 lrm
.MemoryAddress
= compression_state_addr
;
572 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
573 sdi
.Address
= compression_state_addr
;
574 sdi
.ImmediateData
= 0;
577 if (level
== 0 && array_layer
== 0) {
578 /* If the predicate is true, we want to write 0 to the fast clear type
579 * and, if it's false, leave it alone. We can do this by writing
581 * clear_type = clear_type & ~predicate;
583 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
584 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
585 lrm
.MemoryAddress
= fast_clear_type_addr
;
587 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
588 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
589 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
592 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
593 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
594 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
595 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
596 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
598 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
599 srm
.MemoryAddress
= fast_clear_type_addr
;
600 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
603 } else if (level
== 0 && array_layer
== 0) {
604 /* In this case, we are doing a partial resolve to get rid of fast-clear
605 * colors. We don't care about the compression state but we do care
606 * about how much fast clear is allowed by the final layout.
608 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
609 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
611 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
612 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
613 lrm
.MemoryAddress
= fast_clear_type_addr
;
615 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
617 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
618 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
620 /* We need to compute (fast_clear_supported < image->fast_clear).
621 * We do this by subtracting and storing the carry bit.
623 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
624 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
625 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
626 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
627 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
629 /* Store the predicate */
630 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
632 /* If the predicate is true, we want to write 0 to the fast clear type
633 * and, if it's false, leave it alone. We can do this by writing
635 * clear_type = clear_type & ~predicate;
637 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
638 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
639 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
640 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
641 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
643 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
644 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
645 srm
.MemoryAddress
= fast_clear_type_addr
;
648 /* In this case, we're trying to do a partial resolve on a slice that
649 * doesn't have clear color. There's nothing to do.
651 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
655 #else /* GEN_GEN <= 8 */
656 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
657 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
659 /* We don't support fast clears on anything other than the first slice. */
660 if (level
> 0 || array_layer
> 0)
663 /* On gen8, we don't have a concept of default clear colors because we
664 * can't sample from CCS surfaces. It's enough to just load the fast clear
665 * state into the predicate register.
667 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
668 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
669 lrm
.MemoryAddress
= fast_clear_type_addr
;
671 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
672 sdi
.Address
= fast_clear_type_addr
;
673 sdi
.ImmediateData
= 0;
677 /* We use the first half of src0 for the actual predicate. Set the second
678 * half of src0 and all of src1 to 0 as the predicate operation will be
679 * doing an implicit src0 != src1.
681 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
682 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
683 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
685 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
686 mip
.LoadOperation
= LOAD_LOADINV
;
687 mip
.CombineOperation
= COMBINE_SET
;
688 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
691 /* CCS_D only supports full resolves and BLORP will assert on us if we try
692 * to do a partial resolve on a CCS_D surface.
694 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
695 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
696 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
698 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
699 array_layer
, 1, resolve_op
, true);
703 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
704 const struct anv_image
*image
,
705 VkImageAspectFlagBits aspect
,
706 enum isl_aux_usage aux_usage
,
709 uint32_t layer_count
)
711 /* The aspect must be exactly one of the image aspects. */
712 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
714 /* The only compression types with more than just fast-clears are MCS,
715 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
716 * track the current fast-clear and compression state. This leaves us
717 * with just MCS and CCS_E.
719 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
720 aux_usage
!= ISL_AUX_USAGE_MCS
)
723 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
724 level
, base_layer
, layer_count
, true);
728 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
729 const struct anv_image
*image
,
730 VkImageAspectFlagBits aspect
)
732 assert(cmd_buffer
&& image
);
733 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
735 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
736 ANV_FAST_CLEAR_NONE
);
738 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
739 enum isl_aux_usage aux_usage
= image
->planes
[plane
].aux_usage
;
741 /* The fast clear value dword(s) will be copied into a surface state object.
742 * Ensure that the restrictions of the fields in the dword(s) are followed.
744 * CCS buffers on SKL+ can have any value set for the clear colors.
746 if (image
->samples
== 1 && GEN_GEN
>= 9)
749 /* Other combinations of auxiliary buffers and platforms require specific
750 * values in the clear value dword(s).
752 struct anv_address addr
=
753 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
755 for (; i
< cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
; i
+= 4) {
756 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
760 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
761 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
762 sdi
.ImmediateData
= 0;
763 } else if (GEN_VERSIONx10
>= 75) {
764 /* Pre-SKL, the dword containing the clear values also contains
765 * other fields, so we need to initialize those fields to match the
766 * values that would be in a color attachment.
769 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
770 ISL_CHANNEL_SELECT_GREEN
<< 22 |
771 ISL_CHANNEL_SELECT_BLUE
<< 19 |
772 ISL_CHANNEL_SELECT_ALPHA
<< 16;
773 } else if (GEN_VERSIONx10
== 70) {
774 /* On IVB, the dword containing the clear values also contains
775 * other fields that must be zero or can be zero.
778 sdi
.ImmediateData
= 0;
786 /* Copy the fast-clear value dword(s) between a surface state object and an
787 * image's fast clear state buffer.
790 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
791 struct anv_state surface_state
,
792 const struct anv_image
*image
,
793 VkImageAspectFlagBits aspect
,
794 bool copy_from_surface_state
)
796 assert(cmd_buffer
&& image
);
797 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
799 struct anv_bo
*ss_bo
=
800 &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
;
801 uint32_t ss_clear_offset
= surface_state
.offset
+
802 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
;
803 const struct anv_address entry_addr
=
804 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
805 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
807 if (copy_from_surface_state
) {
808 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
.bo
, entry_addr
.offset
,
809 ss_bo
, ss_clear_offset
, copy_size
);
811 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_bo
, ss_clear_offset
,
812 entry_addr
.bo
, entry_addr
.offset
, copy_size
);
814 /* Updating a surface state object may require that the state cache be
815 * invalidated. From the SKL PRM, Shared Functions -> State -> State
818 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
819 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
820 * modified [...], the L1 state cache must be invalidated to ensure
821 * the new surface or sampler state is fetched from system memory.
823 * In testing, SKL doesn't actually seem to need this, but HSW does.
825 cmd_buffer
->state
.pending_pipe_bits
|=
826 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
831 * @brief Transitions a color buffer from one layout to another.
833 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
836 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
837 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
838 * this represents the maximum layers to transition at each
839 * specified miplevel.
842 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
843 const struct anv_image
*image
,
844 VkImageAspectFlagBits aspect
,
845 const uint32_t base_level
, uint32_t level_count
,
846 uint32_t base_layer
, uint32_t layer_count
,
847 VkImageLayout initial_layout
,
848 VkImageLayout final_layout
)
850 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
851 /* Validate the inputs. */
853 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
854 /* These values aren't supported for simplicity's sake. */
855 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
856 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
857 /* Ensure the subresource range is valid. */
858 uint64_t last_level_num
= base_level
+ level_count
;
859 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
860 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
861 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
862 assert(last_level_num
<= image
->levels
);
863 /* The spec disallows these final layouts. */
864 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
865 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
867 /* No work is necessary if the layout stays the same or if this subresource
868 * range lacks auxiliary data.
870 if (initial_layout
== final_layout
)
873 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
875 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
876 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
877 /* This surface is a linear compressed image with a tiled shadow surface
878 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
879 * we need to ensure the shadow copy is up-to-date.
881 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
882 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
883 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
884 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
886 anv_image_copy_to_shadow(cmd_buffer
, image
,
887 base_level
, level_count
,
888 base_layer
, layer_count
);
891 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
894 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
896 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
897 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
898 /* A subresource in the undefined layout may have been aliased and
899 * populated with any arrangement of bits. Therefore, we must initialize
900 * the related aux buffer and clear buffer entry with desirable values.
901 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
902 * images with VK_IMAGE_TILING_OPTIMAL.
904 * Initialize the relevant clear buffer entries.
906 if (base_level
== 0 && base_layer
== 0)
907 init_fast_clear_color(cmd_buffer
, image
, aspect
);
909 /* Initialize the aux buffers to enable correct rendering. In order to
910 * ensure that things such as storage images work correctly, aux buffers
911 * need to be initialized to valid data.
913 * Having an aux buffer with invalid data is a problem for two reasons:
915 * 1) Having an invalid value in the buffer can confuse the hardware.
916 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
917 * invalid and leads to the hardware doing strange things. It
918 * doesn't hang as far as we can tell but rendering corruption can
921 * 2) If this transition is into the GENERAL layout and we then use the
922 * image as a storage image, then we must have the aux buffer in the
923 * pass-through state so that, if we then go to texture from the
924 * image, we get the results of our storage image writes and not the
925 * fast clear color or other random data.
927 * For CCS both of the problems above are real demonstrable issues. In
928 * that case, the only thing we can do is to perform an ambiguate to
929 * transition the aux surface into the pass-through state.
931 * For MCS, (2) is never an issue because we don't support multisampled
932 * storage images. In theory, issue (1) is a problem with MCS but we've
933 * never seen it in the wild. For 4x and 16x, all bit patters could, in
934 * theory, be interpreted as something but we don't know that all bit
935 * patterns are actually valid. For 2x and 8x, you could easily end up
936 * with the MCS referring to an invalid plane because not all bits of
937 * the MCS value are actually used. Even though we've never seen issues
938 * in the wild, it's best to play it safe and initialize the MCS. We
939 * can use a fast-clear for MCS because we only ever touch from render
940 * and texture (no image load store).
942 if (image
->samples
== 1) {
943 for (uint32_t l
= 0; l
< level_count
; l
++) {
944 const uint32_t level
= base_level
+ l
;
946 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
947 if (base_layer
>= aux_layers
)
948 break; /* We will only get fewer layers as level increases */
949 uint32_t level_layer_count
=
950 MIN2(layer_count
, aux_layers
- base_layer
);
952 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
953 base_layer
, level_layer_count
,
954 ISL_AUX_OP_AMBIGUATE
, false);
956 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
957 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
958 level
, base_layer
, level_layer_count
,
963 if (image
->samples
== 4 || image
->samples
== 16) {
964 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
965 "Doing a potentially unnecessary fast-clear to "
966 "define an MCS buffer.");
969 assert(base_level
== 0 && level_count
== 1);
970 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
971 base_layer
, layer_count
,
972 ISL_AUX_OP_FAST_CLEAR
, false);
977 const enum isl_aux_usage initial_aux_usage
=
978 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
979 const enum isl_aux_usage final_aux_usage
=
980 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
982 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
983 * We can handle transitions between CCS_D/E to and from NONE. What we
984 * don't yet handle is switching between CCS_E and CCS_D within a given
985 * image. Doing so in a performant way requires more detailed aux state
986 * tracking such as what is done in i965. For now, just assume that we
987 * only have one type of compression.
989 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
990 final_aux_usage
== ISL_AUX_USAGE_NONE
||
991 initial_aux_usage
== final_aux_usage
);
993 /* If initial aux usage is NONE, there is nothing to resolve */
994 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
997 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
999 /* If the initial layout supports more fast clear than the final layout
1000 * then we need at least a partial resolve.
1002 const enum anv_fast_clear_type initial_fast_clear
=
1003 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1004 const enum anv_fast_clear_type final_fast_clear
=
1005 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1006 if (final_fast_clear
< initial_fast_clear
)
1007 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1009 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1010 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1011 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1013 if (resolve_op
== ISL_AUX_OP_NONE
)
1016 /* Perform a resolve to synchronize data between the main and aux buffer.
1017 * Before we begin, we must satisfy the cache flushing requirement specified
1018 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1020 * Any transition from any value in {Clear, Render, Resolve} to a
1021 * different value in {Clear, Render, Resolve} requires end of pipe
1024 * We perform a flush of the write cache before and after the clear and
1025 * resolve operations to meet this requirement.
1027 * Unlike other drawing, fast clear operations are not properly
1028 * synchronized. The first PIPE_CONTROL here likely ensures that the
1029 * contents of the previous render or clear hit the render target before we
1030 * resolve and the second likely ensures that the resolve is complete before
1031 * we do any more rendering or clearing.
1033 cmd_buffer
->state
.pending_pipe_bits
|=
1034 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1036 for (uint32_t l
= 0; l
< level_count
; l
++) {
1037 uint32_t level
= base_level
+ l
;
1039 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1040 if (base_layer
>= aux_layers
)
1041 break; /* We will only get fewer layers as level increases */
1042 uint32_t level_layer_count
=
1043 MIN2(layer_count
, aux_layers
- base_layer
);
1045 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1046 uint32_t array_layer
= base_layer
+ a
;
1047 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
, aspect
,
1048 level
, array_layer
, resolve_op
,
1053 cmd_buffer
->state
.pending_pipe_bits
|=
1054 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1058 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1061 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1062 struct anv_render_pass
*pass
,
1063 const VkRenderPassBeginInfo
*begin
)
1065 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1066 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1068 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1070 if (pass
->attachment_count
> 0) {
1071 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1072 pass
->attachment_count
*
1073 sizeof(state
->attachments
[0]),
1074 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1075 if (state
->attachments
== NULL
) {
1076 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1077 return anv_batch_set_error(&cmd_buffer
->batch
,
1078 VK_ERROR_OUT_OF_HOST_MEMORY
);
1081 state
->attachments
= NULL
;
1084 /* Reserve one for the NULL state. */
1085 unsigned num_states
= 1;
1086 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1087 if (vk_format_is_color(pass
->attachments
[i
].format
))
1090 if (need_input_attachment_state(&pass
->attachments
[i
]))
1094 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1095 state
->render_pass_states
=
1096 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1097 num_states
* ss_stride
, isl_dev
->ss
.align
);
1099 struct anv_state next_state
= state
->render_pass_states
;
1100 next_state
.alloc_size
= isl_dev
->ss
.size
;
1102 state
->null_surface_state
= next_state
;
1103 next_state
.offset
+= ss_stride
;
1104 next_state
.map
+= ss_stride
;
1106 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1107 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1108 state
->attachments
[i
].color
.state
= next_state
;
1109 next_state
.offset
+= ss_stride
;
1110 next_state
.map
+= ss_stride
;
1113 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1114 state
->attachments
[i
].input
.state
= next_state
;
1115 next_state
.offset
+= ss_stride
;
1116 next_state
.map
+= ss_stride
;
1119 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1120 state
->render_pass_states
.alloc_size
);
1123 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1124 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1126 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1127 isl_extent3d(framebuffer
->width
,
1128 framebuffer
->height
,
1129 framebuffer
->layers
));
1131 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1132 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1133 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1134 VkImageAspectFlags clear_aspects
= 0;
1135 VkImageAspectFlags load_aspects
= 0;
1137 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1138 /* color attachment */
1139 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1140 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1141 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1142 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1145 /* depthstencil attachment */
1146 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1147 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1148 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1149 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1150 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1153 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1154 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1155 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1156 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1157 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1162 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1163 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1164 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1166 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1168 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1169 anv_assert(iview
->vk_format
== att
->format
);
1170 anv_assert(iview
->n_planes
== 1);
1172 union isl_color_value clear_color
= { .u32
= { 0, } };
1173 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1174 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1175 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1176 state
, i
, begin
->renderArea
,
1179 anv_image_fill_surface_state(cmd_buffer
->device
,
1181 VK_IMAGE_ASPECT_COLOR_BIT
,
1182 &iview
->planes
[0].isl
,
1183 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1184 state
->attachments
[i
].aux_usage
,
1187 &state
->attachments
[i
].color
,
1190 add_image_view_relocs(cmd_buffer
, iview
, 0,
1191 state
->attachments
[i
].color
);
1193 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1198 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1199 anv_image_fill_surface_state(cmd_buffer
->device
,
1201 VK_IMAGE_ASPECT_COLOR_BIT
,
1202 &iview
->planes
[0].isl
,
1203 ISL_SURF_USAGE_TEXTURE_BIT
,
1204 state
->attachments
[i
].input_aux_usage
,
1207 &state
->attachments
[i
].input
,
1210 add_image_view_relocs(cmd_buffer
, iview
, 0,
1211 state
->attachments
[i
].input
);
1220 genX(BeginCommandBuffer
)(
1221 VkCommandBuffer commandBuffer
,
1222 const VkCommandBufferBeginInfo
* pBeginInfo
)
1224 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1226 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1227 * command buffer's state. Otherwise, we must *reset* its state. In both
1228 * cases we reset it.
1230 * From the Vulkan 1.0 spec:
1232 * If a command buffer is in the executable state and the command buffer
1233 * was allocated from a command pool with the
1234 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1235 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1236 * as if vkResetCommandBuffer had been called with
1237 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1238 * the command buffer in the recording state.
1240 anv_cmd_buffer_reset(cmd_buffer
);
1242 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1244 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1245 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1247 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1249 /* We sometimes store vertex data in the dynamic state buffer for blorp
1250 * operations and our dynamic state stream may re-use data from previous
1251 * command buffers. In order to prevent stale cache data, we flush the VF
1252 * cache. We could do this on every blorp call but that's not really
1253 * needed as all of the data will get written by the CPU prior to the GPU
1254 * executing anything. The chances are fairly high that they will use
1255 * blorp at least once per primary command buffer so it shouldn't be
1258 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1259 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1261 /* We send an "Indirect State Pointers Disable" packet at
1262 * EndCommandBuffer, so all push contant packets are ignored during a
1263 * context restore. Documentation says after that command, we need to
1264 * emit push constants again before any rendering operation. So we
1265 * flag them dirty here to make sure they get emitted.
1267 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1269 VkResult result
= VK_SUCCESS
;
1270 if (cmd_buffer
->usage_flags
&
1271 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1272 assert(pBeginInfo
->pInheritanceInfo
);
1273 cmd_buffer
->state
.pass
=
1274 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1275 cmd_buffer
->state
.subpass
=
1276 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1278 /* This is optional in the inheritance info. */
1279 cmd_buffer
->state
.framebuffer
=
1280 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1282 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1283 cmd_buffer
->state
.pass
, NULL
);
1285 /* Record that HiZ is enabled if we can. */
1286 if (cmd_buffer
->state
.framebuffer
) {
1287 const struct anv_image_view
* const iview
=
1288 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1291 VkImageLayout layout
=
1292 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.layout
;
1294 enum isl_aux_usage aux_usage
=
1295 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1296 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1298 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1302 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1308 /* From the PRM, Volume 2a:
1310 * "Indirect State Pointers Disable
1312 * At the completion of the post-sync operation associated with this pipe
1313 * control packet, the indirect state pointers in the hardware are
1314 * considered invalid; the indirect pointers are not saved in the context.
1315 * If any new indirect state commands are executed in the command stream
1316 * while the pipe control is pending, the new indirect state commands are
1319 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1320 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1321 * commands are only considered as Indirect State Pointers. Once ISP is
1322 * issued in a context, SW must initialize by programming push constant
1323 * commands for all the shaders (at least to zero length) before attempting
1324 * any rendering operation for the same context."
1326 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1327 * even though they point to a BO that has been already unreferenced at
1328 * the end of the previous batch buffer. This has been fine so far since
1329 * we are protected by these scratch page (every address not covered by
1330 * a BO should be pointing to the scratch page). But on CNL, it is
1331 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1334 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1335 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1336 * context restore, so the mentioned hang doesn't happen. However,
1337 * software must program push constant commands for all stages prior to
1338 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1341 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1343 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1344 pc
.IndirectStatePointersDisable
= true;
1345 pc
.CommandStreamerStallEnable
= true;
1350 genX(EndCommandBuffer
)(
1351 VkCommandBuffer commandBuffer
)
1353 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1355 if (anv_batch_has_error(&cmd_buffer
->batch
))
1356 return cmd_buffer
->batch
.status
;
1358 /* We want every command buffer to start with the PMA fix in a known state,
1359 * so we disable it at the end of the command buffer.
1361 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1363 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1365 emit_isp_disable(cmd_buffer
);
1367 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1373 genX(CmdExecuteCommands
)(
1374 VkCommandBuffer commandBuffer
,
1375 uint32_t commandBufferCount
,
1376 const VkCommandBuffer
* pCmdBuffers
)
1378 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1380 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1382 if (anv_batch_has_error(&primary
->batch
))
1385 /* The secondary command buffers will assume that the PMA fix is disabled
1386 * when they begin executing. Make sure this is true.
1388 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1390 /* The secondary command buffer doesn't know which textures etc. have been
1391 * flushed prior to their execution. Apply those flushes now.
1393 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1395 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1396 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1398 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1399 assert(!anv_batch_has_error(&secondary
->batch
));
1401 if (secondary
->usage_flags
&
1402 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1403 /* If we're continuing a render pass from the primary, we need to
1404 * copy the surface states for the current subpass into the storage
1405 * we allocated for them in BeginCommandBuffer.
1407 struct anv_bo
*ss_bo
=
1408 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1409 struct anv_state src_state
= primary
->state
.render_pass_states
;
1410 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1411 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1413 genX(cmd_buffer_so_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
1414 ss_bo
, src_state
.offset
,
1415 src_state
.alloc_size
);
1418 anv_cmd_buffer_add_secondary(primary
, secondary
);
1421 /* The secondary may have selected a different pipeline (3D or compute) and
1422 * may have changed the current L3$ configuration. Reset our tracking
1423 * variables to invalid values to ensure that we re-emit these in the case
1424 * where we do any draws or compute dispatches from the primary after the
1425 * secondary has returned.
1427 primary
->state
.current_pipeline
= UINT32_MAX
;
1428 primary
->state
.current_l3_config
= NULL
;
1430 /* Each of the secondary command buffers will use its own state base
1431 * address. We need to re-emit state base address for the primary after
1432 * all of the secondaries are done.
1434 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1437 genX(cmd_buffer_emit_state_base_address
)(primary
);
1440 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1441 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1442 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1445 * Program the hardware to use the specified L3 configuration.
1448 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1449 const struct gen_l3_config
*cfg
)
1452 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1455 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1456 intel_logd("L3 config transition: ");
1457 gen_dump_l3_config(cfg
, stderr
);
1460 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1462 /* According to the hardware docs, the L3 partitioning can only be changed
1463 * while the pipeline is completely drained and the caches are flushed,
1464 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1466 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1467 pc
.DCFlushEnable
= true;
1468 pc
.PostSyncOperation
= NoWrite
;
1469 pc
.CommandStreamerStallEnable
= true;
1472 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1473 * invalidation of the relevant caches. Note that because RO invalidation
1474 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1475 * command is processed by the CS) we cannot combine it with the previous
1476 * stalling flush as the hardware documentation suggests, because that
1477 * would cause the CS to stall on previous rendering *after* RO
1478 * invalidation and wouldn't prevent the RO caches from being polluted by
1479 * concurrent rendering before the stall completes. This intentionally
1480 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1481 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1482 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1483 * already guarantee that there is no concurrent GPGPU kernel execution
1484 * (see SKL HSD 2132585).
1486 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1487 pc
.TextureCacheInvalidationEnable
= true;
1488 pc
.ConstantCacheInvalidationEnable
= true;
1489 pc
.InstructionCacheInvalidateEnable
= true;
1490 pc
.StateCacheInvalidationEnable
= true;
1491 pc
.PostSyncOperation
= NoWrite
;
1494 /* Now send a third stalling flush to make sure that invalidation is
1495 * complete when the L3 configuration registers are modified.
1497 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1498 pc
.DCFlushEnable
= true;
1499 pc
.PostSyncOperation
= NoWrite
;
1500 pc
.CommandStreamerStallEnable
= true;
1505 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1508 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1509 .SLMEnable
= has_slm
,
1510 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1511 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1512 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1513 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1515 /* Set up the L3 partitioning. */
1516 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1520 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1521 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1522 cfg
->n
[GEN_L3P_ALL
];
1523 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1524 cfg
->n
[GEN_L3P_ALL
];
1525 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1526 cfg
->n
[GEN_L3P_ALL
];
1528 assert(!cfg
->n
[GEN_L3P_ALL
]);
1530 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1531 * the matching space on the remaining banks has to be allocated to a
1532 * client (URB for all validated configurations) set to the
1533 * lower-bandwidth 2-bank address hashing mode.
1535 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1536 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1537 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1539 /* Minimum number of ways that can be allocated to the URB. */
1540 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1541 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1543 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1544 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1545 .ConvertDC_UC
= !has_dc
,
1546 .ConvertIS_UC
= !has_is
,
1547 .ConvertC_UC
= !has_c
,
1548 .ConvertT_UC
= !has_t
);
1550 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1551 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1552 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1554 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1555 .SLMEnable
= has_slm
,
1556 .URBLowBandwidth
= urb_low_bw
,
1557 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1559 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1561 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1562 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1564 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1565 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1566 .ISLowBandwidth
= 0,
1567 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1569 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1570 .TLowBandwidth
= 0);
1572 /* Set up the L3 partitioning. */
1573 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1574 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1575 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1578 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1579 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1580 * them disabled to avoid crashing the system hard.
1582 uint32_t scratch1
, chicken3
;
1583 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1584 .L3AtomicDisable
= !has_dc
);
1585 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1586 .L3AtomicDisableMask
= true,
1587 .L3AtomicDisable
= !has_dc
);
1588 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1589 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1595 cmd_buffer
->state
.current_l3_config
= cfg
;
1599 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1601 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1603 /* Flushes are pipelined while invalidations are handled immediately.
1604 * Therefore, if we're flushing anything then we need to schedule a stall
1605 * before any invalidations can happen.
1607 if (bits
& ANV_PIPE_FLUSH_BITS
)
1608 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1610 /* If we're going to do an invalidate and we have a pending CS stall that
1611 * has yet to be resolved, we do the CS stall now.
1613 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1614 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1615 bits
|= ANV_PIPE_CS_STALL_BIT
;
1616 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1619 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1620 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1621 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1622 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1623 pipe
.RenderTargetCacheFlushEnable
=
1624 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1626 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1627 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1628 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1631 * According to the Broadwell documentation, any PIPE_CONTROL with the
1632 * "Command Streamer Stall" bit set must also have another bit set,
1633 * with five different options:
1635 * - Render Target Cache Flush
1636 * - Depth Cache Flush
1637 * - Stall at Pixel Scoreboard
1638 * - Post-Sync Operation
1642 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1643 * mesa and it seems to work fine. The choice is fairly arbitrary.
1645 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1646 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1647 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1648 pipe
.StallAtPixelScoreboard
= true;
1651 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1654 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1655 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1656 pipe
.StateCacheInvalidationEnable
=
1657 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1658 pipe
.ConstantCacheInvalidationEnable
=
1659 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1660 pipe
.VFCacheInvalidationEnable
=
1661 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1662 pipe
.TextureCacheInvalidationEnable
=
1663 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1664 pipe
.InstructionCacheInvalidateEnable
=
1665 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1668 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1671 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1674 void genX(CmdPipelineBarrier
)(
1675 VkCommandBuffer commandBuffer
,
1676 VkPipelineStageFlags srcStageMask
,
1677 VkPipelineStageFlags destStageMask
,
1679 uint32_t memoryBarrierCount
,
1680 const VkMemoryBarrier
* pMemoryBarriers
,
1681 uint32_t bufferMemoryBarrierCount
,
1682 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1683 uint32_t imageMemoryBarrierCount
,
1684 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1686 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1688 /* XXX: Right now, we're really dumb and just flush whatever categories
1689 * the app asks for. One of these days we may make this a bit better
1690 * but right now that's all the hardware allows for in most areas.
1692 VkAccessFlags src_flags
= 0;
1693 VkAccessFlags dst_flags
= 0;
1695 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1696 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1697 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1700 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1701 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1702 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1705 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1706 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1707 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1708 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1709 const VkImageSubresourceRange
*range
=
1710 &pImageMemoryBarriers
[i
].subresourceRange
;
1712 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1713 transition_depth_buffer(cmd_buffer
, image
,
1714 pImageMemoryBarriers
[i
].oldLayout
,
1715 pImageMemoryBarriers
[i
].newLayout
);
1716 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1717 VkImageAspectFlags color_aspects
=
1718 anv_image_expand_aspects(image
, range
->aspectMask
);
1719 uint32_t aspect_bit
;
1721 uint32_t base_layer
, layer_count
;
1722 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1724 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1726 base_layer
= range
->baseArrayLayer
;
1727 layer_count
= anv_get_layerCount(image
, range
);
1730 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1731 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1732 range
->baseMipLevel
,
1733 anv_get_levelCount(image
, range
),
1734 base_layer
, layer_count
,
1735 pImageMemoryBarriers
[i
].oldLayout
,
1736 pImageMemoryBarriers
[i
].newLayout
);
1741 cmd_buffer
->state
.pending_pipe_bits
|=
1742 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1743 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1747 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1749 VkShaderStageFlags stages
=
1750 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1752 /* In order to avoid thrash, we assume that vertex and fragment stages
1753 * always exist. In the rare case where one is missing *and* the other
1754 * uses push concstants, this may be suboptimal. However, avoiding stalls
1755 * seems more important.
1757 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1759 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1763 const unsigned push_constant_kb
= 32;
1764 #elif GEN_IS_HASWELL
1765 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1767 const unsigned push_constant_kb
= 16;
1770 const unsigned num_stages
=
1771 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1772 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1774 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1775 * units of 2KB. Incidentally, these are the same platforms that have
1776 * 32KB worth of push constant space.
1778 if (push_constant_kb
== 32)
1779 size_per_stage
&= ~1u;
1781 uint32_t kb_used
= 0;
1782 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1783 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1784 anv_batch_emit(&cmd_buffer
->batch
,
1785 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1786 alloc
._3DCommandSubOpcode
= 18 + i
;
1787 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1788 alloc
.ConstantBufferSize
= push_size
;
1790 kb_used
+= push_size
;
1793 anv_batch_emit(&cmd_buffer
->batch
,
1794 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1795 alloc
.ConstantBufferOffset
= kb_used
;
1796 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1799 cmd_buffer
->state
.push_constant_stages
= stages
;
1801 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1803 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1804 * the next 3DPRIMITIVE command after programming the
1805 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1807 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1808 * pipeline setup, we need to dirty push constants.
1810 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1813 static const struct anv_descriptor
*
1814 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1815 const struct anv_pipeline_binding
*binding
)
1817 assert(binding
->set
< MAX_SETS
);
1818 const struct anv_descriptor_set
*set
=
1819 pipe_state
->descriptors
[binding
->set
];
1820 const uint32_t offset
=
1821 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1822 return &set
->descriptors
[offset
+ binding
->index
];
1826 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1827 const struct anv_pipeline_binding
*binding
)
1829 assert(binding
->set
< MAX_SETS
);
1830 const struct anv_descriptor_set
*set
=
1831 pipe_state
->descriptors
[binding
->set
];
1833 uint32_t dynamic_offset_idx
=
1834 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1835 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1838 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1842 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1843 gl_shader_stage stage
,
1844 struct anv_state
*bt_state
)
1846 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1847 struct anv_cmd_pipeline_state
*pipe_state
;
1848 struct anv_pipeline
*pipeline
;
1849 uint32_t bias
, state_offset
;
1852 case MESA_SHADER_COMPUTE
:
1853 pipe_state
= &cmd_buffer
->state
.compute
.base
;
1857 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
1861 pipeline
= pipe_state
->pipeline
;
1863 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1864 *bt_state
= (struct anv_state
) { 0, };
1868 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1869 if (bias
+ map
->surface_count
== 0) {
1870 *bt_state
= (struct anv_state
) { 0, };
1874 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1875 bias
+ map
->surface_count
,
1877 uint32_t *bt_map
= bt_state
->map
;
1879 if (bt_state
->map
== NULL
)
1880 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1882 if (stage
== MESA_SHADER_COMPUTE
&&
1883 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
1884 struct anv_bo
*bo
= cmd_buffer
->state
.compute
.num_workgroups
.bo
;
1885 uint32_t bo_offset
= cmd_buffer
->state
.compute
.num_workgroups
.offset
;
1887 struct anv_state surface_state
;
1889 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1891 const enum isl_format format
=
1892 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1893 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1894 format
, bo_offset
, 12, 1);
1896 bt_map
[0] = surface_state
.offset
+ state_offset
;
1897 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1900 if (map
->surface_count
== 0)
1903 if (map
->image_count
> 0) {
1905 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1906 if (result
!= VK_SUCCESS
)
1909 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1913 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1914 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1916 struct anv_state surface_state
;
1918 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1919 /* Color attachment binding */
1920 assert(stage
== MESA_SHADER_FRAGMENT
);
1921 assert(binding
->binding
== 0);
1922 if (binding
->index
< subpass
->color_count
) {
1923 const unsigned att
=
1924 subpass
->color_attachments
[binding
->index
].attachment
;
1926 /* From the Vulkan 1.0.46 spec:
1928 * "If any color or depth/stencil attachments are
1929 * VK_ATTACHMENT_UNUSED, then no writes occur for those
1932 if (att
== VK_ATTACHMENT_UNUSED
) {
1933 surface_state
= cmd_buffer
->state
.null_surface_state
;
1935 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
1938 surface_state
= cmd_buffer
->state
.null_surface_state
;
1941 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1945 const struct anv_descriptor
*desc
=
1946 anv_descriptor_for_binding(pipe_state
, binding
);
1948 switch (desc
->type
) {
1949 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1950 /* Nothing for us to do here */
1953 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1954 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
1955 struct anv_surface_state sstate
=
1956 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
1957 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
1958 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
1959 surface_state
= sstate
.state
;
1960 assert(surface_state
.alloc_size
);
1961 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1962 binding
->plane
, sstate
);
1965 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1966 assert(stage
== MESA_SHADER_FRAGMENT
);
1967 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
1968 /* For depth and stencil input attachments, we treat it like any
1969 * old texture that a user may have bound.
1971 struct anv_surface_state sstate
=
1972 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
1973 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
1974 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
1975 surface_state
= sstate
.state
;
1976 assert(surface_state
.alloc_size
);
1977 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1978 binding
->plane
, sstate
);
1980 /* For color input attachments, we create the surface state at
1981 * vkBeginRenderPass time so that we can include aux and clear
1982 * color information.
1984 assert(binding
->input_attachment_index
< subpass
->input_count
);
1985 const unsigned subpass_att
= binding
->input_attachment_index
;
1986 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
1987 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
1991 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1992 struct anv_surface_state sstate
= (binding
->write_only
)
1993 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
1994 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
1995 surface_state
= sstate
.state
;
1996 assert(surface_state
.alloc_size
);
1997 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1998 binding
->plane
, sstate
);
2000 struct brw_image_param
*image_param
=
2001 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2003 *image_param
= desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2004 image_param
->surface_idx
= bias
+ s
;
2008 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2009 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2010 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2011 surface_state
= desc
->buffer_view
->surface_state
;
2012 assert(surface_state
.alloc_size
);
2013 add_surface_state_reloc(cmd_buffer
, surface_state
,
2014 desc
->buffer_view
->bo
,
2015 desc
->buffer_view
->offset
);
2018 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2019 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2020 /* Compute the offset within the buffer */
2021 uint32_t dynamic_offset
=
2022 dynamic_offset_for_binding(pipe_state
, binding
);
2023 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2024 /* Clamp to the buffer size */
2025 offset
= MIN2(offset
, desc
->buffer
->size
);
2026 /* Clamp the range to the buffer size */
2027 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2030 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2031 enum isl_format format
=
2032 anv_isl_format_for_descriptor_type(desc
->type
);
2034 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2035 format
, offset
, range
, 1);
2036 add_surface_state_reloc(cmd_buffer
, surface_state
,
2038 desc
->buffer
->offset
+ offset
);
2042 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2043 surface_state
= (binding
->write_only
)
2044 ? desc
->buffer_view
->writeonly_storage_surface_state
2045 : desc
->buffer_view
->storage_surface_state
;
2046 assert(surface_state
.alloc_size
);
2047 add_surface_state_reloc(cmd_buffer
, surface_state
,
2048 desc
->buffer_view
->bo
,
2049 desc
->buffer_view
->offset
);
2051 struct brw_image_param
*image_param
=
2052 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2054 *image_param
= desc
->buffer_view
->storage_image_param
;
2055 image_param
->surface_idx
= bias
+ s
;
2059 assert(!"Invalid descriptor type");
2063 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2065 assert(image
== map
->image_count
);
2068 anv_state_flush(cmd_buffer
->device
, *bt_state
);
2071 /* The PIPE_CONTROL command description says:
2073 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2074 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2075 * Target Cache Flush by enabling this bit. When render target flush
2076 * is set due to new association of BTI, PS Scoreboard Stall bit must
2077 * be set in this packet."
2079 * FINISHME: Currently we shuffle around the surface states in the binding
2080 * table based on if they are getting used or not. So, we've to do below
2081 * pipe control flush for every binding table upload. Make changes so
2082 * that we do it only when we modify render target surface states.
2084 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2085 pc
.RenderTargetCacheFlushEnable
= true;
2086 pc
.StallAtPixelScoreboard
= true;
2094 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2095 gl_shader_stage stage
,
2096 struct anv_state
*state
)
2098 struct anv_cmd_pipeline_state
*pipe_state
=
2099 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2100 &cmd_buffer
->state
.gfx
.base
;
2101 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2103 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2104 *state
= (struct anv_state
) { 0, };
2108 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2109 if (map
->sampler_count
== 0) {
2110 *state
= (struct anv_state
) { 0, };
2114 uint32_t size
= map
->sampler_count
* 16;
2115 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2117 if (state
->map
== NULL
)
2118 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2120 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2121 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2122 const struct anv_descriptor
*desc
=
2123 anv_descriptor_for_binding(pipe_state
, binding
);
2125 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2126 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2129 struct anv_sampler
*sampler
= desc
->sampler
;
2131 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2132 * happens to be zero.
2134 if (sampler
== NULL
)
2137 memcpy(state
->map
+ (s
* 16),
2138 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2141 anv_state_flush(cmd_buffer
->device
, *state
);
2147 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2149 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2151 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2152 pipeline
->active_stages
;
2154 VkResult result
= VK_SUCCESS
;
2155 anv_foreach_stage(s
, dirty
) {
2156 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2157 if (result
!= VK_SUCCESS
)
2159 result
= emit_binding_table(cmd_buffer
, s
,
2160 &cmd_buffer
->state
.binding_tables
[s
]);
2161 if (result
!= VK_SUCCESS
)
2165 if (result
!= VK_SUCCESS
) {
2166 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2168 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2169 if (result
!= VK_SUCCESS
)
2172 /* Re-emit state base addresses so we get the new surface state base
2173 * address before we start emitting binding tables etc.
2175 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2177 /* Re-emit all active binding tables */
2178 dirty
|= pipeline
->active_stages
;
2179 anv_foreach_stage(s
, dirty
) {
2180 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2181 if (result
!= VK_SUCCESS
) {
2182 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2185 result
= emit_binding_table(cmd_buffer
, s
,
2186 &cmd_buffer
->state
.binding_tables
[s
]);
2187 if (result
!= VK_SUCCESS
) {
2188 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2194 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2200 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2203 static const uint32_t sampler_state_opcodes
[] = {
2204 [MESA_SHADER_VERTEX
] = 43,
2205 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2206 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2207 [MESA_SHADER_GEOMETRY
] = 46,
2208 [MESA_SHADER_FRAGMENT
] = 47,
2209 [MESA_SHADER_COMPUTE
] = 0,
2212 static const uint32_t binding_table_opcodes
[] = {
2213 [MESA_SHADER_VERTEX
] = 38,
2214 [MESA_SHADER_TESS_CTRL
] = 39,
2215 [MESA_SHADER_TESS_EVAL
] = 40,
2216 [MESA_SHADER_GEOMETRY
] = 41,
2217 [MESA_SHADER_FRAGMENT
] = 42,
2218 [MESA_SHADER_COMPUTE
] = 0,
2221 anv_foreach_stage(s
, stages
) {
2222 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2223 assert(binding_table_opcodes
[s
] > 0);
2225 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2226 anv_batch_emit(&cmd_buffer
->batch
,
2227 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2228 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2229 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2233 /* Always emit binding table pointers if we're asked to, since on SKL
2234 * this is what flushes push constants. */
2235 anv_batch_emit(&cmd_buffer
->batch
,
2236 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2237 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2238 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2244 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2245 VkShaderStageFlags dirty_stages
)
2247 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2248 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2250 static const uint32_t push_constant_opcodes
[] = {
2251 [MESA_SHADER_VERTEX
] = 21,
2252 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2253 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2254 [MESA_SHADER_GEOMETRY
] = 22,
2255 [MESA_SHADER_FRAGMENT
] = 23,
2256 [MESA_SHADER_COMPUTE
] = 0,
2259 VkShaderStageFlags flushed
= 0;
2261 anv_foreach_stage(stage
, dirty_stages
) {
2262 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2263 assert(push_constant_opcodes
[stage
] > 0);
2265 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2266 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2268 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2269 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2270 const struct brw_stage_prog_data
*prog_data
=
2271 pipeline
->shaders
[stage
]->prog_data
;
2272 const struct anv_pipeline_bind_map
*bind_map
=
2273 &pipeline
->shaders
[stage
]->bind_map
;
2275 /* The Skylake PRM contains the following restriction:
2277 * "The driver must ensure The following case does not occur
2278 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2279 * buffer 3 read length equal to zero committed followed by a
2280 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2283 * To avoid this, we program the buffers in the highest slots.
2284 * This way, slot 0 is only used if slot 3 is also used.
2288 for (int i
= 3; i
>= 0; i
--) {
2289 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2290 if (range
->length
== 0)
2293 const unsigned surface
=
2294 prog_data
->binding_table
.ubo_start
+ range
->block
;
2296 assert(surface
<= bind_map
->surface_count
);
2297 const struct anv_pipeline_binding
*binding
=
2298 &bind_map
->surface_to_descriptor
[surface
];
2300 const struct anv_descriptor
*desc
=
2301 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2303 struct anv_address read_addr
;
2305 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2306 read_len
= MIN2(range
->length
,
2307 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2308 read_addr
= (struct anv_address
) {
2309 .bo
= desc
->buffer_view
->bo
,
2310 .offset
= desc
->buffer_view
->offset
+
2314 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2316 uint32_t dynamic_offset
=
2317 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2318 uint32_t buf_offset
=
2319 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2320 uint32_t buf_range
=
2321 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2323 read_len
= MIN2(range
->length
,
2324 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2325 read_addr
= (struct anv_address
) {
2326 .bo
= desc
->buffer
->bo
,
2327 .offset
= desc
->buffer
->offset
+ buf_offset
+
2333 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2334 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2339 struct anv_state state
=
2340 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2342 if (state
.alloc_size
> 0) {
2343 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2344 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2345 .offset
= state
.offset
,
2347 c
.ConstantBody
.ReadLength
[n
] =
2348 DIV_ROUND_UP(state
.alloc_size
, 32);
2351 /* For Ivy Bridge, the push constants packets have a different
2352 * rule that would require us to iterate in the other direction
2353 * and possibly mess around with dynamic state base address.
2354 * Don't bother; just emit regular push constants at n = 0.
2356 struct anv_state state
=
2357 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2359 if (state
.alloc_size
> 0) {
2360 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2361 c
.ConstantBody
.ReadLength
[0] =
2362 DIV_ROUND_UP(state
.alloc_size
, 32);
2368 flushed
|= mesa_to_vk_shader_stage(stage
);
2371 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2375 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2377 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2380 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2382 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2384 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2386 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2389 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2390 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2392 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2393 GENX(3DSTATE_VERTEX_BUFFERS
));
2395 for_each_bit(vb
, vb_emit
) {
2396 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2397 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2399 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2400 .VertexBufferIndex
= vb
,
2403 .MemoryObjectControlState
= GENX(MOCS
),
2405 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
2406 /* Our implementation of VK_KHR_multiview uses instancing to draw
2407 * the different views. If the client asks for instancing, we
2408 * need to use the Instance Data Step Rate to ensure that we
2409 * repeat the client's per-instance data once for each view.
2411 .InstanceDataStepRate
= anv_subpass_view_count(pipeline
->subpass
),
2412 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2415 .AddressModifyEnable
= true,
2416 .BufferPitch
= pipeline
->binding_stride
[vb
],
2417 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
2420 .BufferSize
= buffer
->size
- offset
2422 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
2426 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2431 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2433 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2434 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2436 /* The exact descriptor layout is pulled from the pipeline, so we need
2437 * to re-emit binding tables on every pipeline change.
2439 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2441 /* If the pipeline changed, we may need to re-allocate push constant
2444 cmd_buffer_alloc_push_constants(cmd_buffer
);
2448 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2449 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2450 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2452 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2453 * stall needs to be sent just prior to any 3DSTATE_VS,
2454 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2455 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2456 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2457 * PIPE_CONTROL needs to be sent before any combination of VS
2458 * associated 3DSTATE."
2460 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2461 pc
.DepthStallEnable
= true;
2462 pc
.PostSyncOperation
= WriteImmediateData
;
2464 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2469 /* Render targets live in the same binding table as fragment descriptors */
2470 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2471 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2473 /* We emit the binding tables and sampler tables first, then emit push
2474 * constants and then finally emit binding table and sampler table
2475 * pointers. It has to happen in this order, since emitting the binding
2476 * tables may change the push constants (in case of storage images). After
2477 * emitting push constants, on SKL+ we have to emit the corresponding
2478 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2481 if (cmd_buffer
->state
.descriptors_dirty
)
2482 dirty
= flush_descriptor_sets(cmd_buffer
);
2484 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2485 /* Because we're pushing UBOs, we have to push whenever either
2486 * descriptors or push constants is dirty.
2488 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2489 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2490 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2494 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2496 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2497 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2499 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2500 ANV_CMD_DIRTY_PIPELINE
)) {
2501 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2502 pipeline
->depth_clamp_enable
);
2505 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
2506 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2508 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2510 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2514 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2515 struct anv_bo
*bo
, uint32_t offset
,
2516 uint32_t size
, uint32_t index
)
2518 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2519 GENX(3DSTATE_VERTEX_BUFFERS
));
2521 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2522 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2523 .VertexBufferIndex
= index
,
2524 .AddressModifyEnable
= true,
2527 .MemoryObjectControlState
= GENX(MOCS
),
2528 .BufferStartingAddress
= { bo
, offset
},
2531 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2532 .BufferStartingAddress
= { bo
, offset
},
2533 .EndAddress
= { bo
, offset
+ size
},
2539 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2540 struct anv_bo
*bo
, uint32_t offset
)
2542 emit_vertex_bo(cmd_buffer
, bo
, offset
, 8, ANV_SVGS_VB_INDEX
);
2546 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2547 uint32_t base_vertex
, uint32_t base_instance
)
2549 struct anv_state id_state
=
2550 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2552 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2553 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2555 anv_state_flush(cmd_buffer
->device
, id_state
);
2557 emit_base_vertex_instance_bo(cmd_buffer
,
2558 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
, id_state
.offset
);
2562 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2564 struct anv_state state
=
2565 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2567 ((uint32_t *)state
.map
)[0] = draw_index
;
2569 anv_state_flush(cmd_buffer
->device
, state
);
2571 emit_vertex_bo(cmd_buffer
,
2572 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2573 state
.offset
, 4, ANV_DRAWID_VB_INDEX
);
2577 VkCommandBuffer commandBuffer
,
2578 uint32_t vertexCount
,
2579 uint32_t instanceCount
,
2580 uint32_t firstVertex
,
2581 uint32_t firstInstance
)
2583 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2584 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2585 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2587 if (anv_batch_has_error(&cmd_buffer
->batch
))
2590 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2592 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2593 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2594 if (vs_prog_data
->uses_drawid
)
2595 emit_draw_index(cmd_buffer
, 0);
2597 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2598 * different views. We need to multiply instanceCount by the view count.
2600 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2602 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2603 prim
.VertexAccessType
= SEQUENTIAL
;
2604 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2605 prim
.VertexCountPerInstance
= vertexCount
;
2606 prim
.StartVertexLocation
= firstVertex
;
2607 prim
.InstanceCount
= instanceCount
;
2608 prim
.StartInstanceLocation
= firstInstance
;
2609 prim
.BaseVertexLocation
= 0;
2613 void genX(CmdDrawIndexed
)(
2614 VkCommandBuffer commandBuffer
,
2615 uint32_t indexCount
,
2616 uint32_t instanceCount
,
2617 uint32_t firstIndex
,
2618 int32_t vertexOffset
,
2619 uint32_t firstInstance
)
2621 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2622 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2623 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2625 if (anv_batch_has_error(&cmd_buffer
->batch
))
2628 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2630 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2631 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2632 if (vs_prog_data
->uses_drawid
)
2633 emit_draw_index(cmd_buffer
, 0);
2635 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2636 * different views. We need to multiply instanceCount by the view count.
2638 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2640 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2641 prim
.VertexAccessType
= RANDOM
;
2642 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2643 prim
.VertexCountPerInstance
= indexCount
;
2644 prim
.StartVertexLocation
= firstIndex
;
2645 prim
.InstanceCount
= instanceCount
;
2646 prim
.StartInstanceLocation
= firstInstance
;
2647 prim
.BaseVertexLocation
= vertexOffset
;
2651 /* Auto-Draw / Indirect Registers */
2652 #define GEN7_3DPRIM_END_OFFSET 0x2420
2653 #define GEN7_3DPRIM_START_VERTEX 0x2430
2654 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2655 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2656 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2657 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2659 /* MI_MATH only exists on Haswell+ */
2660 #if GEN_IS_HASWELL || GEN_GEN >= 8
2662 /* Emit dwords to multiply GPR0 by N */
2664 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2666 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2668 #define append_alu(opcode, operand1, operand2) \
2669 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2672 unsigned top_bit
= 31 - __builtin_clz(N
);
2673 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2674 /* We get our initial data in GPR0 and we write the final data out to
2675 * GPR0 but we use GPR1 as our scratch register.
2677 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2678 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2680 /* Shift the current value left by 1 */
2681 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2682 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2683 append_alu(MI_ALU_ADD
, 0, 0);
2686 /* Store ACCU to R1 and add R0 to R1 */
2687 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2688 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2689 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2690 append_alu(MI_ALU_ADD
, 0, 0);
2693 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2700 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2702 uint32_t num_dwords
;
2703 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2705 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2706 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2709 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2712 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2713 struct anv_buffer
*buffer
, uint64_t offset
,
2716 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2717 struct anv_bo
*bo
= buffer
->bo
;
2718 uint32_t bo_offset
= buffer
->offset
+ offset
;
2720 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
2722 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2723 if (view_count
> 1) {
2724 #if GEN_IS_HASWELL || GEN_GEN >= 8
2725 emit_lrm(batch
, CS_GPR(0), bo
, bo_offset
+ 4);
2726 emit_mul_gpr0(batch
, view_count
);
2727 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2729 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2730 "MI_MATH is not supported on Ivy Bridge");
2731 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2734 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2737 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
2740 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
2741 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
2743 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
2744 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2748 void genX(CmdDrawIndirect
)(
2749 VkCommandBuffer commandBuffer
,
2751 VkDeviceSize offset
,
2755 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2756 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2757 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2758 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2760 if (anv_batch_has_error(&cmd_buffer
->batch
))
2763 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2765 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2766 struct anv_bo
*bo
= buffer
->bo
;
2767 uint32_t bo_offset
= buffer
->offset
+ offset
;
2769 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2770 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
2771 if (vs_prog_data
->uses_drawid
)
2772 emit_draw_index(cmd_buffer
, i
);
2774 load_indirect_parameters(cmd_buffer
, buffer
, offset
, false);
2776 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2777 prim
.IndirectParameterEnable
= true;
2778 prim
.VertexAccessType
= SEQUENTIAL
;
2779 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2786 void genX(CmdDrawIndexedIndirect
)(
2787 VkCommandBuffer commandBuffer
,
2789 VkDeviceSize offset
,
2793 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2794 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2795 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2796 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2798 if (anv_batch_has_error(&cmd_buffer
->batch
))
2801 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2803 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2804 struct anv_bo
*bo
= buffer
->bo
;
2805 uint32_t bo_offset
= buffer
->offset
+ offset
;
2807 /* TODO: We need to stomp base vertex to 0 somehow */
2808 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2809 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
2810 if (vs_prog_data
->uses_drawid
)
2811 emit_draw_index(cmd_buffer
, i
);
2813 load_indirect_parameters(cmd_buffer
, buffer
, offset
, true);
2815 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2816 prim
.IndirectParameterEnable
= true;
2817 prim
.VertexAccessType
= RANDOM
;
2818 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2826 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2828 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2829 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2832 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2833 if (result
!= VK_SUCCESS
) {
2834 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2836 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2837 if (result
!= VK_SUCCESS
)
2840 /* Re-emit state base addresses so we get the new surface state base
2841 * address before we start emitting binding tables etc.
2843 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2845 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2846 if (result
!= VK_SUCCESS
) {
2847 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2852 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
2853 if (result
!= VK_SUCCESS
) {
2854 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2858 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
2859 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2860 .BindingTablePointer
= surfaces
.offset
,
2861 .SamplerStatePointer
= samplers
.offset
,
2863 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
2865 struct anv_state state
=
2866 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
2867 pipeline
->interface_descriptor_data
,
2868 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
2871 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
2872 anv_batch_emit(&cmd_buffer
->batch
,
2873 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
2874 mid
.InterfaceDescriptorTotalLength
= size
;
2875 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
2882 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2884 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2885 MAYBE_UNUSED VkResult result
;
2887 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
2889 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2891 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
2893 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
2894 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
2896 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
2897 * the only bits that are changed are scoreboard related: Scoreboard
2898 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
2899 * these scoreboard related states, a MEDIA_STATE_FLUSH is
2902 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2903 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2905 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2908 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
2909 cmd_buffer
->state
.compute
.pipeline_dirty
) {
2910 /* FIXME: figure out descriptors for gen7 */
2911 result
= flush_compute_descriptor_set(cmd_buffer
);
2912 if (result
!= VK_SUCCESS
)
2915 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
2918 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
2919 struct anv_state push_state
=
2920 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
2922 if (push_state
.alloc_size
) {
2923 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
2924 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
2925 curbe
.CURBEDataStartAddress
= push_state
.offset
;
2930 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
2932 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2938 verify_cmd_parser(const struct anv_device
*device
,
2939 int required_version
,
2940 const char *function
)
2942 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
2943 return vk_errorf(device
->instance
, device
->instance
,
2944 VK_ERROR_FEATURE_NOT_PRESENT
,
2945 "cmd parser version %d is required for %s",
2946 required_version
, function
);
2954 void genX(CmdDispatch
)(
2955 VkCommandBuffer commandBuffer
,
2960 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2961 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2962 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
2964 if (anv_batch_has_error(&cmd_buffer
->batch
))
2967 if (prog_data
->uses_num_work_groups
) {
2968 struct anv_state state
=
2969 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
2970 uint32_t *sizes
= state
.map
;
2974 anv_state_flush(cmd_buffer
->device
, state
);
2975 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
2976 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2977 .offset
= state
.offset
,
2981 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2983 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
2984 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2985 ggw
.ThreadDepthCounterMaximum
= 0;
2986 ggw
.ThreadHeightCounterMaximum
= 0;
2987 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2988 ggw
.ThreadGroupIDXDimension
= x
;
2989 ggw
.ThreadGroupIDYDimension
= y
;
2990 ggw
.ThreadGroupIDZDimension
= z
;
2991 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2992 ggw
.BottomExecutionMask
= 0xffffffff;
2995 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2998 #define GPGPU_DISPATCHDIMX 0x2500
2999 #define GPGPU_DISPATCHDIMY 0x2504
3000 #define GPGPU_DISPATCHDIMZ 0x2508
3002 void genX(CmdDispatchIndirect
)(
3003 VkCommandBuffer commandBuffer
,
3005 VkDeviceSize offset
)
3007 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3008 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3009 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3010 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3011 struct anv_bo
*bo
= buffer
->bo
;
3012 uint32_t bo_offset
= buffer
->offset
+ offset
;
3013 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3016 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3017 * indirect dispatch registers to be written.
3019 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3020 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3024 if (prog_data
->uses_num_work_groups
) {
3025 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3027 .offset
= bo_offset
,
3031 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3033 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
3034 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
3035 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
3038 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3039 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3040 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3041 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3043 /* Load compute_dispatch_indirect_x_size into SRC0 */
3044 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
3046 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3047 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3048 mip
.LoadOperation
= LOAD_LOAD
;
3049 mip
.CombineOperation
= COMBINE_SET
;
3050 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3053 /* Load compute_dispatch_indirect_y_size into SRC0 */
3054 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
3056 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3057 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3058 mip
.LoadOperation
= LOAD_LOAD
;
3059 mip
.CombineOperation
= COMBINE_OR
;
3060 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3063 /* Load compute_dispatch_indirect_z_size into SRC0 */
3064 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
3066 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3067 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3068 mip
.LoadOperation
= LOAD_LOAD
;
3069 mip
.CombineOperation
= COMBINE_OR
;
3070 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3073 /* predicate = !predicate; */
3074 #define COMPARE_FALSE 1
3075 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3076 mip
.LoadOperation
= LOAD_LOADINV
;
3077 mip
.CombineOperation
= COMBINE_OR
;
3078 mip
.CompareOperation
= COMPARE_FALSE
;
3082 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3083 ggw
.IndirectParameterEnable
= true;
3084 ggw
.PredicateEnable
= GEN_GEN
<= 7;
3085 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3086 ggw
.ThreadDepthCounterMaximum
= 0;
3087 ggw
.ThreadHeightCounterMaximum
= 0;
3088 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3089 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3090 ggw
.BottomExecutionMask
= 0xffffffff;
3093 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3097 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3100 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3102 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3105 #if GEN_GEN >= 8 && GEN_GEN < 10
3106 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3108 * Software must clear the COLOR_CALC_STATE Valid field in
3109 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3110 * with Pipeline Select set to GPGPU.
3112 * The internal hardware docs recommend the same workaround for Gen9
3115 if (pipeline
== GPGPU
)
3116 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3119 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3120 * PIPELINE_SELECT [DevBWR+]":
3124 * Software must ensure all the write caches are flushed through a
3125 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3126 * command to invalidate read only caches prior to programming
3127 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3129 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3130 pc
.RenderTargetCacheFlushEnable
= true;
3131 pc
.DepthCacheFlushEnable
= true;
3132 pc
.DCFlushEnable
= true;
3133 pc
.PostSyncOperation
= NoWrite
;
3134 pc
.CommandStreamerStallEnable
= true;
3137 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3138 pc
.TextureCacheInvalidationEnable
= true;
3139 pc
.ConstantCacheInvalidationEnable
= true;
3140 pc
.StateCacheInvalidationEnable
= true;
3141 pc
.InstructionCacheInvalidateEnable
= true;
3142 pc
.PostSyncOperation
= NoWrite
;
3145 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3149 ps
.PipelineSelection
= pipeline
;
3153 if (devinfo
->is_geminilake
) {
3156 * "This chicken bit works around a hardware issue with barrier logic
3157 * encountered when switching between GPGPU and 3D pipelines. To
3158 * workaround the issue, this mode bit should be set after a pipeline
3162 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3164 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3165 : GLK_BARRIER_MODE_3D_HULL
,
3166 .GLKBarrierModeMask
= 1);
3167 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3171 cmd_buffer
->state
.current_pipeline
= pipeline
;
3175 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3177 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3181 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3183 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3187 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3192 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3194 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3195 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3196 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3197 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3198 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3199 * Depth Flush Bit set, followed by another pipelined depth stall
3200 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3201 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3202 * via a preceding MI_FLUSH)."
3204 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3205 pipe
.DepthStallEnable
= true;
3207 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3208 pipe
.DepthCacheFlushEnable
= true;
3210 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3211 pipe
.DepthStallEnable
= true;
3216 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3218 struct anv_device
*device
= cmd_buffer
->device
;
3219 const struct anv_image_view
*iview
=
3220 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3221 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3223 /* FIXME: Width and Height are wrong */
3225 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3227 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3228 device
->isl_dev
.ds
.size
/ 4);
3232 struct isl_depth_stencil_hiz_emit_info info
= {
3233 .mocs
= device
->default_mocs
,
3237 info
.view
= &iview
->planes
[0].isl
;
3239 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3240 uint32_t depth_plane
=
3241 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3242 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3244 info
.depth_surf
= &surface
->isl
;
3246 info
.depth_address
=
3247 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3248 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3249 image
->planes
[depth_plane
].bo
,
3250 image
->planes
[depth_plane
].bo_offset
+
3254 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.attachment
;
3255 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3256 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3257 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3260 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3261 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3262 image
->planes
[depth_plane
].bo
,
3263 image
->planes
[depth_plane
].bo_offset
+
3264 image
->planes
[depth_plane
].aux_surface
.offset
);
3266 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3270 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3271 uint32_t stencil_plane
=
3272 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3273 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3275 info
.stencil_surf
= &surface
->isl
;
3277 info
.stencil_address
=
3278 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3279 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3280 image
->planes
[stencil_plane
].bo
,
3281 image
->planes
[stencil_plane
].bo_offset
+ surface
->offset
);
3284 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3286 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3290 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3291 uint32_t subpass_id
)
3293 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3294 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3295 cmd_state
->subpass
= subpass
;
3297 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3299 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3300 * different views. If the client asks for instancing, we need to use the
3301 * Instance Data Step Rate to ensure that we repeat the client's
3302 * per-instance data once for each view. Since this bit is in
3303 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3307 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3309 /* It is possible to start a render pass with an old pipeline. Because the
3310 * render pass and subpass index are both baked into the pipeline, this is
3311 * highly unlikely. In order to do so, it requires that you have a render
3312 * pass with a single subpass and that you use that render pass twice
3313 * back-to-back and use the same pipeline at the start of the second render
3314 * pass as at the end of the first. In order to avoid unpredictable issues
3315 * with this edge case, we just dirty the pipeline at the start of every
3318 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3320 /* Accumulate any subpass flushes that need to happen before the subpass */
3321 cmd_buffer
->state
.pending_pipe_bits
|=
3322 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3324 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3325 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3327 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3328 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3329 if (a
== VK_ATTACHMENT_UNUSED
)
3332 assert(a
< cmd_state
->pass
->attachment_count
);
3333 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3335 struct anv_image_view
*iview
= fb
->attachments
[a
];
3336 const struct anv_image
*image
= iview
->image
;
3338 /* A resolve is necessary before use as an input attachment if the clear
3339 * color or auxiliary buffer usage isn't supported by the sampler.
3341 const bool input_needs_resolve
=
3342 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3343 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3345 VkImageLayout target_layout
;
3346 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3347 !input_needs_resolve
) {
3348 /* Layout transitions before the final only help to enable sampling
3349 * as an input attachment. If the input attachment supports sampling
3350 * using the auxiliary surface, we can skip such transitions by
3351 * making the target layout one that is CCS-aware.
3353 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3355 target_layout
= subpass
->attachments
[i
].layout
;
3358 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3359 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3361 uint32_t base_layer
, layer_count
;
3362 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3364 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3365 iview
->planes
[0].isl
.base_level
);
3367 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3368 layer_count
= fb
->layers
;
3371 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3372 iview
->planes
[0].isl
.base_level
, 1,
3373 base_layer
, layer_count
,
3374 att_state
->current_layout
, target_layout
);
3375 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3376 transition_depth_buffer(cmd_buffer
, image
,
3377 att_state
->current_layout
, target_layout
);
3378 att_state
->aux_usage
=
3379 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3380 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3382 att_state
->current_layout
= target_layout
;
3384 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3385 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3387 /* Multi-planar images are not supported as attachments */
3388 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3389 assert(image
->n_planes
== 1);
3391 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
3392 uint32_t clear_layer_count
= fb
->layers
;
3394 if (att_state
->fast_clear
) {
3395 /* We only support fast-clears on the first layer */
3396 assert(iview
->planes
[0].isl
.base_level
== 0);
3397 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3399 anv_image_ccs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3400 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
, false);
3402 clear_layer_count
--;
3404 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3405 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3406 true /* copy from ss */);
3408 if (att_state
->clear_color_is_zero
) {
3409 /* This image has the auxiliary buffer enabled. We can mark the
3410 * subresource as not needing a resolve because the clear color
3411 * will match what's in every RENDER_SURFACE_STATE object when
3412 * it's being used for sampling.
3414 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3415 VK_IMAGE_ASPECT_COLOR_BIT
,
3416 ANV_FAST_CLEAR_DEFAULT_VALUE
);
3418 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3419 VK_IMAGE_ASPECT_COLOR_BIT
,
3420 ANV_FAST_CLEAR_ANY
);
3424 if (clear_layer_count
> 0) {
3425 assert(image
->n_planes
== 1);
3426 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3427 att_state
->aux_usage
,
3428 iview
->planes
[0].isl
.format
,
3429 iview
->planes
[0].isl
.swizzle
,
3430 iview
->planes
[0].isl
.base_level
,
3431 base_clear_layer
, clear_layer_count
,
3433 vk_to_isl_color(att_state
->clear_value
.color
));
3435 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
3436 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3437 if (att_state
->fast_clear
) {
3438 /* We currently only support HiZ for single-layer images */
3439 assert(iview
->planes
[0].isl
.base_level
== 0);
3440 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3441 assert(fb
->layers
== 1);
3443 anv_image_hiz_clear(cmd_buffer
, image
,
3444 att_state
->pending_clear_aspects
,
3445 iview
->planes
[0].isl
.base_level
,
3446 iview
->planes
[0].isl
.base_array_layer
,
3447 fb
->layers
, render_area
,
3448 att_state
->clear_value
.depthStencil
.stencil
);
3450 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3451 att_state
->pending_clear_aspects
,
3452 att_state
->aux_usage
,
3453 iview
->planes
[0].isl
.base_level
,
3454 iview
->planes
[0].isl
.base_array_layer
,
3455 fb
->layers
, render_area
,
3456 att_state
->clear_value
.depthStencil
.depth
,
3457 att_state
->clear_value
.depthStencil
.stencil
);
3460 assert(att_state
->pending_clear_aspects
== 0);
3463 if (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3464 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
3465 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3466 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3467 false /* copy to ss */);
3470 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
3471 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3472 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3473 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3474 false /* copy to ss */);
3478 if (subpass
->attachments
[i
].usage
==
3479 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
3480 /* We assume that if we're starting a subpass, we're going to do some
3481 * rendering so we may end up with compressed data.
3483 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
3484 VK_IMAGE_ASPECT_COLOR_BIT
,
3485 att_state
->aux_usage
,
3486 iview
->planes
[0].isl
.base_level
,
3487 iview
->planes
[0].isl
.base_array_layer
,
3489 } else if (subpass
->attachments
[i
].usage
==
3490 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
3491 /* We may be writing depth or stencil so we need to mark the surface.
3492 * Unfortunately, there's no way to know at this point whether the
3493 * depth or stencil tests used will actually write to the surface.
3495 * Even though stencil may be plane 1, it always shares a base_level
3498 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
3499 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3500 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3501 VK_IMAGE_ASPECT_DEPTH_BIT
,
3502 att_state
->aux_usage
,
3503 ds_view
->base_level
,
3504 ds_view
->base_array_layer
,
3507 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
3508 /* Even though stencil may be plane 1, it always shares a
3509 * base_level with depth.
3511 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3512 VK_IMAGE_ASPECT_STENCIL_BIT
,
3514 ds_view
->base_level
,
3515 ds_view
->base_array_layer
,
3520 att_state
->pending_clear_aspects
= 0;
3521 att_state
->pending_load_aspects
= 0;
3524 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3528 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
3530 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3531 struct anv_subpass
*subpass
= cmd_state
->subpass
;
3532 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3534 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3536 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3537 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3538 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3539 if (a
== VK_ATTACHMENT_UNUSED
)
3542 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3545 assert(a
< cmd_state
->pass
->attachment_count
);
3546 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3547 struct anv_image_view
*iview
= fb
->attachments
[a
];
3548 const struct anv_image
*image
= iview
->image
;
3550 /* Transition the image into the final layout for this render pass */
3551 VkImageLayout target_layout
=
3552 cmd_state
->pass
->attachments
[a
].final_layout
;
3554 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3555 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3557 uint32_t base_layer
, layer_count
;
3558 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3560 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3561 iview
->planes
[0].isl
.base_level
);
3563 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3564 layer_count
= fb
->layers
;
3567 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3568 iview
->planes
[0].isl
.base_level
, 1,
3569 base_layer
, layer_count
,
3570 att_state
->current_layout
, target_layout
);
3571 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3572 transition_depth_buffer(cmd_buffer
, image
,
3573 att_state
->current_layout
, target_layout
);
3577 /* Accumulate any subpass flushes that need to happen after the subpass.
3578 * Yes, they do get accumulated twice in the NextSubpass case but since
3579 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
3580 * ORing the bits in twice so it's harmless.
3582 cmd_buffer
->state
.pending_pipe_bits
|=
3583 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
3586 void genX(CmdBeginRenderPass
)(
3587 VkCommandBuffer commandBuffer
,
3588 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3589 VkSubpassContents contents
)
3591 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3592 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3593 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3595 cmd_buffer
->state
.framebuffer
= framebuffer
;
3596 cmd_buffer
->state
.pass
= pass
;
3597 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3599 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3601 /* If we failed to setup the attachments we should not try to go further */
3602 if (result
!= VK_SUCCESS
) {
3603 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3607 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3609 cmd_buffer_begin_subpass(cmd_buffer
, 0);
3612 void genX(CmdNextSubpass
)(
3613 VkCommandBuffer commandBuffer
,
3614 VkSubpassContents contents
)
3616 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3618 if (anv_batch_has_error(&cmd_buffer
->batch
))
3621 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3623 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
3624 cmd_buffer_end_subpass(cmd_buffer
);
3625 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3628 void genX(CmdEndRenderPass
)(
3629 VkCommandBuffer commandBuffer
)
3631 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3633 if (anv_batch_has_error(&cmd_buffer
->batch
))
3636 cmd_buffer_end_subpass(cmd_buffer
);
3638 cmd_buffer
->state
.hiz_enabled
= false;
3641 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
3644 /* Remove references to render pass specific state. This enables us to
3645 * detect whether or not we're in a renderpass.
3647 cmd_buffer
->state
.framebuffer
= NULL
;
3648 cmd_buffer
->state
.pass
= NULL
;
3649 cmd_buffer
->state
.subpass
= NULL
;