2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "common/gen_l3_config.h"
31 #include "genxml/gen_macros.h"
32 #include "genxml/genX_pack.h"
35 emit_lrm(struct anv_batch
*batch
,
36 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
54 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
56 struct anv_device
*device
= cmd_buffer
->device
;
58 /* XXX: Do we need this on more than just BDW? */
60 /* Emit a render target cache flush.
62 * This isn't documented anywhere in the PRM. However, it seems to be
63 * necessary prior to changing the surface state base adress. Without
64 * this, we get GPU hangs when using multi-level command buffers which
65 * clear depth, reset state base address, and then go render stuff.
67 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
68 pc
.RenderTargetCacheFlushEnable
= true;
72 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
73 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
74 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
75 sba
.GeneralStateBaseAddressModifyEnable
= true;
77 sba
.SurfaceStateBaseAddress
=
78 anv_cmd_buffer_surface_base_address(cmd_buffer
);
79 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
80 sba
.SurfaceStateBaseAddressModifyEnable
= true;
82 sba
.DynamicStateBaseAddress
=
83 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
84 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
85 sba
.DynamicStateBaseAddressModifyEnable
= true;
87 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
88 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
89 sba
.IndirectObjectBaseAddressModifyEnable
= true;
91 sba
.InstructionBaseAddress
=
92 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
93 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
94 sba
.InstructionBaseAddressModifyEnable
= true;
97 /* Broadwell requires that we specify a buffer size for a bunch of
98 * these fields. However, since we will be growing the BO's live, we
99 * just set them all to the maximum.
101 sba
.GeneralStateBufferSize
= 0xfffff;
102 sba
.GeneralStateBufferSizeModifyEnable
= true;
103 sba
.DynamicStateBufferSize
= 0xfffff;
104 sba
.DynamicStateBufferSizeModifyEnable
= true;
105 sba
.IndirectObjectBufferSize
= 0xfffff;
106 sba
.IndirectObjectBufferSizeModifyEnable
= true;
107 sba
.InstructionBufferSize
= 0xfffff;
108 sba
.InstructionBuffersizeModifyEnable
= true;
112 /* After re-setting the surface state base address, we have to do some
113 * cache flusing so that the sampler engine will pick up the new
114 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
115 * Shared Function > 3D Sampler > State > State Caching (page 96):
117 * Coherency with system memory in the state cache, like the texture
118 * cache is handled partially by software. It is expected that the
119 * command stream or shader will issue Cache Flush operation or
120 * Cache_Flush sampler message to ensure that the L1 cache remains
121 * coherent with system memory.
125 * Whenever the value of the Dynamic_State_Base_Addr,
126 * Surface_State_Base_Addr are altered, the L1 state cache must be
127 * invalidated to ensure the new surface or sampler state is fetched
128 * from system memory.
130 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
131 * which, according the PIPE_CONTROL instruction documentation in the
134 * Setting this bit is independent of any other bit in this packet.
135 * This bit controls the invalidation of the L1 and L2 state caches
136 * at the top of the pipe i.e. at the parsing time.
138 * Unfortunately, experimentation seems to indicate that state cache
139 * invalidation through a PIPE_CONTROL does nothing whatsoever in
140 * regards to surface state and binding tables. In stead, it seems that
141 * invalidating the texture cache is what is actually needed.
143 * XXX: As far as we have been able to determine through
144 * experimentation, shows that flush the texture cache appears to be
145 * sufficient. The theory here is that all of the sampling/rendering
146 * units cache the binding table in the texture cache. However, we have
147 * yet to be able to actually confirm this.
149 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
150 pc
.TextureCacheInvalidationEnable
= true;
155 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
156 struct anv_state state
,
157 struct anv_bo
*bo
, uint32_t offset
)
159 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
161 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
162 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
166 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
167 const struct anv_image_view
*iview
,
168 enum isl_aux_usage aux_usage
,
169 struct anv_state state
)
171 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
173 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
174 state
.offset
+ isl_dev
->ss
.addr_offset
,
175 iview
->bo
, iview
->offset
);
177 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
178 uint32_t aux_offset
= iview
->offset
+ iview
->image
->aux_surface
.offset
;
180 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
181 * used to store other information. This should be ok, however, because
182 * surface buffer addresses are always 4K page alinged.
184 assert((aux_offset
& 0xfff) == 0);
185 uint32_t *aux_addr_dw
= state
.map
+ isl_dev
->ss
.aux_addr_offset
;
186 aux_offset
+= *aux_addr_dw
& 0xfff;
188 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
189 state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
190 iview
->bo
, aux_offset
);
194 static enum isl_aux_usage
195 fb_attachment_get_aux_usage(struct anv_device
*device
,
196 struct anv_framebuffer
*fb
,
199 struct anv_image_view
*iview
= fb
->attachments
[attachment
];
201 if (iview
->image
->aux_surface
.isl
.size
== 0)
202 return ISL_AUX_USAGE_NONE
; /* No aux surface */
204 assert(iview
->image
->aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
206 if (isl_format_supports_lossless_compression(&device
->info
,
208 return ISL_AUX_USAGE_CCS_E
;
210 return ISL_AUX_USAGE_NONE
;
214 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
216 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
219 /* We only allocate input attachment states for color and depth surfaces.
220 * Stencil doesn't allow compression so we can just use the texture surface
221 * state from the view
223 return vk_format_is_color(att
->format
) || vk_format_has_depth(att
->format
);
227 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
230 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
231 struct anv_render_pass
*pass
,
232 const VkRenderPassBeginInfo
*begin
)
234 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
235 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
237 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
239 if (pass
->attachment_count
== 0) {
240 state
->attachments
= NULL
;
244 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
245 pass
->attachment_count
*
246 sizeof(state
->attachments
[0]),
247 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
248 if (state
->attachments
== NULL
) {
249 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
253 bool need_null_state
= false;
254 unsigned num_states
= 0;
255 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
256 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
259 /* We need a null state for any depth-stencil-only subpasses.
260 * Importantly, this includes depth/stencil clears so we create one
261 * whenever we have depth or stencil
263 need_null_state
= true;
266 if (need_input_attachment_state(&pass
->attachments
[i
]))
269 num_states
+= need_null_state
;
271 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
272 state
->render_pass_states
=
273 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
274 num_states
* ss_stride
, isl_dev
->ss
.align
);
276 struct anv_state next_state
= state
->render_pass_states
;
277 next_state
.alloc_size
= isl_dev
->ss
.size
;
279 if (need_null_state
) {
280 state
->null_surface_state
= next_state
;
281 next_state
.offset
+= ss_stride
;
282 next_state
.map
+= ss_stride
;
285 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
286 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
287 state
->attachments
[i
].color_rt_state
= next_state
;
288 next_state
.offset
+= ss_stride
;
289 next_state
.map
+= ss_stride
;
292 if (need_input_attachment_state(&pass
->attachments
[i
])) {
293 state
->attachments
[i
].input_att_state
= next_state
;
294 next_state
.offset
+= ss_stride
;
295 next_state
.map
+= ss_stride
;
298 assert(next_state
.offset
== state
->render_pass_states
.offset
+
299 state
->render_pass_states
.alloc_size
);
302 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
303 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
305 if (need_null_state
) {
306 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
307 .SurfaceType
= SURFTYPE_NULL
,
308 .SurfaceArray
= framebuffer
->layers
> 0,
309 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
313 .TiledSurface
= true,
315 .Width
= framebuffer
->width
- 1,
316 .Height
= framebuffer
->height
- 1,
317 .Depth
= framebuffer
->layers
- 1,
318 .RenderTargetViewExtent
= framebuffer
->layers
- 1,
320 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
->null_surface_state
.map
,
324 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
325 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
326 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
327 VkImageAspectFlags clear_aspects
= 0;
329 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
330 /* color attachment */
331 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
332 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
335 /* depthstencil attachment */
336 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
337 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
338 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
340 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
341 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
342 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
346 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
348 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
350 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
351 assert(iview
->vk_format
== att
->format
);
353 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
354 state
->attachments
[i
].aux_usage
=
355 fb_attachment_get_aux_usage(cmd_buffer
->device
, framebuffer
, i
);
357 struct isl_view view
= iview
->isl
;
358 view
.usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
359 isl_surf_fill_state(isl_dev
,
360 state
->attachments
[i
].color_rt_state
.map
,
361 .surf
= &iview
->image
->color_surface
.isl
,
363 .aux_surf
= &iview
->image
->aux_surface
.isl
,
364 .aux_usage
= state
->attachments
[i
].aux_usage
,
365 .mocs
= cmd_buffer
->device
->default_mocs
);
367 add_image_view_relocs(cmd_buffer
, iview
,
368 state
->attachments
[i
].aux_usage
,
369 state
->attachments
[i
].color_rt_state
);
371 state
->attachments
[i
].aux_usage
= ISL_AUX_USAGE_NONE
;
374 if (need_input_attachment_state(&pass
->attachments
[i
])) {
375 const struct isl_surf
*surf
;
376 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
377 surf
= &iview
->image
->color_surface
.isl
;
379 surf
= &iview
->image
->depth_surface
.isl
;
382 struct isl_view view
= iview
->isl
;
383 view
.usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
384 isl_surf_fill_state(isl_dev
,
385 state
->attachments
[i
].input_att_state
.map
,
388 .aux_surf
= &iview
->image
->aux_surface
.isl
,
389 .aux_usage
= state
->attachments
[i
].aux_usage
,
390 .mocs
= cmd_buffer
->device
->default_mocs
);
392 add_image_view_relocs(cmd_buffer
, iview
,
393 state
->attachments
[i
].aux_usage
,
394 state
->attachments
[i
].input_att_state
);
398 if (!cmd_buffer
->device
->info
.has_llc
)
399 anv_state_clflush(state
->render_pass_states
);
404 genX(BeginCommandBuffer
)(
405 VkCommandBuffer commandBuffer
,
406 const VkCommandBufferBeginInfo
* pBeginInfo
)
408 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
410 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
411 * command buffer's state. Otherwise, we must *reset* its state. In both
414 * From the Vulkan 1.0 spec:
416 * If a command buffer is in the executable state and the command buffer
417 * was allocated from a command pool with the
418 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
419 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
420 * as if vkResetCommandBuffer had been called with
421 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
422 * the command buffer in the recording state.
424 anv_cmd_buffer_reset(cmd_buffer
);
426 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
428 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
429 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
431 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
433 if (cmd_buffer
->usage_flags
&
434 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
435 cmd_buffer
->state
.pass
=
436 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
437 cmd_buffer
->state
.subpass
=
438 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
439 cmd_buffer
->state
.framebuffer
= NULL
;
441 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, cmd_buffer
->state
.pass
,
444 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
451 genX(EndCommandBuffer
)(
452 VkCommandBuffer commandBuffer
)
454 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
456 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
458 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
464 genX(CmdExecuteCommands
)(
465 VkCommandBuffer commandBuffer
,
466 uint32_t commandBufferCount
,
467 const VkCommandBuffer
* pCmdBuffers
)
469 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
471 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
473 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
474 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
476 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
478 if (secondary
->usage_flags
&
479 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
480 /* If we're continuing a render pass from the primary, we need to
481 * copy the surface states for the current subpass into the storage
482 * we allocated for them in BeginCommandBuffer.
484 struct anv_bo
*ss_bo
= &primary
->device
->surface_state_block_pool
.bo
;
485 struct anv_state src_state
= primary
->state
.render_pass_states
;
486 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
487 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
489 genX(cmd_buffer_gpu_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
490 ss_bo
, src_state
.offset
,
491 src_state
.alloc_size
);
494 anv_cmd_buffer_add_secondary(primary
, secondary
);
497 /* Each of the secondary command buffers will use its own state base
498 * address. We need to re-emit state base address for the primary after
499 * all of the secondaries are done.
501 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
504 genX(cmd_buffer_emit_state_base_address
)(primary
);
507 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
508 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
509 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
512 * Program the hardware to use the specified L3 configuration.
515 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
516 const struct gen_l3_config
*cfg
)
519 if (cfg
== cmd_buffer
->state
.current_l3_config
)
522 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
523 fprintf(stderr
, "L3 config transition: ");
524 gen_dump_l3_config(cfg
, stderr
);
527 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
529 /* According to the hardware docs, the L3 partitioning can only be changed
530 * while the pipeline is completely drained and the caches are flushed,
531 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
533 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
534 pc
.DCFlushEnable
= true;
535 pc
.PostSyncOperation
= NoWrite
;
536 pc
.CommandStreamerStallEnable
= true;
539 /* ...followed by a second pipelined PIPE_CONTROL that initiates
540 * invalidation of the relevant caches. Note that because RO invalidation
541 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
542 * command is processed by the CS) we cannot combine it with the previous
543 * stalling flush as the hardware documentation suggests, because that
544 * would cause the CS to stall on previous rendering *after* RO
545 * invalidation and wouldn't prevent the RO caches from being polluted by
546 * concurrent rendering before the stall completes. This intentionally
547 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
548 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
549 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
550 * already guarantee that there is no concurrent GPGPU kernel execution
551 * (see SKL HSD 2132585).
553 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
554 pc
.TextureCacheInvalidationEnable
= true;
555 pc
.ConstantCacheInvalidationEnable
= true;
556 pc
.InstructionCacheInvalidateEnable
= true;
557 pc
.StateCacheInvalidationEnable
= true;
558 pc
.PostSyncOperation
= NoWrite
;
561 /* Now send a third stalling flush to make sure that invalidation is
562 * complete when the L3 configuration registers are modified.
564 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
565 pc
.DCFlushEnable
= true;
566 pc
.PostSyncOperation
= NoWrite
;
567 pc
.CommandStreamerStallEnable
= true;
572 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
575 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
576 .SLMEnable
= has_slm
,
577 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
578 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
579 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
580 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
582 /* Set up the L3 partitioning. */
583 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
587 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
588 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
590 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
592 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
595 assert(!cfg
->n
[GEN_L3P_ALL
]);
597 /* When enabled SLM only uses a portion of the L3 on half of the banks,
598 * the matching space on the remaining banks has to be allocated to a
599 * client (URB for all validated configurations) set to the
600 * lower-bandwidth 2-bank address hashing mode.
602 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
603 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
604 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
606 /* Minimum number of ways that can be allocated to the URB. */
607 const unsigned n0_urb
= (devinfo
->is_baytrail
? 32 : 0);
608 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
610 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
611 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
612 .ConvertDC_UC
= !has_dc
,
613 .ConvertIS_UC
= !has_is
,
614 .ConvertC_UC
= !has_c
,
615 .ConvertT_UC
= !has_t
);
617 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
618 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
619 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
621 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
622 .SLMEnable
= has_slm
,
623 .URBLowBandwidth
= urb_low_bw
,
624 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
626 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
628 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
629 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
631 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
632 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
634 .CAllocation
= cfg
->n
[GEN_L3P_C
],
636 .TAllocation
= cfg
->n
[GEN_L3P_T
],
639 /* Set up the L3 partitioning. */
640 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
641 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
642 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
645 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
646 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
647 * them disabled to avoid crashing the system hard.
649 uint32_t scratch1
, chicken3
;
650 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
651 .L3AtomicDisable
= !has_dc
);
652 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
653 .L3AtomicDisableMask
= true,
654 .L3AtomicDisable
= !has_dc
);
655 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
656 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
662 cmd_buffer
->state
.current_l3_config
= cfg
;
666 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
668 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
670 /* Flushes are pipelined while invalidations are handled immediately.
671 * Therefore, if we're flushing anything then we need to schedule a stall
672 * before any invalidations can happen.
674 if (bits
& ANV_PIPE_FLUSH_BITS
)
675 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
677 /* If we're going to do an invalidate and we have a pending CS stall that
678 * has yet to be resolved, we do the CS stall now.
680 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
681 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
682 bits
|= ANV_PIPE_CS_STALL_BIT
;
683 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
686 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
687 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
688 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
689 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
690 pipe
.RenderTargetCacheFlushEnable
=
691 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
693 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
694 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
695 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
698 * According to the Broadwell documentation, any PIPE_CONTROL with the
699 * "Command Streamer Stall" bit set must also have another bit set,
700 * with five different options:
702 * - Render Target Cache Flush
703 * - Depth Cache Flush
704 * - Stall at Pixel Scoreboard
705 * - Post-Sync Operation
709 * I chose "Stall at Pixel Scoreboard" since that's what we use in
710 * mesa and it seems to work fine. The choice is fairly arbitrary.
712 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
713 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
714 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
715 pipe
.StallAtPixelScoreboard
= true;
718 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
721 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
722 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
723 pipe
.StateCacheInvalidationEnable
=
724 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
725 pipe
.ConstantCacheInvalidationEnable
=
726 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
727 pipe
.VFCacheInvalidationEnable
=
728 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
729 pipe
.TextureCacheInvalidationEnable
=
730 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
731 pipe
.InstructionCacheInvalidateEnable
=
732 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
735 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
738 cmd_buffer
->state
.pending_pipe_bits
= bits
;
741 void genX(CmdPipelineBarrier
)(
742 VkCommandBuffer commandBuffer
,
743 VkPipelineStageFlags srcStageMask
,
744 VkPipelineStageFlags destStageMask
,
746 uint32_t memoryBarrierCount
,
747 const VkMemoryBarrier
* pMemoryBarriers
,
748 uint32_t bufferMemoryBarrierCount
,
749 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
750 uint32_t imageMemoryBarrierCount
,
751 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
753 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
756 /* XXX: Right now, we're really dumb and just flush whatever categories
757 * the app asks for. One of these days we may make this a bit better
758 * but right now that's all the hardware allows for in most areas.
760 VkAccessFlags src_flags
= 0;
761 VkAccessFlags dst_flags
= 0;
763 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
764 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
765 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
768 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
769 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
770 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
773 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
774 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
775 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
778 enum anv_pipe_bits pipe_bits
= 0;
780 for_each_bit(b
, src_flags
) {
781 switch ((VkAccessFlagBits
)(1 << b
)) {
782 case VK_ACCESS_SHADER_WRITE_BIT
:
783 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
785 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
786 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
788 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
789 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
791 case VK_ACCESS_TRANSFER_WRITE_BIT
:
792 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
793 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
796 break; /* Nothing to do */
800 for_each_bit(b
, dst_flags
) {
801 switch ((VkAccessFlagBits
)(1 << b
)) {
802 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
803 case VK_ACCESS_INDEX_READ_BIT
:
804 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
805 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
807 case VK_ACCESS_UNIFORM_READ_BIT
:
808 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
809 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
811 case VK_ACCESS_SHADER_READ_BIT
:
812 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
813 case VK_ACCESS_TRANSFER_READ_BIT
:
814 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
817 break; /* Nothing to do */
821 cmd_buffer
->state
.pending_pipe_bits
|= pipe_bits
;
825 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
827 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
829 /* In order to avoid thrash, we assume that vertex and fragment stages
830 * always exist. In the rare case where one is missing *and* the other
831 * uses push concstants, this may be suboptimal. However, avoiding stalls
832 * seems more important.
834 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
836 if (stages
== cmd_buffer
->state
.push_constant_stages
)
840 const unsigned push_constant_kb
= 32;
842 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
844 const unsigned push_constant_kb
= 16;
847 const unsigned num_stages
=
848 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
849 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
851 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
852 * units of 2KB. Incidentally, these are the same platforms that have
853 * 32KB worth of push constant space.
855 if (push_constant_kb
== 32)
856 size_per_stage
&= ~1u;
858 uint32_t kb_used
= 0;
859 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
860 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
861 anv_batch_emit(&cmd_buffer
->batch
,
862 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
863 alloc
._3DCommandSubOpcode
= 18 + i
;
864 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
865 alloc
.ConstantBufferSize
= push_size
;
867 kb_used
+= push_size
;
870 anv_batch_emit(&cmd_buffer
->batch
,
871 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
872 alloc
.ConstantBufferOffset
= kb_used
;
873 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
876 cmd_buffer
->state
.push_constant_stages
= stages
;
878 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
880 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
881 * the next 3DPRIMITIVE command after programming the
882 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
884 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
885 * pipeline setup, we need to dirty push constants.
887 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
891 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
892 gl_shader_stage stage
,
893 struct anv_state
*bt_state
)
895 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
896 struct anv_pipeline
*pipeline
;
897 uint32_t bias
, state_offset
;
900 case MESA_SHADER_COMPUTE
:
901 pipeline
= cmd_buffer
->state
.compute_pipeline
;
905 pipeline
= cmd_buffer
->state
.pipeline
;
910 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
911 *bt_state
= (struct anv_state
) { 0, };
915 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
916 if (bias
+ map
->surface_count
== 0) {
917 *bt_state
= (struct anv_state
) { 0, };
921 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
922 bias
+ map
->surface_count
,
924 uint32_t *bt_map
= bt_state
->map
;
926 if (bt_state
->map
== NULL
)
927 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
929 if (stage
== MESA_SHADER_COMPUTE
&&
930 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
931 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
932 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
934 struct anv_state surface_state
;
936 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
938 const enum isl_format format
=
939 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
940 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
941 format
, bo_offset
, 12, 1);
943 bt_map
[0] = surface_state
.offset
+ state_offset
;
944 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
947 if (map
->surface_count
== 0)
950 if (map
->image_count
> 0) {
952 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
953 if (result
!= VK_SUCCESS
)
956 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
960 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
961 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
963 struct anv_state surface_state
;
965 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
966 /* Color attachment binding */
967 assert(stage
== MESA_SHADER_FRAGMENT
);
968 assert(binding
->binding
== 0);
969 if (binding
->index
< subpass
->color_count
) {
970 const unsigned att
= subpass
->color_attachments
[binding
->index
];
971 surface_state
= cmd_buffer
->state
.attachments
[att
].color_rt_state
;
973 surface_state
= cmd_buffer
->state
.null_surface_state
;
976 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
980 struct anv_descriptor_set
*set
=
981 cmd_buffer
->state
.descriptors
[binding
->set
];
982 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
983 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
985 switch (desc
->type
) {
986 case VK_DESCRIPTOR_TYPE_SAMPLER
:
987 /* Nothing for us to do here */
990 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
991 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
992 surface_state
= desc
->image_view
->sampler_surface_state
;
993 assert(surface_state
.alloc_size
);
994 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
995 desc
->image_view
->image
->aux_usage
,
999 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1000 assert(stage
== MESA_SHADER_FRAGMENT
);
1001 if (desc
->image_view
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
1002 /* For stencil input attachments, we treat it like any old texture
1003 * that a user may have bound.
1005 surface_state
= desc
->image_view
->sampler_surface_state
;
1006 assert(surface_state
.alloc_size
);
1007 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1008 desc
->image_view
->image
->aux_usage
,
1011 /* For depth and color input attachments, we create the surface
1012 * state at vkBeginRenderPass time so that we can include aux
1013 * and clear color information.
1015 assert(binding
->input_attachment_index
< subpass
->input_count
);
1016 const unsigned subpass_att
= binding
->input_attachment_index
;
1017 const unsigned att
= subpass
->input_attachments
[subpass_att
];
1018 surface_state
= cmd_buffer
->state
.attachments
[att
].input_att_state
;
1022 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1023 surface_state
= desc
->image_view
->storage_surface_state
;
1024 assert(surface_state
.alloc_size
);
1025 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1026 desc
->image_view
->image
->aux_usage
,
1029 struct brw_image_param
*image_param
=
1030 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1032 *image_param
= desc
->image_view
->storage_image_param
;
1033 image_param
->surface_idx
= bias
+ s
;
1037 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
1038 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
1039 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
1040 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
1041 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
1042 surface_state
= desc
->buffer_view
->surface_state
;
1043 assert(surface_state
.alloc_size
);
1044 add_surface_state_reloc(cmd_buffer
, surface_state
,
1045 desc
->buffer_view
->bo
,
1046 desc
->buffer_view
->offset
);
1049 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
1050 surface_state
= desc
->buffer_view
->storage_surface_state
;
1051 assert(surface_state
.alloc_size
);
1052 add_surface_state_reloc(cmd_buffer
, surface_state
,
1053 desc
->buffer_view
->bo
,
1054 desc
->buffer_view
->offset
);
1056 struct brw_image_param
*image_param
=
1057 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1059 *image_param
= desc
->buffer_view
->storage_image_param
;
1060 image_param
->surface_idx
= bias
+ s
;
1064 assert(!"Invalid descriptor type");
1068 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1070 assert(image
== map
->image_count
);
1073 if (!cmd_buffer
->device
->info
.has_llc
)
1074 anv_state_clflush(*bt_state
);
1080 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1081 gl_shader_stage stage
,
1082 struct anv_state
*state
)
1084 struct anv_pipeline
*pipeline
;
1086 if (stage
== MESA_SHADER_COMPUTE
)
1087 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1089 pipeline
= cmd_buffer
->state
.pipeline
;
1091 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1092 *state
= (struct anv_state
) { 0, };
1096 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1097 if (map
->sampler_count
== 0) {
1098 *state
= (struct anv_state
) { 0, };
1102 uint32_t size
= map
->sampler_count
* 16;
1103 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1105 if (state
->map
== NULL
)
1106 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1108 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1109 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1110 struct anv_descriptor_set
*set
=
1111 cmd_buffer
->state
.descriptors
[binding
->set
];
1112 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1113 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1115 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1116 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1119 struct anv_sampler
*sampler
= desc
->sampler
;
1121 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1122 * happens to be zero.
1124 if (sampler
== NULL
)
1127 memcpy(state
->map
+ (s
* 16),
1128 sampler
->state
, sizeof(sampler
->state
));
1131 if (!cmd_buffer
->device
->info
.has_llc
)
1132 anv_state_clflush(*state
);
1138 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1140 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1141 cmd_buffer
->state
.pipeline
->active_stages
;
1143 VkResult result
= VK_SUCCESS
;
1144 anv_foreach_stage(s
, dirty
) {
1145 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1146 if (result
!= VK_SUCCESS
)
1148 result
= emit_binding_table(cmd_buffer
, s
,
1149 &cmd_buffer
->state
.binding_tables
[s
]);
1150 if (result
!= VK_SUCCESS
)
1154 if (result
!= VK_SUCCESS
) {
1155 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1157 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1158 assert(result
== VK_SUCCESS
);
1160 /* Re-emit state base addresses so we get the new surface state base
1161 * address before we start emitting binding tables etc.
1163 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1165 /* Re-emit all active binding tables */
1166 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
1167 anv_foreach_stage(s
, dirty
) {
1168 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1169 if (result
!= VK_SUCCESS
)
1171 result
= emit_binding_table(cmd_buffer
, s
,
1172 &cmd_buffer
->state
.binding_tables
[s
]);
1173 if (result
!= VK_SUCCESS
)
1178 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1184 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1187 static const uint32_t sampler_state_opcodes
[] = {
1188 [MESA_SHADER_VERTEX
] = 43,
1189 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1190 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1191 [MESA_SHADER_GEOMETRY
] = 46,
1192 [MESA_SHADER_FRAGMENT
] = 47,
1193 [MESA_SHADER_COMPUTE
] = 0,
1196 static const uint32_t binding_table_opcodes
[] = {
1197 [MESA_SHADER_VERTEX
] = 38,
1198 [MESA_SHADER_TESS_CTRL
] = 39,
1199 [MESA_SHADER_TESS_EVAL
] = 40,
1200 [MESA_SHADER_GEOMETRY
] = 41,
1201 [MESA_SHADER_FRAGMENT
] = 42,
1202 [MESA_SHADER_COMPUTE
] = 0,
1205 anv_foreach_stage(s
, stages
) {
1206 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1207 anv_batch_emit(&cmd_buffer
->batch
,
1208 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1209 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1210 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1214 /* Always emit binding table pointers if we're asked to, since on SKL
1215 * this is what flushes push constants. */
1216 anv_batch_emit(&cmd_buffer
->batch
,
1217 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1218 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1219 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1225 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1227 static const uint32_t push_constant_opcodes
[] = {
1228 [MESA_SHADER_VERTEX
] = 21,
1229 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1230 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1231 [MESA_SHADER_GEOMETRY
] = 22,
1232 [MESA_SHADER_FRAGMENT
] = 23,
1233 [MESA_SHADER_COMPUTE
] = 0,
1236 VkShaderStageFlags flushed
= 0;
1238 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
1239 if (stage
== MESA_SHADER_COMPUTE
)
1242 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1244 if (state
.offset
== 0) {
1245 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1246 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1248 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1249 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1250 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1252 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
1253 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1255 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
1256 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1262 flushed
|= mesa_to_vk_shader_stage(stage
);
1265 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1271 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1273 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1276 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1278 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1280 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1282 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1285 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1286 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1288 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1289 GENX(3DSTATE_VERTEX_BUFFERS
));
1291 for_each_bit(vb
, vb_emit
) {
1292 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1293 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1295 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1296 .VertexBufferIndex
= vb
,
1299 .MemoryObjectControlState
= GENX(MOCS
),
1301 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1302 .InstanceDataStepRate
= 1,
1303 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1306 .AddressModifyEnable
= true,
1307 .BufferPitch
= pipeline
->binding_stride
[vb
],
1308 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1311 .BufferSize
= buffer
->size
- offset
1313 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1317 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1322 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1324 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1325 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1327 /* The exact descriptor layout is pulled from the pipeline, so we need
1328 * to re-emit binding tables on every pipeline change.
1330 cmd_buffer
->state
.descriptors_dirty
|=
1331 cmd_buffer
->state
.pipeline
->active_stages
;
1333 /* If the pipeline changed, we may need to re-allocate push constant
1336 cmd_buffer_alloc_push_constants(cmd_buffer
);
1340 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1341 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1342 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1344 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1345 * stall needs to be sent just prior to any 3DSTATE_VS,
1346 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1347 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1348 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1349 * PIPE_CONTROL needs to be sent before any combination of VS
1350 * associated 3DSTATE."
1352 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1353 pc
.DepthStallEnable
= true;
1354 pc
.PostSyncOperation
= WriteImmediateData
;
1356 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1361 /* Render targets live in the same binding table as fragment descriptors */
1362 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1363 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1365 /* We emit the binding tables and sampler tables first, then emit push
1366 * constants and then finally emit binding table and sampler table
1367 * pointers. It has to happen in this order, since emitting the binding
1368 * tables may change the push constants (in case of storage images). After
1369 * emitting push constants, on SKL+ we have to emit the corresponding
1370 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1373 if (cmd_buffer
->state
.descriptors_dirty
)
1374 dirty
= flush_descriptor_sets(cmd_buffer
);
1376 if (cmd_buffer
->state
.push_constants_dirty
) {
1378 /* On Sky Lake and later, the binding table pointers commands are
1379 * what actually flush the changes to push constant state so we need
1380 * to dirty them so they get re-emitted below.
1382 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1384 cmd_buffer_flush_push_constants(cmd_buffer
);
1389 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1391 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1392 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1394 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1395 ANV_CMD_DIRTY_PIPELINE
)) {
1396 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1397 pipeline
->depth_clamp_enable
);
1400 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1401 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1403 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1405 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1409 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1410 struct anv_bo
*bo
, uint32_t offset
)
1412 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1413 GENX(3DSTATE_VERTEX_BUFFERS
));
1415 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1416 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1417 .VertexBufferIndex
= 32, /* Reserved for this */
1418 .AddressModifyEnable
= true,
1421 .MemoryObjectControlState
= GENX(MOCS
),
1422 .BufferStartingAddress
= { bo
, offset
},
1425 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1426 .BufferStartingAddress
= { bo
, offset
},
1427 .EndAddress
= { bo
, offset
+ 8 },
1433 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1434 uint32_t base_vertex
, uint32_t base_instance
)
1436 struct anv_state id_state
=
1437 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1439 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1440 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1442 if (!cmd_buffer
->device
->info
.has_llc
)
1443 anv_state_clflush(id_state
);
1445 emit_base_vertex_instance_bo(cmd_buffer
,
1446 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
1450 VkCommandBuffer commandBuffer
,
1451 uint32_t vertexCount
,
1452 uint32_t instanceCount
,
1453 uint32_t firstVertex
,
1454 uint32_t firstInstance
)
1456 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1457 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1458 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1460 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1462 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1463 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1465 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1466 prim
.VertexAccessType
= SEQUENTIAL
;
1467 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1468 prim
.VertexCountPerInstance
= vertexCount
;
1469 prim
.StartVertexLocation
= firstVertex
;
1470 prim
.InstanceCount
= instanceCount
;
1471 prim
.StartInstanceLocation
= firstInstance
;
1472 prim
.BaseVertexLocation
= 0;
1476 void genX(CmdDrawIndexed
)(
1477 VkCommandBuffer commandBuffer
,
1478 uint32_t indexCount
,
1479 uint32_t instanceCount
,
1480 uint32_t firstIndex
,
1481 int32_t vertexOffset
,
1482 uint32_t firstInstance
)
1484 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1485 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1486 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1488 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1490 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1491 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1493 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1494 prim
.VertexAccessType
= RANDOM
;
1495 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1496 prim
.VertexCountPerInstance
= indexCount
;
1497 prim
.StartVertexLocation
= firstIndex
;
1498 prim
.InstanceCount
= instanceCount
;
1499 prim
.StartInstanceLocation
= firstInstance
;
1500 prim
.BaseVertexLocation
= vertexOffset
;
1504 /* Auto-Draw / Indirect Registers */
1505 #define GEN7_3DPRIM_END_OFFSET 0x2420
1506 #define GEN7_3DPRIM_START_VERTEX 0x2430
1507 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1508 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1509 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1510 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1512 void genX(CmdDrawIndirect
)(
1513 VkCommandBuffer commandBuffer
,
1515 VkDeviceSize offset
,
1519 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1520 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1521 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1522 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1523 struct anv_bo
*bo
= buffer
->bo
;
1524 uint32_t bo_offset
= buffer
->offset
+ offset
;
1526 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1528 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1529 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
1531 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1532 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1533 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1534 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
1535 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
1537 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1538 prim
.IndirectParameterEnable
= true;
1539 prim
.VertexAccessType
= SEQUENTIAL
;
1540 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1544 void genX(CmdDrawIndexedIndirect
)(
1545 VkCommandBuffer commandBuffer
,
1547 VkDeviceSize offset
,
1551 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1552 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1553 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1554 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1555 struct anv_bo
*bo
= buffer
->bo
;
1556 uint32_t bo_offset
= buffer
->offset
+ offset
;
1558 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1560 /* TODO: We need to stomp base vertex to 0 somehow */
1561 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1562 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
1564 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1565 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1566 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1567 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
1568 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
1570 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1571 prim
.IndirectParameterEnable
= true;
1572 prim
.VertexAccessType
= RANDOM
;
1573 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1578 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
1580 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1581 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
1584 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1585 if (result
!= VK_SUCCESS
) {
1586 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1587 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1588 assert(result
== VK_SUCCESS
);
1590 /* Re-emit state base addresses so we get the new surface state base
1591 * address before we start emitting binding tables etc.
1593 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1595 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1596 assert(result
== VK_SUCCESS
);
1599 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
1600 assert(result
== VK_SUCCESS
);
1602 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
1603 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1604 .BindingTablePointer
= surfaces
.offset
,
1605 .SamplerStatePointer
= samplers
.offset
,
1607 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
1609 struct anv_state state
=
1610 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
1611 pipeline
->interface_descriptor_data
,
1612 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
1615 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
1616 anv_batch_emit(&cmd_buffer
->batch
,
1617 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
1618 mid
.InterfaceDescriptorTotalLength
= size
;
1619 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
1626 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1628 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1629 MAYBE_UNUSED VkResult result
;
1631 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
1633 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1635 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
1637 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1638 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
1640 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
1641 * the only bits that are changed are scoreboard related: Scoreboard
1642 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
1643 * these scoreboard related states, a MEDIA_STATE_FLUSH is
1646 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1647 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1649 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1652 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
1653 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
1654 /* FIXME: figure out descriptors for gen7 */
1655 result
= flush_compute_descriptor_set(cmd_buffer
);
1656 assert(result
== VK_SUCCESS
);
1657 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
1660 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
1661 struct anv_state push_state
=
1662 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
1664 if (push_state
.alloc_size
) {
1665 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
1666 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
1667 curbe
.CURBEDataStartAddress
= push_state
.offset
;
1672 cmd_buffer
->state
.compute_dirty
= 0;
1674 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1680 verify_cmd_parser(const struct anv_device
*device
,
1681 int required_version
,
1682 const char *function
)
1684 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
1685 vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
1686 "cmd parser version %d is required for %s",
1687 required_version
, function
);
1696 void genX(CmdDispatch
)(
1697 VkCommandBuffer commandBuffer
,
1702 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1703 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1704 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1706 if (prog_data
->uses_num_work_groups
) {
1707 struct anv_state state
=
1708 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
1709 uint32_t *sizes
= state
.map
;
1713 if (!cmd_buffer
->device
->info
.has_llc
)
1714 anv_state_clflush(state
);
1715 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
1716 cmd_buffer
->state
.num_workgroups_bo
=
1717 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
1720 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1722 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
1723 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1724 ggw
.ThreadDepthCounterMaximum
= 0;
1725 ggw
.ThreadHeightCounterMaximum
= 0;
1726 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1727 ggw
.ThreadGroupIDXDimension
= x
;
1728 ggw
.ThreadGroupIDYDimension
= y
;
1729 ggw
.ThreadGroupIDZDimension
= z
;
1730 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1731 ggw
.BottomExecutionMask
= 0xffffffff;
1734 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1737 #define GPGPU_DISPATCHDIMX 0x2500
1738 #define GPGPU_DISPATCHDIMY 0x2504
1739 #define GPGPU_DISPATCHDIMZ 0x2508
1741 #define MI_PREDICATE_SRC0 0x2400
1742 #define MI_PREDICATE_SRC1 0x2408
1744 void genX(CmdDispatchIndirect
)(
1745 VkCommandBuffer commandBuffer
,
1747 VkDeviceSize offset
)
1749 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1750 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1751 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1752 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1753 struct anv_bo
*bo
= buffer
->bo
;
1754 uint32_t bo_offset
= buffer
->offset
+ offset
;
1755 struct anv_batch
*batch
= &cmd_buffer
->batch
;
1758 /* Linux 4.4 added command parser version 5 which allows the GPGPU
1759 * indirect dispatch registers to be written.
1761 if (!verify_cmd_parser(cmd_buffer
->device
, 5, "vkCmdDispatchIndirect"))
1765 if (prog_data
->uses_num_work_groups
) {
1766 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
1767 cmd_buffer
->state
.num_workgroups_bo
= bo
;
1770 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1772 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
1773 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
1774 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
1777 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
1778 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
1779 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
1780 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
1782 /* Load compute_dispatch_indirect_x_size into SRC0 */
1783 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
1785 /* predicate = (compute_dispatch_indirect_x_size == 0); */
1786 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1787 mip
.LoadOperation
= LOAD_LOAD
;
1788 mip
.CombineOperation
= COMBINE_SET
;
1789 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1792 /* Load compute_dispatch_indirect_y_size into SRC0 */
1793 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
1795 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
1796 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1797 mip
.LoadOperation
= LOAD_LOAD
;
1798 mip
.CombineOperation
= COMBINE_OR
;
1799 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1802 /* Load compute_dispatch_indirect_z_size into SRC0 */
1803 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
1805 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
1806 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1807 mip
.LoadOperation
= LOAD_LOAD
;
1808 mip
.CombineOperation
= COMBINE_OR
;
1809 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1812 /* predicate = !predicate; */
1813 #define COMPARE_FALSE 1
1814 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1815 mip
.LoadOperation
= LOAD_LOADINV
;
1816 mip
.CombineOperation
= COMBINE_OR
;
1817 mip
.CompareOperation
= COMPARE_FALSE
;
1821 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
1822 ggw
.IndirectParameterEnable
= true;
1823 ggw
.PredicateEnable
= GEN_GEN
<= 7;
1824 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1825 ggw
.ThreadDepthCounterMaximum
= 0;
1826 ggw
.ThreadHeightCounterMaximum
= 0;
1827 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1828 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1829 ggw
.BottomExecutionMask
= 0xffffffff;
1832 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1836 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
1839 #if GEN_GEN >= 8 && GEN_GEN < 10
1840 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
1842 * Software must clear the COLOR_CALC_STATE Valid field in
1843 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
1844 * with Pipeline Select set to GPGPU.
1846 * The internal hardware docs recommend the same workaround for Gen9
1849 if (pipeline
== GPGPU
)
1850 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
1852 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
1853 * PIPELINE_SELECT [DevBWR+]":
1857 * Software must ensure all the write caches are flushed through a
1858 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
1859 * command to invalidate read only caches prior to programming
1860 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
1862 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1863 pc
.RenderTargetCacheFlushEnable
= true;
1864 pc
.DepthCacheFlushEnable
= true;
1865 pc
.DCFlushEnable
= true;
1866 pc
.PostSyncOperation
= NoWrite
;
1867 pc
.CommandStreamerStallEnable
= true;
1870 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1871 pc
.TextureCacheInvalidationEnable
= true;
1872 pc
.ConstantCacheInvalidationEnable
= true;
1873 pc
.StateCacheInvalidationEnable
= true;
1874 pc
.InstructionCacheInvalidateEnable
= true;
1875 pc
.PostSyncOperation
= NoWrite
;
1881 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
1883 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
1884 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
1886 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
1890 ps
.PipelineSelection
= _3D
;
1893 cmd_buffer
->state
.current_pipeline
= _3D
;
1898 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
1900 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
1901 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
1903 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
1907 ps
.PipelineSelection
= GPGPU
;
1910 cmd_buffer
->state
.current_pipeline
= GPGPU
;
1915 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
1920 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
1922 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
1923 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
1924 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
1925 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
1926 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
1927 * Depth Flush Bit set, followed by another pipelined depth stall
1928 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
1929 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
1930 * via a preceding MI_FLUSH)."
1932 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1933 pipe
.DepthStallEnable
= true;
1935 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1936 pipe
.DepthCacheFlushEnable
= true;
1938 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1939 pipe
.DepthStallEnable
= true;
1944 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
1946 struct anv_device
*device
= cmd_buffer
->device
;
1947 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1948 const struct anv_image_view
*iview
=
1949 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1950 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
1951 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1952 const bool has_hiz
= image
!= NULL
&& anv_image_has_hiz(image
);
1953 const bool has_stencil
=
1954 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1956 /* FIXME: Implement the PMA stall W/A */
1957 /* FIXME: Width and Height are wrong */
1959 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
1961 /* Emit 3DSTATE_DEPTH_BUFFER */
1963 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
1964 db
.SurfaceType
= SURFTYPE_2D
;
1965 db
.DepthWriteEnable
= true;
1966 db
.StencilWriteEnable
= has_stencil
;
1968 if (cmd_buffer
->state
.pass
->subpass_count
== 1) {
1969 db
.HierarchicalDepthBufferEnable
= has_hiz
;
1971 anv_finishme("Multiple-subpass HiZ not implemented");
1974 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
1975 &image
->depth_surface
.isl
);
1977 db
.SurfaceBaseAddress
= (struct anv_address
) {
1979 .offset
= image
->offset
+ image
->depth_surface
.offset
,
1981 db
.DepthBufferObjectControlState
= GENX(MOCS
);
1983 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
1984 db
.Height
= image
->extent
.height
- 1;
1985 db
.Width
= image
->extent
.width
- 1;
1986 db
.LOD
= iview
->isl
.base_level
;
1987 db
.Depth
= image
->array_size
- 1; /* FIXME: 3-D */
1988 db
.MinimumArrayElement
= iview
->isl
.base_array_layer
;
1992 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2;
1994 db
.RenderTargetViewExtent
= 1 - 1;
1997 /* Even when no depth buffer is present, the hardware requires that
1998 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
2000 * If a null depth buffer is bound, the driver must instead bind depth as:
2001 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
2002 * 3DSTATE_DEPTH.Width = 1
2003 * 3DSTATE_DEPTH.Height = 1
2004 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
2005 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
2006 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
2007 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
2008 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
2010 * The PRM is wrong, though. The width and height must be programmed to
2011 * actual framebuffer's width and height, even when neither depth buffer
2012 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
2013 * be combined with a stencil buffer so we use D32_FLOAT instead.
2015 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2016 db
.SurfaceType
= SURFTYPE_2D
;
2017 db
.SurfaceFormat
= D32_FLOAT
;
2018 db
.Width
= fb
->width
- 1;
2019 db
.Height
= fb
->height
- 1;
2020 db
.StencilWriteEnable
= has_stencil
;
2025 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
) {
2026 hdb
.HierarchicalDepthBufferObjectControlState
= GENX(MOCS
);
2027 hdb
.SurfacePitch
= image
->aux_surface
.isl
.row_pitch
- 1;
2028 hdb
.SurfaceBaseAddress
= (struct anv_address
) {
2030 .offset
= image
->offset
+ image
->aux_surface
.offset
,
2033 /* From the SKL PRM Vol2a:
2035 * The interpretation of this field is dependent on Surface Type
2037 * - SURFTYPE_1D: distance in pixels between array slices
2038 * - SURFTYPE_2D/CUBE: distance in rows between array slices
2039 * - SURFTYPE_3D: distance in rows between R - slices
2042 image
->aux_surface
.isl
.dim
== ISL_SURF_DIM_1D
?
2043 isl_surf_get_array_pitch_el(&image
->aux_surface
.isl
) >> 2 :
2044 isl_surf_get_array_pitch_el_rows(&image
->aux_surface
.isl
) >> 2;
2048 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
);
2051 /* Emit 3DSTATE_STENCIL_BUFFER */
2053 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
2054 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2055 sb
.StencilBufferEnable
= true;
2057 sb
.StencilBufferObjectControlState
= GENX(MOCS
);
2059 sb
.SurfacePitch
= image
->stencil_surface
.isl
.row_pitch
- 1;
2062 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2;
2064 sb
.SurfaceBaseAddress
= (struct anv_address
) {
2066 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
2070 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
2073 /* From the IVB PRM Vol2P1, 11.5.5.4 3DSTATE_CLEAR_PARAMS:
2075 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along with
2076 * the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
2077 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)
2079 * Testing also shows that some variant of this restriction may exist HSW+.
2080 * On BDW+, it is not possible to emit 2 of these packets consecutively when
2081 * both have DepthClearValueValid set. An analysis of such state programming
2082 * on SKL showed that the GPU doesn't register the latter packet's clear
2085 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
) {
2087 cp
.DepthClearValueValid
= true;
2089 cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2090 cp
.DepthClearValue
=
2091 cmd_buffer
->state
.attachments
[ds
].clear_value
.depthStencil
.depth
;
2097 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
2098 struct anv_subpass
*subpass
)
2100 cmd_buffer
->state
.subpass
= subpass
;
2102 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
2104 cmd_buffer_emit_depth_stencil(cmd_buffer
);
2105 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_HIZ_RESOLVE
);
2106 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_DEPTH_CLEAR
);
2108 anv_cmd_buffer_clear_subpass(cmd_buffer
);
2111 void genX(CmdBeginRenderPass
)(
2112 VkCommandBuffer commandBuffer
,
2113 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2114 VkSubpassContents contents
)
2116 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2117 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2118 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2120 cmd_buffer
->state
.framebuffer
= framebuffer
;
2121 cmd_buffer
->state
.pass
= pass
;
2122 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2123 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
2125 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2127 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
2130 void genX(CmdNextSubpass
)(
2131 VkCommandBuffer commandBuffer
,
2132 VkSubpassContents contents
)
2134 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2136 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2138 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2139 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
2142 void genX(CmdEndRenderPass
)(
2143 VkCommandBuffer commandBuffer
)
2145 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2147 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_DEPTH_RESOLVE
);
2148 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2151 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
2156 emit_ps_depth_count(struct anv_cmd_buffer
*cmd_buffer
,
2157 struct anv_bo
*bo
, uint32_t offset
)
2159 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2160 pc
.DestinationAddressType
= DAT_PPGTT
;
2161 pc
.PostSyncOperation
= WritePSDepthCount
;
2162 pc
.DepthStallEnable
= true;
2163 pc
.Address
= (struct anv_address
) { bo
, offset
};
2165 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2166 pc
.CommandStreamerStallEnable
= true;
2171 emit_query_availability(struct anv_cmd_buffer
*cmd_buffer
,
2172 struct anv_bo
*bo
, uint32_t offset
)
2174 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2175 pc
.DestinationAddressType
= DAT_PPGTT
;
2176 pc
.PostSyncOperation
= WriteImmediateData
;
2177 pc
.Address
= (struct anv_address
) { bo
, offset
};
2178 pc
.ImmediateData
= 1;
2182 void genX(CmdBeginQuery
)(
2183 VkCommandBuffer commandBuffer
,
2184 VkQueryPool queryPool
,
2186 VkQueryControlFlags flags
)
2188 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2189 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2191 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
2192 * that the pipelining of the depth write breaks. What we see is that
2193 * samples from the render pass clear leaks into the first query
2194 * immediately after the clear. Doing a pipecontrol with a post-sync
2195 * operation and DepthStallEnable seems to work around the issue.
2197 if (cmd_buffer
->state
.need_query_wa
) {
2198 cmd_buffer
->state
.need_query_wa
= false;
2199 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2200 pc
.DepthCacheFlushEnable
= true;
2201 pc
.DepthStallEnable
= true;
2205 switch (pool
->type
) {
2206 case VK_QUERY_TYPE_OCCLUSION
:
2207 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2208 query
* sizeof(struct anv_query_pool_slot
));
2211 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2217 void genX(CmdEndQuery
)(
2218 VkCommandBuffer commandBuffer
,
2219 VkQueryPool queryPool
,
2222 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2223 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2225 switch (pool
->type
) {
2226 case VK_QUERY_TYPE_OCCLUSION
:
2227 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2228 query
* sizeof(struct anv_query_pool_slot
) + 8);
2230 emit_query_availability(cmd_buffer
, &pool
->bo
,
2231 query
* sizeof(struct anv_query_pool_slot
) + 16);
2234 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2240 #define TIMESTAMP 0x2358
2242 void genX(CmdWriteTimestamp
)(
2243 VkCommandBuffer commandBuffer
,
2244 VkPipelineStageFlagBits pipelineStage
,
2245 VkQueryPool queryPool
,
2248 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2249 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2250 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
2252 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
2254 switch (pipelineStage
) {
2255 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
2256 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2257 srm
.RegisterAddress
= TIMESTAMP
;
2258 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
};
2260 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2261 srm
.RegisterAddress
= TIMESTAMP
+ 4;
2262 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
+ 4 };
2267 /* Everything else is bottom-of-pipe */
2268 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2269 pc
.DestinationAddressType
= DAT_PPGTT
;
2270 pc
.PostSyncOperation
= WriteTimestamp
;
2271 pc
.Address
= (struct anv_address
) { &pool
->bo
, offset
};
2273 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2274 pc
.CommandStreamerStallEnable
= true;
2279 emit_query_availability(cmd_buffer
, &pool
->bo
, query
+ 16);
2282 #if GEN_GEN > 7 || GEN_IS_HASWELL
2284 #define alu_opcode(v) __gen_uint((v), 20, 31)
2285 #define alu_operand1(v) __gen_uint((v), 10, 19)
2286 #define alu_operand2(v) __gen_uint((v), 0, 9)
2287 #define alu(opcode, operand1, operand2) \
2288 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
2290 #define OPCODE_NOOP 0x000
2291 #define OPCODE_LOAD 0x080
2292 #define OPCODE_LOADINV 0x480
2293 #define OPCODE_LOAD0 0x081
2294 #define OPCODE_LOAD1 0x481
2295 #define OPCODE_ADD 0x100
2296 #define OPCODE_SUB 0x101
2297 #define OPCODE_AND 0x102
2298 #define OPCODE_OR 0x103
2299 #define OPCODE_XOR 0x104
2300 #define OPCODE_STORE 0x180
2301 #define OPCODE_STOREINV 0x580
2303 #define OPERAND_R0 0x00
2304 #define OPERAND_R1 0x01
2305 #define OPERAND_R2 0x02
2306 #define OPERAND_R3 0x03
2307 #define OPERAND_R4 0x04
2308 #define OPERAND_SRCA 0x20
2309 #define OPERAND_SRCB 0x21
2310 #define OPERAND_ACCU 0x31
2311 #define OPERAND_ZF 0x32
2312 #define OPERAND_CF 0x33
2314 #define CS_GPR(n) (0x2600 + (n) * 8)
2317 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
2318 struct anv_bo
*bo
, uint32_t offset
)
2320 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2321 lrm
.RegisterAddress
= reg
,
2322 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2324 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2325 lrm
.RegisterAddress
= reg
+ 4;
2326 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2331 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
2332 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
2334 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2335 srm
.RegisterAddress
= reg
;
2336 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2339 if (flags
& VK_QUERY_RESULT_64_BIT
) {
2340 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2341 srm
.RegisterAddress
= reg
+ 4;
2342 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2347 void genX(CmdCopyQueryPoolResults
)(
2348 VkCommandBuffer commandBuffer
,
2349 VkQueryPool queryPool
,
2350 uint32_t firstQuery
,
2351 uint32_t queryCount
,
2352 VkBuffer destBuffer
,
2353 VkDeviceSize destOffset
,
2354 VkDeviceSize destStride
,
2355 VkQueryResultFlags flags
)
2357 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2358 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2359 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
2360 uint32_t slot_offset
, dst_offset
;
2362 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
2363 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2364 pc
.CommandStreamerStallEnable
= true;
2365 pc
.StallAtPixelScoreboard
= true;
2369 dst_offset
= buffer
->offset
+ destOffset
;
2370 for (uint32_t i
= 0; i
< queryCount
; i
++) {
2372 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
2373 switch (pool
->type
) {
2374 case VK_QUERY_TYPE_OCCLUSION
:
2375 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2376 CS_GPR(0), &pool
->bo
, slot_offset
);
2377 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2378 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
2380 /* FIXME: We need to clamp the result for 32 bit. */
2382 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
2383 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
2384 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
2385 dw
[3] = alu(OPCODE_SUB
, 0, 0);
2386 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
2389 case VK_QUERY_TYPE_TIMESTAMP
:
2390 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2391 CS_GPR(2), &pool
->bo
, slot_offset
);
2395 unreachable("unhandled query type");
2398 store_query_result(&cmd_buffer
->batch
,
2399 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
2401 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
2402 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
2403 &pool
->bo
, slot_offset
+ 16);
2404 if (flags
& VK_QUERY_RESULT_64_BIT
)
2405 store_query_result(&cmd_buffer
->batch
,
2406 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
2408 store_query_result(&cmd_buffer
->batch
,
2409 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
2412 dst_offset
+= destStride
;
2417 void genX(CmdCopyQueryPoolResults
)(
2418 VkCommandBuffer commandBuffer
,
2419 VkQueryPool queryPool
,
2420 uint32_t firstQuery
,
2421 uint32_t queryCount
,
2422 VkBuffer destBuffer
,
2423 VkDeviceSize destOffset
,
2424 VkDeviceSize destStride
,
2425 VkQueryResultFlags flags
)
2427 anv_finishme("Queries not yet supported on Ivy Bridge");