2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
,
37 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
39 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
40 lrm
.RegisterAddress
= reg
;
41 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
46 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
48 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
49 lri
.RegisterOffset
= reg
;
54 #if GEN_IS_HASWELL || GEN_GEN >= 8
56 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
58 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
59 lrr
.SourceRegisterAddress
= src
;
60 lrr
.DestinationRegisterAddress
= dst
;
66 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
68 struct anv_device
*device
= cmd_buffer
->device
;
70 /* Emit a render target cache flush.
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
77 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
78 pc
.DCFlushEnable
= true;
79 pc
.RenderTargetCacheFlushEnable
= true;
80 pc
.CommandStreamerStallEnable
= true;
83 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
84 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
85 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
86 sba
.GeneralStateBaseAddressModifyEnable
= true;
88 sba
.SurfaceStateBaseAddress
=
89 anv_cmd_buffer_surface_base_address(cmd_buffer
);
90 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
91 sba
.SurfaceStateBaseAddressModifyEnable
= true;
93 sba
.DynamicStateBaseAddress
=
94 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
95 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
96 sba
.DynamicStateBaseAddressModifyEnable
= true;
98 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
99 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
100 sba
.IndirectObjectBaseAddressModifyEnable
= true;
102 sba
.InstructionBaseAddress
=
103 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
104 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
105 sba
.InstructionBaseAddressModifyEnable
= true;
108 /* Broadwell requires that we specify a buffer size for a bunch of
109 * these fields. However, since we will be growing the BO's live, we
110 * just set them all to the maximum.
112 sba
.GeneralStateBufferSize
= 0xfffff;
113 sba
.GeneralStateBufferSizeModifyEnable
= true;
114 sba
.DynamicStateBufferSize
= 0xfffff;
115 sba
.DynamicStateBufferSizeModifyEnable
= true;
116 sba
.IndirectObjectBufferSize
= 0xfffff;
117 sba
.IndirectObjectBufferSizeModifyEnable
= true;
118 sba
.InstructionBufferSize
= 0xfffff;
119 sba
.InstructionBuffersizeModifyEnable
= true;
123 /* After re-setting the surface state base address, we have to do some
124 * cache flusing so that the sampler engine will pick up the new
125 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
126 * Shared Function > 3D Sampler > State > State Caching (page 96):
128 * Coherency with system memory in the state cache, like the texture
129 * cache is handled partially by software. It is expected that the
130 * command stream or shader will issue Cache Flush operation or
131 * Cache_Flush sampler message to ensure that the L1 cache remains
132 * coherent with system memory.
136 * Whenever the value of the Dynamic_State_Base_Addr,
137 * Surface_State_Base_Addr are altered, the L1 state cache must be
138 * invalidated to ensure the new surface or sampler state is fetched
139 * from system memory.
141 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
142 * which, according the PIPE_CONTROL instruction documentation in the
145 * Setting this bit is independent of any other bit in this packet.
146 * This bit controls the invalidation of the L1 and L2 state caches
147 * at the top of the pipe i.e. at the parsing time.
149 * Unfortunately, experimentation seems to indicate that state cache
150 * invalidation through a PIPE_CONTROL does nothing whatsoever in
151 * regards to surface state and binding tables. In stead, it seems that
152 * invalidating the texture cache is what is actually needed.
154 * XXX: As far as we have been able to determine through
155 * experimentation, shows that flush the texture cache appears to be
156 * sufficient. The theory here is that all of the sampling/rendering
157 * units cache the binding table in the texture cache. However, we have
158 * yet to be able to actually confirm this.
160 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
161 pc
.TextureCacheInvalidationEnable
= true;
162 pc
.ConstantCacheInvalidationEnable
= true;
163 pc
.StateCacheInvalidationEnable
= true;
168 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
169 struct anv_state state
,
170 struct anv_bo
*bo
, uint32_t offset
)
172 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
175 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
176 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
177 if (result
!= VK_SUCCESS
)
178 anv_batch_set_error(&cmd_buffer
->batch
, result
);
182 add_image_relocs(struct anv_cmd_buffer
* const cmd_buffer
,
183 const struct anv_image
* const image
,
184 const VkImageAspectFlags aspect_mask
,
185 const enum isl_aux_usage aux_usage
,
186 const struct anv_state state
)
188 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
189 const uint32_t surf_offset
= image
->offset
+
190 anv_image_get_surface_for_aspect_mask(image
, aspect_mask
)->offset
;
192 add_surface_state_reloc(cmd_buffer
, state
, image
->bo
, surf_offset
);
194 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
195 uint32_t aux_offset
= image
->offset
+ image
->aux_surface
.offset
;
197 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
198 * used to store other information. This should be ok, however, because
199 * surface buffer addresses are always 4K page alinged.
201 assert((aux_offset
& 0xfff) == 0);
202 uint32_t *aux_addr_dw
= state
.map
+ isl_dev
->ss
.aux_addr_offset
;
203 aux_offset
+= *aux_addr_dw
& 0xfff;
206 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
207 &cmd_buffer
->pool
->alloc
,
208 state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
209 image
->bo
, aux_offset
);
210 if (result
!= VK_SUCCESS
)
211 anv_batch_set_error(&cmd_buffer
->batch
, result
);
216 color_is_zero_one(VkClearColorValue value
, enum isl_format format
)
218 if (isl_format_has_int_channel(format
)) {
219 for (unsigned i
= 0; i
< 4; i
++) {
220 if (value
.int32
[i
] != 0 && value
.int32
[i
] != 1)
224 for (unsigned i
= 0; i
< 4; i
++) {
225 if (value
.float32
[i
] != 0.0f
&& value
.float32
[i
] != 1.0f
)
234 color_attachment_compute_aux_usage(struct anv_device
* device
,
235 struct anv_cmd_state
* cmd_state
,
236 uint32_t att
, VkRect2D render_area
,
237 union isl_color_value
*fast_clear_color
)
239 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
240 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
242 if (iview
->isl
.base_array_layer
>=
243 anv_image_aux_layers(iview
->image
, iview
->isl
.base_level
)) {
244 /* There is no aux buffer which corresponds to the level and layer(s)
247 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
248 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
249 att_state
->fast_clear
= false;
251 } else if (iview
->image
->aux_usage
== ISL_AUX_USAGE_MCS
) {
252 att_state
->aux_usage
= ISL_AUX_USAGE_MCS
;
253 att_state
->input_aux_usage
= ISL_AUX_USAGE_MCS
;
254 att_state
->fast_clear
= false;
258 assert(iview
->image
->aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
260 att_state
->clear_color_is_zero_one
=
261 color_is_zero_one(att_state
->clear_value
.color
, iview
->isl
.format
);
262 att_state
->clear_color_is_zero
=
263 att_state
->clear_value
.color
.uint32
[0] == 0 &&
264 att_state
->clear_value
.color
.uint32
[1] == 0 &&
265 att_state
->clear_value
.color
.uint32
[2] == 0 &&
266 att_state
->clear_value
.color
.uint32
[3] == 0;
268 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
269 /* Start off assuming fast clears are possible */
270 att_state
->fast_clear
= true;
272 /* Potentially, we could do partial fast-clears but doing so has crazy
273 * alignment restrictions. It's easier to just restrict to full size
274 * fast clears for now.
276 if (render_area
.offset
.x
!= 0 ||
277 render_area
.offset
.y
!= 0 ||
278 render_area
.extent
.width
!= iview
->extent
.width
||
279 render_area
.extent
.height
!= iview
->extent
.height
)
280 att_state
->fast_clear
= false;
282 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
283 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
284 att_state
->fast_clear
= false;
286 /* We allow fast clears when all aux layers of the miplevel are targeted.
287 * See add_fast_clear_state_buffer() for more information. Also, because
288 * we only either do a fast clear or a normal clear and not both, this
289 * complies with the gen7 restriction of not fast-clearing multiple
292 if (cmd_state
->framebuffer
->layers
!=
293 anv_image_aux_layers(iview
->image
, iview
->isl
.base_level
)) {
294 att_state
->fast_clear
= false;
296 anv_perf_warn("Not fast-clearing the first layer in "
297 "a multi-layer fast clear.");
301 /* We only allow fast clears in the GENERAL layout if the auxiliary
302 * buffer is always enabled and the fast-clear value is all 0's. See
303 * add_fast_clear_state_buffer() for more information.
305 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
306 VK_IMAGE_LAYOUT_GENERAL
&&
307 (!att_state
->clear_color_is_zero
||
308 iview
->image
->aux_usage
== ISL_AUX_USAGE_NONE
)) {
309 att_state
->fast_clear
= false;
312 if (att_state
->fast_clear
) {
313 memcpy(fast_clear_color
->u32
, att_state
->clear_value
.color
.uint32
,
314 sizeof(fast_clear_color
->u32
));
317 att_state
->fast_clear
= false;
321 * TODO: Consider using a heuristic to determine if temporarily enabling
322 * CCS_E for this image view would be beneficial.
324 * While fast-clear resolves and partial resolves are fairly cheap in the
325 * case where you render to most of the pixels, full resolves are not
326 * because they potentially involve reading and writing the entire
327 * framebuffer. If we can't texture with CCS_E, we should leave it off and
328 * limit ourselves to fast clears.
330 if (iview
->image
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
331 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
332 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_E
;
333 } else if (att_state
->fast_clear
) {
334 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
335 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
337 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
338 * setting is only allowed if Surface Format supported for Fast
339 * Clear. In addition, if the surface is bound to the sampling
340 * engine, Surface Format must be supported for Render Target
341 * Compression for surfaces bound to the sampling engine."
343 * In other words, we can only sample from a fast-cleared image if it
344 * also supports color compression.
346 if (isl_format_supports_ccs_e(&device
->info
, iview
->isl
.format
))
347 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
349 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
351 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
352 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
357 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
359 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
362 /* We only allocate input attachment states for color surfaces. Compression
363 * is not yet enabled for depth textures and stencil doesn't allow
364 * compression so we can just use the texture surface state from the view.
366 return vk_format_is_color(att
->format
);
369 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
370 * the initial layout is undefined, the HiZ buffer and depth buffer will
371 * represent the same data at the end of this operation.
374 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
375 const struct anv_image
*image
,
376 VkImageLayout initial_layout
,
377 VkImageLayout final_layout
)
381 /* A transition is a no-op if HiZ is not enabled, or if the initial and
382 * final layouts are equal.
384 * The undefined layout indicates that the user doesn't care about the data
385 * that's currently in the buffer. Therefore, a data-preserving resolve
386 * operation is not needed.
388 if (image
->aux_usage
!= ISL_AUX_USAGE_HIZ
|| initial_layout
== final_layout
)
391 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
392 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
, image
->aspects
,
394 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
395 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
, image
->aspects
,
398 enum blorp_hiz_op hiz_op
;
399 if (hiz_enabled
&& !enable_hiz
) {
400 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
401 } else if (!hiz_enabled
&& enable_hiz
) {
402 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
404 assert(hiz_enabled
== enable_hiz
);
405 /* If the same buffer will be used, no resolves are necessary. */
406 hiz_op
= BLORP_HIZ_OP_NONE
;
409 if (hiz_op
!= BLORP_HIZ_OP_NONE
)
410 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, hiz_op
);
413 static inline uint32_t
414 get_fast_clear_state_entry_offset(const struct anv_device
*device
,
415 const struct anv_image
*image
,
418 assert(device
&& image
);
419 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
420 assert(level
< anv_image_aux_levels(image
));
421 const uint32_t offset
= image
->offset
+ image
->aux_surface
.offset
+
422 image
->aux_surface
.isl
.size
+
423 anv_fast_clear_state_entry_size(device
) * level
;
424 assert(offset
< image
->offset
+ image
->size
);
429 init_fast_clear_state_entry(struct anv_cmd_buffer
*cmd_buffer
,
430 const struct anv_image
*image
,
433 assert(cmd_buffer
&& image
);
434 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
435 assert(level
< anv_image_aux_levels(image
));
437 /* The fast clear value dword(s) will be copied into a surface state object.
438 * Ensure that the restrictions of the fields in the dword(s) are followed.
440 * CCS buffers on SKL+ can have any value set for the clear colors.
442 if (image
->samples
== 1 && GEN_GEN
>= 9)
445 /* Other combinations of auxiliary buffers and platforms require specific
446 * values in the clear value dword(s).
449 for (; i
< cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
; i
+= 4) {
450 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
451 const uint32_t entry_offset
=
452 get_fast_clear_state_entry_offset(cmd_buffer
->device
, image
, level
);
453 sdi
.Address
= (struct anv_address
) { image
->bo
, entry_offset
+ i
};
456 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
457 assert(image
->aux_usage
== ISL_AUX_USAGE_MCS
);
458 sdi
.ImmediateData
= 0;
459 } else if (GEN_VERSIONx10
>= 75) {
460 /* Pre-SKL, the dword containing the clear values also contains
461 * other fields, so we need to initialize those fields to match the
462 * values that would be in a color attachment.
465 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
466 ISL_CHANNEL_SELECT_GREEN
<< 22 |
467 ISL_CHANNEL_SELECT_BLUE
<< 19 |
468 ISL_CHANNEL_SELECT_ALPHA
<< 16;
469 } else if (GEN_VERSIONx10
== 70) {
470 /* On IVB, the dword containing the clear values also contains
471 * other fields that must be zero or can be zero.
474 sdi
.ImmediateData
= 0;
480 /* Copy the fast-clear value dword(s) between a surface state object and an
481 * image's fast clear state buffer.
484 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
485 struct anv_state surface_state
,
486 const struct anv_image
*image
,
488 bool copy_from_surface_state
)
490 assert(cmd_buffer
&& image
);
491 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
492 assert(level
< anv_image_aux_levels(image
));
494 struct anv_bo
*ss_bo
=
495 &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
;
496 uint32_t ss_clear_offset
= surface_state
.offset
+
497 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
;
498 uint32_t entry_offset
=
499 get_fast_clear_state_entry_offset(cmd_buffer
->device
, image
, level
);
500 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
502 if (copy_from_surface_state
) {
503 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, image
->bo
, entry_offset
,
504 ss_bo
, ss_clear_offset
, copy_size
);
506 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_bo
, ss_clear_offset
,
507 image
->bo
, entry_offset
, copy_size
);
509 /* Updating a surface state object may require that the state cache be
510 * invalidated. From the SKL PRM, Shared Functions -> State -> State
513 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
514 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
515 * modified [...], the L1 state cache must be invalidated to ensure
516 * the new surface or sampler state is fetched from system memory.
518 * In testing, SKL doesn't actually seem to need this, but HSW does.
520 cmd_buffer
->state
.pending_pipe_bits
|=
521 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
526 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
527 const struct anv_image
*image
,
528 const uint32_t base_level
, uint32_t level_count
,
529 uint32_t base_layer
, uint32_t layer_count
,
530 VkImageLayout initial_layout
,
531 VkImageLayout final_layout
)
533 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
535 if (image
->aux_surface
.isl
.size
== 0 ||
536 base_level
>= anv_image_aux_levels(image
))
539 if (initial_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
540 initial_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
)
543 /* A transition of a 3D subresource works on all slices at a time. */
544 if (image
->type
== VK_IMAGE_TYPE_3D
) {
546 layer_count
= anv_minify(image
->extent
.depth
, base_level
);
549 /* We're interested in the subresource range subset that has aux data. */
550 level_count
= MIN2(level_count
, anv_image_aux_levels(image
) - base_level
);
552 /* We're transitioning from an undefined layout. We must ensure that the
553 * clear values buffer is filled with valid data.
555 for (unsigned l
= 0; l
< level_count
; l
++)
556 init_fast_clear_state_entry(cmd_buffer
, image
, base_level
+ l
);
558 if (image
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
559 image
->aux_usage
== ISL_AUX_USAGE_MCS
) {
560 /* We're transitioning from an undefined layout so it doesn't really
561 * matter what data ends up in the color buffer. We do, however, need to
562 * ensure that the auxiliary surface is not in an undefined state. This
563 * state is possible for CCS buffers SKL+ and MCS buffers with certain
564 * sample counts that require certain bits to be reserved (2x and 8x).
565 * One easy way to get to a valid state is to fast-clear the specified
568 * Even for MCS buffers that have sample counts that don't require
569 * certain bits to be reserved (4x and 8x), we're unsure if the hardware
570 * will be okay with the sample mappings given by the undefined buffer.
571 * We don't have any data to show that this is a problem, but we want to
572 * avoid causing difficult-to-debug problems.
574 if (image
->samples
== 4 || image
->samples
== 16) {
575 anv_perf_warn("Doing a potentially unnecessary fast-clear to define "
579 anv_image_fast_clear(cmd_buffer
, image
, base_level
, level_count
,
580 base_layer
, layer_count
);
585 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
588 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
589 struct anv_render_pass
*pass
,
590 const VkRenderPassBeginInfo
*begin
)
592 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
593 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
595 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
597 if (pass
->attachment_count
> 0) {
598 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
599 pass
->attachment_count
*
600 sizeof(state
->attachments
[0]),
601 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
602 if (state
->attachments
== NULL
) {
603 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
604 return anv_batch_set_error(&cmd_buffer
->batch
,
605 VK_ERROR_OUT_OF_HOST_MEMORY
);
608 state
->attachments
= NULL
;
611 /* Reserve one for the NULL state. */
612 unsigned num_states
= 1;
613 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
614 if (vk_format_is_color(pass
->attachments
[i
].format
))
617 if (need_input_attachment_state(&pass
->attachments
[i
]))
621 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
622 state
->render_pass_states
=
623 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
624 num_states
* ss_stride
, isl_dev
->ss
.align
);
626 struct anv_state next_state
= state
->render_pass_states
;
627 next_state
.alloc_size
= isl_dev
->ss
.size
;
629 state
->null_surface_state
= next_state
;
630 next_state
.offset
+= ss_stride
;
631 next_state
.map
+= ss_stride
;
633 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
634 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
635 state
->attachments
[i
].color_rt_state
= next_state
;
636 next_state
.offset
+= ss_stride
;
637 next_state
.map
+= ss_stride
;
640 if (need_input_attachment_state(&pass
->attachments
[i
])) {
641 state
->attachments
[i
].input_att_state
= next_state
;
642 next_state
.offset
+= ss_stride
;
643 next_state
.map
+= ss_stride
;
646 assert(next_state
.offset
== state
->render_pass_states
.offset
+
647 state
->render_pass_states
.alloc_size
);
650 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
651 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
653 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
654 .SurfaceType
= SURFTYPE_NULL
,
655 .SurfaceArray
= framebuffer
->layers
> 0,
656 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
660 .TiledSurface
= true,
662 .Width
= framebuffer
->width
- 1,
663 .Height
= framebuffer
->height
- 1,
664 .Depth
= framebuffer
->layers
- 1,
665 .RenderTargetViewExtent
= framebuffer
->layers
- 1,
667 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
->null_surface_state
.map
,
670 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
671 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
672 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
673 VkImageAspectFlags clear_aspects
= 0;
675 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
676 /* color attachment */
677 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
678 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
681 /* depthstencil attachment */
682 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
683 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
684 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
686 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
687 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
688 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
692 state
->attachments
[i
].current_layout
= att
->initial_layout
;
693 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
695 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
697 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
698 anv_assert(iview
->vk_format
== att
->format
);
700 union isl_color_value clear_color
= { .u32
= { 0, } };
701 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
702 color_attachment_compute_aux_usage(cmd_buffer
->device
,
703 state
, i
, begin
->renderArea
,
706 struct isl_view view
= iview
->isl
;
707 view
.usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
708 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
709 isl_surf_fill_state(isl_dev
,
710 state
->attachments
[i
].color_rt_state
.map
,
711 .surf
= &iview
->image
->color_surface
.isl
,
713 .aux_surf
= &iview
->image
->aux_surface
.isl
,
714 .aux_usage
= state
->attachments
[i
].aux_usage
,
715 .clear_color
= clear_color
,
716 .mocs
= cmd_buffer
->device
->default_mocs
);
718 add_image_relocs(cmd_buffer
, iview
->image
, iview
->aspect_mask
,
719 state
->attachments
[i
].aux_usage
,
720 state
->attachments
[i
].color_rt_state
);
722 /* This field will be initialized after the first subpass
725 state
->attachments
[i
].aux_usage
= ISL_AUX_USAGE_NONE
;
727 state
->attachments
[i
].input_aux_usage
= ISL_AUX_USAGE_NONE
;
730 if (need_input_attachment_state(&pass
->attachments
[i
])) {
731 struct isl_view view
= iview
->isl
;
732 view
.usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
733 isl_surf_fill_state(isl_dev
,
734 state
->attachments
[i
].input_att_state
.map
,
735 .surf
= &iview
->image
->color_surface
.isl
,
737 .aux_surf
= &iview
->image
->aux_surface
.isl
,
738 .aux_usage
= state
->attachments
[i
].input_aux_usage
,
739 .clear_color
= clear_color
,
740 .mocs
= cmd_buffer
->device
->default_mocs
);
742 add_image_relocs(cmd_buffer
, iview
->image
, iview
->aspect_mask
,
743 state
->attachments
[i
].input_aux_usage
,
744 state
->attachments
[i
].input_att_state
);
748 anv_state_flush(cmd_buffer
->device
, state
->render_pass_states
);
755 genX(BeginCommandBuffer
)(
756 VkCommandBuffer commandBuffer
,
757 const VkCommandBufferBeginInfo
* pBeginInfo
)
759 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
761 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
762 * command buffer's state. Otherwise, we must *reset* its state. In both
765 * From the Vulkan 1.0 spec:
767 * If a command buffer is in the executable state and the command buffer
768 * was allocated from a command pool with the
769 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
770 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
771 * as if vkResetCommandBuffer had been called with
772 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
773 * the command buffer in the recording state.
775 anv_cmd_buffer_reset(cmd_buffer
);
777 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
779 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
780 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
782 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
784 /* We sometimes store vertex data in the dynamic state buffer for blorp
785 * operations and our dynamic state stream may re-use data from previous
786 * command buffers. In order to prevent stale cache data, we flush the VF
787 * cache. We could do this on every blorp call but that's not really
788 * needed as all of the data will get written by the CPU prior to the GPU
789 * executing anything. The chances are fairly high that they will use
790 * blorp at least once per primary command buffer so it shouldn't be
793 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
794 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
796 VkResult result
= VK_SUCCESS
;
797 if (cmd_buffer
->usage_flags
&
798 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
799 cmd_buffer
->state
.pass
=
800 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
801 cmd_buffer
->state
.subpass
=
802 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
803 cmd_buffer
->state
.framebuffer
= NULL
;
805 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
806 cmd_buffer
->state
.pass
, NULL
);
808 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
815 genX(EndCommandBuffer
)(
816 VkCommandBuffer commandBuffer
)
818 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
820 if (anv_batch_has_error(&cmd_buffer
->batch
))
821 return cmd_buffer
->batch
.status
;
823 /* We want every command buffer to start with the PMA fix in a known state,
824 * so we disable it at the end of the command buffer.
826 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
828 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
830 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
836 genX(CmdExecuteCommands
)(
837 VkCommandBuffer commandBuffer
,
838 uint32_t commandBufferCount
,
839 const VkCommandBuffer
* pCmdBuffers
)
841 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
843 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
845 if (anv_batch_has_error(&primary
->batch
))
848 /* The secondary command buffers will assume that the PMA fix is disabled
849 * when they begin executing. Make sure this is true.
851 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
853 /* The secondary command buffer doesn't know which textures etc. have been
854 * flushed prior to their execution. Apply those flushes now.
856 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
858 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
859 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
861 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
862 assert(!anv_batch_has_error(&secondary
->batch
));
864 if (secondary
->usage_flags
&
865 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
866 /* If we're continuing a render pass from the primary, we need to
867 * copy the surface states for the current subpass into the storage
868 * we allocated for them in BeginCommandBuffer.
870 struct anv_bo
*ss_bo
=
871 &primary
->device
->surface_state_pool
.block_pool
.bo
;
872 struct anv_state src_state
= primary
->state
.render_pass_states
;
873 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
874 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
876 genX(cmd_buffer_so_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
877 ss_bo
, src_state
.offset
,
878 src_state
.alloc_size
);
881 anv_cmd_buffer_add_secondary(primary
, secondary
);
884 /* Each of the secondary command buffers will use its own state base
885 * address. We need to re-emit state base address for the primary after
886 * all of the secondaries are done.
888 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
891 genX(cmd_buffer_emit_state_base_address
)(primary
);
894 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
895 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
896 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
899 * Program the hardware to use the specified L3 configuration.
902 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
903 const struct gen_l3_config
*cfg
)
906 if (cfg
== cmd_buffer
->state
.current_l3_config
)
909 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
910 fprintf(stderr
, "L3 config transition: ");
911 gen_dump_l3_config(cfg
, stderr
);
914 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
916 /* According to the hardware docs, the L3 partitioning can only be changed
917 * while the pipeline is completely drained and the caches are flushed,
918 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
920 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
921 pc
.DCFlushEnable
= true;
922 pc
.PostSyncOperation
= NoWrite
;
923 pc
.CommandStreamerStallEnable
= true;
926 /* ...followed by a second pipelined PIPE_CONTROL that initiates
927 * invalidation of the relevant caches. Note that because RO invalidation
928 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
929 * command is processed by the CS) we cannot combine it with the previous
930 * stalling flush as the hardware documentation suggests, because that
931 * would cause the CS to stall on previous rendering *after* RO
932 * invalidation and wouldn't prevent the RO caches from being polluted by
933 * concurrent rendering before the stall completes. This intentionally
934 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
935 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
936 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
937 * already guarantee that there is no concurrent GPGPU kernel execution
938 * (see SKL HSD 2132585).
940 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
941 pc
.TextureCacheInvalidationEnable
= true;
942 pc
.ConstantCacheInvalidationEnable
= true;
943 pc
.InstructionCacheInvalidateEnable
= true;
944 pc
.StateCacheInvalidationEnable
= true;
945 pc
.PostSyncOperation
= NoWrite
;
948 /* Now send a third stalling flush to make sure that invalidation is
949 * complete when the L3 configuration registers are modified.
951 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
952 pc
.DCFlushEnable
= true;
953 pc
.PostSyncOperation
= NoWrite
;
954 pc
.CommandStreamerStallEnable
= true;
959 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
962 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
963 .SLMEnable
= has_slm
,
964 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
965 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
966 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
967 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
969 /* Set up the L3 partitioning. */
970 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
974 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
975 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
977 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
979 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
982 assert(!cfg
->n
[GEN_L3P_ALL
]);
984 /* When enabled SLM only uses a portion of the L3 on half of the banks,
985 * the matching space on the remaining banks has to be allocated to a
986 * client (URB for all validated configurations) set to the
987 * lower-bandwidth 2-bank address hashing mode.
989 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
990 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
991 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
993 /* Minimum number of ways that can be allocated to the URB. */
994 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
995 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
997 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
998 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
999 .ConvertDC_UC
= !has_dc
,
1000 .ConvertIS_UC
= !has_is
,
1001 .ConvertC_UC
= !has_c
,
1002 .ConvertT_UC
= !has_t
);
1004 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1005 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1006 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1008 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1009 .SLMEnable
= has_slm
,
1010 .URBLowBandwidth
= urb_low_bw
,
1011 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1013 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1015 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1016 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1018 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1019 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1020 .ISLowBandwidth
= 0,
1021 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1023 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1024 .TLowBandwidth
= 0);
1026 /* Set up the L3 partitioning. */
1027 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1028 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1029 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1032 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1033 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1034 * them disabled to avoid crashing the system hard.
1036 uint32_t scratch1
, chicken3
;
1037 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1038 .L3AtomicDisable
= !has_dc
);
1039 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1040 .L3AtomicDisableMask
= true,
1041 .L3AtomicDisable
= !has_dc
);
1042 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1043 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1049 cmd_buffer
->state
.current_l3_config
= cfg
;
1053 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1055 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1057 /* Flushes are pipelined while invalidations are handled immediately.
1058 * Therefore, if we're flushing anything then we need to schedule a stall
1059 * before any invalidations can happen.
1061 if (bits
& ANV_PIPE_FLUSH_BITS
)
1062 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1064 /* If we're going to do an invalidate and we have a pending CS stall that
1065 * has yet to be resolved, we do the CS stall now.
1067 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1068 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1069 bits
|= ANV_PIPE_CS_STALL_BIT
;
1070 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1073 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1074 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1075 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1076 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1077 pipe
.RenderTargetCacheFlushEnable
=
1078 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1080 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1081 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1082 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1085 * According to the Broadwell documentation, any PIPE_CONTROL with the
1086 * "Command Streamer Stall" bit set must also have another bit set,
1087 * with five different options:
1089 * - Render Target Cache Flush
1090 * - Depth Cache Flush
1091 * - Stall at Pixel Scoreboard
1092 * - Post-Sync Operation
1096 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1097 * mesa and it seems to work fine. The choice is fairly arbitrary.
1099 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1100 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1101 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1102 pipe
.StallAtPixelScoreboard
= true;
1105 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1108 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1109 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1110 pipe
.StateCacheInvalidationEnable
=
1111 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1112 pipe
.ConstantCacheInvalidationEnable
=
1113 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1114 pipe
.VFCacheInvalidationEnable
=
1115 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1116 pipe
.TextureCacheInvalidationEnable
=
1117 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1118 pipe
.InstructionCacheInvalidateEnable
=
1119 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1122 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1125 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1128 void genX(CmdPipelineBarrier
)(
1129 VkCommandBuffer commandBuffer
,
1130 VkPipelineStageFlags srcStageMask
,
1131 VkPipelineStageFlags destStageMask
,
1133 uint32_t memoryBarrierCount
,
1134 const VkMemoryBarrier
* pMemoryBarriers
,
1135 uint32_t bufferMemoryBarrierCount
,
1136 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1137 uint32_t imageMemoryBarrierCount
,
1138 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1140 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1142 /* XXX: Right now, we're really dumb and just flush whatever categories
1143 * the app asks for. One of these days we may make this a bit better
1144 * but right now that's all the hardware allows for in most areas.
1146 VkAccessFlags src_flags
= 0;
1147 VkAccessFlags dst_flags
= 0;
1149 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1150 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1151 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1154 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1155 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1156 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1159 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1160 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1161 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1162 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1163 const VkImageSubresourceRange
*range
=
1164 &pImageMemoryBarriers
[i
].subresourceRange
;
1166 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1167 transition_depth_buffer(cmd_buffer
, image
,
1168 pImageMemoryBarriers
[i
].oldLayout
,
1169 pImageMemoryBarriers
[i
].newLayout
);
1170 } else if (range
->aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
) {
1171 transition_color_buffer(cmd_buffer
, image
,
1172 range
->baseMipLevel
,
1173 anv_get_levelCount(image
, range
),
1174 range
->baseArrayLayer
,
1175 anv_get_layerCount(image
, range
),
1176 pImageMemoryBarriers
[i
].oldLayout
,
1177 pImageMemoryBarriers
[i
].newLayout
);
1181 cmd_buffer
->state
.pending_pipe_bits
|=
1182 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1183 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1187 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1189 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
1191 /* In order to avoid thrash, we assume that vertex and fragment stages
1192 * always exist. In the rare case where one is missing *and* the other
1193 * uses push concstants, this may be suboptimal. However, avoiding stalls
1194 * seems more important.
1196 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1198 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1202 const unsigned push_constant_kb
= 32;
1203 #elif GEN_IS_HASWELL
1204 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1206 const unsigned push_constant_kb
= 16;
1209 const unsigned num_stages
=
1210 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1211 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1213 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1214 * units of 2KB. Incidentally, these are the same platforms that have
1215 * 32KB worth of push constant space.
1217 if (push_constant_kb
== 32)
1218 size_per_stage
&= ~1u;
1220 uint32_t kb_used
= 0;
1221 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1222 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1223 anv_batch_emit(&cmd_buffer
->batch
,
1224 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1225 alloc
._3DCommandSubOpcode
= 18 + i
;
1226 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1227 alloc
.ConstantBufferSize
= push_size
;
1229 kb_used
+= push_size
;
1232 anv_batch_emit(&cmd_buffer
->batch
,
1233 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1234 alloc
.ConstantBufferOffset
= kb_used
;
1235 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1238 cmd_buffer
->state
.push_constant_stages
= stages
;
1240 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1242 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1243 * the next 3DPRIMITIVE command after programming the
1244 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1246 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1247 * pipeline setup, we need to dirty push constants.
1249 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1253 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1254 gl_shader_stage stage
,
1255 struct anv_state
*bt_state
)
1257 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1258 struct anv_pipeline
*pipeline
;
1259 uint32_t bias
, state_offset
;
1262 case MESA_SHADER_COMPUTE
:
1263 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1267 pipeline
= cmd_buffer
->state
.pipeline
;
1272 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1273 *bt_state
= (struct anv_state
) { 0, };
1277 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1278 if (bias
+ map
->surface_count
== 0) {
1279 *bt_state
= (struct anv_state
) { 0, };
1283 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1284 bias
+ map
->surface_count
,
1286 uint32_t *bt_map
= bt_state
->map
;
1288 if (bt_state
->map
== NULL
)
1289 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1291 if (stage
== MESA_SHADER_COMPUTE
&&
1292 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
1293 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
1294 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
1296 struct anv_state surface_state
;
1298 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1300 const enum isl_format format
=
1301 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1302 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1303 format
, bo_offset
, 12, 1);
1305 bt_map
[0] = surface_state
.offset
+ state_offset
;
1306 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1309 if (map
->surface_count
== 0)
1312 if (map
->image_count
> 0) {
1314 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1315 if (result
!= VK_SUCCESS
)
1318 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1322 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1323 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1325 struct anv_state surface_state
;
1327 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1328 /* Color attachment binding */
1329 assert(stage
== MESA_SHADER_FRAGMENT
);
1330 assert(binding
->binding
== 0);
1331 if (binding
->index
< subpass
->color_count
) {
1332 const unsigned att
=
1333 subpass
->color_attachments
[binding
->index
].attachment
;
1335 /* From the Vulkan 1.0.46 spec:
1337 * "If any color or depth/stencil attachments are
1338 * VK_ATTACHMENT_UNUSED, then no writes occur for those
1341 if (att
== VK_ATTACHMENT_UNUSED
) {
1342 surface_state
= cmd_buffer
->state
.null_surface_state
;
1344 surface_state
= cmd_buffer
->state
.attachments
[att
].color_rt_state
;
1347 surface_state
= cmd_buffer
->state
.null_surface_state
;
1350 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1354 struct anv_descriptor_set
*set
=
1355 cmd_buffer
->state
.descriptors
[binding
->set
];
1356 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1357 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1359 switch (desc
->type
) {
1360 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1361 /* Nothing for us to do here */
1364 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1365 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
1366 surface_state
= desc
->aux_usage
== ISL_AUX_USAGE_NONE
?
1367 desc
->image_view
->no_aux_sampler_surface_state
:
1368 desc
->image_view
->sampler_surface_state
;
1369 assert(surface_state
.alloc_size
);
1370 add_image_relocs(cmd_buffer
, desc
->image_view
->image
,
1371 desc
->image_view
->aspect_mask
,
1372 desc
->aux_usage
, surface_state
);
1374 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1375 assert(stage
== MESA_SHADER_FRAGMENT
);
1376 if (desc
->image_view
->aspect_mask
!= VK_IMAGE_ASPECT_COLOR_BIT
) {
1377 /* For depth and stencil input attachments, we treat it like any
1378 * old texture that a user may have bound.
1380 surface_state
= desc
->aux_usage
== ISL_AUX_USAGE_NONE
?
1381 desc
->image_view
->no_aux_sampler_surface_state
:
1382 desc
->image_view
->sampler_surface_state
;
1383 assert(surface_state
.alloc_size
);
1384 add_image_relocs(cmd_buffer
, desc
->image_view
->image
,
1385 desc
->image_view
->aspect_mask
,
1386 desc
->aux_usage
, surface_state
);
1388 /* For color input attachments, we create the surface state at
1389 * vkBeginRenderPass time so that we can include aux and clear
1390 * color information.
1392 assert(binding
->input_attachment_index
< subpass
->input_count
);
1393 const unsigned subpass_att
= binding
->input_attachment_index
;
1394 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
1395 surface_state
= cmd_buffer
->state
.attachments
[att
].input_att_state
;
1399 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1400 surface_state
= (binding
->write_only
)
1401 ? desc
->image_view
->writeonly_storage_surface_state
1402 : desc
->image_view
->storage_surface_state
;
1403 assert(surface_state
.alloc_size
);
1404 add_image_relocs(cmd_buffer
, desc
->image_view
->image
,
1405 desc
->image_view
->aspect_mask
,
1406 desc
->image_view
->image
->aux_usage
, surface_state
);
1408 struct brw_image_param
*image_param
=
1409 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1411 *image_param
= desc
->image_view
->storage_image_param
;
1412 image_param
->surface_idx
= bias
+ s
;
1416 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
1417 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
1418 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
1419 surface_state
= desc
->buffer_view
->surface_state
;
1420 assert(surface_state
.alloc_size
);
1421 add_surface_state_reloc(cmd_buffer
, surface_state
,
1422 desc
->buffer_view
->bo
,
1423 desc
->buffer_view
->offset
);
1426 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
1427 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
1428 uint32_t dynamic_offset_idx
=
1429 pipeline
->layout
->set
[binding
->set
].dynamic_offset_start
+
1430 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1433 /* Compute the offset within the buffer */
1434 uint64_t offset
= desc
->offset
+
1435 cmd_buffer
->state
.dynamic_offsets
[dynamic_offset_idx
];
1436 /* Clamp to the buffer size */
1437 offset
= MIN2(offset
, desc
->buffer
->size
);
1438 /* Clamp the range to the buffer size */
1439 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
1442 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
1443 enum isl_format format
=
1444 anv_isl_format_for_descriptor_type(desc
->type
);
1446 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1447 format
, offset
, range
, 1);
1448 add_surface_state_reloc(cmd_buffer
, surface_state
,
1450 desc
->buffer
->offset
+ offset
);
1454 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
1455 surface_state
= (binding
->write_only
)
1456 ? desc
->buffer_view
->writeonly_storage_surface_state
1457 : desc
->buffer_view
->storage_surface_state
;
1458 assert(surface_state
.alloc_size
);
1459 add_surface_state_reloc(cmd_buffer
, surface_state
,
1460 desc
->buffer_view
->bo
,
1461 desc
->buffer_view
->offset
);
1463 struct brw_image_param
*image_param
=
1464 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1466 *image_param
= desc
->buffer_view
->storage_image_param
;
1467 image_param
->surface_idx
= bias
+ s
;
1471 assert(!"Invalid descriptor type");
1475 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1477 assert(image
== map
->image_count
);
1480 anv_state_flush(cmd_buffer
->device
, *bt_state
);
1486 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1487 gl_shader_stage stage
,
1488 struct anv_state
*state
)
1490 struct anv_pipeline
*pipeline
;
1492 if (stage
== MESA_SHADER_COMPUTE
)
1493 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1495 pipeline
= cmd_buffer
->state
.pipeline
;
1497 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1498 *state
= (struct anv_state
) { 0, };
1502 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1503 if (map
->sampler_count
== 0) {
1504 *state
= (struct anv_state
) { 0, };
1508 uint32_t size
= map
->sampler_count
* 16;
1509 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1511 if (state
->map
== NULL
)
1512 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1514 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1515 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1516 struct anv_descriptor_set
*set
=
1517 cmd_buffer
->state
.descriptors
[binding
->set
];
1518 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1519 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1521 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1522 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1525 struct anv_sampler
*sampler
= desc
->sampler
;
1527 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1528 * happens to be zero.
1530 if (sampler
== NULL
)
1533 memcpy(state
->map
+ (s
* 16),
1534 sampler
->state
, sizeof(sampler
->state
));
1537 anv_state_flush(cmd_buffer
->device
, *state
);
1543 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1545 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1546 cmd_buffer
->state
.pipeline
->active_stages
;
1548 VkResult result
= VK_SUCCESS
;
1549 anv_foreach_stage(s
, dirty
) {
1550 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1551 if (result
!= VK_SUCCESS
)
1553 result
= emit_binding_table(cmd_buffer
, s
,
1554 &cmd_buffer
->state
.binding_tables
[s
]);
1555 if (result
!= VK_SUCCESS
)
1559 if (result
!= VK_SUCCESS
) {
1560 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1562 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1563 if (result
!= VK_SUCCESS
)
1566 /* Re-emit state base addresses so we get the new surface state base
1567 * address before we start emitting binding tables etc.
1569 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1571 /* Re-emit all active binding tables */
1572 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
1573 anv_foreach_stage(s
, dirty
) {
1574 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1575 if (result
!= VK_SUCCESS
) {
1576 anv_batch_set_error(&cmd_buffer
->batch
, result
);
1579 result
= emit_binding_table(cmd_buffer
, s
,
1580 &cmd_buffer
->state
.binding_tables
[s
]);
1581 if (result
!= VK_SUCCESS
) {
1582 anv_batch_set_error(&cmd_buffer
->batch
, result
);
1588 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1594 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1597 static const uint32_t sampler_state_opcodes
[] = {
1598 [MESA_SHADER_VERTEX
] = 43,
1599 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1600 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1601 [MESA_SHADER_GEOMETRY
] = 46,
1602 [MESA_SHADER_FRAGMENT
] = 47,
1603 [MESA_SHADER_COMPUTE
] = 0,
1606 static const uint32_t binding_table_opcodes
[] = {
1607 [MESA_SHADER_VERTEX
] = 38,
1608 [MESA_SHADER_TESS_CTRL
] = 39,
1609 [MESA_SHADER_TESS_EVAL
] = 40,
1610 [MESA_SHADER_GEOMETRY
] = 41,
1611 [MESA_SHADER_FRAGMENT
] = 42,
1612 [MESA_SHADER_COMPUTE
] = 0,
1615 anv_foreach_stage(s
, stages
) {
1616 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1617 anv_batch_emit(&cmd_buffer
->batch
,
1618 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1619 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1620 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1624 /* Always emit binding table pointers if we're asked to, since on SKL
1625 * this is what flushes push constants. */
1626 anv_batch_emit(&cmd_buffer
->batch
,
1627 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1628 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1629 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1635 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1637 static const uint32_t push_constant_opcodes
[] = {
1638 [MESA_SHADER_VERTEX
] = 21,
1639 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1640 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1641 [MESA_SHADER_GEOMETRY
] = 22,
1642 [MESA_SHADER_FRAGMENT
] = 23,
1643 [MESA_SHADER_COMPUTE
] = 0,
1646 VkShaderStageFlags flushed
= 0;
1648 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
1649 if (stage
== MESA_SHADER_COMPUTE
)
1652 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1654 if (state
.offset
== 0) {
1655 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1656 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1658 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1659 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1660 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1662 .Buffer
[2] = { &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
, state
.offset
},
1663 .ReadLength
[2] = DIV_ROUND_UP(state
.alloc_size
, 32),
1665 .Buffer
[0] = { .offset
= state
.offset
},
1666 .ReadLength
[0] = DIV_ROUND_UP(state
.alloc_size
, 32),
1672 flushed
|= mesa_to_vk_shader_stage(stage
);
1675 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1681 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1683 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1686 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1688 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1690 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1692 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1695 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1696 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1698 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1699 GENX(3DSTATE_VERTEX_BUFFERS
));
1701 for_each_bit(vb
, vb_emit
) {
1702 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1703 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1705 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1706 .VertexBufferIndex
= vb
,
1709 .MemoryObjectControlState
= GENX(MOCS
),
1711 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1712 /* Our implementation of VK_KHR_multiview uses instancing to draw
1713 * the different views. If the client asks for instancing, we
1714 * need to use the Instance Data Step Rate to ensure that we
1715 * repeat the client's per-instance data once for each view.
1717 .InstanceDataStepRate
= anv_subpass_view_count(pipeline
->subpass
),
1718 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1721 .AddressModifyEnable
= true,
1722 .BufferPitch
= pipeline
->binding_stride
[vb
],
1723 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1726 .BufferSize
= buffer
->size
- offset
1728 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1732 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1737 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1739 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1740 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1742 /* The exact descriptor layout is pulled from the pipeline, so we need
1743 * to re-emit binding tables on every pipeline change.
1745 cmd_buffer
->state
.descriptors_dirty
|=
1746 cmd_buffer
->state
.pipeline
->active_stages
;
1748 /* If the pipeline changed, we may need to re-allocate push constant
1751 cmd_buffer_alloc_push_constants(cmd_buffer
);
1755 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1756 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1757 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1759 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1760 * stall needs to be sent just prior to any 3DSTATE_VS,
1761 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1762 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1763 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1764 * PIPE_CONTROL needs to be sent before any combination of VS
1765 * associated 3DSTATE."
1767 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1768 pc
.DepthStallEnable
= true;
1769 pc
.PostSyncOperation
= WriteImmediateData
;
1771 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1776 /* Render targets live in the same binding table as fragment descriptors */
1777 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1778 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1780 /* We emit the binding tables and sampler tables first, then emit push
1781 * constants and then finally emit binding table and sampler table
1782 * pointers. It has to happen in this order, since emitting the binding
1783 * tables may change the push constants (in case of storage images). After
1784 * emitting push constants, on SKL+ we have to emit the corresponding
1785 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1788 if (cmd_buffer
->state
.descriptors_dirty
)
1789 dirty
= flush_descriptor_sets(cmd_buffer
);
1791 if (cmd_buffer
->state
.push_constants_dirty
) {
1793 /* On Sky Lake and later, the binding table pointers commands are
1794 * what actually flush the changes to push constant state so we need
1795 * to dirty them so they get re-emitted below.
1797 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1799 cmd_buffer_flush_push_constants(cmd_buffer
);
1804 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1806 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1807 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1809 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1810 ANV_CMD_DIRTY_PIPELINE
)) {
1811 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1812 pipeline
->depth_clamp_enable
);
1815 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1816 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1818 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1820 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1824 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
1825 struct anv_bo
*bo
, uint32_t offset
,
1826 uint32_t size
, uint32_t index
)
1828 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1829 GENX(3DSTATE_VERTEX_BUFFERS
));
1831 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1832 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1833 .VertexBufferIndex
= index
,
1834 .AddressModifyEnable
= true,
1837 .MemoryObjectControlState
= GENX(MOCS
),
1838 .BufferStartingAddress
= { bo
, offset
},
1841 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1842 .BufferStartingAddress
= { bo
, offset
},
1843 .EndAddress
= { bo
, offset
+ size
},
1849 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1850 struct anv_bo
*bo
, uint32_t offset
)
1852 emit_vertex_bo(cmd_buffer
, bo
, offset
, 8, ANV_SVGS_VB_INDEX
);
1856 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1857 uint32_t base_vertex
, uint32_t base_instance
)
1859 struct anv_state id_state
=
1860 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1862 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1863 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1865 anv_state_flush(cmd_buffer
->device
, id_state
);
1867 emit_base_vertex_instance_bo(cmd_buffer
,
1868 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
, id_state
.offset
);
1872 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
1874 struct anv_state state
=
1875 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
1877 ((uint32_t *)state
.map
)[0] = draw_index
;
1879 anv_state_flush(cmd_buffer
->device
, state
);
1881 emit_vertex_bo(cmd_buffer
,
1882 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
1883 state
.offset
, 4, ANV_DRAWID_VB_INDEX
);
1887 VkCommandBuffer commandBuffer
,
1888 uint32_t vertexCount
,
1889 uint32_t instanceCount
,
1890 uint32_t firstVertex
,
1891 uint32_t firstInstance
)
1893 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1894 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1895 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1897 if (anv_batch_has_error(&cmd_buffer
->batch
))
1900 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1902 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1903 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1904 if (vs_prog_data
->uses_drawid
)
1905 emit_draw_index(cmd_buffer
, 0);
1907 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1908 * different views. We need to multiply instanceCount by the view count.
1910 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
1912 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1913 prim
.VertexAccessType
= SEQUENTIAL
;
1914 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1915 prim
.VertexCountPerInstance
= vertexCount
;
1916 prim
.StartVertexLocation
= firstVertex
;
1917 prim
.InstanceCount
= instanceCount
;
1918 prim
.StartInstanceLocation
= firstInstance
;
1919 prim
.BaseVertexLocation
= 0;
1923 void genX(CmdDrawIndexed
)(
1924 VkCommandBuffer commandBuffer
,
1925 uint32_t indexCount
,
1926 uint32_t instanceCount
,
1927 uint32_t firstIndex
,
1928 int32_t vertexOffset
,
1929 uint32_t firstInstance
)
1931 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1932 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1933 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1935 if (anv_batch_has_error(&cmd_buffer
->batch
))
1938 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1940 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1941 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1942 if (vs_prog_data
->uses_drawid
)
1943 emit_draw_index(cmd_buffer
, 0);
1945 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1946 * different views. We need to multiply instanceCount by the view count.
1948 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
1950 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1951 prim
.VertexAccessType
= RANDOM
;
1952 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1953 prim
.VertexCountPerInstance
= indexCount
;
1954 prim
.StartVertexLocation
= firstIndex
;
1955 prim
.InstanceCount
= instanceCount
;
1956 prim
.StartInstanceLocation
= firstInstance
;
1957 prim
.BaseVertexLocation
= vertexOffset
;
1961 /* Auto-Draw / Indirect Registers */
1962 #define GEN7_3DPRIM_END_OFFSET 0x2420
1963 #define GEN7_3DPRIM_START_VERTEX 0x2430
1964 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1965 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1966 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1967 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1969 /* MI_MATH only exists on Haswell+ */
1970 #if GEN_IS_HASWELL || GEN_GEN >= 8
1973 mi_alu(uint32_t opcode
, uint32_t op1
, uint32_t op2
)
1975 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
1976 .ALUOpcode
= opcode
,
1982 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
1987 #define CS_GPR(n) (0x2600 + (n) * 8)
1989 /* Emit dwords to multiply GPR0 by N */
1991 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
1993 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
1995 #define append_alu(opcode, operand1, operand2) \
1996 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
1999 unsigned top_bit
= 31 - __builtin_clz(N
);
2000 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2001 /* We get our initial data in GPR0 and we write the final data out to
2002 * GPR0 but we use GPR1 as our scratch register.
2004 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2005 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2007 /* Shift the current value left by 1 */
2008 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2009 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2010 append_alu(MI_ALU_ADD
, 0, 0);
2013 /* Store ACCU to R1 and add R0 to R1 */
2014 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2015 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2016 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2017 append_alu(MI_ALU_ADD
, 0, 0);
2020 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2027 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2029 uint32_t num_dwords
;
2030 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2032 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2033 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2036 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2039 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2040 struct anv_buffer
*buffer
, uint64_t offset
,
2043 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2044 struct anv_bo
*bo
= buffer
->bo
;
2045 uint32_t bo_offset
= buffer
->offset
+ offset
;
2047 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
2049 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2050 if (view_count
> 1) {
2051 #if GEN_IS_HASWELL || GEN_GEN >= 8
2052 emit_lrm(batch
, CS_GPR(0), bo
, bo_offset
+ 4);
2053 emit_mul_gpr0(batch
, view_count
);
2054 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2056 anv_finishme("Multiview + indirect draw requires MI_MATH\n"
2057 "MI_MATH is not supported on Ivy Bridge");
2058 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2061 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2064 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
2067 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
2068 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
2070 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
2071 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2075 void genX(CmdDrawIndirect
)(
2076 VkCommandBuffer commandBuffer
,
2078 VkDeviceSize offset
,
2082 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2083 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2084 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2085 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2087 if (anv_batch_has_error(&cmd_buffer
->batch
))
2090 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2092 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2093 struct anv_bo
*bo
= buffer
->bo
;
2094 uint32_t bo_offset
= buffer
->offset
+ offset
;
2096 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2097 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
2098 if (vs_prog_data
->uses_drawid
)
2099 emit_draw_index(cmd_buffer
, i
);
2101 load_indirect_parameters(cmd_buffer
, buffer
, offset
, false);
2103 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2104 prim
.IndirectParameterEnable
= true;
2105 prim
.VertexAccessType
= SEQUENTIAL
;
2106 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2113 void genX(CmdDrawIndexedIndirect
)(
2114 VkCommandBuffer commandBuffer
,
2116 VkDeviceSize offset
,
2120 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2121 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2122 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2123 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2125 if (anv_batch_has_error(&cmd_buffer
->batch
))
2128 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2130 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2131 struct anv_bo
*bo
= buffer
->bo
;
2132 uint32_t bo_offset
= buffer
->offset
+ offset
;
2134 /* TODO: We need to stomp base vertex to 0 somehow */
2135 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2136 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
2137 if (vs_prog_data
->uses_drawid
)
2138 emit_draw_index(cmd_buffer
, i
);
2140 load_indirect_parameters(cmd_buffer
, buffer
, offset
, true);
2142 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2143 prim
.IndirectParameterEnable
= true;
2144 prim
.VertexAccessType
= RANDOM
;
2145 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2153 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2155 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2156 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2159 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2160 if (result
!= VK_SUCCESS
) {
2161 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2163 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2164 if (result
!= VK_SUCCESS
)
2167 /* Re-emit state base addresses so we get the new surface state base
2168 * address before we start emitting binding tables etc.
2170 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2172 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2173 if (result
!= VK_SUCCESS
) {
2174 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2179 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
2180 if (result
!= VK_SUCCESS
) {
2181 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2185 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
2186 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2187 .BindingTablePointer
= surfaces
.offset
,
2188 .SamplerStatePointer
= samplers
.offset
,
2190 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
2192 struct anv_state state
=
2193 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
2194 pipeline
->interface_descriptor_data
,
2195 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
2198 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
2199 anv_batch_emit(&cmd_buffer
->batch
,
2200 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
2201 mid
.InterfaceDescriptorTotalLength
= size
;
2202 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
2209 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2211 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2212 MAYBE_UNUSED VkResult result
;
2214 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
2216 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2218 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
2220 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2221 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
2223 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
2224 * the only bits that are changed are scoreboard related: Scoreboard
2225 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
2226 * these scoreboard related states, a MEDIA_STATE_FLUSH is
2229 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2230 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2232 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2235 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
2236 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
2237 /* FIXME: figure out descriptors for gen7 */
2238 result
= flush_compute_descriptor_set(cmd_buffer
);
2239 if (result
!= VK_SUCCESS
)
2242 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
2245 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
2246 struct anv_state push_state
=
2247 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
2249 if (push_state
.alloc_size
) {
2250 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
2251 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
2252 curbe
.CURBEDataStartAddress
= push_state
.offset
;
2257 cmd_buffer
->state
.compute_dirty
= 0;
2259 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2265 verify_cmd_parser(const struct anv_device
*device
,
2266 int required_version
,
2267 const char *function
)
2269 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
2270 return vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
2271 "cmd parser version %d is required for %s",
2272 required_version
, function
);
2280 void genX(CmdDispatch
)(
2281 VkCommandBuffer commandBuffer
,
2286 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2287 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2288 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
2290 if (anv_batch_has_error(&cmd_buffer
->batch
))
2293 if (prog_data
->uses_num_work_groups
) {
2294 struct anv_state state
=
2295 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
2296 uint32_t *sizes
= state
.map
;
2300 anv_state_flush(cmd_buffer
->device
, state
);
2301 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
2302 cmd_buffer
->state
.num_workgroups_bo
=
2303 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
;
2306 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2308 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
2309 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2310 ggw
.ThreadDepthCounterMaximum
= 0;
2311 ggw
.ThreadHeightCounterMaximum
= 0;
2312 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2313 ggw
.ThreadGroupIDXDimension
= x
;
2314 ggw
.ThreadGroupIDYDimension
= y
;
2315 ggw
.ThreadGroupIDZDimension
= z
;
2316 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2317 ggw
.BottomExecutionMask
= 0xffffffff;
2320 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2323 #define GPGPU_DISPATCHDIMX 0x2500
2324 #define GPGPU_DISPATCHDIMY 0x2504
2325 #define GPGPU_DISPATCHDIMZ 0x2508
2327 #define MI_PREDICATE_SRC0 0x2400
2328 #define MI_PREDICATE_SRC1 0x2408
2330 void genX(CmdDispatchIndirect
)(
2331 VkCommandBuffer commandBuffer
,
2333 VkDeviceSize offset
)
2335 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2336 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2337 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2338 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
2339 struct anv_bo
*bo
= buffer
->bo
;
2340 uint32_t bo_offset
= buffer
->offset
+ offset
;
2341 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2344 /* Linux 4.4 added command parser version 5 which allows the GPGPU
2345 * indirect dispatch registers to be written.
2347 if (verify_cmd_parser(cmd_buffer
->device
, 5,
2348 "vkCmdDispatchIndirect") != VK_SUCCESS
)
2352 if (prog_data
->uses_num_work_groups
) {
2353 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
2354 cmd_buffer
->state
.num_workgroups_bo
= bo
;
2357 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2359 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
2360 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
2361 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
2364 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
2365 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
2366 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
2367 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
2369 /* Load compute_dispatch_indirect_x_size into SRC0 */
2370 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
2372 /* predicate = (compute_dispatch_indirect_x_size == 0); */
2373 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2374 mip
.LoadOperation
= LOAD_LOAD
;
2375 mip
.CombineOperation
= COMBINE_SET
;
2376 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2379 /* Load compute_dispatch_indirect_y_size into SRC0 */
2380 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
2382 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
2383 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2384 mip
.LoadOperation
= LOAD_LOAD
;
2385 mip
.CombineOperation
= COMBINE_OR
;
2386 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2389 /* Load compute_dispatch_indirect_z_size into SRC0 */
2390 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
2392 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
2393 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2394 mip
.LoadOperation
= LOAD_LOAD
;
2395 mip
.CombineOperation
= COMBINE_OR
;
2396 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2399 /* predicate = !predicate; */
2400 #define COMPARE_FALSE 1
2401 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2402 mip
.LoadOperation
= LOAD_LOADINV
;
2403 mip
.CombineOperation
= COMBINE_OR
;
2404 mip
.CompareOperation
= COMPARE_FALSE
;
2408 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
2409 ggw
.IndirectParameterEnable
= true;
2410 ggw
.PredicateEnable
= GEN_GEN
<= 7;
2411 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2412 ggw
.ThreadDepthCounterMaximum
= 0;
2413 ggw
.ThreadHeightCounterMaximum
= 0;
2414 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2415 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2416 ggw
.BottomExecutionMask
= 0xffffffff;
2419 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2423 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
2426 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
2429 #if GEN_GEN >= 8 && GEN_GEN < 10
2430 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
2432 * Software must clear the COLOR_CALC_STATE Valid field in
2433 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
2434 * with Pipeline Select set to GPGPU.
2436 * The internal hardware docs recommend the same workaround for Gen9
2439 if (pipeline
== GPGPU
)
2440 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
2443 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
2444 * PIPELINE_SELECT [DevBWR+]":
2448 * Software must ensure all the write caches are flushed through a
2449 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
2450 * command to invalidate read only caches prior to programming
2451 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
2453 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2454 pc
.RenderTargetCacheFlushEnable
= true;
2455 pc
.DepthCacheFlushEnable
= true;
2456 pc
.DCFlushEnable
= true;
2457 pc
.PostSyncOperation
= NoWrite
;
2458 pc
.CommandStreamerStallEnable
= true;
2461 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2462 pc
.TextureCacheInvalidationEnable
= true;
2463 pc
.ConstantCacheInvalidationEnable
= true;
2464 pc
.StateCacheInvalidationEnable
= true;
2465 pc
.InstructionCacheInvalidateEnable
= true;
2466 pc
.PostSyncOperation
= NoWrite
;
2469 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2473 ps
.PipelineSelection
= pipeline
;
2476 cmd_buffer
->state
.current_pipeline
= pipeline
;
2480 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
2482 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
2486 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
2488 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
2492 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
2497 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
2499 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
2500 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
2501 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
2502 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
2503 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
2504 * Depth Flush Bit set, followed by another pipelined depth stall
2505 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
2506 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
2507 * via a preceding MI_FLUSH)."
2509 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2510 pipe
.DepthStallEnable
= true;
2512 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2513 pipe
.DepthCacheFlushEnable
= true;
2515 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2516 pipe
.DepthStallEnable
= true;
2521 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
2523 struct anv_device
*device
= cmd_buffer
->device
;
2524 const struct anv_image_view
*iview
=
2525 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2526 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
2528 /* FIXME: Width and Height are wrong */
2530 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
2532 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
2533 device
->isl_dev
.ds
.size
/ 4);
2537 struct isl_depth_stencil_hiz_emit_info info
= {
2538 .mocs
= device
->default_mocs
,
2542 info
.view
= &iview
->isl
;
2544 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
2545 info
.depth_surf
= &image
->depth_surface
.isl
;
2547 info
.depth_address
=
2548 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2549 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
2551 image
->offset
+ image
->depth_surface
.offset
);
2554 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.attachment
;
2555 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
2556 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
2557 info
.hiz_surf
= &image
->aux_surface
.isl
;
2560 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2561 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
2563 image
->offset
+ image
->aux_surface
.offset
);
2565 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
2569 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
2570 info
.stencil_surf
= &image
->stencil_surface
.isl
;
2572 info
.stencil_address
=
2573 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2574 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
2576 image
->offset
+ image
->stencil_surface
.offset
);
2579 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
2581 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
2586 * @brief Perform any layout transitions required at the beginning and/or end
2587 * of the current subpass for depth buffers.
2589 * TODO: Consider preprocessing the attachment reference array at render pass
2590 * create time to determine if no layout transition is needed at the
2591 * beginning and/or end of each subpass.
2593 * @param cmd_buffer The command buffer the transition is happening within.
2594 * @param subpass_end If true, marks that the transition is happening at the
2595 * end of the subpass.
2598 cmd_buffer_subpass_transition_layouts(struct anv_cmd_buffer
* const cmd_buffer
,
2599 const bool subpass_end
)
2601 /* We need a non-NULL command buffer. */
2604 const struct anv_cmd_state
* const cmd_state
= &cmd_buffer
->state
;
2605 const struct anv_subpass
* const subpass
= cmd_state
->subpass
;
2607 /* This function must be called within a subpass. */
2610 /* If there are attachment references, the array shouldn't be NULL.
2612 if (subpass
->attachment_count
> 0)
2613 assert(subpass
->attachments
);
2615 /* Iterate over the array of attachment references. */
2616 for (const VkAttachmentReference
*att_ref
= subpass
->attachments
;
2617 att_ref
< subpass
->attachments
+ subpass
->attachment_count
; att_ref
++) {
2619 /* If the attachment is unused, we can't perform a layout transition. */
2620 if (att_ref
->attachment
== VK_ATTACHMENT_UNUSED
)
2623 /* This attachment index shouldn't go out of bounds. */
2624 assert(att_ref
->attachment
< cmd_state
->pass
->attachment_count
);
2626 const struct anv_render_pass_attachment
* const att_desc
=
2627 &cmd_state
->pass
->attachments
[att_ref
->attachment
];
2628 struct anv_attachment_state
* const att_state
=
2629 &cmd_buffer
->state
.attachments
[att_ref
->attachment
];
2631 /* The attachment should not be used in a subpass after its last. */
2632 assert(att_desc
->last_subpass_idx
>= anv_get_subpass_id(cmd_state
));
2634 if (subpass_end
&& anv_get_subpass_id(cmd_state
) <
2635 att_desc
->last_subpass_idx
) {
2636 /* We're calling this function on a buffer twice in one subpass and
2637 * this is not the last use of the buffer. The layout should not have
2638 * changed from the first call and no transition is necessary.
2640 assert(att_ref
->layout
== att_state
->current_layout
);
2644 /* Get the appropriate target layout for this attachment. */
2645 const VkImageLayout target_layout
= subpass_end
?
2646 att_desc
->final_layout
: att_ref
->layout
;
2648 /* The attachment index must be less than the number of attachments
2649 * within the framebuffer.
2651 assert(att_ref
->attachment
< cmd_state
->framebuffer
->attachment_count
);
2653 const struct anv_image_view
* const iview
=
2654 cmd_state
->framebuffer
->attachments
[att_ref
->attachment
];
2655 const struct anv_image
* const image
= iview
->image
;
2657 /* Perform the layout transition. */
2658 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
2659 transition_depth_buffer(cmd_buffer
, image
,
2660 att_state
->current_layout
, target_layout
);
2661 att_state
->aux_usage
=
2662 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
2663 image
->aspects
, target_layout
);
2664 } else if (image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2665 transition_color_buffer(cmd_buffer
, image
,
2666 iview
->isl
.base_level
, 1,
2667 iview
->isl
.base_array_layer
,
2668 iview
->isl
.array_len
,
2669 att_state
->current_layout
, target_layout
);
2672 att_state
->current_layout
= target_layout
;
2676 /* Update the clear value dword(s) in surface state objects or the fast clear
2677 * state buffer entry for the color attachments used in this subpass.
2680 cmd_buffer_subpass_sync_fast_clear_values(struct anv_cmd_buffer
*cmd_buffer
)
2682 assert(cmd_buffer
&& cmd_buffer
->state
.subpass
);
2684 const struct anv_cmd_state
*state
= &cmd_buffer
->state
;
2686 /* Iterate through every color attachment used in this subpass. */
2687 for (uint32_t i
= 0; i
< state
->subpass
->color_count
; ++i
) {
2689 /* The attachment should be one of the attachments described in the
2690 * render pass and used in the subpass.
2692 const uint32_t a
= state
->subpass
->color_attachments
[i
].attachment
;
2693 assert(a
< state
->pass
->attachment_count
);
2694 if (a
== VK_ATTACHMENT_UNUSED
)
2697 /* Store some information regarding this attachment. */
2698 const struct anv_attachment_state
*att_state
= &state
->attachments
[a
];
2699 const struct anv_image_view
*iview
= state
->framebuffer
->attachments
[a
];
2700 const struct anv_render_pass_attachment
*rp_att
=
2701 &state
->pass
->attachments
[a
];
2703 if (att_state
->aux_usage
== ISL_AUX_USAGE_NONE
)
2706 /* The fast clear state entry must be updated if a fast clear is going to
2707 * happen. The surface state must be updated if the clear value from a
2708 * prior fast clear may be needed.
2710 if (att_state
->pending_clear_aspects
&& att_state
->fast_clear
) {
2711 /* Update the fast clear state entry. */
2712 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color_rt_state
,
2713 iview
->image
, iview
->isl
.base_level
,
2714 true /* copy from ss */);
2715 } else if (rp_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
2716 /* The attachment may have been fast-cleared in a previous render
2717 * pass and the value is needed now. Update the surface state(s).
2719 * TODO: Do this only once per render pass instead of every subpass.
2721 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color_rt_state
,
2722 iview
->image
, iview
->isl
.base_level
,
2723 false /* copy to ss */);
2725 if (need_input_attachment_state(rp_att
) &&
2726 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
2727 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input_att_state
,
2728 iview
->image
, iview
->isl
.base_level
,
2729 false /* copy to ss */);
2737 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
2738 struct anv_subpass
*subpass
)
2740 cmd_buffer
->state
.subpass
= subpass
;
2742 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
2744 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2745 * different views. If the client asks for instancing, we need to use the
2746 * Instance Data Step Rate to ensure that we repeat the client's
2747 * per-instance data once for each view. Since this bit is in
2748 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
2752 cmd_buffer
->state
.vb_dirty
|= ~0;
2754 /* Perform transitions to the subpass layout before any writes have
2757 cmd_buffer_subpass_transition_layouts(cmd_buffer
, false);
2759 /* Update clear values *after* performing automatic layout transitions.
2760 * This ensures that transitions from the UNDEFINED layout have had a chance
2761 * to populate the clear value buffer with the correct values for the
2762 * LOAD_OP_LOAD loadOp and that the fast-clears will update the buffer
2763 * without the aforementioned layout transition overwriting the fast-clear
2766 cmd_buffer_subpass_sync_fast_clear_values(cmd_buffer
);
2768 cmd_buffer_emit_depth_stencil(cmd_buffer
);
2770 anv_cmd_buffer_clear_subpass(cmd_buffer
);
2773 void genX(CmdBeginRenderPass
)(
2774 VkCommandBuffer commandBuffer
,
2775 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2776 VkSubpassContents contents
)
2778 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2779 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2780 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2782 cmd_buffer
->state
.framebuffer
= framebuffer
;
2783 cmd_buffer
->state
.pass
= pass
;
2784 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2786 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
2788 /* If we failed to setup the attachments we should not try to go further */
2789 if (result
!= VK_SUCCESS
) {
2790 assert(anv_batch_has_error(&cmd_buffer
->batch
));
2794 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2796 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
2798 cmd_buffer
->state
.pending_pipe_bits
|=
2799 cmd_buffer
->state
.pass
->subpass_flushes
[0];
2802 void genX(CmdNextSubpass
)(
2803 VkCommandBuffer commandBuffer
,
2804 VkSubpassContents contents
)
2806 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2808 if (anv_batch_has_error(&cmd_buffer
->batch
))
2811 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2813 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2815 /* Perform transitions to the final layout after all writes have occurred.
2817 cmd_buffer_subpass_transition_layouts(cmd_buffer
, true);
2819 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
2821 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
2822 cmd_buffer
->state
.pending_pipe_bits
|=
2823 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
2826 void genX(CmdEndRenderPass
)(
2827 VkCommandBuffer commandBuffer
)
2829 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2831 if (anv_batch_has_error(&cmd_buffer
->batch
))
2834 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2836 /* Perform transitions to the final layout after all writes have occurred.
2838 cmd_buffer_subpass_transition_layouts(cmd_buffer
, true);
2840 cmd_buffer
->state
.pending_pipe_bits
|=
2841 cmd_buffer
->state
.pass
->subpass_flushes
[cmd_buffer
->state
.pass
->subpass_count
];
2843 cmd_buffer
->state
.hiz_enabled
= false;
2846 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
2849 /* Remove references to render pass specific state. This enables us to
2850 * detect whether or not we're in a renderpass.
2852 cmd_buffer
->state
.framebuffer
= NULL
;
2853 cmd_buffer
->state
.pass
= NULL
;
2854 cmd_buffer
->state
.subpass
= NULL
;