2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "common/gen_l3_config.h"
31 #include "genxml/gen_macros.h"
32 #include "genxml/genX_pack.h"
35 emit_lrm(struct anv_batch
*batch
,
36 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
54 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
56 struct anv_device
*device
= cmd_buffer
->device
;
58 /* Emit a render target cache flush.
60 * This isn't documented anywhere in the PRM. However, it seems to be
61 * necessary prior to changing the surface state base adress. Without
62 * this, we get GPU hangs when using multi-level command buffers which
63 * clear depth, reset state base address, and then go render stuff.
65 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
66 pc
.DCFlushEnable
= true;
67 pc
.RenderTargetCacheFlushEnable
= true;
68 pc
.CommandStreamerStallEnable
= true;
71 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
72 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
73 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
74 sba
.GeneralStateBaseAddressModifyEnable
= true;
76 sba
.SurfaceStateBaseAddress
=
77 anv_cmd_buffer_surface_base_address(cmd_buffer
);
78 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
79 sba
.SurfaceStateBaseAddressModifyEnable
= true;
81 sba
.DynamicStateBaseAddress
=
82 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
83 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
84 sba
.DynamicStateBaseAddressModifyEnable
= true;
86 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
87 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
88 sba
.IndirectObjectBaseAddressModifyEnable
= true;
90 sba
.InstructionBaseAddress
=
91 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
92 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
93 sba
.InstructionBaseAddressModifyEnable
= true;
96 /* Broadwell requires that we specify a buffer size for a bunch of
97 * these fields. However, since we will be growing the BO's live, we
98 * just set them all to the maximum.
100 sba
.GeneralStateBufferSize
= 0xfffff;
101 sba
.GeneralStateBufferSizeModifyEnable
= true;
102 sba
.DynamicStateBufferSize
= 0xfffff;
103 sba
.DynamicStateBufferSizeModifyEnable
= true;
104 sba
.IndirectObjectBufferSize
= 0xfffff;
105 sba
.IndirectObjectBufferSizeModifyEnable
= true;
106 sba
.InstructionBufferSize
= 0xfffff;
107 sba
.InstructionBuffersizeModifyEnable
= true;
111 /* After re-setting the surface state base address, we have to do some
112 * cache flusing so that the sampler engine will pick up the new
113 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
114 * Shared Function > 3D Sampler > State > State Caching (page 96):
116 * Coherency with system memory in the state cache, like the texture
117 * cache is handled partially by software. It is expected that the
118 * command stream or shader will issue Cache Flush operation or
119 * Cache_Flush sampler message to ensure that the L1 cache remains
120 * coherent with system memory.
124 * Whenever the value of the Dynamic_State_Base_Addr,
125 * Surface_State_Base_Addr are altered, the L1 state cache must be
126 * invalidated to ensure the new surface or sampler state is fetched
127 * from system memory.
129 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
130 * which, according the PIPE_CONTROL instruction documentation in the
133 * Setting this bit is independent of any other bit in this packet.
134 * This bit controls the invalidation of the L1 and L2 state caches
135 * at the top of the pipe i.e. at the parsing time.
137 * Unfortunately, experimentation seems to indicate that state cache
138 * invalidation through a PIPE_CONTROL does nothing whatsoever in
139 * regards to surface state and binding tables. In stead, it seems that
140 * invalidating the texture cache is what is actually needed.
142 * XXX: As far as we have been able to determine through
143 * experimentation, shows that flush the texture cache appears to be
144 * sufficient. The theory here is that all of the sampling/rendering
145 * units cache the binding table in the texture cache. However, we have
146 * yet to be able to actually confirm this.
148 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
149 pc
.TextureCacheInvalidationEnable
= true;
150 pc
.ConstantCacheInvalidationEnable
= true;
151 pc
.StateCacheInvalidationEnable
= true;
156 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
157 struct anv_state state
,
158 struct anv_bo
*bo
, uint32_t offset
)
160 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
162 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
163 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
167 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
168 const struct anv_image_view
*iview
,
169 enum isl_aux_usage aux_usage
,
170 struct anv_state state
)
172 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
174 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
175 state
.offset
+ isl_dev
->ss
.addr_offset
,
176 iview
->bo
, iview
->offset
);
178 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
179 uint32_t aux_offset
= iview
->offset
+ iview
->image
->aux_surface
.offset
;
181 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
182 * used to store other information. This should be ok, however, because
183 * surface buffer addresses are always 4K page alinged.
185 assert((aux_offset
& 0xfff) == 0);
186 uint32_t *aux_addr_dw
= state
.map
+ isl_dev
->ss
.aux_addr_offset
;
187 aux_offset
+= *aux_addr_dw
& 0xfff;
189 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
190 state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
191 iview
->bo
, aux_offset
);
196 color_is_zero_one(VkClearColorValue value
, enum isl_format format
)
198 if (isl_format_has_int_channel(format
)) {
199 for (unsigned i
= 0; i
< 4; i
++) {
200 if (value
.int32
[i
] != 0 && value
.int32
[i
] != 1)
204 for (unsigned i
= 0; i
< 4; i
++) {
205 if (value
.float32
[i
] != 0.0f
&& value
.float32
[i
] != 1.0f
)
214 color_attachment_compute_aux_usage(struct anv_device
*device
,
215 struct anv_attachment_state
*att_state
,
216 struct anv_image_view
*iview
,
217 VkRect2D render_area
,
218 union isl_color_value
*fast_clear_color
)
220 if (iview
->image
->aux_surface
.isl
.size
== 0) {
221 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
222 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
223 att_state
->fast_clear
= false;
227 assert(iview
->image
->aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
229 att_state
->clear_color_is_zero_one
=
230 color_is_zero_one(att_state
->clear_value
.color
, iview
->isl
.format
);
232 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
233 /* Start off assuming fast clears are possible */
234 att_state
->fast_clear
= true;
236 /* Potentially, we could do partial fast-clears but doing so has crazy
237 * alignment restrictions. It's easier to just restrict to full size
238 * fast clears for now.
240 if (render_area
.offset
.x
!= 0 ||
241 render_area
.offset
.y
!= 0 ||
242 render_area
.extent
.width
!= iview
->extent
.width
||
243 render_area
.extent
.height
!= iview
->extent
.height
)
244 att_state
->fast_clear
= false;
247 /* On gen7, we can't do multi-LOD or multi-layer fast-clears. We
248 * technically can, but it comes with crazy restrictions that we
249 * don't want to deal with now.
251 if (iview
->isl
.base_level
> 0 ||
252 iview
->isl
.base_array_layer
> 0 ||
253 iview
->isl
.array_len
> 1)
254 att_state
->fast_clear
= false;
257 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
258 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
259 att_state
->fast_clear
= false;
261 if (att_state
->fast_clear
) {
262 memcpy(fast_clear_color
->u32
, att_state
->clear_value
.color
.uint32
,
263 sizeof(fast_clear_color
->u32
));
266 att_state
->fast_clear
= false;
270 * TODO: Consider using a heuristic to determine if temporarily enabling
271 * CCS_E for this image view would be beneficial.
273 * While fast-clear resolves and partial resolves are fairly cheap in the
274 * case where you render to most of the pixels, full resolves are not
275 * because they potentially involve reading and writing the entire
276 * framebuffer. If we can't texture with CCS_E, we should leave it off and
277 * limit ourselves to fast clears.
279 if (iview
->image
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
280 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
281 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_E
;
282 } else if (att_state
->fast_clear
) {
283 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
285 !isl_format_supports_ccs_e(&device
->info
, iview
->isl
.format
)) {
286 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
288 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
289 * setting is only allowed if Surface Format supported for Fast
290 * Clear. In addition, if the surface is bound to the sampling
291 * engine, Surface Format must be supported for Render Target
292 * Compression for surfaces bound to the sampling engine."
294 * In other words, we can't sample from a fast-cleared image if it
295 * doesn't also support color compression.
297 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
298 } else if (GEN_GEN
== 8) {
299 /* Broadwell can sample from fast-cleared images */
300 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
302 /* Ivy Bridge and Haswell cannot */
303 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
306 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
307 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
312 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
314 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
317 /* We only allocate input attachment states for color surfaces. Compression
318 * is not yet enabled for depth textures and stencil doesn't allow
319 * compression so we can just use the texture surface state from the view.
321 return vk_format_is_color(att
->format
);
324 static enum isl_aux_usage
325 layout_to_hiz_usage(VkImageLayout layout
, uint8_t samples
)
328 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
329 return ISL_AUX_USAGE_HIZ
;
330 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
331 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
332 if (anv_can_sample_with_hiz(GEN_GEN
, samples
))
333 return ISL_AUX_USAGE_HIZ
;
335 case VK_IMAGE_LAYOUT_GENERAL
:
336 /* This buffer could be used as a source or destination in a transfer
337 * operation. Transfer operations current don't perform HiZ-enabled reads
341 return ISL_AUX_USAGE_NONE
;
345 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
346 * the initial layout is undefined, the HiZ buffer and depth buffer will
347 * represent the same data at the end of this operation.
350 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
351 const struct anv_image
*image
,
352 VkImageLayout initial_layout
,
353 VkImageLayout final_layout
)
357 if (image
->aux_usage
!= ISL_AUX_USAGE_HIZ
|| final_layout
== initial_layout
)
360 const bool hiz_enabled
= layout_to_hiz_usage(initial_layout
, image
->samples
) ==
362 const bool enable_hiz
= layout_to_hiz_usage(final_layout
, image
->samples
) ==
365 enum blorp_hiz_op hiz_op
;
366 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
367 /* We've already initialized the aux HiZ buffer at BindImageMemory time,
368 * so there's no need to perform a HIZ resolve or clear to avoid GPU hangs.
369 * This initial layout indicates that the user doesn't care about the data
370 * that's currently in the buffer, so resolves are not necessary except
371 * for the special case noted below.
373 hiz_op
= BLORP_HIZ_OP_NONE
;
374 } else if (hiz_enabled
&& !enable_hiz
) {
375 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
376 } else if (!hiz_enabled
&& enable_hiz
) {
377 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
379 assert(hiz_enabled
== enable_hiz
);
380 /* If the same buffer will be used, no resolves are necessary except for
381 * the special case noted below.
383 hiz_op
= BLORP_HIZ_OP_NONE
;
386 if (hiz_op
!= BLORP_HIZ_OP_NONE
)
387 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, hiz_op
);
389 /* Images that have sampling with HiZ enabled cause all shader sampling to
390 * load data with the HiZ buffer. Therefore, in the case of transitioning to
391 * the general layout - which currently routes all writes to the depth
392 * buffer - we must ensure that the HiZ buffer remains consistent with the
393 * depth buffer by performing an additional HIZ resolve if the operation
394 * required by this transition was not already a HiZ resolve.
396 if (final_layout
== VK_IMAGE_LAYOUT_GENERAL
&&
397 anv_can_sample_with_hiz(GEN_GEN
, image
->samples
) &&
398 hiz_op
!= BLORP_HIZ_OP_HIZ_RESOLVE
) {
399 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, BLORP_HIZ_OP_HIZ_RESOLVE
);
405 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
408 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
409 struct anv_render_pass
*pass
,
410 const VkRenderPassBeginInfo
*begin
)
412 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
413 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
415 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
417 if (pass
->attachment_count
== 0) {
418 state
->attachments
= NULL
;
422 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
423 pass
->attachment_count
*
424 sizeof(state
->attachments
[0]),
425 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
426 if (state
->attachments
== NULL
) {
427 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
431 bool need_null_state
= false;
432 unsigned num_states
= 0;
433 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
434 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
437 /* We need a null state for any depth-stencil-only subpasses.
438 * Importantly, this includes depth/stencil clears so we create one
439 * whenever we have depth or stencil
441 need_null_state
= true;
444 if (need_input_attachment_state(&pass
->attachments
[i
]))
447 num_states
+= need_null_state
;
449 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
450 state
->render_pass_states
=
451 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
452 num_states
* ss_stride
, isl_dev
->ss
.align
);
454 struct anv_state next_state
= state
->render_pass_states
;
455 next_state
.alloc_size
= isl_dev
->ss
.size
;
457 if (need_null_state
) {
458 state
->null_surface_state
= next_state
;
459 next_state
.offset
+= ss_stride
;
460 next_state
.map
+= ss_stride
;
463 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
464 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
465 state
->attachments
[i
].color_rt_state
= next_state
;
466 next_state
.offset
+= ss_stride
;
467 next_state
.map
+= ss_stride
;
470 if (need_input_attachment_state(&pass
->attachments
[i
])) {
471 state
->attachments
[i
].input_att_state
= next_state
;
472 next_state
.offset
+= ss_stride
;
473 next_state
.map
+= ss_stride
;
476 assert(next_state
.offset
== state
->render_pass_states
.offset
+
477 state
->render_pass_states
.alloc_size
);
480 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
481 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
483 if (need_null_state
) {
484 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
485 .SurfaceType
= SURFTYPE_NULL
,
486 .SurfaceArray
= framebuffer
->layers
> 0,
487 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
491 .TiledSurface
= true,
493 .Width
= framebuffer
->width
- 1,
494 .Height
= framebuffer
->height
- 1,
495 .Depth
= framebuffer
->layers
- 1,
496 .RenderTargetViewExtent
= framebuffer
->layers
- 1,
498 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
->null_surface_state
.map
,
502 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
503 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
504 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
505 VkImageAspectFlags clear_aspects
= 0;
507 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
508 /* color attachment */
509 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
510 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
513 /* depthstencil attachment */
514 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
515 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
516 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
518 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
519 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
520 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
524 state
->attachments
[i
].current_layout
= att
->initial_layout
;
525 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
527 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
529 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
530 assert(iview
->vk_format
== att
->format
);
532 union isl_color_value clear_color
= { .u32
= { 0, } };
533 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
534 color_attachment_compute_aux_usage(cmd_buffer
->device
,
535 &state
->attachments
[i
],
536 iview
, begin
->renderArea
,
539 struct isl_view view
= iview
->isl
;
540 view
.usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
541 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
542 isl_surf_fill_state(isl_dev
,
543 state
->attachments
[i
].color_rt_state
.map
,
544 .surf
= &iview
->image
->color_surface
.isl
,
546 .aux_surf
= &iview
->image
->aux_surface
.isl
,
547 .aux_usage
= state
->attachments
[i
].aux_usage
,
548 .clear_color
= clear_color
,
549 .mocs
= cmd_buffer
->device
->default_mocs
);
551 add_image_view_relocs(cmd_buffer
, iview
,
552 state
->attachments
[i
].aux_usage
,
553 state
->attachments
[i
].color_rt_state
);
555 if (iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
556 state
->attachments
[i
].aux_usage
=
557 layout_to_hiz_usage(att
->initial_layout
, iview
->image
->samples
);
559 state
->attachments
[i
].aux_usage
= ISL_AUX_USAGE_NONE
;
561 state
->attachments
[i
].input_aux_usage
= ISL_AUX_USAGE_NONE
;
564 if (need_input_attachment_state(&pass
->attachments
[i
])) {
565 struct isl_view view
= iview
->isl
;
566 view
.usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
567 isl_surf_fill_state(isl_dev
,
568 state
->attachments
[i
].input_att_state
.map
,
569 .surf
= &iview
->image
->color_surface
.isl
,
571 .aux_surf
= &iview
->image
->aux_surface
.isl
,
572 .aux_usage
= state
->attachments
[i
].input_aux_usage
,
573 .clear_color
= clear_color
,
574 .mocs
= cmd_buffer
->device
->default_mocs
);
576 add_image_view_relocs(cmd_buffer
, iview
,
577 state
->attachments
[i
].input_aux_usage
,
578 state
->attachments
[i
].input_att_state
);
582 if (!cmd_buffer
->device
->info
.has_llc
)
583 anv_state_clflush(state
->render_pass_states
);
588 genX(BeginCommandBuffer
)(
589 VkCommandBuffer commandBuffer
,
590 const VkCommandBufferBeginInfo
* pBeginInfo
)
592 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
594 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
595 * command buffer's state. Otherwise, we must *reset* its state. In both
598 * From the Vulkan 1.0 spec:
600 * If a command buffer is in the executable state and the command buffer
601 * was allocated from a command pool with the
602 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
603 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
604 * as if vkResetCommandBuffer had been called with
605 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
606 * the command buffer in the recording state.
608 anv_cmd_buffer_reset(cmd_buffer
);
610 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
612 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
613 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
615 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
617 if (cmd_buffer
->usage_flags
&
618 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
619 cmd_buffer
->state
.pass
=
620 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
621 cmd_buffer
->state
.subpass
=
622 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
623 cmd_buffer
->state
.framebuffer
= NULL
;
625 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, cmd_buffer
->state
.pass
,
628 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
635 genX(EndCommandBuffer
)(
636 VkCommandBuffer commandBuffer
)
638 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
640 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
642 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
648 genX(CmdExecuteCommands
)(
649 VkCommandBuffer commandBuffer
,
650 uint32_t commandBufferCount
,
651 const VkCommandBuffer
* pCmdBuffers
)
653 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
655 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
657 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
658 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
660 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
662 if (secondary
->usage_flags
&
663 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
664 /* If we're continuing a render pass from the primary, we need to
665 * copy the surface states for the current subpass into the storage
666 * we allocated for them in BeginCommandBuffer.
668 struct anv_bo
*ss_bo
= &primary
->device
->surface_state_block_pool
.bo
;
669 struct anv_state src_state
= primary
->state
.render_pass_states
;
670 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
671 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
673 genX(cmd_buffer_gpu_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
674 ss_bo
, src_state
.offset
,
675 src_state
.alloc_size
);
678 anv_cmd_buffer_add_secondary(primary
, secondary
);
681 /* Each of the secondary command buffers will use its own state base
682 * address. We need to re-emit state base address for the primary after
683 * all of the secondaries are done.
685 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
688 genX(cmd_buffer_emit_state_base_address
)(primary
);
691 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
692 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
693 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
696 * Program the hardware to use the specified L3 configuration.
699 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
700 const struct gen_l3_config
*cfg
)
703 if (cfg
== cmd_buffer
->state
.current_l3_config
)
706 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
707 fprintf(stderr
, "L3 config transition: ");
708 gen_dump_l3_config(cfg
, stderr
);
711 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
713 /* According to the hardware docs, the L3 partitioning can only be changed
714 * while the pipeline is completely drained and the caches are flushed,
715 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
717 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
718 pc
.DCFlushEnable
= true;
719 pc
.PostSyncOperation
= NoWrite
;
720 pc
.CommandStreamerStallEnable
= true;
723 /* ...followed by a second pipelined PIPE_CONTROL that initiates
724 * invalidation of the relevant caches. Note that because RO invalidation
725 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
726 * command is processed by the CS) we cannot combine it with the previous
727 * stalling flush as the hardware documentation suggests, because that
728 * would cause the CS to stall on previous rendering *after* RO
729 * invalidation and wouldn't prevent the RO caches from being polluted by
730 * concurrent rendering before the stall completes. This intentionally
731 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
732 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
733 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
734 * already guarantee that there is no concurrent GPGPU kernel execution
735 * (see SKL HSD 2132585).
737 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
738 pc
.TextureCacheInvalidationEnable
= true;
739 pc
.ConstantCacheInvalidationEnable
= true;
740 pc
.InstructionCacheInvalidateEnable
= true;
741 pc
.StateCacheInvalidationEnable
= true;
742 pc
.PostSyncOperation
= NoWrite
;
745 /* Now send a third stalling flush to make sure that invalidation is
746 * complete when the L3 configuration registers are modified.
748 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
749 pc
.DCFlushEnable
= true;
750 pc
.PostSyncOperation
= NoWrite
;
751 pc
.CommandStreamerStallEnable
= true;
756 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
759 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
760 .SLMEnable
= has_slm
,
761 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
762 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
763 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
764 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
766 /* Set up the L3 partitioning. */
767 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
771 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
772 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
774 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
776 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
779 assert(!cfg
->n
[GEN_L3P_ALL
]);
781 /* When enabled SLM only uses a portion of the L3 on half of the banks,
782 * the matching space on the remaining banks has to be allocated to a
783 * client (URB for all validated configurations) set to the
784 * lower-bandwidth 2-bank address hashing mode.
786 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
787 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
788 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
790 /* Minimum number of ways that can be allocated to the URB. */
791 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
792 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
794 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
795 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
796 .ConvertDC_UC
= !has_dc
,
797 .ConvertIS_UC
= !has_is
,
798 .ConvertC_UC
= !has_c
,
799 .ConvertT_UC
= !has_t
);
801 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
802 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
803 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
805 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
806 .SLMEnable
= has_slm
,
807 .URBLowBandwidth
= urb_low_bw
,
808 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
810 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
812 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
813 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
815 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
816 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
818 .CAllocation
= cfg
->n
[GEN_L3P_C
],
820 .TAllocation
= cfg
->n
[GEN_L3P_T
],
823 /* Set up the L3 partitioning. */
824 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
825 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
826 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
829 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
830 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
831 * them disabled to avoid crashing the system hard.
833 uint32_t scratch1
, chicken3
;
834 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
835 .L3AtomicDisable
= !has_dc
);
836 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
837 .L3AtomicDisableMask
= true,
838 .L3AtomicDisable
= !has_dc
);
839 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
840 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
846 cmd_buffer
->state
.current_l3_config
= cfg
;
850 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
852 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
854 /* Flushes are pipelined while invalidations are handled immediately.
855 * Therefore, if we're flushing anything then we need to schedule a stall
856 * before any invalidations can happen.
858 if (bits
& ANV_PIPE_FLUSH_BITS
)
859 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
861 /* If we're going to do an invalidate and we have a pending CS stall that
862 * has yet to be resolved, we do the CS stall now.
864 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
865 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
866 bits
|= ANV_PIPE_CS_STALL_BIT
;
867 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
870 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
871 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
872 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
873 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
874 pipe
.RenderTargetCacheFlushEnable
=
875 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
877 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
878 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
879 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
882 * According to the Broadwell documentation, any PIPE_CONTROL with the
883 * "Command Streamer Stall" bit set must also have another bit set,
884 * with five different options:
886 * - Render Target Cache Flush
887 * - Depth Cache Flush
888 * - Stall at Pixel Scoreboard
889 * - Post-Sync Operation
893 * I chose "Stall at Pixel Scoreboard" since that's what we use in
894 * mesa and it seems to work fine. The choice is fairly arbitrary.
896 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
897 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
898 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
899 pipe
.StallAtPixelScoreboard
= true;
902 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
905 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
906 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
907 pipe
.StateCacheInvalidationEnable
=
908 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
909 pipe
.ConstantCacheInvalidationEnable
=
910 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
911 pipe
.VFCacheInvalidationEnable
=
912 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
913 pipe
.TextureCacheInvalidationEnable
=
914 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
915 pipe
.InstructionCacheInvalidateEnable
=
916 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
919 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
922 cmd_buffer
->state
.pending_pipe_bits
= bits
;
925 void genX(CmdPipelineBarrier
)(
926 VkCommandBuffer commandBuffer
,
927 VkPipelineStageFlags srcStageMask
,
928 VkPipelineStageFlags destStageMask
,
930 uint32_t memoryBarrierCount
,
931 const VkMemoryBarrier
* pMemoryBarriers
,
932 uint32_t bufferMemoryBarrierCount
,
933 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
934 uint32_t imageMemoryBarrierCount
,
935 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
937 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
940 /* XXX: Right now, we're really dumb and just flush whatever categories
941 * the app asks for. One of these days we may make this a bit better
942 * but right now that's all the hardware allows for in most areas.
944 VkAccessFlags src_flags
= 0;
945 VkAccessFlags dst_flags
= 0;
947 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
948 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
949 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
952 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
953 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
954 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
957 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
958 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
959 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
960 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
961 if (pImageMemoryBarriers
[i
].subresourceRange
.aspectMask
&
962 VK_IMAGE_ASPECT_DEPTH_BIT
) {
963 transition_depth_buffer(cmd_buffer
, image
,
964 pImageMemoryBarriers
[i
].oldLayout
,
965 pImageMemoryBarriers
[i
].newLayout
);
969 enum anv_pipe_bits pipe_bits
= 0;
971 for_each_bit(b
, src_flags
) {
972 switch ((VkAccessFlagBits
)(1 << b
)) {
973 case VK_ACCESS_SHADER_WRITE_BIT
:
974 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
976 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
977 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
979 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
980 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
982 case VK_ACCESS_TRANSFER_WRITE_BIT
:
983 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
984 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
987 break; /* Nothing to do */
991 for_each_bit(b
, dst_flags
) {
992 switch ((VkAccessFlagBits
)(1 << b
)) {
993 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
994 case VK_ACCESS_INDEX_READ_BIT
:
995 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
996 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
998 case VK_ACCESS_UNIFORM_READ_BIT
:
999 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1000 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1002 case VK_ACCESS_SHADER_READ_BIT
:
1003 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1004 case VK_ACCESS_TRANSFER_READ_BIT
:
1005 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1008 break; /* Nothing to do */
1012 cmd_buffer
->state
.pending_pipe_bits
|= pipe_bits
;
1016 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1018 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
1020 /* In order to avoid thrash, we assume that vertex and fragment stages
1021 * always exist. In the rare case where one is missing *and* the other
1022 * uses push concstants, this may be suboptimal. However, avoiding stalls
1023 * seems more important.
1025 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1027 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1031 const unsigned push_constant_kb
= 32;
1032 #elif GEN_IS_HASWELL
1033 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1035 const unsigned push_constant_kb
= 16;
1038 const unsigned num_stages
=
1039 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1040 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1042 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1043 * units of 2KB. Incidentally, these are the same platforms that have
1044 * 32KB worth of push constant space.
1046 if (push_constant_kb
== 32)
1047 size_per_stage
&= ~1u;
1049 uint32_t kb_used
= 0;
1050 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1051 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1052 anv_batch_emit(&cmd_buffer
->batch
,
1053 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1054 alloc
._3DCommandSubOpcode
= 18 + i
;
1055 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1056 alloc
.ConstantBufferSize
= push_size
;
1058 kb_used
+= push_size
;
1061 anv_batch_emit(&cmd_buffer
->batch
,
1062 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1063 alloc
.ConstantBufferOffset
= kb_used
;
1064 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1067 cmd_buffer
->state
.push_constant_stages
= stages
;
1069 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1071 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1072 * the next 3DPRIMITIVE command after programming the
1073 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1075 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1076 * pipeline setup, we need to dirty push constants.
1078 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1082 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1083 gl_shader_stage stage
,
1084 struct anv_state
*bt_state
)
1086 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1087 struct anv_pipeline
*pipeline
;
1088 uint32_t bias
, state_offset
;
1091 case MESA_SHADER_COMPUTE
:
1092 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1096 pipeline
= cmd_buffer
->state
.pipeline
;
1101 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1102 *bt_state
= (struct anv_state
) { 0, };
1106 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1107 if (bias
+ map
->surface_count
== 0) {
1108 *bt_state
= (struct anv_state
) { 0, };
1112 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1113 bias
+ map
->surface_count
,
1115 uint32_t *bt_map
= bt_state
->map
;
1117 if (bt_state
->map
== NULL
)
1118 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1120 if (stage
== MESA_SHADER_COMPUTE
&&
1121 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
1122 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
1123 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
1125 struct anv_state surface_state
;
1127 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1129 const enum isl_format format
=
1130 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1131 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1132 format
, bo_offset
, 12, 1);
1134 bt_map
[0] = surface_state
.offset
+ state_offset
;
1135 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1138 if (map
->surface_count
== 0)
1141 if (map
->image_count
> 0) {
1143 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1144 if (result
!= VK_SUCCESS
)
1147 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1151 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1152 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1154 struct anv_state surface_state
;
1156 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1157 /* Color attachment binding */
1158 assert(stage
== MESA_SHADER_FRAGMENT
);
1159 assert(binding
->binding
== 0);
1160 if (binding
->index
< subpass
->color_count
) {
1161 const unsigned att
= subpass
->color_attachments
[binding
->index
];
1162 surface_state
= cmd_buffer
->state
.attachments
[att
].color_rt_state
;
1164 surface_state
= cmd_buffer
->state
.null_surface_state
;
1167 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1171 struct anv_descriptor_set
*set
=
1172 cmd_buffer
->state
.descriptors
[binding
->set
];
1173 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1174 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1176 switch (desc
->type
) {
1177 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1178 /* Nothing for us to do here */
1181 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1182 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
1183 surface_state
= desc
->image_view
->sampler_surface_state
;
1184 assert(surface_state
.alloc_size
);
1185 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1186 desc
->image_view
->image
->aux_usage
,
1190 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1191 assert(stage
== MESA_SHADER_FRAGMENT
);
1192 if (desc
->image_view
->aspect_mask
!= VK_IMAGE_ASPECT_COLOR_BIT
) {
1193 /* For depth and stencil input attachments, we treat it like any
1194 * old texture that a user may have bound.
1196 surface_state
= desc
->image_view
->sampler_surface_state
;
1197 assert(surface_state
.alloc_size
);
1198 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1199 desc
->image_view
->image
->aux_usage
,
1202 /* For color input attachments, we create the surface state at
1203 * vkBeginRenderPass time so that we can include aux and clear
1204 * color information.
1206 assert(binding
->input_attachment_index
< subpass
->input_count
);
1207 const unsigned subpass_att
= binding
->input_attachment_index
;
1208 const unsigned att
= subpass
->input_attachments
[subpass_att
];
1209 surface_state
= cmd_buffer
->state
.attachments
[att
].input_att_state
;
1213 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1214 surface_state
= (binding
->write_only
)
1215 ? desc
->image_view
->writeonly_storage_surface_state
1216 : desc
->image_view
->storage_surface_state
;
1217 assert(surface_state
.alloc_size
);
1218 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1219 desc
->image_view
->image
->aux_usage
,
1222 struct brw_image_param
*image_param
=
1223 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1225 *image_param
= desc
->image_view
->storage_image_param
;
1226 image_param
->surface_idx
= bias
+ s
;
1230 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
1231 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
1232 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
1233 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
1234 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
1235 surface_state
= desc
->buffer_view
->surface_state
;
1236 assert(surface_state
.alloc_size
);
1237 add_surface_state_reloc(cmd_buffer
, surface_state
,
1238 desc
->buffer_view
->bo
,
1239 desc
->buffer_view
->offset
);
1242 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
1243 surface_state
= (binding
->write_only
)
1244 ? desc
->buffer_view
->writeonly_storage_surface_state
1245 : desc
->buffer_view
->storage_surface_state
;
1246 assert(surface_state
.alloc_size
);
1247 add_surface_state_reloc(cmd_buffer
, surface_state
,
1248 desc
->buffer_view
->bo
,
1249 desc
->buffer_view
->offset
);
1251 struct brw_image_param
*image_param
=
1252 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1254 *image_param
= desc
->buffer_view
->storage_image_param
;
1255 image_param
->surface_idx
= bias
+ s
;
1259 assert(!"Invalid descriptor type");
1263 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1265 assert(image
== map
->image_count
);
1268 if (!cmd_buffer
->device
->info
.has_llc
)
1269 anv_state_clflush(*bt_state
);
1275 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1276 gl_shader_stage stage
,
1277 struct anv_state
*state
)
1279 struct anv_pipeline
*pipeline
;
1281 if (stage
== MESA_SHADER_COMPUTE
)
1282 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1284 pipeline
= cmd_buffer
->state
.pipeline
;
1286 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1287 *state
= (struct anv_state
) { 0, };
1291 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1292 if (map
->sampler_count
== 0) {
1293 *state
= (struct anv_state
) { 0, };
1297 uint32_t size
= map
->sampler_count
* 16;
1298 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1300 if (state
->map
== NULL
)
1301 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1303 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1304 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1305 struct anv_descriptor_set
*set
=
1306 cmd_buffer
->state
.descriptors
[binding
->set
];
1307 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1308 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1310 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1311 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1314 struct anv_sampler
*sampler
= desc
->sampler
;
1316 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1317 * happens to be zero.
1319 if (sampler
== NULL
)
1322 memcpy(state
->map
+ (s
* 16),
1323 sampler
->state
, sizeof(sampler
->state
));
1326 if (!cmd_buffer
->device
->info
.has_llc
)
1327 anv_state_clflush(*state
);
1333 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1335 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1336 cmd_buffer
->state
.pipeline
->active_stages
;
1338 VkResult result
= VK_SUCCESS
;
1339 anv_foreach_stage(s
, dirty
) {
1340 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1341 if (result
!= VK_SUCCESS
)
1343 result
= emit_binding_table(cmd_buffer
, s
,
1344 &cmd_buffer
->state
.binding_tables
[s
]);
1345 if (result
!= VK_SUCCESS
)
1349 if (result
!= VK_SUCCESS
) {
1350 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1352 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1353 assert(result
== VK_SUCCESS
);
1355 /* Re-emit state base addresses so we get the new surface state base
1356 * address before we start emitting binding tables etc.
1358 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1360 /* Re-emit all active binding tables */
1361 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
1362 anv_foreach_stage(s
, dirty
) {
1363 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1364 if (result
!= VK_SUCCESS
)
1366 result
= emit_binding_table(cmd_buffer
, s
,
1367 &cmd_buffer
->state
.binding_tables
[s
]);
1368 if (result
!= VK_SUCCESS
)
1373 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1379 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1382 static const uint32_t sampler_state_opcodes
[] = {
1383 [MESA_SHADER_VERTEX
] = 43,
1384 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1385 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1386 [MESA_SHADER_GEOMETRY
] = 46,
1387 [MESA_SHADER_FRAGMENT
] = 47,
1388 [MESA_SHADER_COMPUTE
] = 0,
1391 static const uint32_t binding_table_opcodes
[] = {
1392 [MESA_SHADER_VERTEX
] = 38,
1393 [MESA_SHADER_TESS_CTRL
] = 39,
1394 [MESA_SHADER_TESS_EVAL
] = 40,
1395 [MESA_SHADER_GEOMETRY
] = 41,
1396 [MESA_SHADER_FRAGMENT
] = 42,
1397 [MESA_SHADER_COMPUTE
] = 0,
1400 anv_foreach_stage(s
, stages
) {
1401 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1402 anv_batch_emit(&cmd_buffer
->batch
,
1403 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1404 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1405 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1409 /* Always emit binding table pointers if we're asked to, since on SKL
1410 * this is what flushes push constants. */
1411 anv_batch_emit(&cmd_buffer
->batch
,
1412 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1413 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1414 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1420 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1422 static const uint32_t push_constant_opcodes
[] = {
1423 [MESA_SHADER_VERTEX
] = 21,
1424 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1425 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1426 [MESA_SHADER_GEOMETRY
] = 22,
1427 [MESA_SHADER_FRAGMENT
] = 23,
1428 [MESA_SHADER_COMPUTE
] = 0,
1431 VkShaderStageFlags flushed
= 0;
1433 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
1434 if (stage
== MESA_SHADER_COMPUTE
)
1437 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1439 if (state
.offset
== 0) {
1440 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1441 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1443 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1444 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1445 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1447 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
1448 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1450 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
1451 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1457 flushed
|= mesa_to_vk_shader_stage(stage
);
1460 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1466 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1468 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1471 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1473 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1475 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1477 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1480 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1481 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1483 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1484 GENX(3DSTATE_VERTEX_BUFFERS
));
1486 for_each_bit(vb
, vb_emit
) {
1487 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1488 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1490 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1491 .VertexBufferIndex
= vb
,
1494 .MemoryObjectControlState
= GENX(MOCS
),
1496 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1497 .InstanceDataStepRate
= 1,
1498 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1501 .AddressModifyEnable
= true,
1502 .BufferPitch
= pipeline
->binding_stride
[vb
],
1503 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1506 .BufferSize
= buffer
->size
- offset
1508 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1512 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1517 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1519 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1520 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1522 /* The exact descriptor layout is pulled from the pipeline, so we need
1523 * to re-emit binding tables on every pipeline change.
1525 cmd_buffer
->state
.descriptors_dirty
|=
1526 cmd_buffer
->state
.pipeline
->active_stages
;
1528 /* If the pipeline changed, we may need to re-allocate push constant
1531 cmd_buffer_alloc_push_constants(cmd_buffer
);
1535 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1536 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1537 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1539 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1540 * stall needs to be sent just prior to any 3DSTATE_VS,
1541 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1542 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1543 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1544 * PIPE_CONTROL needs to be sent before any combination of VS
1545 * associated 3DSTATE."
1547 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1548 pc
.DepthStallEnable
= true;
1549 pc
.PostSyncOperation
= WriteImmediateData
;
1551 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1556 /* Render targets live in the same binding table as fragment descriptors */
1557 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1558 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1560 /* We emit the binding tables and sampler tables first, then emit push
1561 * constants and then finally emit binding table and sampler table
1562 * pointers. It has to happen in this order, since emitting the binding
1563 * tables may change the push constants (in case of storage images). After
1564 * emitting push constants, on SKL+ we have to emit the corresponding
1565 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1568 if (cmd_buffer
->state
.descriptors_dirty
)
1569 dirty
= flush_descriptor_sets(cmd_buffer
);
1571 if (cmd_buffer
->state
.push_constants_dirty
) {
1573 /* On Sky Lake and later, the binding table pointers commands are
1574 * what actually flush the changes to push constant state so we need
1575 * to dirty them so they get re-emitted below.
1577 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1579 cmd_buffer_flush_push_constants(cmd_buffer
);
1584 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1586 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1587 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1589 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1590 ANV_CMD_DIRTY_PIPELINE
)) {
1591 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1592 pipeline
->depth_clamp_enable
);
1595 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1596 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1598 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1600 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1604 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
1605 struct anv_bo
*bo
, uint32_t offset
,
1606 uint32_t size
, uint32_t index
)
1608 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1609 GENX(3DSTATE_VERTEX_BUFFERS
));
1611 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1612 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1613 .VertexBufferIndex
= index
,
1614 .AddressModifyEnable
= true,
1617 .MemoryObjectControlState
= GENX(MOCS
),
1618 .BufferStartingAddress
= { bo
, offset
},
1621 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1622 .BufferStartingAddress
= { bo
, offset
},
1623 .EndAddress
= { bo
, offset
+ size
},
1629 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1630 struct anv_bo
*bo
, uint32_t offset
)
1632 emit_vertex_bo(cmd_buffer
, bo
, offset
, 8, ANV_SVGS_VB_INDEX
);
1636 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1637 uint32_t base_vertex
, uint32_t base_instance
)
1639 struct anv_state id_state
=
1640 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1642 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1643 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1645 if (!cmd_buffer
->device
->info
.has_llc
)
1646 anv_state_clflush(id_state
);
1648 emit_base_vertex_instance_bo(cmd_buffer
,
1649 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
1653 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
1655 struct anv_state state
=
1656 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
1658 ((uint32_t *)state
.map
)[0] = draw_index
;
1660 if (!cmd_buffer
->device
->info
.has_llc
)
1661 anv_state_clflush(state
);
1663 emit_vertex_bo(cmd_buffer
,
1664 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
1665 state
.offset
, 4, ANV_DRAWID_VB_INDEX
);
1669 VkCommandBuffer commandBuffer
,
1670 uint32_t vertexCount
,
1671 uint32_t instanceCount
,
1672 uint32_t firstVertex
,
1673 uint32_t firstInstance
)
1675 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1676 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1677 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1679 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1681 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1682 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1683 if (vs_prog_data
->uses_drawid
)
1684 emit_draw_index(cmd_buffer
, 0);
1686 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1687 prim
.VertexAccessType
= SEQUENTIAL
;
1688 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1689 prim
.VertexCountPerInstance
= vertexCount
;
1690 prim
.StartVertexLocation
= firstVertex
;
1691 prim
.InstanceCount
= instanceCount
;
1692 prim
.StartInstanceLocation
= firstInstance
;
1693 prim
.BaseVertexLocation
= 0;
1697 void genX(CmdDrawIndexed
)(
1698 VkCommandBuffer commandBuffer
,
1699 uint32_t indexCount
,
1700 uint32_t instanceCount
,
1701 uint32_t firstIndex
,
1702 int32_t vertexOffset
,
1703 uint32_t firstInstance
)
1705 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1706 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1707 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1709 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1711 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1712 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1713 if (vs_prog_data
->uses_drawid
)
1714 emit_draw_index(cmd_buffer
, 0);
1716 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1717 prim
.VertexAccessType
= RANDOM
;
1718 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1719 prim
.VertexCountPerInstance
= indexCount
;
1720 prim
.StartVertexLocation
= firstIndex
;
1721 prim
.InstanceCount
= instanceCount
;
1722 prim
.StartInstanceLocation
= firstInstance
;
1723 prim
.BaseVertexLocation
= vertexOffset
;
1727 /* Auto-Draw / Indirect Registers */
1728 #define GEN7_3DPRIM_END_OFFSET 0x2420
1729 #define GEN7_3DPRIM_START_VERTEX 0x2430
1730 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1731 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1732 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1733 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1735 void genX(CmdDrawIndirect
)(
1736 VkCommandBuffer commandBuffer
,
1738 VkDeviceSize offset
,
1742 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1743 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1744 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1745 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1746 struct anv_bo
*bo
= buffer
->bo
;
1747 uint32_t bo_offset
= buffer
->offset
+ offset
;
1749 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1751 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1752 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
1753 if (vs_prog_data
->uses_drawid
)
1754 emit_draw_index(cmd_buffer
, 0);
1756 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1757 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1758 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1759 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
1760 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
1762 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1763 prim
.IndirectParameterEnable
= true;
1764 prim
.VertexAccessType
= SEQUENTIAL
;
1765 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1769 void genX(CmdDrawIndexedIndirect
)(
1770 VkCommandBuffer commandBuffer
,
1772 VkDeviceSize offset
,
1776 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1777 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1778 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1779 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1780 struct anv_bo
*bo
= buffer
->bo
;
1781 uint32_t bo_offset
= buffer
->offset
+ offset
;
1783 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1785 /* TODO: We need to stomp base vertex to 0 somehow */
1786 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1787 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
1788 if (vs_prog_data
->uses_drawid
)
1789 emit_draw_index(cmd_buffer
, 0);
1791 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1792 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1793 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1794 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
1795 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
1797 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1798 prim
.IndirectParameterEnable
= true;
1799 prim
.VertexAccessType
= RANDOM
;
1800 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1805 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
1807 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1808 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
1811 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1812 if (result
!= VK_SUCCESS
) {
1813 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1814 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1815 assert(result
== VK_SUCCESS
);
1817 /* Re-emit state base addresses so we get the new surface state base
1818 * address before we start emitting binding tables etc.
1820 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1822 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1823 assert(result
== VK_SUCCESS
);
1826 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
1827 assert(result
== VK_SUCCESS
);
1829 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
1830 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1831 .BindingTablePointer
= surfaces
.offset
,
1832 .SamplerStatePointer
= samplers
.offset
,
1834 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
1836 struct anv_state state
=
1837 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
1838 pipeline
->interface_descriptor_data
,
1839 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
1842 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
1843 anv_batch_emit(&cmd_buffer
->batch
,
1844 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
1845 mid
.InterfaceDescriptorTotalLength
= size
;
1846 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
1853 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1855 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1856 MAYBE_UNUSED VkResult result
;
1858 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
1860 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1862 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
1864 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1865 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
1867 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
1868 * the only bits that are changed are scoreboard related: Scoreboard
1869 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
1870 * these scoreboard related states, a MEDIA_STATE_FLUSH is
1873 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1874 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1876 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1879 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
1880 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
1881 /* FIXME: figure out descriptors for gen7 */
1882 result
= flush_compute_descriptor_set(cmd_buffer
);
1883 assert(result
== VK_SUCCESS
);
1884 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
1887 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
1888 struct anv_state push_state
=
1889 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
1891 if (push_state
.alloc_size
) {
1892 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
1893 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
1894 curbe
.CURBEDataStartAddress
= push_state
.offset
;
1899 cmd_buffer
->state
.compute_dirty
= 0;
1901 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1907 verify_cmd_parser(const struct anv_device
*device
,
1908 int required_version
,
1909 const char *function
)
1911 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
1912 return vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
1913 "cmd parser version %d is required for %s",
1914 required_version
, function
);
1922 void genX(CmdDispatch
)(
1923 VkCommandBuffer commandBuffer
,
1928 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1929 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1930 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1932 if (prog_data
->uses_num_work_groups
) {
1933 struct anv_state state
=
1934 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
1935 uint32_t *sizes
= state
.map
;
1939 if (!cmd_buffer
->device
->info
.has_llc
)
1940 anv_state_clflush(state
);
1941 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
1942 cmd_buffer
->state
.num_workgroups_bo
=
1943 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
1946 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1948 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
1949 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1950 ggw
.ThreadDepthCounterMaximum
= 0;
1951 ggw
.ThreadHeightCounterMaximum
= 0;
1952 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1953 ggw
.ThreadGroupIDXDimension
= x
;
1954 ggw
.ThreadGroupIDYDimension
= y
;
1955 ggw
.ThreadGroupIDZDimension
= z
;
1956 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1957 ggw
.BottomExecutionMask
= 0xffffffff;
1960 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1963 #define GPGPU_DISPATCHDIMX 0x2500
1964 #define GPGPU_DISPATCHDIMY 0x2504
1965 #define GPGPU_DISPATCHDIMZ 0x2508
1967 #define MI_PREDICATE_SRC0 0x2400
1968 #define MI_PREDICATE_SRC1 0x2408
1970 void genX(CmdDispatchIndirect
)(
1971 VkCommandBuffer commandBuffer
,
1973 VkDeviceSize offset
)
1975 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1976 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1977 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1978 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1979 struct anv_bo
*bo
= buffer
->bo
;
1980 uint32_t bo_offset
= buffer
->offset
+ offset
;
1981 struct anv_batch
*batch
= &cmd_buffer
->batch
;
1984 /* Linux 4.4 added command parser version 5 which allows the GPGPU
1985 * indirect dispatch registers to be written.
1987 if (verify_cmd_parser(cmd_buffer
->device
, 5,
1988 "vkCmdDispatchIndirect") != VK_SUCCESS
)
1992 if (prog_data
->uses_num_work_groups
) {
1993 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
1994 cmd_buffer
->state
.num_workgroups_bo
= bo
;
1997 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1999 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
2000 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
2001 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
2004 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
2005 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
2006 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
2007 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
2009 /* Load compute_dispatch_indirect_x_size into SRC0 */
2010 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
2012 /* predicate = (compute_dispatch_indirect_x_size == 0); */
2013 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2014 mip
.LoadOperation
= LOAD_LOAD
;
2015 mip
.CombineOperation
= COMBINE_SET
;
2016 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2019 /* Load compute_dispatch_indirect_y_size into SRC0 */
2020 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
2022 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
2023 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2024 mip
.LoadOperation
= LOAD_LOAD
;
2025 mip
.CombineOperation
= COMBINE_OR
;
2026 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2029 /* Load compute_dispatch_indirect_z_size into SRC0 */
2030 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
2032 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
2033 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2034 mip
.LoadOperation
= LOAD_LOAD
;
2035 mip
.CombineOperation
= COMBINE_OR
;
2036 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2039 /* predicate = !predicate; */
2040 #define COMPARE_FALSE 1
2041 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2042 mip
.LoadOperation
= LOAD_LOADINV
;
2043 mip
.CombineOperation
= COMBINE_OR
;
2044 mip
.CompareOperation
= COMPARE_FALSE
;
2048 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
2049 ggw
.IndirectParameterEnable
= true;
2050 ggw
.PredicateEnable
= GEN_GEN
<= 7;
2051 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2052 ggw
.ThreadDepthCounterMaximum
= 0;
2053 ggw
.ThreadHeightCounterMaximum
= 0;
2054 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2055 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2056 ggw
.BottomExecutionMask
= 0xffffffff;
2059 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2063 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
2066 #if GEN_GEN >= 8 && GEN_GEN < 10
2067 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
2069 * Software must clear the COLOR_CALC_STATE Valid field in
2070 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
2071 * with Pipeline Select set to GPGPU.
2073 * The internal hardware docs recommend the same workaround for Gen9
2076 if (pipeline
== GPGPU
)
2077 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
2079 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
2080 * PIPELINE_SELECT [DevBWR+]":
2084 * Software must ensure all the write caches are flushed through a
2085 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
2086 * command to invalidate read only caches prior to programming
2087 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
2089 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2090 pc
.RenderTargetCacheFlushEnable
= true;
2091 pc
.DepthCacheFlushEnable
= true;
2092 pc
.DCFlushEnable
= true;
2093 pc
.PostSyncOperation
= NoWrite
;
2094 pc
.CommandStreamerStallEnable
= true;
2097 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2098 pc
.TextureCacheInvalidationEnable
= true;
2099 pc
.ConstantCacheInvalidationEnable
= true;
2100 pc
.StateCacheInvalidationEnable
= true;
2101 pc
.InstructionCacheInvalidateEnable
= true;
2102 pc
.PostSyncOperation
= NoWrite
;
2108 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
2110 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
2111 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
2113 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2117 ps
.PipelineSelection
= _3D
;
2120 cmd_buffer
->state
.current_pipeline
= _3D
;
2125 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
2127 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
2128 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
2130 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2134 ps
.PipelineSelection
= GPGPU
;
2137 cmd_buffer
->state
.current_pipeline
= GPGPU
;
2142 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
2147 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
2149 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
2150 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
2151 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
2152 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
2153 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
2154 * Depth Flush Bit set, followed by another pipelined depth stall
2155 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
2156 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
2157 * via a preceding MI_FLUSH)."
2159 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2160 pipe
.DepthStallEnable
= true;
2162 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2163 pipe
.DepthCacheFlushEnable
= true;
2165 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2166 pipe
.DepthStallEnable
= true;
2171 depth_stencil_surface_type(enum isl_surf_dim dim
)
2174 case ISL_SURF_DIM_1D
:
2176 /* From the Sky Lake PRM, 3DSTATAE_DEPTH_BUFFER::SurfaceType
2178 * Programming Notes:
2179 * The Surface Type of the depth buffer must be the same as the
2180 * Surface Type of the render target(s) (defined in
2181 * SURFACE_STATE), unless either the depth buffer or render
2182 * targets are SURFTYPE_NULL (see exception below for SKL). 1D
2183 * surface type not allowed for depth surface and stencil surface.
2186 * If depth/stencil is enabled with 1D render target,
2187 * depth/stencil surface type needs to be set to 2D surface type
2188 * and height set to 1. Depth will use (legacy) TileY and stencil
2189 * will use TileW. For this case only, the Surface Type of the
2190 * depth buffer can be 2D while the Surface Type of the render
2191 * target(s) are 1D, representing an exception to a programming
2198 case ISL_SURF_DIM_2D
:
2200 case ISL_SURF_DIM_3D
:
2202 /* The Sky Lake docs list the value for 3D as "Reserved". However,
2203 * they have the exact same layout as 2D arrays on gen9+, so we can
2211 unreachable("Invalid surface dimension");
2216 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
2218 struct anv_device
*device
= cmd_buffer
->device
;
2219 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
2220 const struct anv_image_view
*iview
=
2221 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2222 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
2223 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
2224 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2225 const bool has_hiz
= image
!= NULL
&&
2226 cmd_buffer
->state
.attachments
[ds
].aux_usage
== ISL_AUX_USAGE_HIZ
;
2227 const bool has_stencil
=
2228 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
2230 /* FIXME: Implement the PMA stall W/A */
2231 /* FIXME: Width and Height are wrong */
2233 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
2235 /* Emit 3DSTATE_DEPTH_BUFFER */
2237 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2239 depth_stencil_surface_type(image
->depth_surface
.isl
.dim
);
2240 db
.DepthWriteEnable
= true;
2241 db
.StencilWriteEnable
= has_stencil
;
2242 db
.HierarchicalDepthBufferEnable
= has_hiz
;
2244 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
2245 &image
->depth_surface
.isl
);
2247 db
.SurfaceBaseAddress
= (struct anv_address
) {
2249 .offset
= image
->offset
+ image
->depth_surface
.offset
,
2251 db
.DepthBufferObjectControlState
= GENX(MOCS
);
2253 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
2254 db
.Height
= image
->extent
.height
- 1;
2255 db
.Width
= image
->extent
.width
- 1;
2256 db
.LOD
= iview
->isl
.base_level
;
2257 db
.MinimumArrayElement
= iview
->isl
.base_array_layer
;
2259 assert(image
->depth_surface
.isl
.dim
!= ISL_SURF_DIM_3D
);
2261 db
.RenderTargetViewExtent
=
2262 iview
->isl
.array_len
- iview
->isl
.base_array_layer
- 1;
2266 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2;
2270 /* Even when no depth buffer is present, the hardware requires that
2271 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
2273 * If a null depth buffer is bound, the driver must instead bind depth as:
2274 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
2275 * 3DSTATE_DEPTH.Width = 1
2276 * 3DSTATE_DEPTH.Height = 1
2277 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
2278 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
2279 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
2280 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
2281 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
2283 * The PRM is wrong, though. The width and height must be programmed to
2284 * actual framebuffer's width and height, even when neither depth buffer
2285 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
2286 * be combined with a stencil buffer so we use D32_FLOAT instead.
2288 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2291 depth_stencil_surface_type(image
->stencil_surface
.isl
.dim
);
2293 db
.SurfaceType
= SURFTYPE_2D
;
2295 db
.SurfaceFormat
= D32_FLOAT
;
2296 db
.Width
= MAX2(fb
->width
, 1) - 1;
2297 db
.Height
= MAX2(fb
->height
, 1) - 1;
2298 db
.StencilWriteEnable
= has_stencil
;
2303 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
) {
2304 hdb
.HierarchicalDepthBufferObjectControlState
= GENX(MOCS
);
2305 hdb
.SurfacePitch
= image
->aux_surface
.isl
.row_pitch
- 1;
2306 hdb
.SurfaceBaseAddress
= (struct anv_address
) {
2308 .offset
= image
->offset
+ image
->aux_surface
.offset
,
2311 /* From the SKL PRM Vol2a:
2313 * The interpretation of this field is dependent on Surface Type
2315 * - SURFTYPE_1D: distance in pixels between array slices
2316 * - SURFTYPE_2D/CUBE: distance in rows between array slices
2317 * - SURFTYPE_3D: distance in rows between R - slices
2319 * Unfortunately, the docs aren't 100% accurate here. They fail to
2320 * mention that the 1-D rule only applies to linear 1-D images.
2321 * Since depth and HiZ buffers are always tiled, they are treated as
2322 * 2-D images. Prior to Sky Lake, this field is always in rows.
2325 isl_surf_get_array_pitch_sa_rows(&image
->aux_surface
.isl
) >> 2;
2329 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
);
2332 /* Emit 3DSTATE_STENCIL_BUFFER */
2334 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
2335 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2336 sb
.StencilBufferEnable
= true;
2338 sb
.StencilBufferObjectControlState
= GENX(MOCS
);
2340 sb
.SurfacePitch
= image
->stencil_surface
.isl
.row_pitch
- 1;
2343 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2;
2345 sb
.SurfaceBaseAddress
= (struct anv_address
) {
2347 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
2351 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
2354 /* From the IVB PRM Vol2P1, 11.5.5.4 3DSTATE_CLEAR_PARAMS:
2356 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along with
2357 * the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
2358 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)
2360 * Testing also shows that some variant of this restriction may exist HSW+.
2361 * On BDW+, it is not possible to emit 2 of these packets consecutively when
2362 * both have DepthClearValueValid set. An analysis of such state programming
2363 * on SKL showed that the GPU doesn't register the latter packet's clear
2366 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
) {
2368 cp
.DepthClearValueValid
= true;
2369 cp
.DepthClearValue
= ANV_HZ_FC_VAL
;
2375 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
2376 struct anv_subpass
*subpass
)
2378 cmd_buffer
->state
.subpass
= subpass
;
2380 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
2382 const struct anv_image_view
*iview
=
2383 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2385 if (iview
&& iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
2386 const uint32_t ds
= subpass
->depth_stencil_attachment
;
2387 transition_depth_buffer(cmd_buffer
, iview
->image
,
2388 cmd_buffer
->state
.attachments
[ds
].current_layout
,
2389 cmd_buffer
->state
.subpass
->depth_stencil_layout
);
2390 cmd_buffer
->state
.attachments
[ds
].current_layout
=
2391 cmd_buffer
->state
.subpass
->depth_stencil_layout
;
2392 cmd_buffer
->state
.attachments
[ds
].aux_usage
=
2393 layout_to_hiz_usage(cmd_buffer
->state
.subpass
->depth_stencil_layout
,
2394 iview
->image
->samples
);
2397 cmd_buffer_emit_depth_stencil(cmd_buffer
);
2399 anv_cmd_buffer_clear_subpass(cmd_buffer
);
2402 void genX(CmdBeginRenderPass
)(
2403 VkCommandBuffer commandBuffer
,
2404 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2405 VkSubpassContents contents
)
2407 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2408 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2409 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2411 cmd_buffer
->state
.framebuffer
= framebuffer
;
2412 cmd_buffer
->state
.pass
= pass
;
2413 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2414 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
2416 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2418 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
2421 void genX(CmdNextSubpass
)(
2422 VkCommandBuffer commandBuffer
,
2423 VkSubpassContents contents
)
2425 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2427 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2429 const struct anv_image_view
*iview
=
2430 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2432 if (iview
&& iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
2433 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2435 if (cmd_buffer
->state
.subpass
- cmd_buffer
->state
.pass
->subpasses
==
2436 cmd_buffer
->state
.pass
->attachments
[ds
].last_subpass_idx
) {
2437 transition_depth_buffer(cmd_buffer
, iview
->image
,
2438 cmd_buffer
->state
.attachments
[ds
].current_layout
,
2439 cmd_buffer
->state
.pass
->attachments
[ds
].final_layout
);
2443 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2444 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
2447 void genX(CmdEndRenderPass
)(
2448 VkCommandBuffer commandBuffer
)
2450 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2452 const struct anv_image_view
*iview
=
2453 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2455 if (iview
&& iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
2456 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2458 if (cmd_buffer
->state
.subpass
- cmd_buffer
->state
.pass
->subpasses
==
2459 cmd_buffer
->state
.pass
->attachments
[ds
].last_subpass_idx
) {
2460 transition_depth_buffer(cmd_buffer
, iview
->image
,
2461 cmd_buffer
->state
.attachments
[ds
].current_layout
,
2462 cmd_buffer
->state
.pass
->attachments
[ds
].final_layout
);
2466 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2469 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
2474 emit_ps_depth_count(struct anv_cmd_buffer
*cmd_buffer
,
2475 struct anv_bo
*bo
, uint32_t offset
)
2477 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2478 pc
.DestinationAddressType
= DAT_PPGTT
;
2479 pc
.PostSyncOperation
= WritePSDepthCount
;
2480 pc
.DepthStallEnable
= true;
2481 pc
.Address
= (struct anv_address
) { bo
, offset
};
2483 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2484 pc
.CommandStreamerStallEnable
= true;
2489 emit_query_availability(struct anv_cmd_buffer
*cmd_buffer
,
2490 struct anv_bo
*bo
, uint32_t offset
)
2492 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2493 pc
.DestinationAddressType
= DAT_PPGTT
;
2494 pc
.PostSyncOperation
= WriteImmediateData
;
2495 pc
.Address
= (struct anv_address
) { bo
, offset
};
2496 pc
.ImmediateData
= 1;
2500 void genX(CmdBeginQuery
)(
2501 VkCommandBuffer commandBuffer
,
2502 VkQueryPool queryPool
,
2504 VkQueryControlFlags flags
)
2506 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2507 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2509 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
2510 * that the pipelining of the depth write breaks. What we see is that
2511 * samples from the render pass clear leaks into the first query
2512 * immediately after the clear. Doing a pipecontrol with a post-sync
2513 * operation and DepthStallEnable seems to work around the issue.
2515 if (cmd_buffer
->state
.need_query_wa
) {
2516 cmd_buffer
->state
.need_query_wa
= false;
2517 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2518 pc
.DepthCacheFlushEnable
= true;
2519 pc
.DepthStallEnable
= true;
2523 switch (pool
->type
) {
2524 case VK_QUERY_TYPE_OCCLUSION
:
2525 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2526 query
* sizeof(struct anv_query_pool_slot
));
2529 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2535 void genX(CmdEndQuery
)(
2536 VkCommandBuffer commandBuffer
,
2537 VkQueryPool queryPool
,
2540 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2541 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2543 switch (pool
->type
) {
2544 case VK_QUERY_TYPE_OCCLUSION
:
2545 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2546 query
* sizeof(struct anv_query_pool_slot
) + 8);
2548 emit_query_availability(cmd_buffer
, &pool
->bo
,
2549 query
* sizeof(struct anv_query_pool_slot
) + 16);
2552 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2558 #define TIMESTAMP 0x2358
2560 void genX(CmdWriteTimestamp
)(
2561 VkCommandBuffer commandBuffer
,
2562 VkPipelineStageFlagBits pipelineStage
,
2563 VkQueryPool queryPool
,
2566 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2567 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2568 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
2570 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
2572 switch (pipelineStage
) {
2573 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
2574 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2575 srm
.RegisterAddress
= TIMESTAMP
;
2576 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
};
2578 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2579 srm
.RegisterAddress
= TIMESTAMP
+ 4;
2580 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
+ 4 };
2585 /* Everything else is bottom-of-pipe */
2586 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2587 pc
.DestinationAddressType
= DAT_PPGTT
;
2588 pc
.PostSyncOperation
= WriteTimestamp
;
2589 pc
.Address
= (struct anv_address
) { &pool
->bo
, offset
};
2591 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2592 pc
.CommandStreamerStallEnable
= true;
2597 emit_query_availability(cmd_buffer
, &pool
->bo
, query
+ 16);
2600 #if GEN_GEN > 7 || GEN_IS_HASWELL
2602 #define alu_opcode(v) __gen_uint((v), 20, 31)
2603 #define alu_operand1(v) __gen_uint((v), 10, 19)
2604 #define alu_operand2(v) __gen_uint((v), 0, 9)
2605 #define alu(opcode, operand1, operand2) \
2606 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
2608 #define OPCODE_NOOP 0x000
2609 #define OPCODE_LOAD 0x080
2610 #define OPCODE_LOADINV 0x480
2611 #define OPCODE_LOAD0 0x081
2612 #define OPCODE_LOAD1 0x481
2613 #define OPCODE_ADD 0x100
2614 #define OPCODE_SUB 0x101
2615 #define OPCODE_AND 0x102
2616 #define OPCODE_OR 0x103
2617 #define OPCODE_XOR 0x104
2618 #define OPCODE_STORE 0x180
2619 #define OPCODE_STOREINV 0x580
2621 #define OPERAND_R0 0x00
2622 #define OPERAND_R1 0x01
2623 #define OPERAND_R2 0x02
2624 #define OPERAND_R3 0x03
2625 #define OPERAND_R4 0x04
2626 #define OPERAND_SRCA 0x20
2627 #define OPERAND_SRCB 0x21
2628 #define OPERAND_ACCU 0x31
2629 #define OPERAND_ZF 0x32
2630 #define OPERAND_CF 0x33
2632 #define CS_GPR(n) (0x2600 + (n) * 8)
2635 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
2636 struct anv_bo
*bo
, uint32_t offset
)
2638 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2639 lrm
.RegisterAddress
= reg
,
2640 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2642 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2643 lrm
.RegisterAddress
= reg
+ 4;
2644 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2649 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
2650 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
2652 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2653 srm
.RegisterAddress
= reg
;
2654 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2657 if (flags
& VK_QUERY_RESULT_64_BIT
) {
2658 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2659 srm
.RegisterAddress
= reg
+ 4;
2660 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2665 void genX(CmdCopyQueryPoolResults
)(
2666 VkCommandBuffer commandBuffer
,
2667 VkQueryPool queryPool
,
2668 uint32_t firstQuery
,
2669 uint32_t queryCount
,
2670 VkBuffer destBuffer
,
2671 VkDeviceSize destOffset
,
2672 VkDeviceSize destStride
,
2673 VkQueryResultFlags flags
)
2675 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2676 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2677 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
2678 uint32_t slot_offset
, dst_offset
;
2680 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
2681 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2682 pc
.CommandStreamerStallEnable
= true;
2683 pc
.StallAtPixelScoreboard
= true;
2687 dst_offset
= buffer
->offset
+ destOffset
;
2688 for (uint32_t i
= 0; i
< queryCount
; i
++) {
2690 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
2691 switch (pool
->type
) {
2692 case VK_QUERY_TYPE_OCCLUSION
:
2693 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2694 CS_GPR(0), &pool
->bo
, slot_offset
);
2695 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2696 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
2698 /* FIXME: We need to clamp the result for 32 bit. */
2700 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
2701 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
2702 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
2703 dw
[3] = alu(OPCODE_SUB
, 0, 0);
2704 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
2707 case VK_QUERY_TYPE_TIMESTAMP
:
2708 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2709 CS_GPR(2), &pool
->bo
, slot_offset
);
2713 unreachable("unhandled query type");
2716 store_query_result(&cmd_buffer
->batch
,
2717 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
2719 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
2720 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
2721 &pool
->bo
, slot_offset
+ 16);
2722 if (flags
& VK_QUERY_RESULT_64_BIT
)
2723 store_query_result(&cmd_buffer
->batch
,
2724 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
2726 store_query_result(&cmd_buffer
->batch
,
2727 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
2730 dst_offset
+= destStride
;
2735 void genX(CmdCopyQueryPoolResults
)(
2736 VkCommandBuffer commandBuffer
,
2737 VkQueryPool queryPool
,
2738 uint32_t firstQuery
,
2739 uint32_t queryCount
,
2740 VkBuffer destBuffer
,
2741 VkDeviceSize destOffset
,
2742 VkDeviceSize destStride
,
2743 VkQueryResultFlags flags
)
2745 anv_finishme("Queries not yet supported on Ivy Bridge");