2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
,
37 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
39 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
40 lrm
.RegisterAddress
= reg
;
41 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
46 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
48 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
49 lri
.RegisterOffset
= reg
;
54 #if GEN_IS_HASWELL || GEN_GEN >= 8
56 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
58 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
59 lrr
.SourceRegisterAddress
= src
;
60 lrr
.DestinationRegisterAddress
= dst
;
66 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
68 struct anv_device
*device
= cmd_buffer
->device
;
70 /* Emit a render target cache flush.
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
77 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
78 pc
.DCFlushEnable
= true;
79 pc
.RenderTargetCacheFlushEnable
= true;
80 pc
.CommandStreamerStallEnable
= true;
83 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
84 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
85 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
86 sba
.GeneralStateBaseAddressModifyEnable
= true;
88 sba
.SurfaceStateBaseAddress
=
89 anv_cmd_buffer_surface_base_address(cmd_buffer
);
90 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
91 sba
.SurfaceStateBaseAddressModifyEnable
= true;
93 sba
.DynamicStateBaseAddress
=
94 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
95 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
96 sba
.DynamicStateBaseAddressModifyEnable
= true;
98 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
99 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
100 sba
.IndirectObjectBaseAddressModifyEnable
= true;
102 sba
.InstructionBaseAddress
=
103 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
104 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
105 sba
.InstructionBaseAddressModifyEnable
= true;
108 /* Broadwell requires that we specify a buffer size for a bunch of
109 * these fields. However, since we will be growing the BO's live, we
110 * just set them all to the maximum.
112 sba
.GeneralStateBufferSize
= 0xfffff;
113 sba
.GeneralStateBufferSizeModifyEnable
= true;
114 sba
.DynamicStateBufferSize
= 0xfffff;
115 sba
.DynamicStateBufferSizeModifyEnable
= true;
116 sba
.IndirectObjectBufferSize
= 0xfffff;
117 sba
.IndirectObjectBufferSizeModifyEnable
= true;
118 sba
.InstructionBufferSize
= 0xfffff;
119 sba
.InstructionBuffersizeModifyEnable
= true;
123 /* After re-setting the surface state base address, we have to do some
124 * cache flusing so that the sampler engine will pick up the new
125 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
126 * Shared Function > 3D Sampler > State > State Caching (page 96):
128 * Coherency with system memory in the state cache, like the texture
129 * cache is handled partially by software. It is expected that the
130 * command stream or shader will issue Cache Flush operation or
131 * Cache_Flush sampler message to ensure that the L1 cache remains
132 * coherent with system memory.
136 * Whenever the value of the Dynamic_State_Base_Addr,
137 * Surface_State_Base_Addr are altered, the L1 state cache must be
138 * invalidated to ensure the new surface or sampler state is fetched
139 * from system memory.
141 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
142 * which, according the PIPE_CONTROL instruction documentation in the
145 * Setting this bit is independent of any other bit in this packet.
146 * This bit controls the invalidation of the L1 and L2 state caches
147 * at the top of the pipe i.e. at the parsing time.
149 * Unfortunately, experimentation seems to indicate that state cache
150 * invalidation through a PIPE_CONTROL does nothing whatsoever in
151 * regards to surface state and binding tables. In stead, it seems that
152 * invalidating the texture cache is what is actually needed.
154 * XXX: As far as we have been able to determine through
155 * experimentation, shows that flush the texture cache appears to be
156 * sufficient. The theory here is that all of the sampling/rendering
157 * units cache the binding table in the texture cache. However, we have
158 * yet to be able to actually confirm this.
160 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
161 pc
.TextureCacheInvalidationEnable
= true;
162 pc
.ConstantCacheInvalidationEnable
= true;
163 pc
.StateCacheInvalidationEnable
= true;
168 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
169 struct anv_state state
,
170 struct anv_bo
*bo
, uint32_t offset
)
172 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
175 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
176 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
177 if (result
!= VK_SUCCESS
)
178 anv_batch_set_error(&cmd_buffer
->batch
, result
);
182 add_image_relocs(struct anv_cmd_buffer
* const cmd_buffer
,
183 const struct anv_image
* const image
,
184 const VkImageAspectFlags aspect_mask
,
185 const enum isl_aux_usage aux_usage
,
186 const struct anv_state state
)
188 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
189 const uint32_t surf_offset
= image
->offset
+
190 anv_image_get_surface_for_aspect_mask(image
, aspect_mask
)->offset
;
192 add_surface_state_reloc(cmd_buffer
, state
, image
->bo
, surf_offset
);
194 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
195 uint32_t aux_offset
= image
->offset
+ image
->aux_surface
.offset
;
197 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
198 * used to store other information. This should be ok, however, because
199 * surface buffer addresses are always 4K page alinged.
201 assert((aux_offset
& 0xfff) == 0);
202 uint32_t *aux_addr_dw
= state
.map
+ isl_dev
->ss
.aux_addr_offset
;
203 aux_offset
+= *aux_addr_dw
& 0xfff;
206 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
207 &cmd_buffer
->pool
->alloc
,
208 state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
209 image
->bo
, aux_offset
);
210 if (result
!= VK_SUCCESS
)
211 anv_batch_set_error(&cmd_buffer
->batch
, result
);
216 color_is_zero_one(VkClearColorValue value
, enum isl_format format
)
218 if (isl_format_has_int_channel(format
)) {
219 for (unsigned i
= 0; i
< 4; i
++) {
220 if (value
.int32
[i
] != 0 && value
.int32
[i
] != 1)
224 for (unsigned i
= 0; i
< 4; i
++) {
225 if (value
.float32
[i
] != 0.0f
&& value
.float32
[i
] != 1.0f
)
234 color_attachment_compute_aux_usage(struct anv_device
* device
,
235 struct anv_cmd_state
* cmd_state
,
236 uint32_t att
, VkRect2D render_area
,
237 union isl_color_value
*fast_clear_color
)
239 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
240 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
242 if (iview
->isl
.base_array_layer
>=
243 anv_image_aux_layers(iview
->image
, iview
->isl
.base_level
)) {
244 /* There is no aux buffer which corresponds to the level and layer(s)
247 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
248 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
249 att_state
->fast_clear
= false;
251 } else if (iview
->image
->aux_usage
== ISL_AUX_USAGE_MCS
) {
252 att_state
->aux_usage
= ISL_AUX_USAGE_MCS
;
253 att_state
->input_aux_usage
= ISL_AUX_USAGE_MCS
;
254 att_state
->fast_clear
= false;
256 } else if (iview
->image
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
257 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
258 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_E
;
260 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
261 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
263 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
264 * setting is only allowed if Surface Format supported for Fast
265 * Clear. In addition, if the surface is bound to the sampling
266 * engine, Surface Format must be supported for Render Target
267 * Compression for surfaces bound to the sampling engine."
269 * In other words, we can only sample from a fast-cleared image if it
270 * also supports color compression.
272 if (isl_format_supports_ccs_e(&device
->info
, iview
->isl
.format
)) {
273 /* TODO: Consider using a heuristic to determine if temporarily enabling
274 * CCS_E for this image view would be beneficial.
276 * While fast-clear resolves and partial resolves are fairly cheap in the
277 * case where you render to most of the pixels, full resolves are not
278 * because they potentially involve reading and writing the entire
279 * framebuffer. If we can't texture with CCS_E, we should leave it off and
280 * limit ourselves to fast clears.
282 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
284 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
288 assert(iview
->image
->aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
290 att_state
->clear_color_is_zero_one
=
291 color_is_zero_one(att_state
->clear_value
.color
, iview
->isl
.format
);
292 att_state
->clear_color_is_zero
=
293 att_state
->clear_value
.color
.uint32
[0] == 0 &&
294 att_state
->clear_value
.color
.uint32
[1] == 0 &&
295 att_state
->clear_value
.color
.uint32
[2] == 0 &&
296 att_state
->clear_value
.color
.uint32
[3] == 0;
298 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
299 /* Start off assuming fast clears are possible */
300 att_state
->fast_clear
= true;
302 /* Potentially, we could do partial fast-clears but doing so has crazy
303 * alignment restrictions. It's easier to just restrict to full size
304 * fast clears for now.
306 if (render_area
.offset
.x
!= 0 ||
307 render_area
.offset
.y
!= 0 ||
308 render_area
.extent
.width
!= iview
->extent
.width
||
309 render_area
.extent
.height
!= iview
->extent
.height
)
310 att_state
->fast_clear
= false;
312 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
313 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
314 att_state
->fast_clear
= false;
316 /* We allow fast clears when all aux layers of the miplevel are targeted.
317 * See add_fast_clear_state_buffer() for more information. Also, because
318 * we only either do a fast clear or a normal clear and not both, this
319 * complies with the gen7 restriction of not fast-clearing multiple
322 if (cmd_state
->framebuffer
->layers
!=
323 anv_image_aux_layers(iview
->image
, iview
->isl
.base_level
)) {
324 att_state
->fast_clear
= false;
326 anv_perf_warn("Not fast-clearing the first layer in "
327 "a multi-layer fast clear.");
331 /* We only allow fast clears in the GENERAL layout if the auxiliary
332 * buffer is always enabled and the fast-clear value is all 0's. See
333 * add_fast_clear_state_buffer() for more information.
335 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
336 VK_IMAGE_LAYOUT_GENERAL
&&
337 (!att_state
->clear_color_is_zero
||
338 iview
->image
->aux_usage
== ISL_AUX_USAGE_NONE
)) {
339 att_state
->fast_clear
= false;
342 if (att_state
->fast_clear
) {
343 memcpy(fast_clear_color
->u32
, att_state
->clear_value
.color
.uint32
,
344 sizeof(fast_clear_color
->u32
));
347 att_state
->fast_clear
= false;
352 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
354 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
357 /* We only allocate input attachment states for color surfaces. Compression
358 * is not yet enabled for depth textures and stencil doesn't allow
359 * compression so we can just use the texture surface state from the view.
361 return vk_format_is_color(att
->format
);
364 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
365 * the initial layout is undefined, the HiZ buffer and depth buffer will
366 * represent the same data at the end of this operation.
369 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
370 const struct anv_image
*image
,
371 VkImageLayout initial_layout
,
372 VkImageLayout final_layout
)
376 /* A transition is a no-op if HiZ is not enabled, or if the initial and
377 * final layouts are equal.
379 * The undefined layout indicates that the user doesn't care about the data
380 * that's currently in the buffer. Therefore, a data-preserving resolve
381 * operation is not needed.
383 if (image
->aux_usage
!= ISL_AUX_USAGE_HIZ
|| initial_layout
== final_layout
)
386 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
387 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
, image
->aspects
,
389 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
390 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
, image
->aspects
,
393 enum blorp_hiz_op hiz_op
;
394 if (hiz_enabled
&& !enable_hiz
) {
395 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
396 } else if (!hiz_enabled
&& enable_hiz
) {
397 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
399 assert(hiz_enabled
== enable_hiz
);
400 /* If the same buffer will be used, no resolves are necessary. */
401 hiz_op
= BLORP_HIZ_OP_NONE
;
404 if (hiz_op
!= BLORP_HIZ_OP_NONE
)
405 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, hiz_op
);
408 static inline uint32_t
409 get_fast_clear_state_entry_offset(const struct anv_device
*device
,
410 const struct anv_image
*image
,
413 assert(device
&& image
);
414 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
415 assert(level
< anv_image_aux_levels(image
));
416 const uint32_t offset
= image
->offset
+ image
->aux_surface
.offset
+
417 image
->aux_surface
.isl
.size
+
418 anv_fast_clear_state_entry_size(device
) * level
;
419 assert(offset
< image
->offset
+ image
->size
);
424 init_fast_clear_state_entry(struct anv_cmd_buffer
*cmd_buffer
,
425 const struct anv_image
*image
,
428 assert(cmd_buffer
&& image
);
429 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
430 assert(level
< anv_image_aux_levels(image
));
432 /* The fast clear value dword(s) will be copied into a surface state object.
433 * Ensure that the restrictions of the fields in the dword(s) are followed.
435 * CCS buffers on SKL+ can have any value set for the clear colors.
437 if (image
->samples
== 1 && GEN_GEN
>= 9)
440 /* Other combinations of auxiliary buffers and platforms require specific
441 * values in the clear value dword(s).
444 for (; i
< cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
; i
+= 4) {
445 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
446 const uint32_t entry_offset
=
447 get_fast_clear_state_entry_offset(cmd_buffer
->device
, image
, level
);
448 sdi
.Address
= (struct anv_address
) { image
->bo
, entry_offset
+ i
};
451 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
452 assert(image
->aux_usage
== ISL_AUX_USAGE_MCS
);
453 sdi
.ImmediateData
= 0;
454 } else if (GEN_VERSIONx10
>= 75) {
455 /* Pre-SKL, the dword containing the clear values also contains
456 * other fields, so we need to initialize those fields to match the
457 * values that would be in a color attachment.
460 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
461 ISL_CHANNEL_SELECT_GREEN
<< 22 |
462 ISL_CHANNEL_SELECT_BLUE
<< 19 |
463 ISL_CHANNEL_SELECT_ALPHA
<< 16;
464 } else if (GEN_VERSIONx10
== 70) {
465 /* On IVB, the dword containing the clear values also contains
466 * other fields that must be zero or can be zero.
469 sdi
.ImmediateData
= 0;
475 /* Copy the fast-clear value dword(s) between a surface state object and an
476 * image's fast clear state buffer.
479 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
480 struct anv_state surface_state
,
481 const struct anv_image
*image
,
483 bool copy_from_surface_state
)
485 assert(cmd_buffer
&& image
);
486 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
487 assert(level
< anv_image_aux_levels(image
));
489 struct anv_bo
*ss_bo
=
490 &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
;
491 uint32_t ss_clear_offset
= surface_state
.offset
+
492 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
;
493 uint32_t entry_offset
=
494 get_fast_clear_state_entry_offset(cmd_buffer
->device
, image
, level
);
495 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
497 if (copy_from_surface_state
) {
498 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, image
->bo
, entry_offset
,
499 ss_bo
, ss_clear_offset
, copy_size
);
501 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_bo
, ss_clear_offset
,
502 image
->bo
, entry_offset
, copy_size
);
504 /* Updating a surface state object may require that the state cache be
505 * invalidated. From the SKL PRM, Shared Functions -> State -> State
508 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
509 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
510 * modified [...], the L1 state cache must be invalidated to ensure
511 * the new surface or sampler state is fetched from system memory.
513 * In testing, SKL doesn't actually seem to need this, but HSW does.
515 cmd_buffer
->state
.pending_pipe_bits
|=
516 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
521 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
522 const struct anv_image
*image
,
523 const uint32_t base_level
, uint32_t level_count
,
524 uint32_t base_layer
, uint32_t layer_count
,
525 VkImageLayout initial_layout
,
526 VkImageLayout final_layout
)
528 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
530 if (image
->aux_surface
.isl
.size
== 0 ||
531 base_level
>= anv_image_aux_levels(image
))
534 if (initial_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
535 initial_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
)
538 /* A transition of a 3D subresource works on all slices at a time. */
539 if (image
->type
== VK_IMAGE_TYPE_3D
) {
541 layer_count
= anv_minify(image
->extent
.depth
, base_level
);
544 /* We're interested in the subresource range subset that has aux data. */
545 level_count
= MIN2(level_count
, anv_image_aux_levels(image
) - base_level
);
547 /* We're transitioning from an undefined layout. We must ensure that the
548 * clear values buffer is filled with valid data.
550 for (unsigned l
= 0; l
< level_count
; l
++)
551 init_fast_clear_state_entry(cmd_buffer
, image
, base_level
+ l
);
553 if (image
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
554 image
->aux_usage
== ISL_AUX_USAGE_MCS
) {
555 /* We're transitioning from an undefined layout so it doesn't really
556 * matter what data ends up in the color buffer. We do, however, need to
557 * ensure that the auxiliary surface is not in an undefined state. This
558 * state is possible for CCS buffers SKL+ and MCS buffers with certain
559 * sample counts that require certain bits to be reserved (2x and 8x).
560 * One easy way to get to a valid state is to fast-clear the specified
563 * Even for MCS buffers that have sample counts that don't require
564 * certain bits to be reserved (4x and 8x), we're unsure if the hardware
565 * will be okay with the sample mappings given by the undefined buffer.
566 * We don't have any data to show that this is a problem, but we want to
567 * avoid causing difficult-to-debug problems.
569 if (image
->samples
== 4 || image
->samples
== 16) {
570 anv_perf_warn("Doing a potentially unnecessary fast-clear to define "
574 anv_image_fast_clear(cmd_buffer
, image
, base_level
, level_count
,
575 base_layer
, layer_count
);
580 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
583 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
584 struct anv_render_pass
*pass
,
585 const VkRenderPassBeginInfo
*begin
)
587 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
588 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
590 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
592 if (pass
->attachment_count
> 0) {
593 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
594 pass
->attachment_count
*
595 sizeof(state
->attachments
[0]),
596 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
597 if (state
->attachments
== NULL
) {
598 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
599 return anv_batch_set_error(&cmd_buffer
->batch
,
600 VK_ERROR_OUT_OF_HOST_MEMORY
);
603 state
->attachments
= NULL
;
606 /* Reserve one for the NULL state. */
607 unsigned num_states
= 1;
608 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
609 if (vk_format_is_color(pass
->attachments
[i
].format
))
612 if (need_input_attachment_state(&pass
->attachments
[i
]))
616 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
617 state
->render_pass_states
=
618 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
619 num_states
* ss_stride
, isl_dev
->ss
.align
);
621 struct anv_state next_state
= state
->render_pass_states
;
622 next_state
.alloc_size
= isl_dev
->ss
.size
;
624 state
->null_surface_state
= next_state
;
625 next_state
.offset
+= ss_stride
;
626 next_state
.map
+= ss_stride
;
628 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
629 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
630 state
->attachments
[i
].color_rt_state
= next_state
;
631 next_state
.offset
+= ss_stride
;
632 next_state
.map
+= ss_stride
;
635 if (need_input_attachment_state(&pass
->attachments
[i
])) {
636 state
->attachments
[i
].input_att_state
= next_state
;
637 next_state
.offset
+= ss_stride
;
638 next_state
.map
+= ss_stride
;
641 assert(next_state
.offset
== state
->render_pass_states
.offset
+
642 state
->render_pass_states
.alloc_size
);
645 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
646 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
648 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
649 .SurfaceType
= SURFTYPE_NULL
,
650 .SurfaceArray
= framebuffer
->layers
> 0,
651 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
655 .TiledSurface
= true,
657 .Width
= framebuffer
->width
- 1,
658 .Height
= framebuffer
->height
- 1,
659 .Depth
= framebuffer
->layers
- 1,
660 .RenderTargetViewExtent
= framebuffer
->layers
- 1,
662 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
->null_surface_state
.map
,
665 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
666 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
667 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
668 VkImageAspectFlags clear_aspects
= 0;
670 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
671 /* color attachment */
672 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
673 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
676 /* depthstencil attachment */
677 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
678 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
679 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
681 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
682 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
683 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
687 state
->attachments
[i
].current_layout
= att
->initial_layout
;
688 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
690 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
692 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
693 anv_assert(iview
->vk_format
== att
->format
);
695 union isl_color_value clear_color
= { .u32
= { 0, } };
696 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
697 color_attachment_compute_aux_usage(cmd_buffer
->device
,
698 state
, i
, begin
->renderArea
,
701 struct isl_view view
= iview
->isl
;
702 view
.usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
703 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
704 isl_surf_fill_state(isl_dev
,
705 state
->attachments
[i
].color_rt_state
.map
,
706 .surf
= &iview
->image
->color_surface
.isl
,
708 .aux_surf
= &iview
->image
->aux_surface
.isl
,
709 .aux_usage
= state
->attachments
[i
].aux_usage
,
710 .clear_color
= clear_color
,
711 .mocs
= cmd_buffer
->device
->default_mocs
);
713 add_image_relocs(cmd_buffer
, iview
->image
, iview
->aspect_mask
,
714 state
->attachments
[i
].aux_usage
,
715 state
->attachments
[i
].color_rt_state
);
717 /* This field will be initialized after the first subpass
720 state
->attachments
[i
].aux_usage
= ISL_AUX_USAGE_NONE
;
722 state
->attachments
[i
].input_aux_usage
= ISL_AUX_USAGE_NONE
;
725 if (need_input_attachment_state(&pass
->attachments
[i
])) {
726 struct isl_view view
= iview
->isl
;
727 view
.usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
728 isl_surf_fill_state(isl_dev
,
729 state
->attachments
[i
].input_att_state
.map
,
730 .surf
= &iview
->image
->color_surface
.isl
,
732 .aux_surf
= &iview
->image
->aux_surface
.isl
,
733 .aux_usage
= state
->attachments
[i
].input_aux_usage
,
734 .clear_color
= clear_color
,
735 .mocs
= cmd_buffer
->device
->default_mocs
);
737 add_image_relocs(cmd_buffer
, iview
->image
, iview
->aspect_mask
,
738 state
->attachments
[i
].input_aux_usage
,
739 state
->attachments
[i
].input_att_state
);
743 anv_state_flush(cmd_buffer
->device
, state
->render_pass_states
);
750 genX(BeginCommandBuffer
)(
751 VkCommandBuffer commandBuffer
,
752 const VkCommandBufferBeginInfo
* pBeginInfo
)
754 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
756 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
757 * command buffer's state. Otherwise, we must *reset* its state. In both
760 * From the Vulkan 1.0 spec:
762 * If a command buffer is in the executable state and the command buffer
763 * was allocated from a command pool with the
764 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
765 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
766 * as if vkResetCommandBuffer had been called with
767 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
768 * the command buffer in the recording state.
770 anv_cmd_buffer_reset(cmd_buffer
);
772 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
774 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
775 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
777 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
779 /* We sometimes store vertex data in the dynamic state buffer for blorp
780 * operations and our dynamic state stream may re-use data from previous
781 * command buffers. In order to prevent stale cache data, we flush the VF
782 * cache. We could do this on every blorp call but that's not really
783 * needed as all of the data will get written by the CPU prior to the GPU
784 * executing anything. The chances are fairly high that they will use
785 * blorp at least once per primary command buffer so it shouldn't be
788 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
789 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
791 VkResult result
= VK_SUCCESS
;
792 if (cmd_buffer
->usage_flags
&
793 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
794 cmd_buffer
->state
.pass
=
795 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
796 cmd_buffer
->state
.subpass
=
797 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
798 cmd_buffer
->state
.framebuffer
= NULL
;
800 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
801 cmd_buffer
->state
.pass
, NULL
);
803 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
810 genX(EndCommandBuffer
)(
811 VkCommandBuffer commandBuffer
)
813 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
815 if (anv_batch_has_error(&cmd_buffer
->batch
))
816 return cmd_buffer
->batch
.status
;
818 /* We want every command buffer to start with the PMA fix in a known state,
819 * so we disable it at the end of the command buffer.
821 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
823 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
825 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
831 genX(CmdExecuteCommands
)(
832 VkCommandBuffer commandBuffer
,
833 uint32_t commandBufferCount
,
834 const VkCommandBuffer
* pCmdBuffers
)
836 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
838 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
840 if (anv_batch_has_error(&primary
->batch
))
843 /* The secondary command buffers will assume that the PMA fix is disabled
844 * when they begin executing. Make sure this is true.
846 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
848 /* The secondary command buffer doesn't know which textures etc. have been
849 * flushed prior to their execution. Apply those flushes now.
851 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
853 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
854 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
856 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
857 assert(!anv_batch_has_error(&secondary
->batch
));
859 if (secondary
->usage_flags
&
860 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
861 /* If we're continuing a render pass from the primary, we need to
862 * copy the surface states for the current subpass into the storage
863 * we allocated for them in BeginCommandBuffer.
865 struct anv_bo
*ss_bo
=
866 &primary
->device
->surface_state_pool
.block_pool
.bo
;
867 struct anv_state src_state
= primary
->state
.render_pass_states
;
868 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
869 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
871 genX(cmd_buffer_so_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
872 ss_bo
, src_state
.offset
,
873 src_state
.alloc_size
);
876 anv_cmd_buffer_add_secondary(primary
, secondary
);
879 /* Each of the secondary command buffers will use its own state base
880 * address. We need to re-emit state base address for the primary after
881 * all of the secondaries are done.
883 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
886 genX(cmd_buffer_emit_state_base_address
)(primary
);
889 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
890 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
891 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
894 * Program the hardware to use the specified L3 configuration.
897 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
898 const struct gen_l3_config
*cfg
)
901 if (cfg
== cmd_buffer
->state
.current_l3_config
)
904 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
905 fprintf(stderr
, "L3 config transition: ");
906 gen_dump_l3_config(cfg
, stderr
);
909 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
911 /* According to the hardware docs, the L3 partitioning can only be changed
912 * while the pipeline is completely drained and the caches are flushed,
913 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
915 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
916 pc
.DCFlushEnable
= true;
917 pc
.PostSyncOperation
= NoWrite
;
918 pc
.CommandStreamerStallEnable
= true;
921 /* ...followed by a second pipelined PIPE_CONTROL that initiates
922 * invalidation of the relevant caches. Note that because RO invalidation
923 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
924 * command is processed by the CS) we cannot combine it with the previous
925 * stalling flush as the hardware documentation suggests, because that
926 * would cause the CS to stall on previous rendering *after* RO
927 * invalidation and wouldn't prevent the RO caches from being polluted by
928 * concurrent rendering before the stall completes. This intentionally
929 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
930 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
931 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
932 * already guarantee that there is no concurrent GPGPU kernel execution
933 * (see SKL HSD 2132585).
935 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
936 pc
.TextureCacheInvalidationEnable
= true;
937 pc
.ConstantCacheInvalidationEnable
= true;
938 pc
.InstructionCacheInvalidateEnable
= true;
939 pc
.StateCacheInvalidationEnable
= true;
940 pc
.PostSyncOperation
= NoWrite
;
943 /* Now send a third stalling flush to make sure that invalidation is
944 * complete when the L3 configuration registers are modified.
946 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
947 pc
.DCFlushEnable
= true;
948 pc
.PostSyncOperation
= NoWrite
;
949 pc
.CommandStreamerStallEnable
= true;
954 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
957 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
958 .SLMEnable
= has_slm
,
959 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
960 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
961 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
962 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
964 /* Set up the L3 partitioning. */
965 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
969 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
970 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
972 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
974 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
977 assert(!cfg
->n
[GEN_L3P_ALL
]);
979 /* When enabled SLM only uses a portion of the L3 on half of the banks,
980 * the matching space on the remaining banks has to be allocated to a
981 * client (URB for all validated configurations) set to the
982 * lower-bandwidth 2-bank address hashing mode.
984 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
985 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
986 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
988 /* Minimum number of ways that can be allocated to the URB. */
989 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
990 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
992 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
993 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
994 .ConvertDC_UC
= !has_dc
,
995 .ConvertIS_UC
= !has_is
,
996 .ConvertC_UC
= !has_c
,
997 .ConvertT_UC
= !has_t
);
999 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1000 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1001 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1003 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1004 .SLMEnable
= has_slm
,
1005 .URBLowBandwidth
= urb_low_bw
,
1006 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1008 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1010 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1011 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1013 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1014 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1015 .ISLowBandwidth
= 0,
1016 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1018 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1019 .TLowBandwidth
= 0);
1021 /* Set up the L3 partitioning. */
1022 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1023 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1024 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1027 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1028 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1029 * them disabled to avoid crashing the system hard.
1031 uint32_t scratch1
, chicken3
;
1032 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1033 .L3AtomicDisable
= !has_dc
);
1034 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1035 .L3AtomicDisableMask
= true,
1036 .L3AtomicDisable
= !has_dc
);
1037 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1038 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1044 cmd_buffer
->state
.current_l3_config
= cfg
;
1048 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1050 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1052 /* Flushes are pipelined while invalidations are handled immediately.
1053 * Therefore, if we're flushing anything then we need to schedule a stall
1054 * before any invalidations can happen.
1056 if (bits
& ANV_PIPE_FLUSH_BITS
)
1057 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1059 /* If we're going to do an invalidate and we have a pending CS stall that
1060 * has yet to be resolved, we do the CS stall now.
1062 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1063 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1064 bits
|= ANV_PIPE_CS_STALL_BIT
;
1065 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1068 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1069 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1070 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1071 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1072 pipe
.RenderTargetCacheFlushEnable
=
1073 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1075 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1076 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1077 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1080 * According to the Broadwell documentation, any PIPE_CONTROL with the
1081 * "Command Streamer Stall" bit set must also have another bit set,
1082 * with five different options:
1084 * - Render Target Cache Flush
1085 * - Depth Cache Flush
1086 * - Stall at Pixel Scoreboard
1087 * - Post-Sync Operation
1091 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1092 * mesa and it seems to work fine. The choice is fairly arbitrary.
1094 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1095 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1096 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1097 pipe
.StallAtPixelScoreboard
= true;
1100 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1103 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1104 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1105 pipe
.StateCacheInvalidationEnable
=
1106 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1107 pipe
.ConstantCacheInvalidationEnable
=
1108 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1109 pipe
.VFCacheInvalidationEnable
=
1110 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1111 pipe
.TextureCacheInvalidationEnable
=
1112 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1113 pipe
.InstructionCacheInvalidateEnable
=
1114 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1117 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1120 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1123 void genX(CmdPipelineBarrier
)(
1124 VkCommandBuffer commandBuffer
,
1125 VkPipelineStageFlags srcStageMask
,
1126 VkPipelineStageFlags destStageMask
,
1128 uint32_t memoryBarrierCount
,
1129 const VkMemoryBarrier
* pMemoryBarriers
,
1130 uint32_t bufferMemoryBarrierCount
,
1131 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1132 uint32_t imageMemoryBarrierCount
,
1133 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1135 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1137 /* XXX: Right now, we're really dumb and just flush whatever categories
1138 * the app asks for. One of these days we may make this a bit better
1139 * but right now that's all the hardware allows for in most areas.
1141 VkAccessFlags src_flags
= 0;
1142 VkAccessFlags dst_flags
= 0;
1144 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1145 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1146 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1149 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1150 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1151 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1154 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1155 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1156 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1157 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1158 const VkImageSubresourceRange
*range
=
1159 &pImageMemoryBarriers
[i
].subresourceRange
;
1161 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1162 transition_depth_buffer(cmd_buffer
, image
,
1163 pImageMemoryBarriers
[i
].oldLayout
,
1164 pImageMemoryBarriers
[i
].newLayout
);
1165 } else if (range
->aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
) {
1166 transition_color_buffer(cmd_buffer
, image
,
1167 range
->baseMipLevel
,
1168 anv_get_levelCount(image
, range
),
1169 range
->baseArrayLayer
,
1170 anv_get_layerCount(image
, range
),
1171 pImageMemoryBarriers
[i
].oldLayout
,
1172 pImageMemoryBarriers
[i
].newLayout
);
1176 cmd_buffer
->state
.pending_pipe_bits
|=
1177 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1178 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1182 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1184 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
1186 /* In order to avoid thrash, we assume that vertex and fragment stages
1187 * always exist. In the rare case where one is missing *and* the other
1188 * uses push concstants, this may be suboptimal. However, avoiding stalls
1189 * seems more important.
1191 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1193 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1197 const unsigned push_constant_kb
= 32;
1198 #elif GEN_IS_HASWELL
1199 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1201 const unsigned push_constant_kb
= 16;
1204 const unsigned num_stages
=
1205 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1206 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1208 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1209 * units of 2KB. Incidentally, these are the same platforms that have
1210 * 32KB worth of push constant space.
1212 if (push_constant_kb
== 32)
1213 size_per_stage
&= ~1u;
1215 uint32_t kb_used
= 0;
1216 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1217 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1218 anv_batch_emit(&cmd_buffer
->batch
,
1219 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1220 alloc
._3DCommandSubOpcode
= 18 + i
;
1221 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1222 alloc
.ConstantBufferSize
= push_size
;
1224 kb_used
+= push_size
;
1227 anv_batch_emit(&cmd_buffer
->batch
,
1228 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1229 alloc
.ConstantBufferOffset
= kb_used
;
1230 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1233 cmd_buffer
->state
.push_constant_stages
= stages
;
1235 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1237 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1238 * the next 3DPRIMITIVE command after programming the
1239 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1241 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1242 * pipeline setup, we need to dirty push constants.
1244 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1248 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1249 gl_shader_stage stage
,
1250 struct anv_state
*bt_state
)
1252 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1253 struct anv_pipeline
*pipeline
;
1254 uint32_t bias
, state_offset
;
1257 case MESA_SHADER_COMPUTE
:
1258 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1262 pipeline
= cmd_buffer
->state
.pipeline
;
1267 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1268 *bt_state
= (struct anv_state
) { 0, };
1272 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1273 if (bias
+ map
->surface_count
== 0) {
1274 *bt_state
= (struct anv_state
) { 0, };
1278 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1279 bias
+ map
->surface_count
,
1281 uint32_t *bt_map
= bt_state
->map
;
1283 if (bt_state
->map
== NULL
)
1284 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1286 if (stage
== MESA_SHADER_COMPUTE
&&
1287 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
1288 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
1289 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
1291 struct anv_state surface_state
;
1293 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1295 const enum isl_format format
=
1296 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1297 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1298 format
, bo_offset
, 12, 1);
1300 bt_map
[0] = surface_state
.offset
+ state_offset
;
1301 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1304 if (map
->surface_count
== 0)
1307 if (map
->image_count
> 0) {
1309 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1310 if (result
!= VK_SUCCESS
)
1313 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1317 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1318 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1320 struct anv_state surface_state
;
1322 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1323 /* Color attachment binding */
1324 assert(stage
== MESA_SHADER_FRAGMENT
);
1325 assert(binding
->binding
== 0);
1326 if (binding
->index
< subpass
->color_count
) {
1327 const unsigned att
=
1328 subpass
->color_attachments
[binding
->index
].attachment
;
1330 /* From the Vulkan 1.0.46 spec:
1332 * "If any color or depth/stencil attachments are
1333 * VK_ATTACHMENT_UNUSED, then no writes occur for those
1336 if (att
== VK_ATTACHMENT_UNUSED
) {
1337 surface_state
= cmd_buffer
->state
.null_surface_state
;
1339 surface_state
= cmd_buffer
->state
.attachments
[att
].color_rt_state
;
1342 surface_state
= cmd_buffer
->state
.null_surface_state
;
1345 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1349 struct anv_descriptor_set
*set
=
1350 cmd_buffer
->state
.descriptors
[binding
->set
];
1351 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1352 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1354 switch (desc
->type
) {
1355 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1356 /* Nothing for us to do here */
1359 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1360 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
1361 surface_state
= desc
->aux_usage
== ISL_AUX_USAGE_NONE
?
1362 desc
->image_view
->no_aux_sampler_surface_state
:
1363 desc
->image_view
->sampler_surface_state
;
1364 assert(surface_state
.alloc_size
);
1365 add_image_relocs(cmd_buffer
, desc
->image_view
->image
,
1366 desc
->image_view
->aspect_mask
,
1367 desc
->aux_usage
, surface_state
);
1369 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1370 assert(stage
== MESA_SHADER_FRAGMENT
);
1371 if (desc
->image_view
->aspect_mask
!= VK_IMAGE_ASPECT_COLOR_BIT
) {
1372 /* For depth and stencil input attachments, we treat it like any
1373 * old texture that a user may have bound.
1375 surface_state
= desc
->aux_usage
== ISL_AUX_USAGE_NONE
?
1376 desc
->image_view
->no_aux_sampler_surface_state
:
1377 desc
->image_view
->sampler_surface_state
;
1378 assert(surface_state
.alloc_size
);
1379 add_image_relocs(cmd_buffer
, desc
->image_view
->image
,
1380 desc
->image_view
->aspect_mask
,
1381 desc
->aux_usage
, surface_state
);
1383 /* For color input attachments, we create the surface state at
1384 * vkBeginRenderPass time so that we can include aux and clear
1385 * color information.
1387 assert(binding
->input_attachment_index
< subpass
->input_count
);
1388 const unsigned subpass_att
= binding
->input_attachment_index
;
1389 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
1390 surface_state
= cmd_buffer
->state
.attachments
[att
].input_att_state
;
1394 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1395 surface_state
= (binding
->write_only
)
1396 ? desc
->image_view
->writeonly_storage_surface_state
1397 : desc
->image_view
->storage_surface_state
;
1398 assert(surface_state
.alloc_size
);
1399 add_image_relocs(cmd_buffer
, desc
->image_view
->image
,
1400 desc
->image_view
->aspect_mask
,
1401 desc
->image_view
->image
->aux_usage
, surface_state
);
1403 struct brw_image_param
*image_param
=
1404 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1406 *image_param
= desc
->image_view
->storage_image_param
;
1407 image_param
->surface_idx
= bias
+ s
;
1411 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
1412 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
1413 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
1414 surface_state
= desc
->buffer_view
->surface_state
;
1415 assert(surface_state
.alloc_size
);
1416 add_surface_state_reloc(cmd_buffer
, surface_state
,
1417 desc
->buffer_view
->bo
,
1418 desc
->buffer_view
->offset
);
1421 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
1422 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
1423 uint32_t dynamic_offset_idx
=
1424 pipeline
->layout
->set
[binding
->set
].dynamic_offset_start
+
1425 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1428 /* Compute the offset within the buffer */
1429 uint64_t offset
= desc
->offset
+
1430 cmd_buffer
->state
.dynamic_offsets
[dynamic_offset_idx
];
1431 /* Clamp to the buffer size */
1432 offset
= MIN2(offset
, desc
->buffer
->size
);
1433 /* Clamp the range to the buffer size */
1434 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
1437 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
1438 enum isl_format format
=
1439 anv_isl_format_for_descriptor_type(desc
->type
);
1441 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1442 format
, offset
, range
, 1);
1443 add_surface_state_reloc(cmd_buffer
, surface_state
,
1445 desc
->buffer
->offset
+ offset
);
1449 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
1450 surface_state
= (binding
->write_only
)
1451 ? desc
->buffer_view
->writeonly_storage_surface_state
1452 : desc
->buffer_view
->storage_surface_state
;
1453 assert(surface_state
.alloc_size
);
1454 add_surface_state_reloc(cmd_buffer
, surface_state
,
1455 desc
->buffer_view
->bo
,
1456 desc
->buffer_view
->offset
);
1458 struct brw_image_param
*image_param
=
1459 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1461 *image_param
= desc
->buffer_view
->storage_image_param
;
1462 image_param
->surface_idx
= bias
+ s
;
1466 assert(!"Invalid descriptor type");
1470 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1472 assert(image
== map
->image_count
);
1475 anv_state_flush(cmd_buffer
->device
, *bt_state
);
1481 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1482 gl_shader_stage stage
,
1483 struct anv_state
*state
)
1485 struct anv_pipeline
*pipeline
;
1487 if (stage
== MESA_SHADER_COMPUTE
)
1488 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1490 pipeline
= cmd_buffer
->state
.pipeline
;
1492 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1493 *state
= (struct anv_state
) { 0, };
1497 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1498 if (map
->sampler_count
== 0) {
1499 *state
= (struct anv_state
) { 0, };
1503 uint32_t size
= map
->sampler_count
* 16;
1504 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1506 if (state
->map
== NULL
)
1507 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1509 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1510 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1511 struct anv_descriptor_set
*set
=
1512 cmd_buffer
->state
.descriptors
[binding
->set
];
1513 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1514 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1516 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1517 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1520 struct anv_sampler
*sampler
= desc
->sampler
;
1522 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1523 * happens to be zero.
1525 if (sampler
== NULL
)
1528 memcpy(state
->map
+ (s
* 16),
1529 sampler
->state
, sizeof(sampler
->state
));
1532 anv_state_flush(cmd_buffer
->device
, *state
);
1538 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1540 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1541 cmd_buffer
->state
.pipeline
->active_stages
;
1543 VkResult result
= VK_SUCCESS
;
1544 anv_foreach_stage(s
, dirty
) {
1545 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1546 if (result
!= VK_SUCCESS
)
1548 result
= emit_binding_table(cmd_buffer
, s
,
1549 &cmd_buffer
->state
.binding_tables
[s
]);
1550 if (result
!= VK_SUCCESS
)
1554 if (result
!= VK_SUCCESS
) {
1555 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1557 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1558 if (result
!= VK_SUCCESS
)
1561 /* Re-emit state base addresses so we get the new surface state base
1562 * address before we start emitting binding tables etc.
1564 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1566 /* Re-emit all active binding tables */
1567 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
1568 anv_foreach_stage(s
, dirty
) {
1569 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1570 if (result
!= VK_SUCCESS
) {
1571 anv_batch_set_error(&cmd_buffer
->batch
, result
);
1574 result
= emit_binding_table(cmd_buffer
, s
,
1575 &cmd_buffer
->state
.binding_tables
[s
]);
1576 if (result
!= VK_SUCCESS
) {
1577 anv_batch_set_error(&cmd_buffer
->batch
, result
);
1583 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1589 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1592 static const uint32_t sampler_state_opcodes
[] = {
1593 [MESA_SHADER_VERTEX
] = 43,
1594 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1595 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1596 [MESA_SHADER_GEOMETRY
] = 46,
1597 [MESA_SHADER_FRAGMENT
] = 47,
1598 [MESA_SHADER_COMPUTE
] = 0,
1601 static const uint32_t binding_table_opcodes
[] = {
1602 [MESA_SHADER_VERTEX
] = 38,
1603 [MESA_SHADER_TESS_CTRL
] = 39,
1604 [MESA_SHADER_TESS_EVAL
] = 40,
1605 [MESA_SHADER_GEOMETRY
] = 41,
1606 [MESA_SHADER_FRAGMENT
] = 42,
1607 [MESA_SHADER_COMPUTE
] = 0,
1610 anv_foreach_stage(s
, stages
) {
1611 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1612 anv_batch_emit(&cmd_buffer
->batch
,
1613 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1614 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1615 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1619 /* Always emit binding table pointers if we're asked to, since on SKL
1620 * this is what flushes push constants. */
1621 anv_batch_emit(&cmd_buffer
->batch
,
1622 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1623 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1624 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1630 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1632 static const uint32_t push_constant_opcodes
[] = {
1633 [MESA_SHADER_VERTEX
] = 21,
1634 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1635 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1636 [MESA_SHADER_GEOMETRY
] = 22,
1637 [MESA_SHADER_FRAGMENT
] = 23,
1638 [MESA_SHADER_COMPUTE
] = 0,
1641 VkShaderStageFlags flushed
= 0;
1643 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
1644 if (stage
== MESA_SHADER_COMPUTE
)
1647 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1649 if (state
.offset
== 0) {
1650 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1651 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1653 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1654 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1655 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1657 .Buffer
[2] = { &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
, state
.offset
},
1658 .ReadLength
[2] = DIV_ROUND_UP(state
.alloc_size
, 32),
1660 .Buffer
[0] = { .offset
= state
.offset
},
1661 .ReadLength
[0] = DIV_ROUND_UP(state
.alloc_size
, 32),
1667 flushed
|= mesa_to_vk_shader_stage(stage
);
1670 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1676 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1678 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1681 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1683 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1685 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1687 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1690 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1691 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1693 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1694 GENX(3DSTATE_VERTEX_BUFFERS
));
1696 for_each_bit(vb
, vb_emit
) {
1697 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1698 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1700 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1701 .VertexBufferIndex
= vb
,
1704 .MemoryObjectControlState
= GENX(MOCS
),
1706 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1707 /* Our implementation of VK_KHR_multiview uses instancing to draw
1708 * the different views. If the client asks for instancing, we
1709 * need to use the Instance Data Step Rate to ensure that we
1710 * repeat the client's per-instance data once for each view.
1712 .InstanceDataStepRate
= anv_subpass_view_count(pipeline
->subpass
),
1713 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1716 .AddressModifyEnable
= true,
1717 .BufferPitch
= pipeline
->binding_stride
[vb
],
1718 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1721 .BufferSize
= buffer
->size
- offset
1723 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1727 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1732 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1734 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1735 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1737 /* The exact descriptor layout is pulled from the pipeline, so we need
1738 * to re-emit binding tables on every pipeline change.
1740 cmd_buffer
->state
.descriptors_dirty
|=
1741 cmd_buffer
->state
.pipeline
->active_stages
;
1743 /* If the pipeline changed, we may need to re-allocate push constant
1746 cmd_buffer_alloc_push_constants(cmd_buffer
);
1750 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1751 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1752 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1754 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1755 * stall needs to be sent just prior to any 3DSTATE_VS,
1756 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1757 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1758 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1759 * PIPE_CONTROL needs to be sent before any combination of VS
1760 * associated 3DSTATE."
1762 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1763 pc
.DepthStallEnable
= true;
1764 pc
.PostSyncOperation
= WriteImmediateData
;
1766 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1771 /* Render targets live in the same binding table as fragment descriptors */
1772 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1773 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1775 /* We emit the binding tables and sampler tables first, then emit push
1776 * constants and then finally emit binding table and sampler table
1777 * pointers. It has to happen in this order, since emitting the binding
1778 * tables may change the push constants (in case of storage images). After
1779 * emitting push constants, on SKL+ we have to emit the corresponding
1780 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1783 if (cmd_buffer
->state
.descriptors_dirty
)
1784 dirty
= flush_descriptor_sets(cmd_buffer
);
1786 if (cmd_buffer
->state
.push_constants_dirty
) {
1788 /* On Sky Lake and later, the binding table pointers commands are
1789 * what actually flush the changes to push constant state so we need
1790 * to dirty them so they get re-emitted below.
1792 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1794 cmd_buffer_flush_push_constants(cmd_buffer
);
1799 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1801 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1802 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1804 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1805 ANV_CMD_DIRTY_PIPELINE
)) {
1806 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1807 pipeline
->depth_clamp_enable
);
1810 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1811 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1813 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1815 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1819 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
1820 struct anv_bo
*bo
, uint32_t offset
,
1821 uint32_t size
, uint32_t index
)
1823 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1824 GENX(3DSTATE_VERTEX_BUFFERS
));
1826 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1827 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1828 .VertexBufferIndex
= index
,
1829 .AddressModifyEnable
= true,
1832 .MemoryObjectControlState
= GENX(MOCS
),
1833 .BufferStartingAddress
= { bo
, offset
},
1836 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1837 .BufferStartingAddress
= { bo
, offset
},
1838 .EndAddress
= { bo
, offset
+ size
},
1844 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1845 struct anv_bo
*bo
, uint32_t offset
)
1847 emit_vertex_bo(cmd_buffer
, bo
, offset
, 8, ANV_SVGS_VB_INDEX
);
1851 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1852 uint32_t base_vertex
, uint32_t base_instance
)
1854 struct anv_state id_state
=
1855 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1857 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1858 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1860 anv_state_flush(cmd_buffer
->device
, id_state
);
1862 emit_base_vertex_instance_bo(cmd_buffer
,
1863 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
, id_state
.offset
);
1867 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
1869 struct anv_state state
=
1870 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
1872 ((uint32_t *)state
.map
)[0] = draw_index
;
1874 anv_state_flush(cmd_buffer
->device
, state
);
1876 emit_vertex_bo(cmd_buffer
,
1877 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
1878 state
.offset
, 4, ANV_DRAWID_VB_INDEX
);
1882 VkCommandBuffer commandBuffer
,
1883 uint32_t vertexCount
,
1884 uint32_t instanceCount
,
1885 uint32_t firstVertex
,
1886 uint32_t firstInstance
)
1888 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1889 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1890 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1892 if (anv_batch_has_error(&cmd_buffer
->batch
))
1895 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1897 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1898 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1899 if (vs_prog_data
->uses_drawid
)
1900 emit_draw_index(cmd_buffer
, 0);
1902 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1903 * different views. We need to multiply instanceCount by the view count.
1905 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
1907 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1908 prim
.VertexAccessType
= SEQUENTIAL
;
1909 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1910 prim
.VertexCountPerInstance
= vertexCount
;
1911 prim
.StartVertexLocation
= firstVertex
;
1912 prim
.InstanceCount
= instanceCount
;
1913 prim
.StartInstanceLocation
= firstInstance
;
1914 prim
.BaseVertexLocation
= 0;
1918 void genX(CmdDrawIndexed
)(
1919 VkCommandBuffer commandBuffer
,
1920 uint32_t indexCount
,
1921 uint32_t instanceCount
,
1922 uint32_t firstIndex
,
1923 int32_t vertexOffset
,
1924 uint32_t firstInstance
)
1926 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1927 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1928 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1930 if (anv_batch_has_error(&cmd_buffer
->batch
))
1933 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1935 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1936 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1937 if (vs_prog_data
->uses_drawid
)
1938 emit_draw_index(cmd_buffer
, 0);
1940 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1941 * different views. We need to multiply instanceCount by the view count.
1943 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
1945 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1946 prim
.VertexAccessType
= RANDOM
;
1947 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1948 prim
.VertexCountPerInstance
= indexCount
;
1949 prim
.StartVertexLocation
= firstIndex
;
1950 prim
.InstanceCount
= instanceCount
;
1951 prim
.StartInstanceLocation
= firstInstance
;
1952 prim
.BaseVertexLocation
= vertexOffset
;
1956 /* Auto-Draw / Indirect Registers */
1957 #define GEN7_3DPRIM_END_OFFSET 0x2420
1958 #define GEN7_3DPRIM_START_VERTEX 0x2430
1959 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1960 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1961 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1962 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1964 /* MI_MATH only exists on Haswell+ */
1965 #if GEN_IS_HASWELL || GEN_GEN >= 8
1968 mi_alu(uint32_t opcode
, uint32_t op1
, uint32_t op2
)
1970 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
1971 .ALUOpcode
= opcode
,
1977 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
1982 #define CS_GPR(n) (0x2600 + (n) * 8)
1984 /* Emit dwords to multiply GPR0 by N */
1986 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
1988 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
1990 #define append_alu(opcode, operand1, operand2) \
1991 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
1994 unsigned top_bit
= 31 - __builtin_clz(N
);
1995 for (int i
= top_bit
- 1; i
>= 0; i
--) {
1996 /* We get our initial data in GPR0 and we write the final data out to
1997 * GPR0 but we use GPR1 as our scratch register.
1999 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2000 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2002 /* Shift the current value left by 1 */
2003 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2004 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2005 append_alu(MI_ALU_ADD
, 0, 0);
2008 /* Store ACCU to R1 and add R0 to R1 */
2009 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2010 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2011 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2012 append_alu(MI_ALU_ADD
, 0, 0);
2015 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2022 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2024 uint32_t num_dwords
;
2025 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2027 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2028 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2031 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2034 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2035 struct anv_buffer
*buffer
, uint64_t offset
,
2038 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2039 struct anv_bo
*bo
= buffer
->bo
;
2040 uint32_t bo_offset
= buffer
->offset
+ offset
;
2042 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
2044 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2045 if (view_count
> 1) {
2046 #if GEN_IS_HASWELL || GEN_GEN >= 8
2047 emit_lrm(batch
, CS_GPR(0), bo
, bo_offset
+ 4);
2048 emit_mul_gpr0(batch
, view_count
);
2049 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2051 anv_finishme("Multiview + indirect draw requires MI_MATH\n"
2052 "MI_MATH is not supported on Ivy Bridge");
2053 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2056 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2059 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
2062 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
2063 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
2065 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
2066 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2070 void genX(CmdDrawIndirect
)(
2071 VkCommandBuffer commandBuffer
,
2073 VkDeviceSize offset
,
2077 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2078 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2079 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2080 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2082 if (anv_batch_has_error(&cmd_buffer
->batch
))
2085 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2087 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2088 struct anv_bo
*bo
= buffer
->bo
;
2089 uint32_t bo_offset
= buffer
->offset
+ offset
;
2091 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2092 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
2093 if (vs_prog_data
->uses_drawid
)
2094 emit_draw_index(cmd_buffer
, i
);
2096 load_indirect_parameters(cmd_buffer
, buffer
, offset
, false);
2098 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2099 prim
.IndirectParameterEnable
= true;
2100 prim
.VertexAccessType
= SEQUENTIAL
;
2101 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2108 void genX(CmdDrawIndexedIndirect
)(
2109 VkCommandBuffer commandBuffer
,
2111 VkDeviceSize offset
,
2115 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2116 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2117 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2118 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2120 if (anv_batch_has_error(&cmd_buffer
->batch
))
2123 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2125 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2126 struct anv_bo
*bo
= buffer
->bo
;
2127 uint32_t bo_offset
= buffer
->offset
+ offset
;
2129 /* TODO: We need to stomp base vertex to 0 somehow */
2130 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2131 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
2132 if (vs_prog_data
->uses_drawid
)
2133 emit_draw_index(cmd_buffer
, i
);
2135 load_indirect_parameters(cmd_buffer
, buffer
, offset
, true);
2137 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2138 prim
.IndirectParameterEnable
= true;
2139 prim
.VertexAccessType
= RANDOM
;
2140 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2148 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2150 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2151 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2154 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2155 if (result
!= VK_SUCCESS
) {
2156 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2158 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2159 if (result
!= VK_SUCCESS
)
2162 /* Re-emit state base addresses so we get the new surface state base
2163 * address before we start emitting binding tables etc.
2165 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2167 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2168 if (result
!= VK_SUCCESS
) {
2169 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2174 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
2175 if (result
!= VK_SUCCESS
) {
2176 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2180 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
2181 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2182 .BindingTablePointer
= surfaces
.offset
,
2183 .SamplerStatePointer
= samplers
.offset
,
2185 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
2187 struct anv_state state
=
2188 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
2189 pipeline
->interface_descriptor_data
,
2190 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
2193 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
2194 anv_batch_emit(&cmd_buffer
->batch
,
2195 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
2196 mid
.InterfaceDescriptorTotalLength
= size
;
2197 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
2204 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2206 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2207 MAYBE_UNUSED VkResult result
;
2209 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
2211 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2213 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
2215 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2216 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
2218 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
2219 * the only bits that are changed are scoreboard related: Scoreboard
2220 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
2221 * these scoreboard related states, a MEDIA_STATE_FLUSH is
2224 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2225 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2227 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2230 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
2231 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
2232 /* FIXME: figure out descriptors for gen7 */
2233 result
= flush_compute_descriptor_set(cmd_buffer
);
2234 if (result
!= VK_SUCCESS
)
2237 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
2240 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
2241 struct anv_state push_state
=
2242 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
2244 if (push_state
.alloc_size
) {
2245 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
2246 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
2247 curbe
.CURBEDataStartAddress
= push_state
.offset
;
2252 cmd_buffer
->state
.compute_dirty
= 0;
2254 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2260 verify_cmd_parser(const struct anv_device
*device
,
2261 int required_version
,
2262 const char *function
)
2264 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
2265 return vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
2266 "cmd parser version %d is required for %s",
2267 required_version
, function
);
2275 void genX(CmdDispatch
)(
2276 VkCommandBuffer commandBuffer
,
2281 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2282 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2283 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
2285 if (anv_batch_has_error(&cmd_buffer
->batch
))
2288 if (prog_data
->uses_num_work_groups
) {
2289 struct anv_state state
=
2290 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
2291 uint32_t *sizes
= state
.map
;
2295 anv_state_flush(cmd_buffer
->device
, state
);
2296 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
2297 cmd_buffer
->state
.num_workgroups_bo
=
2298 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
;
2301 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2303 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
2304 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2305 ggw
.ThreadDepthCounterMaximum
= 0;
2306 ggw
.ThreadHeightCounterMaximum
= 0;
2307 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2308 ggw
.ThreadGroupIDXDimension
= x
;
2309 ggw
.ThreadGroupIDYDimension
= y
;
2310 ggw
.ThreadGroupIDZDimension
= z
;
2311 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2312 ggw
.BottomExecutionMask
= 0xffffffff;
2315 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2318 #define GPGPU_DISPATCHDIMX 0x2500
2319 #define GPGPU_DISPATCHDIMY 0x2504
2320 #define GPGPU_DISPATCHDIMZ 0x2508
2322 #define MI_PREDICATE_SRC0 0x2400
2323 #define MI_PREDICATE_SRC1 0x2408
2325 void genX(CmdDispatchIndirect
)(
2326 VkCommandBuffer commandBuffer
,
2328 VkDeviceSize offset
)
2330 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2331 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2332 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2333 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
2334 struct anv_bo
*bo
= buffer
->bo
;
2335 uint32_t bo_offset
= buffer
->offset
+ offset
;
2336 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2339 /* Linux 4.4 added command parser version 5 which allows the GPGPU
2340 * indirect dispatch registers to be written.
2342 if (verify_cmd_parser(cmd_buffer
->device
, 5,
2343 "vkCmdDispatchIndirect") != VK_SUCCESS
)
2347 if (prog_data
->uses_num_work_groups
) {
2348 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
2349 cmd_buffer
->state
.num_workgroups_bo
= bo
;
2352 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2354 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
2355 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
2356 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
2359 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
2360 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
2361 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
2362 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
2364 /* Load compute_dispatch_indirect_x_size into SRC0 */
2365 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
2367 /* predicate = (compute_dispatch_indirect_x_size == 0); */
2368 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2369 mip
.LoadOperation
= LOAD_LOAD
;
2370 mip
.CombineOperation
= COMBINE_SET
;
2371 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2374 /* Load compute_dispatch_indirect_y_size into SRC0 */
2375 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
2377 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
2378 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2379 mip
.LoadOperation
= LOAD_LOAD
;
2380 mip
.CombineOperation
= COMBINE_OR
;
2381 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2384 /* Load compute_dispatch_indirect_z_size into SRC0 */
2385 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
2387 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
2388 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2389 mip
.LoadOperation
= LOAD_LOAD
;
2390 mip
.CombineOperation
= COMBINE_OR
;
2391 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2394 /* predicate = !predicate; */
2395 #define COMPARE_FALSE 1
2396 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2397 mip
.LoadOperation
= LOAD_LOADINV
;
2398 mip
.CombineOperation
= COMBINE_OR
;
2399 mip
.CompareOperation
= COMPARE_FALSE
;
2403 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
2404 ggw
.IndirectParameterEnable
= true;
2405 ggw
.PredicateEnable
= GEN_GEN
<= 7;
2406 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2407 ggw
.ThreadDepthCounterMaximum
= 0;
2408 ggw
.ThreadHeightCounterMaximum
= 0;
2409 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2410 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2411 ggw
.BottomExecutionMask
= 0xffffffff;
2414 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2418 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
2421 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
2424 #if GEN_GEN >= 8 && GEN_GEN < 10
2425 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
2427 * Software must clear the COLOR_CALC_STATE Valid field in
2428 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
2429 * with Pipeline Select set to GPGPU.
2431 * The internal hardware docs recommend the same workaround for Gen9
2434 if (pipeline
== GPGPU
)
2435 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
2438 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
2439 * PIPELINE_SELECT [DevBWR+]":
2443 * Software must ensure all the write caches are flushed through a
2444 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
2445 * command to invalidate read only caches prior to programming
2446 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
2448 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2449 pc
.RenderTargetCacheFlushEnable
= true;
2450 pc
.DepthCacheFlushEnable
= true;
2451 pc
.DCFlushEnable
= true;
2452 pc
.PostSyncOperation
= NoWrite
;
2453 pc
.CommandStreamerStallEnable
= true;
2456 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2457 pc
.TextureCacheInvalidationEnable
= true;
2458 pc
.ConstantCacheInvalidationEnable
= true;
2459 pc
.StateCacheInvalidationEnable
= true;
2460 pc
.InstructionCacheInvalidateEnable
= true;
2461 pc
.PostSyncOperation
= NoWrite
;
2464 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2468 ps
.PipelineSelection
= pipeline
;
2471 cmd_buffer
->state
.current_pipeline
= pipeline
;
2475 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
2477 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
2481 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
2483 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
2487 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
2492 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
2494 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
2495 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
2496 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
2497 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
2498 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
2499 * Depth Flush Bit set, followed by another pipelined depth stall
2500 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
2501 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
2502 * via a preceding MI_FLUSH)."
2504 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2505 pipe
.DepthStallEnable
= true;
2507 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2508 pipe
.DepthCacheFlushEnable
= true;
2510 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2511 pipe
.DepthStallEnable
= true;
2516 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
2518 struct anv_device
*device
= cmd_buffer
->device
;
2519 const struct anv_image_view
*iview
=
2520 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2521 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
2523 /* FIXME: Width and Height are wrong */
2525 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
2527 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
2528 device
->isl_dev
.ds
.size
/ 4);
2532 struct isl_depth_stencil_hiz_emit_info info
= {
2533 .mocs
= device
->default_mocs
,
2537 info
.view
= &iview
->isl
;
2539 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
2540 info
.depth_surf
= &image
->depth_surface
.isl
;
2542 info
.depth_address
=
2543 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2544 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
2546 image
->offset
+ image
->depth_surface
.offset
);
2549 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.attachment
;
2550 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
2551 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
2552 info
.hiz_surf
= &image
->aux_surface
.isl
;
2555 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2556 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
2558 image
->offset
+ image
->aux_surface
.offset
);
2560 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
2564 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
2565 info
.stencil_surf
= &image
->stencil_surface
.isl
;
2567 info
.stencil_address
=
2568 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2569 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
2571 image
->offset
+ image
->stencil_surface
.offset
);
2574 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
2576 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
2581 * @brief Perform any layout transitions required at the beginning and/or end
2582 * of the current subpass for depth buffers.
2584 * TODO: Consider preprocessing the attachment reference array at render pass
2585 * create time to determine if no layout transition is needed at the
2586 * beginning and/or end of each subpass.
2588 * @param cmd_buffer The command buffer the transition is happening within.
2589 * @param subpass_end If true, marks that the transition is happening at the
2590 * end of the subpass.
2593 cmd_buffer_subpass_transition_layouts(struct anv_cmd_buffer
* const cmd_buffer
,
2594 const bool subpass_end
)
2596 /* We need a non-NULL command buffer. */
2599 const struct anv_cmd_state
* const cmd_state
= &cmd_buffer
->state
;
2600 const struct anv_subpass
* const subpass
= cmd_state
->subpass
;
2602 /* This function must be called within a subpass. */
2605 /* If there are attachment references, the array shouldn't be NULL.
2607 if (subpass
->attachment_count
> 0)
2608 assert(subpass
->attachments
);
2610 /* Iterate over the array of attachment references. */
2611 for (const VkAttachmentReference
*att_ref
= subpass
->attachments
;
2612 att_ref
< subpass
->attachments
+ subpass
->attachment_count
; att_ref
++) {
2614 /* If the attachment is unused, we can't perform a layout transition. */
2615 if (att_ref
->attachment
== VK_ATTACHMENT_UNUSED
)
2618 /* This attachment index shouldn't go out of bounds. */
2619 assert(att_ref
->attachment
< cmd_state
->pass
->attachment_count
);
2621 const struct anv_render_pass_attachment
* const att_desc
=
2622 &cmd_state
->pass
->attachments
[att_ref
->attachment
];
2623 struct anv_attachment_state
* const att_state
=
2624 &cmd_buffer
->state
.attachments
[att_ref
->attachment
];
2626 /* The attachment should not be used in a subpass after its last. */
2627 assert(att_desc
->last_subpass_idx
>= anv_get_subpass_id(cmd_state
));
2629 if (subpass_end
&& anv_get_subpass_id(cmd_state
) <
2630 att_desc
->last_subpass_idx
) {
2631 /* We're calling this function on a buffer twice in one subpass and
2632 * this is not the last use of the buffer. The layout should not have
2633 * changed from the first call and no transition is necessary.
2635 assert(att_ref
->layout
== att_state
->current_layout
);
2639 /* Get the appropriate target layout for this attachment. */
2640 const VkImageLayout target_layout
= subpass_end
?
2641 att_desc
->final_layout
: att_ref
->layout
;
2643 /* The attachment index must be less than the number of attachments
2644 * within the framebuffer.
2646 assert(att_ref
->attachment
< cmd_state
->framebuffer
->attachment_count
);
2648 const struct anv_image_view
* const iview
=
2649 cmd_state
->framebuffer
->attachments
[att_ref
->attachment
];
2650 const struct anv_image
* const image
= iview
->image
;
2652 /* Perform the layout transition. */
2653 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
2654 transition_depth_buffer(cmd_buffer
, image
,
2655 att_state
->current_layout
, target_layout
);
2656 att_state
->aux_usage
=
2657 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
2658 image
->aspects
, target_layout
);
2659 } else if (image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2660 transition_color_buffer(cmd_buffer
, image
,
2661 iview
->isl
.base_level
, 1,
2662 iview
->isl
.base_array_layer
,
2663 iview
->isl
.array_len
,
2664 att_state
->current_layout
, target_layout
);
2667 att_state
->current_layout
= target_layout
;
2671 /* Update the clear value dword(s) in surface state objects or the fast clear
2672 * state buffer entry for the color attachments used in this subpass.
2675 cmd_buffer_subpass_sync_fast_clear_values(struct anv_cmd_buffer
*cmd_buffer
)
2677 assert(cmd_buffer
&& cmd_buffer
->state
.subpass
);
2679 const struct anv_cmd_state
*state
= &cmd_buffer
->state
;
2681 /* Iterate through every color attachment used in this subpass. */
2682 for (uint32_t i
= 0; i
< state
->subpass
->color_count
; ++i
) {
2684 /* The attachment should be one of the attachments described in the
2685 * render pass and used in the subpass.
2687 const uint32_t a
= state
->subpass
->color_attachments
[i
].attachment
;
2688 assert(a
< state
->pass
->attachment_count
);
2689 if (a
== VK_ATTACHMENT_UNUSED
)
2692 /* Store some information regarding this attachment. */
2693 const struct anv_attachment_state
*att_state
= &state
->attachments
[a
];
2694 const struct anv_image_view
*iview
= state
->framebuffer
->attachments
[a
];
2695 const struct anv_render_pass_attachment
*rp_att
=
2696 &state
->pass
->attachments
[a
];
2698 if (att_state
->aux_usage
== ISL_AUX_USAGE_NONE
)
2701 /* The fast clear state entry must be updated if a fast clear is going to
2702 * happen. The surface state must be updated if the clear value from a
2703 * prior fast clear may be needed.
2705 if (att_state
->pending_clear_aspects
&& att_state
->fast_clear
) {
2706 /* Update the fast clear state entry. */
2707 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color_rt_state
,
2708 iview
->image
, iview
->isl
.base_level
,
2709 true /* copy from ss */);
2710 } else if (rp_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
2711 /* The attachment may have been fast-cleared in a previous render
2712 * pass and the value is needed now. Update the surface state(s).
2714 * TODO: Do this only once per render pass instead of every subpass.
2716 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color_rt_state
,
2717 iview
->image
, iview
->isl
.base_level
,
2718 false /* copy to ss */);
2720 if (need_input_attachment_state(rp_att
) &&
2721 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
2722 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input_att_state
,
2723 iview
->image
, iview
->isl
.base_level
,
2724 false /* copy to ss */);
2732 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
2733 struct anv_subpass
*subpass
)
2735 cmd_buffer
->state
.subpass
= subpass
;
2737 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
2739 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2740 * different views. If the client asks for instancing, we need to use the
2741 * Instance Data Step Rate to ensure that we repeat the client's
2742 * per-instance data once for each view. Since this bit is in
2743 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
2747 cmd_buffer
->state
.vb_dirty
|= ~0;
2749 /* Perform transitions to the subpass layout before any writes have
2752 cmd_buffer_subpass_transition_layouts(cmd_buffer
, false);
2754 /* Update clear values *after* performing automatic layout transitions.
2755 * This ensures that transitions from the UNDEFINED layout have had a chance
2756 * to populate the clear value buffer with the correct values for the
2757 * LOAD_OP_LOAD loadOp and that the fast-clears will update the buffer
2758 * without the aforementioned layout transition overwriting the fast-clear
2761 cmd_buffer_subpass_sync_fast_clear_values(cmd_buffer
);
2763 cmd_buffer_emit_depth_stencil(cmd_buffer
);
2765 anv_cmd_buffer_clear_subpass(cmd_buffer
);
2768 void genX(CmdBeginRenderPass
)(
2769 VkCommandBuffer commandBuffer
,
2770 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2771 VkSubpassContents contents
)
2773 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2774 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2775 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2777 cmd_buffer
->state
.framebuffer
= framebuffer
;
2778 cmd_buffer
->state
.pass
= pass
;
2779 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2781 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
2783 /* If we failed to setup the attachments we should not try to go further */
2784 if (result
!= VK_SUCCESS
) {
2785 assert(anv_batch_has_error(&cmd_buffer
->batch
));
2789 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2791 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
2793 cmd_buffer
->state
.pending_pipe_bits
|=
2794 cmd_buffer
->state
.pass
->subpass_flushes
[0];
2797 void genX(CmdNextSubpass
)(
2798 VkCommandBuffer commandBuffer
,
2799 VkSubpassContents contents
)
2801 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2803 if (anv_batch_has_error(&cmd_buffer
->batch
))
2806 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2808 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2810 /* Perform transitions to the final layout after all writes have occurred.
2812 cmd_buffer_subpass_transition_layouts(cmd_buffer
, true);
2814 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
2816 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
2817 cmd_buffer
->state
.pending_pipe_bits
|=
2818 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
2821 void genX(CmdEndRenderPass
)(
2822 VkCommandBuffer commandBuffer
)
2824 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2826 if (anv_batch_has_error(&cmd_buffer
->batch
))
2829 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2831 /* Perform transitions to the final layout after all writes have occurred.
2833 cmd_buffer_subpass_transition_layouts(cmd_buffer
, true);
2835 cmd_buffer
->state
.pending_pipe_bits
|=
2836 cmd_buffer
->state
.pass
->subpass_flushes
[cmd_buffer
->state
.pass
->subpass_count
];
2838 cmd_buffer
->state
.hiz_enabled
= false;
2841 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
2844 /* Remove references to render pass specific state. This enables us to
2845 * detect whether or not we're in a renderpass.
2847 cmd_buffer
->state
.framebuffer
= NULL
;
2848 cmd_buffer
->state
.pass
= NULL
;
2849 cmd_buffer
->state
.subpass
= NULL
;