projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
anv: Set framebuffer to NULL in secondary command buffers
[mesa.git] / src / intel / vulkan / genX_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26
27 #include "anv_private.h"
28 #include "vk_format_info.h"
29
30 #include "common/gen_l3_config.h"
31 #include "genxml/gen_macros.h"
32 #include "genxml/genX_pack.h"
33
34 static void
35 emit_lrm(struct anv_batch *batch,
36 uint32_t reg, struct anv_bo *bo, uint32_t offset)
37 {
38 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
39 lrm.RegisterAddress = reg;
40 lrm.MemoryAddress = (struct anv_address) { bo, offset };
41 }
42 }
43
44 static void
45 emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
46 {
47 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
48 lri.RegisterOffset = reg;
49 lri.DataDWord = imm;
50 }
51 }
52
53 void
54 genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
55 {
56 struct anv_device *device = cmd_buffer->device;
57
58 /* XXX: Do we need this on more than just BDW? */
59 #if (GEN_GEN >= 8)
60 /* Emit a render target cache flush.
61 *
62 * This isn't documented anywhere in the PRM. However, it seems to be
63 * necessary prior to changing the surface state base adress. Without
64 * this, we get GPU hangs when using multi-level command buffers which
65 * clear depth, reset state base address, and then go render stuff.
66 */
67 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
68 pc.RenderTargetCacheFlushEnable = true;
69 }
70 #endif
71
72 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
73 sba.GeneralStateBaseAddress = (struct anv_address) { NULL, 0 };
74 sba.GeneralStateMemoryObjectControlState = GENX(MOCS);
75 sba.GeneralStateBaseAddressModifyEnable = true;
76
77 sba.SurfaceStateBaseAddress =
78 anv_cmd_buffer_surface_base_address(cmd_buffer);
79 sba.SurfaceStateMemoryObjectControlState = GENX(MOCS);
80 sba.SurfaceStateBaseAddressModifyEnable = true;
81
82 sba.DynamicStateBaseAddress =
83 (struct anv_address) { &device->dynamic_state_block_pool.bo, 0 };
84 sba.DynamicStateMemoryObjectControlState = GENX(MOCS);
85 sba.DynamicStateBaseAddressModifyEnable = true;
86
87 sba.IndirectObjectBaseAddress = (struct anv_address) { NULL, 0 };
88 sba.IndirectObjectMemoryObjectControlState = GENX(MOCS);
89 sba.IndirectObjectBaseAddressModifyEnable = true;
90
91 sba.InstructionBaseAddress =
92 (struct anv_address) { &device->instruction_block_pool.bo, 0 };
93 sba.InstructionMemoryObjectControlState = GENX(MOCS);
94 sba.InstructionBaseAddressModifyEnable = true;
95
96 # if (GEN_GEN >= 8)
97 /* Broadwell requires that we specify a buffer size for a bunch of
98 * these fields. However, since we will be growing the BO's live, we
99 * just set them all to the maximum.
100 */
101 sba.GeneralStateBufferSize = 0xfffff;
102 sba.GeneralStateBufferSizeModifyEnable = true;
103 sba.DynamicStateBufferSize = 0xfffff;
104 sba.DynamicStateBufferSizeModifyEnable = true;
105 sba.IndirectObjectBufferSize = 0xfffff;
106 sba.IndirectObjectBufferSizeModifyEnable = true;
107 sba.InstructionBufferSize = 0xfffff;
108 sba.InstructionBuffersizeModifyEnable = true;
109 # endif
110 }
111
112 /* After re-setting the surface state base address, we have to do some
113 * cache flusing so that the sampler engine will pick up the new
114 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
115 * Shared Function > 3D Sampler > State > State Caching (page 96):
116 *
117 * Coherency with system memory in the state cache, like the texture
118 * cache is handled partially by software. It is expected that the
119 * command stream or shader will issue Cache Flush operation or
120 * Cache_Flush sampler message to ensure that the L1 cache remains
121 * coherent with system memory.
122 *
123 * [...]
124 *
125 * Whenever the value of the Dynamic_State_Base_Addr,
126 * Surface_State_Base_Addr are altered, the L1 state cache must be
127 * invalidated to ensure the new surface or sampler state is fetched
128 * from system memory.
129 *
130 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
131 * which, according the PIPE_CONTROL instruction documentation in the
132 * Broadwell PRM:
133 *
134 * Setting this bit is independent of any other bit in this packet.
135 * This bit controls the invalidation of the L1 and L2 state caches
136 * at the top of the pipe i.e. at the parsing time.
137 *
138 * Unfortunately, experimentation seems to indicate that state cache
139 * invalidation through a PIPE_CONTROL does nothing whatsoever in
140 * regards to surface state and binding tables. In stead, it seems that
141 * invalidating the texture cache is what is actually needed.
142 *
143 * XXX: As far as we have been able to determine through
144 * experimentation, shows that flush the texture cache appears to be
145 * sufficient. The theory here is that all of the sampling/rendering
146 * units cache the binding table in the texture cache. However, we have
147 * yet to be able to actually confirm this.
148 */
149 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
150 pc.TextureCacheInvalidationEnable = true;
151 }
152 }
153
154 /**
155 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
156 */
157 static void
158 genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer *cmd_buffer,
159 struct anv_render_pass *pass,
160 struct anv_framebuffer *framebuffer,
161 const VkClearValue *clear_values)
162 {
163 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
164 struct anv_cmd_state *state = &cmd_buffer->state;
165
166 vk_free(&cmd_buffer->pool->alloc, state->attachments);
167
168 if (pass->attachment_count == 0) {
169 state->attachments = NULL;
170 return;
171 }
172
173 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
174 pass->attachment_count *
175 sizeof(state->attachments[0]),
176 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
177 if (state->attachments == NULL) {
178 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
179 abort();
180 }
181
182 bool need_null_state = false;
183 for (uint32_t s = 0; s < pass->subpass_count; ++s) {
184 if (pass->subpasses[s].color_count == 0) {
185 need_null_state = true;
186 break;
187 }
188 }
189
190 unsigned num_states = need_null_state;
191 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
192 if (vk_format_is_color(pass->attachments[i].format))
193 num_states++;
194 }
195
196 const uint32_t ss_stride = align_u32(isl_dev->ss.size, isl_dev->ss.align);
197 state->render_pass_states =
198 anv_state_stream_alloc(&cmd_buffer->surface_state_stream,
199 num_states * ss_stride, isl_dev->ss.align);
200
201 struct anv_state next_state = state->render_pass_states;
202 next_state.alloc_size = isl_dev->ss.size;
203
204 if (need_null_state) {
205 state->null_surface_state = next_state;
206 next_state.offset += ss_stride;
207 next_state.map += ss_stride;
208 }
209
210 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
211 if (vk_format_is_color(pass->attachments[i].format)) {
212 state->attachments[i].color_rt_state = next_state;
213 next_state.offset += ss_stride;
214 next_state.map += ss_stride;
215 }
216 }
217 assert(next_state.offset == state->render_pass_states.offset +
218 state->render_pass_states.alloc_size);
219
220 if (framebuffer) {
221 assert(pass->attachment_count == framebuffer->attachment_count);
222
223 if (need_null_state) {
224 struct GENX(RENDER_SURFACE_STATE) null_ss = {
225 .SurfaceType = SURFTYPE_NULL,
226 .SurfaceArray = framebuffer->layers > 0,
227 .SurfaceFormat = ISL_FORMAT_R8G8B8A8_UNORM,
228 #if GEN_GEN >= 8
229 .TileMode = YMAJOR,
230 #else
231 .TiledSurface = true,
232 #endif
233 .Width = framebuffer->width - 1,
234 .Height = framebuffer->height - 1,
235 .Depth = framebuffer->layers - 1,
236 .RenderTargetViewExtent = framebuffer->layers - 1,
237 };
238 GENX(RENDER_SURFACE_STATE_pack)(NULL, state->null_surface_state.map,
239 &null_ss);
240 }
241
242 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
243 struct anv_render_pass_attachment *att = &pass->attachments[i];
244 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
245 VkImageAspectFlags clear_aspects = 0;
246
247 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
248 /* color attachment */
249 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
250 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
251 }
252 } else {
253 /* depthstencil attachment */
254 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
255 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
256 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
257 }
258 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
259 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
260 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
261 }
262 }
263
264 state->attachments[i].pending_clear_aspects = clear_aspects;
265 if (clear_aspects)
266 state->attachments[i].clear_value = clear_values[i];
267
268 struct anv_image_view *iview = framebuffer->attachments[i];
269 assert(iview->vk_format == att->format);
270
271 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
272 struct isl_view view = iview->isl;
273 view.usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
274 isl_surf_fill_state(isl_dev,
275 state->attachments[i].color_rt_state.map,
276 .surf = &iview->image->color_surface.isl,
277 .view = &view,
278 .mocs = cmd_buffer->device->default_mocs);
279
280 anv_cmd_buffer_add_surface_state_reloc(cmd_buffer,
281 state->attachments[i].color_rt_state, iview->bo, iview->offset);
282 }
283 }
284
285 if (!cmd_buffer->device->info.has_llc)
286 anv_state_clflush(state->render_pass_states);
287 }
288 }
289
290 VkResult
291 genX(BeginCommandBuffer)(
292 VkCommandBuffer commandBuffer,
293 const VkCommandBufferBeginInfo* pBeginInfo)
294 {
295 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
296
297 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
298 * command buffer's state. Otherwise, we must *reset* its state. In both
299 * cases we reset it.
300 *
301 * From the Vulkan 1.0 spec:
302 *
303 * If a command buffer is in the executable state and the command buffer
304 * was allocated from a command pool with the
305 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
306 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
307 * as if vkResetCommandBuffer had been called with
308 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
309 * the command buffer in the recording state.
310 */
311 anv_cmd_buffer_reset(cmd_buffer);
312
313 cmd_buffer->usage_flags = pBeginInfo->flags;
314
315 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY ||
316 !(cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT));
317
318 genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
319
320 if (cmd_buffer->usage_flags &
321 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
322 cmd_buffer->state.pass =
323 anv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
324 cmd_buffer->state.subpass =
325 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
326 cmd_buffer->state.framebuffer = NULL;
327
328 genX(cmd_buffer_setup_attachments)(cmd_buffer, cmd_buffer->state.pass,
329 NULL, NULL);
330
331 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
332 }
333
334 return VK_SUCCESS;
335 }
336
337 VkResult
338 genX(EndCommandBuffer)(
339 VkCommandBuffer commandBuffer)
340 {
341 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
342
343 anv_cmd_buffer_end_batch_buffer(cmd_buffer);
344
345 return VK_SUCCESS;
346 }
347
348 void
349 genX(CmdExecuteCommands)(
350 VkCommandBuffer commandBuffer,
351 uint32_t commandBufferCount,
352 const VkCommandBuffer* pCmdBuffers)
353 {
354 ANV_FROM_HANDLE(anv_cmd_buffer, primary, commandBuffer);
355
356 assert(primary->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
357
358 for (uint32_t i = 0; i < commandBufferCount; i++) {
359 ANV_FROM_HANDLE(anv_cmd_buffer, secondary, pCmdBuffers[i]);
360
361 assert(secondary->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY);
362
363 if (secondary->usage_flags &
364 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
365 /* If we're continuing a render pass from the primary, we need to
366 * copy the surface states for the current subpass into the storage
367 * we allocated for them in BeginCommandBuffer.
368 */
369 struct anv_bo *ss_bo = &primary->device->surface_state_block_pool.bo;
370 struct anv_state src_state = primary->state.render_pass_states;
371 struct anv_state dst_state = secondary->state.render_pass_states;
372 assert(src_state.alloc_size == dst_state.alloc_size);
373
374 genX(cmd_buffer_gpu_memcpy)(primary, ss_bo, dst_state.offset,
375 ss_bo, src_state.offset,
376 src_state.alloc_size);
377 }
378
379 anv_cmd_buffer_add_secondary(primary, secondary);
380 }
381
382 /* Each of the secondary command buffers will use its own state base
383 * address. We need to re-emit state base address for the primary after
384 * all of the secondaries are done.
385 *
386 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
387 * address calls?
388 */
389 genX(cmd_buffer_emit_state_base_address)(primary);
390 }
391
392 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
393 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
394 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
395
396 /**
397 * Program the hardware to use the specified L3 configuration.
398 */
399 void
400 genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
401 const struct gen_l3_config *cfg)
402 {
403 assert(cfg);
404 if (cfg == cmd_buffer->state.current_l3_config)
405 return;
406
407 if (unlikely(INTEL_DEBUG & DEBUG_L3)) {
408 fprintf(stderr, "L3 config transition: ");
409 gen_dump_l3_config(cfg, stderr);
410 }
411
412 const bool has_slm = cfg->n[GEN_L3P_SLM];
413
414 /* According to the hardware docs, the L3 partitioning can only be changed
415 * while the pipeline is completely drained and the caches are flushed,
416 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
417 */
418 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
419 pc.DCFlushEnable = true;
420 pc.PostSyncOperation = NoWrite;
421 pc.CommandStreamerStallEnable = true;
422 }
423
424 /* ...followed by a second pipelined PIPE_CONTROL that initiates
425 * invalidation of the relevant caches. Note that because RO invalidation
426 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
427 * command is processed by the CS) we cannot combine it with the previous
428 * stalling flush as the hardware documentation suggests, because that
429 * would cause the CS to stall on previous rendering *after* RO
430 * invalidation and wouldn't prevent the RO caches from being polluted by
431 * concurrent rendering before the stall completes. This intentionally
432 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
433 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
434 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
435 * already guarantee that there is no concurrent GPGPU kernel execution
436 * (see SKL HSD 2132585).
437 */
438 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
439 pc.TextureCacheInvalidationEnable = true;
440 pc.ConstantCacheInvalidationEnable = true;
441 pc.InstructionCacheInvalidateEnable = true;
442 pc.StateCacheInvalidationEnable = true;
443 pc.PostSyncOperation = NoWrite;
444 }
445
446 /* Now send a third stalling flush to make sure that invalidation is
447 * complete when the L3 configuration registers are modified.
448 */
449 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
450 pc.DCFlushEnable = true;
451 pc.PostSyncOperation = NoWrite;
452 pc.CommandStreamerStallEnable = true;
453 }
454
455 #if GEN_GEN >= 8
456
457 assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
458
459 uint32_t l3cr;
460 anv_pack_struct(&l3cr, GENX(L3CNTLREG),
461 .SLMEnable = has_slm,
462 .URBAllocation = cfg->n[GEN_L3P_URB],
463 .ROAllocation = cfg->n[GEN_L3P_RO],
464 .DCAllocation = cfg->n[GEN_L3P_DC],
465 .AllAllocation = cfg->n[GEN_L3P_ALL]);
466
467 /* Set up the L3 partitioning. */
468 emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG_num), l3cr);
469
470 #else
471
472 const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL];
473 const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] ||
474 cfg->n[GEN_L3P_ALL];
475 const bool has_c = cfg->n[GEN_L3P_C] || cfg->n[GEN_L3P_RO] ||
476 cfg->n[GEN_L3P_ALL];
477 const bool has_t = cfg->n[GEN_L3P_T] || cfg->n[GEN_L3P_RO] ||
478 cfg->n[GEN_L3P_ALL];
479
480 assert(!cfg->n[GEN_L3P_ALL]);
481
482 /* When enabled SLM only uses a portion of the L3 on half of the banks,
483 * the matching space on the remaining banks has to be allocated to a
484 * client (URB for all validated configurations) set to the
485 * lower-bandwidth 2-bank address hashing mode.
486 */
487 const struct gen_device_info *devinfo = &cmd_buffer->device->info;
488 const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
489 assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
490
491 /* Minimum number of ways that can be allocated to the URB. */
492 const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0);
493 assert(cfg->n[GEN_L3P_URB] >= n0_urb);
494
495 uint32_t l3sqcr1, l3cr2, l3cr3;
496 anv_pack_struct(&l3sqcr1, GENX(L3SQCREG1),
497 .ConvertDC_UC = !has_dc,
498 .ConvertIS_UC = !has_is,
499 .ConvertC_UC = !has_c,
500 .ConvertT_UC = !has_t);
501 l3sqcr1 |=
502 GEN_IS_HASWELL ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
503 devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
504 IVB_L3SQCREG1_SQGHPCI_DEFAULT;
505
506 anv_pack_struct(&l3cr2, GENX(L3CNTLREG2),
507 .SLMEnable = has_slm,
508 .URBLowBandwidth = urb_low_bw,
509 .URBAllocation = cfg->n[GEN_L3P_URB],
510 #if !GEN_IS_HASWELL
511 .ALLAllocation = cfg->n[GEN_L3P_ALL],
512 #endif
513 .ROAllocation = cfg->n[GEN_L3P_RO],
514 .DCAllocation = cfg->n[GEN_L3P_DC]);
515
516 anv_pack_struct(&l3cr3, GENX(L3CNTLREG3),
517 .ISAllocation = cfg->n[GEN_L3P_IS],
518 .ISLowBandwidth = 0,
519 .CAllocation = cfg->n[GEN_L3P_C],
520 .CLowBandwidth = 0,
521 .TAllocation = cfg->n[GEN_L3P_T],
522 .TLowBandwidth = 0);
523
524 /* Set up the L3 partitioning. */
525 emit_lri(&cmd_buffer->batch, GENX(L3SQCREG1_num), l3sqcr1);
526 emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG2_num), l3cr2);
527 emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG3_num), l3cr3);
528
529 #if GEN_IS_HASWELL
530 if (cmd_buffer->device->instance->physicalDevice.cmd_parser_version >= 4) {
531 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
532 * them disabled to avoid crashing the system hard.
533 */
534 uint32_t scratch1, chicken3;
535 anv_pack_struct(&scratch1, GENX(SCRATCH1),
536 .L3AtomicDisable = !has_dc);
537 anv_pack_struct(&chicken3, GENX(CHICKEN3),
538 .L3AtomicDisableMask = true,
539 .L3AtomicDisable = !has_dc);
540 emit_lri(&cmd_buffer->batch, GENX(SCRATCH1_num), scratch1);
541 emit_lri(&cmd_buffer->batch, GENX(CHICKEN3_num), chicken3);
542 }
543 #endif
544
545 #endif
546
547 cmd_buffer->state.current_l3_config = cfg;
548 }
549
550 void
551 genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
552 {
553 enum anv_pipe_bits bits = cmd_buffer->state.pending_pipe_bits;
554
555 /* Flushes are pipelined while invalidations are handled immediately.
556 * Therefore, if we're flushing anything then we need to schedule a stall
557 * before any invalidations can happen.
558 */
559 if (bits & ANV_PIPE_FLUSH_BITS)
560 bits |= ANV_PIPE_NEEDS_CS_STALL_BIT;
561
562 /* If we're going to do an invalidate and we have a pending CS stall that
563 * has yet to be resolved, we do the CS stall now.
564 */
565 if ((bits & ANV_PIPE_INVALIDATE_BITS) &&
566 (bits & ANV_PIPE_NEEDS_CS_STALL_BIT)) {
567 bits |= ANV_PIPE_CS_STALL_BIT;
568 bits &= ~ANV_PIPE_NEEDS_CS_STALL_BIT;
569 }
570
571 if (bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_CS_STALL_BIT)) {
572 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
573 pipe.DepthCacheFlushEnable = bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
574 pipe.DCFlushEnable = bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT;
575 pipe.RenderTargetCacheFlushEnable =
576 bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
577
578 pipe.DepthStallEnable = bits & ANV_PIPE_DEPTH_STALL_BIT;
579 pipe.CommandStreamerStallEnable = bits & ANV_PIPE_CS_STALL_BIT;
580 pipe.StallAtPixelScoreboard = bits & ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
581
582 /*
583 * According to the Broadwell documentation, any PIPE_CONTROL with the
584 * "Command Streamer Stall" bit set must also have another bit set,
585 * with five different options:
586 *
587 * - Render Target Cache Flush
588 * - Depth Cache Flush
589 * - Stall at Pixel Scoreboard
590 * - Post-Sync Operation
591 * - Depth Stall
592 * - DC Flush Enable
593 *
594 * I chose "Stall at Pixel Scoreboard" since that's what we use in
595 * mesa and it seems to work fine. The choice is fairly arbitrary.
596 */
597 if ((bits & ANV_PIPE_CS_STALL_BIT) &&
598 !(bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_DEPTH_STALL_BIT |
599 ANV_PIPE_STALL_AT_SCOREBOARD_BIT)))
600 pipe.StallAtPixelScoreboard = true;
601 }
602
603 bits &= ~(ANV_PIPE_FLUSH_BITS | ANV_PIPE_CS_STALL_BIT);
604 }
605
606 if (bits & ANV_PIPE_INVALIDATE_BITS) {
607 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
608 pipe.StateCacheInvalidationEnable =
609 bits & ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
610 pipe.ConstantCacheInvalidationEnable =
611 bits & ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
612 pipe.VFCacheInvalidationEnable =
613 bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
614 pipe.TextureCacheInvalidationEnable =
615 bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
616 pipe.InstructionCacheInvalidateEnable =
617 bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT;
618 }
619
620 bits &= ~ANV_PIPE_INVALIDATE_BITS;
621 }
622
623 cmd_buffer->state.pending_pipe_bits = bits;
624 }
625
626 void genX(CmdPipelineBarrier)(
627 VkCommandBuffer commandBuffer,
628 VkPipelineStageFlags srcStageMask,
629 VkPipelineStageFlags destStageMask,
630 VkBool32 byRegion,
631 uint32_t memoryBarrierCount,
632 const VkMemoryBarrier* pMemoryBarriers,
633 uint32_t bufferMemoryBarrierCount,
634 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
635 uint32_t imageMemoryBarrierCount,
636 const VkImageMemoryBarrier* pImageMemoryBarriers)
637 {
638 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
639 uint32_t b;
640
641 /* XXX: Right now, we're really dumb and just flush whatever categories
642 * the app asks for. One of these days we may make this a bit better
643 * but right now that's all the hardware allows for in most areas.
644 */
645 VkAccessFlags src_flags = 0;
646 VkAccessFlags dst_flags = 0;
647
648 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
649 src_flags |= pMemoryBarriers[i].srcAccessMask;
650 dst_flags |= pMemoryBarriers[i].dstAccessMask;
651 }
652
653 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
654 src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
655 dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
656 }
657
658 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
659 src_flags |= pImageMemoryBarriers[i].srcAccessMask;
660 dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
661 }
662
663 enum anv_pipe_bits pipe_bits = 0;
664
665 for_each_bit(b, src_flags) {
666 switch ((VkAccessFlagBits)(1 << b)) {
667 case VK_ACCESS_SHADER_WRITE_BIT:
668 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
669 break;
670 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
671 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
672 break;
673 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
674 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
675 break;
676 case VK_ACCESS_TRANSFER_WRITE_BIT:
677 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
678 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
679 break;
680 default:
681 break; /* Nothing to do */
682 }
683 }
684
685 for_each_bit(b, dst_flags) {
686 switch ((VkAccessFlagBits)(1 << b)) {
687 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
688 case VK_ACCESS_INDEX_READ_BIT:
689 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
690 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
691 break;
692 case VK_ACCESS_UNIFORM_READ_BIT:
693 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
694 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
695 break;
696 case VK_ACCESS_SHADER_READ_BIT:
697 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
698 case VK_ACCESS_TRANSFER_READ_BIT:
699 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
700 break;
701 default:
702 break; /* Nothing to do */
703 }
704 }
705
706 cmd_buffer->state.pending_pipe_bits |= pipe_bits;
707 }
708
709 static void
710 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer *cmd_buffer)
711 {
712 VkShaderStageFlags stages = cmd_buffer->state.pipeline->active_stages;
713
714 /* In order to avoid thrash, we assume that vertex and fragment stages
715 * always exist. In the rare case where one is missing *and* the other
716 * uses push concstants, this may be suboptimal. However, avoiding stalls
717 * seems more important.
718 */
719 stages |= VK_SHADER_STAGE_FRAGMENT_BIT | VK_SHADER_STAGE_VERTEX_BIT;
720
721 if (stages == cmd_buffer->state.push_constant_stages)
722 return;
723
724 #if GEN_GEN >= 8
725 const unsigned push_constant_kb = 32;
726 #elif GEN_IS_HASWELL
727 const unsigned push_constant_kb = cmd_buffer->device->info.gt == 3 ? 32 : 16;
728 #else
729 const unsigned push_constant_kb = 16;
730 #endif
731
732 const unsigned num_stages =
733 _mesa_bitcount(stages & VK_SHADER_STAGE_ALL_GRAPHICS);
734 unsigned size_per_stage = push_constant_kb / num_stages;
735
736 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
737 * units of 2KB. Incidentally, these are the same platforms that have
738 * 32KB worth of push constant space.
739 */
740 if (push_constant_kb == 32)
741 size_per_stage &= ~1u;
742
743 uint32_t kb_used = 0;
744 for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) {
745 unsigned push_size = (stages & (1 << i)) ? size_per_stage : 0;
746 anv_batch_emit(&cmd_buffer->batch,
747 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) {
748 alloc._3DCommandSubOpcode = 18 + i;
749 alloc.ConstantBufferOffset = (push_size > 0) ? kb_used : 0;
750 alloc.ConstantBufferSize = push_size;
751 }
752 kb_used += push_size;
753 }
754
755 anv_batch_emit(&cmd_buffer->batch,
756 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS), alloc) {
757 alloc.ConstantBufferOffset = kb_used;
758 alloc.ConstantBufferSize = push_constant_kb - kb_used;
759 }
760
761 cmd_buffer->state.push_constant_stages = stages;
762
763 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
764 *
765 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
766 * the next 3DPRIMITIVE command after programming the
767 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
768 *
769 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
770 * pipeline setup, we need to dirty push constants.
771 */
772 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_ALL_GRAPHICS;
773 }
774
775 static VkResult
776 emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
777 gl_shader_stage stage,
778 struct anv_state *bt_state)
779 {
780 struct anv_subpass *subpass = cmd_buffer->state.subpass;
781 struct anv_pipeline *pipeline;
782 uint32_t bias, state_offset;
783
784 switch (stage) {
785 case MESA_SHADER_COMPUTE:
786 pipeline = cmd_buffer->state.compute_pipeline;
787 bias = 1;
788 break;
789 default:
790 pipeline = cmd_buffer->state.pipeline;
791 bias = 0;
792 break;
793 }
794
795 if (!anv_pipeline_has_stage(pipeline, stage)) {
796 *bt_state = (struct anv_state) { 0, };
797 return VK_SUCCESS;
798 }
799
800 struct anv_pipeline_bind_map *map = &pipeline->shaders[stage]->bind_map;
801 if (bias + map->surface_count == 0) {
802 *bt_state = (struct anv_state) { 0, };
803 return VK_SUCCESS;
804 }
805
806 *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer,
807 bias + map->surface_count,
808 &state_offset);
809 uint32_t *bt_map = bt_state->map;
810
811 if (bt_state->map == NULL)
812 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
813
814 if (stage == MESA_SHADER_COMPUTE &&
815 get_cs_prog_data(cmd_buffer->state.compute_pipeline)->uses_num_work_groups) {
816 struct anv_bo *bo = cmd_buffer->state.num_workgroups_bo;
817 uint32_t bo_offset = cmd_buffer->state.num_workgroups_offset;
818
819 struct anv_state surface_state;
820 surface_state =
821 anv_cmd_buffer_alloc_surface_state(cmd_buffer);
822
823 const enum isl_format format =
824 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER);
825 anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
826 format, bo_offset, 12, 1);
827
828 bt_map[0] = surface_state.offset + state_offset;
829 anv_cmd_buffer_add_surface_state_reloc(cmd_buffer, surface_state,
830 bo, bo_offset);
831 }
832
833 if (map->surface_count == 0)
834 goto out;
835
836 if (map->image_count > 0) {
837 VkResult result =
838 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, images);
839 if (result != VK_SUCCESS)
840 return result;
841
842 cmd_buffer->state.push_constants_dirty |= 1 << stage;
843 }
844
845 uint32_t image = 0;
846 for (uint32_t s = 0; s < map->surface_count; s++) {
847 struct anv_pipeline_binding *binding = &map->surface_to_descriptor[s];
848
849 struct anv_state surface_state;
850 struct anv_bo *bo;
851 uint32_t bo_offset;
852
853 if (binding->set == ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS) {
854 /* Color attachment binding */
855 assert(stage == MESA_SHADER_FRAGMENT);
856 assert(binding->binding == 0);
857 if (binding->index < subpass->color_count) {
858 const unsigned att = subpass->color_attachments[binding->index];
859 surface_state = cmd_buffer->state.attachments[att].color_rt_state;
860 } else {
861 surface_state = cmd_buffer->state.null_surface_state;
862 }
863
864 bt_map[bias + s] = surface_state.offset + state_offset;
865 continue;
866 }
867
868 struct anv_descriptor_set *set =
869 cmd_buffer->state.descriptors[binding->set];
870 uint32_t offset = set->layout->binding[binding->binding].descriptor_index;
871 struct anv_descriptor *desc = &set->descriptors[offset + binding->index];
872
873 switch (desc->type) {
874 case VK_DESCRIPTOR_TYPE_SAMPLER:
875 /* Nothing for us to do here */
876 continue;
877
878 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
879 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
880 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
881 surface_state = desc->image_view->sampler_surface_state;
882 assert(surface_state.alloc_size);
883 bo = desc->image_view->bo;
884 bo_offset = desc->image_view->offset;
885 break;
886
887 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: {
888 surface_state = desc->image_view->storage_surface_state;
889 assert(surface_state.alloc_size);
890 bo = desc->image_view->bo;
891 bo_offset = desc->image_view->offset;
892
893 struct brw_image_param *image_param =
894 &cmd_buffer->state.push_constants[stage]->images[image++];
895
896 *image_param = desc->image_view->storage_image_param;
897 image_param->surface_idx = bias + s;
898 break;
899 }
900
901 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
902 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
903 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
904 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
905 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
906 surface_state = desc->buffer_view->surface_state;
907 assert(surface_state.alloc_size);
908 bo = desc->buffer_view->bo;
909 bo_offset = desc->buffer_view->offset;
910 break;
911
912 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
913 surface_state = desc->buffer_view->storage_surface_state;
914 assert(surface_state.alloc_size);
915 bo = desc->buffer_view->bo;
916 bo_offset = desc->buffer_view->offset;
917
918 struct brw_image_param *image_param =
919 &cmd_buffer->state.push_constants[stage]->images[image++];
920
921 *image_param = desc->buffer_view->storage_image_param;
922 image_param->surface_idx = bias + s;
923 break;
924
925 default:
926 assert(!"Invalid descriptor type");
927 continue;
928 }
929
930 bt_map[bias + s] = surface_state.offset + state_offset;
931 anv_cmd_buffer_add_surface_state_reloc(cmd_buffer, surface_state,
932 bo, bo_offset);
933 }
934 assert(image == map->image_count);
935
936 out:
937 if (!cmd_buffer->device->info.has_llc)
938 anv_state_clflush(*bt_state);
939
940 return VK_SUCCESS;
941 }
942
943 static VkResult
944 emit_samplers(struct anv_cmd_buffer *cmd_buffer,
945 gl_shader_stage stage,
946 struct anv_state *state)
947 {
948 struct anv_pipeline *pipeline;
949
950 if (stage == MESA_SHADER_COMPUTE)
951 pipeline = cmd_buffer->state.compute_pipeline;
952 else
953 pipeline = cmd_buffer->state.pipeline;
954
955 if (!anv_pipeline_has_stage(pipeline, stage)) {
956 *state = (struct anv_state) { 0, };
957 return VK_SUCCESS;
958 }
959
960 struct anv_pipeline_bind_map *map = &pipeline->shaders[stage]->bind_map;
961 if (map->sampler_count == 0) {
962 *state = (struct anv_state) { 0, };
963 return VK_SUCCESS;
964 }
965
966 uint32_t size = map->sampler_count * 16;
967 *state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 32);
968
969 if (state->map == NULL)
970 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
971
972 for (uint32_t s = 0; s < map->sampler_count; s++) {
973 struct anv_pipeline_binding *binding = &map->sampler_to_descriptor[s];
974 struct anv_descriptor_set *set =
975 cmd_buffer->state.descriptors[binding->set];
976 uint32_t offset = set->layout->binding[binding->binding].descriptor_index;
977 struct anv_descriptor *desc = &set->descriptors[offset + binding->index];
978
979 if (desc->type != VK_DESCRIPTOR_TYPE_SAMPLER &&
980 desc->type != VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
981 continue;
982
983 struct anv_sampler *sampler = desc->sampler;
984
985 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
986 * happens to be zero.
987 */
988 if (sampler == NULL)
989 continue;
990
991 memcpy(state->map + (s * 16),
992 sampler->state, sizeof(sampler->state));
993 }
994
995 if (!cmd_buffer->device->info.has_llc)
996 anv_state_clflush(*state);
997
998 return VK_SUCCESS;
999 }
1000
1001 static uint32_t
1002 flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer)
1003 {
1004 VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
1005 cmd_buffer->state.pipeline->active_stages;
1006
1007 VkResult result = VK_SUCCESS;
1008 anv_foreach_stage(s, dirty) {
1009 result = emit_samplers(cmd_buffer, s, &cmd_buffer->state.samplers[s]);
1010 if (result != VK_SUCCESS)
1011 break;
1012 result = emit_binding_table(cmd_buffer, s,
1013 &cmd_buffer->state.binding_tables[s]);
1014 if (result != VK_SUCCESS)
1015 break;
1016 }
1017
1018 if (result != VK_SUCCESS) {
1019 assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
1020
1021 result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
1022 assert(result == VK_SUCCESS);
1023
1024 /* Re-emit state base addresses so we get the new surface state base
1025 * address before we start emitting binding tables etc.
1026 */
1027 genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
1028
1029 /* Re-emit all active binding tables */
1030 dirty |= cmd_buffer->state.pipeline->active_stages;
1031 anv_foreach_stage(s, dirty) {
1032 result = emit_samplers(cmd_buffer, s, &cmd_buffer->state.samplers[s]);
1033 if (result != VK_SUCCESS)
1034 return result;
1035 result = emit_binding_table(cmd_buffer, s,
1036 &cmd_buffer->state.binding_tables[s]);
1037 if (result != VK_SUCCESS)
1038 return result;
1039 }
1040 }
1041
1042 cmd_buffer->state.descriptors_dirty &= ~dirty;
1043
1044 return dirty;
1045 }
1046
1047 static void
1048 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
1049 uint32_t stages)
1050 {
1051 static const uint32_t sampler_state_opcodes[] = {
1052 [MESA_SHADER_VERTEX] = 43,
1053 [MESA_SHADER_TESS_CTRL] = 44, /* HS */
1054 [MESA_SHADER_TESS_EVAL] = 45, /* DS */
1055 [MESA_SHADER_GEOMETRY] = 46,
1056 [MESA_SHADER_FRAGMENT] = 47,
1057 [MESA_SHADER_COMPUTE] = 0,
1058 };
1059
1060 static const uint32_t binding_table_opcodes[] = {
1061 [MESA_SHADER_VERTEX] = 38,
1062 [MESA_SHADER_TESS_CTRL] = 39,
1063 [MESA_SHADER_TESS_EVAL] = 40,
1064 [MESA_SHADER_GEOMETRY] = 41,
1065 [MESA_SHADER_FRAGMENT] = 42,
1066 [MESA_SHADER_COMPUTE] = 0,
1067 };
1068
1069 anv_foreach_stage(s, stages) {
1070 if (cmd_buffer->state.samplers[s].alloc_size > 0) {
1071 anv_batch_emit(&cmd_buffer->batch,
1072 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ssp) {
1073 ssp._3DCommandSubOpcode = sampler_state_opcodes[s];
1074 ssp.PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset;
1075 }
1076 }
1077
1078 /* Always emit binding table pointers if we're asked to, since on SKL
1079 * this is what flushes push constants. */
1080 anv_batch_emit(&cmd_buffer->batch,
1081 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), btp) {
1082 btp._3DCommandSubOpcode = binding_table_opcodes[s];
1083 btp.PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset;
1084 }
1085 }
1086 }
1087
1088 static uint32_t
1089 cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
1090 {
1091 static const uint32_t push_constant_opcodes[] = {
1092 [MESA_SHADER_VERTEX] = 21,
1093 [MESA_SHADER_TESS_CTRL] = 25, /* HS */
1094 [MESA_SHADER_TESS_EVAL] = 26, /* DS */
1095 [MESA_SHADER_GEOMETRY] = 22,
1096 [MESA_SHADER_FRAGMENT] = 23,
1097 [MESA_SHADER_COMPUTE] = 0,
1098 };
1099
1100 VkShaderStageFlags flushed = 0;
1101
1102 anv_foreach_stage(stage, cmd_buffer->state.push_constants_dirty) {
1103 if (stage == MESA_SHADER_COMPUTE)
1104 continue;
1105
1106 struct anv_state state = anv_cmd_buffer_push_constants(cmd_buffer, stage);
1107
1108 if (state.offset == 0) {
1109 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS), c)
1110 c._3DCommandSubOpcode = push_constant_opcodes[stage];
1111 } else {
1112 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS), c) {
1113 c._3DCommandSubOpcode = push_constant_opcodes[stage],
1114 c.ConstantBody = (struct GENX(3DSTATE_CONSTANT_BODY)) {
1115 #if GEN_GEN >= 9
1116 .PointerToConstantBuffer2 = { &cmd_buffer->device->dynamic_state_block_pool.bo, state.offset },
1117 .ConstantBuffer2ReadLength = DIV_ROUND_UP(state.alloc_size, 32),
1118 #else
1119 .PointerToConstantBuffer0 = { .offset = state.offset },
1120 .ConstantBuffer0ReadLength = DIV_ROUND_UP(state.alloc_size, 32),
1121 #endif
1122 };
1123 }
1124 }
1125
1126 flushed |= mesa_to_vk_shader_stage(stage);
1127 }
1128
1129 cmd_buffer->state.push_constants_dirty &= ~VK_SHADER_STAGE_ALL_GRAPHICS;
1130
1131 return flushed;
1132 }
1133
1134 void
1135 genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
1136 {
1137 struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
1138 uint32_t *p;
1139
1140 uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
1141
1142 assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
1143
1144 genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->urb.l3_config);
1145
1146 genX(flush_pipeline_select_3d)(cmd_buffer);
1147
1148 if (vb_emit) {
1149 const uint32_t num_buffers = __builtin_popcount(vb_emit);
1150 const uint32_t num_dwords = 1 + num_buffers * 4;
1151
1152 p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
1153 GENX(3DSTATE_VERTEX_BUFFERS));
1154 uint32_t vb, i = 0;
1155 for_each_bit(vb, vb_emit) {
1156 struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1157 uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
1158
1159 struct GENX(VERTEX_BUFFER_STATE) state = {
1160 .VertexBufferIndex = vb,
1161
1162 #if GEN_GEN >= 8
1163 .MemoryObjectControlState = GENX(MOCS),
1164 #else
1165 .BufferAccessType = pipeline->instancing_enable[vb] ? INSTANCEDATA : VERTEXDATA,
1166 .InstanceDataStepRate = 1,
1167 .VertexBufferMemoryObjectControlState = GENX(MOCS),
1168 #endif
1169
1170 .AddressModifyEnable = true,
1171 .BufferPitch = pipeline->binding_stride[vb],
1172 .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
1173
1174 #if GEN_GEN >= 8
1175 .BufferSize = buffer->size - offset
1176 #else
1177 .EndAddress = { buffer->bo, buffer->offset + buffer->size - 1},
1178 #endif
1179 };
1180
1181 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, &p[1 + i * 4], &state);
1182 i++;
1183 }
1184 }
1185
1186 cmd_buffer->state.vb_dirty &= ~vb_emit;
1187
1188 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_PIPELINE) {
1189 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
1190
1191 /* The exact descriptor layout is pulled from the pipeline, so we need
1192 * to re-emit binding tables on every pipeline change.
1193 */
1194 cmd_buffer->state.descriptors_dirty |=
1195 cmd_buffer->state.pipeline->active_stages;
1196
1197 /* If the pipeline changed, we may need to re-allocate push constant
1198 * space in the URB.
1199 */
1200 cmd_buffer_alloc_push_constants(cmd_buffer);
1201 }
1202
1203 #if GEN_GEN <= 7
1204 if (cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_VERTEX_BIT ||
1205 cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_VERTEX_BIT) {
1206 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1207 *
1208 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1209 * stall needs to be sent just prior to any 3DSTATE_VS,
1210 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1211 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1212 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1213 * PIPE_CONTROL needs to be sent before any combination of VS
1214 * associated 3DSTATE."
1215 */
1216 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1217 pc.DepthStallEnable = true;
1218 pc.PostSyncOperation = WriteImmediateData;
1219 pc.Address =
1220 (struct anv_address) { &cmd_buffer->device->workaround_bo, 0 };
1221 }
1222 }
1223 #endif
1224
1225 /* Render targets live in the same binding table as fragment descriptors */
1226 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_RENDER_TARGETS)
1227 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
1228
1229 /* We emit the binding tables and sampler tables first, then emit push
1230 * constants and then finally emit binding table and sampler table
1231 * pointers. It has to happen in this order, since emitting the binding
1232 * tables may change the push constants (in case of storage images). After
1233 * emitting push constants, on SKL+ we have to emit the corresponding
1234 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1235 */
1236 uint32_t dirty = 0;
1237 if (cmd_buffer->state.descriptors_dirty)
1238 dirty = flush_descriptor_sets(cmd_buffer);
1239
1240 if (cmd_buffer->state.push_constants_dirty) {
1241 #if GEN_GEN >= 9
1242 /* On Sky Lake and later, the binding table pointers commands are
1243 * what actually flush the changes to push constant state so we need
1244 * to dirty them so they get re-emitted below.
1245 */
1246 dirty |= cmd_buffer_flush_push_constants(cmd_buffer);
1247 #else
1248 cmd_buffer_flush_push_constants(cmd_buffer);
1249 #endif
1250 }
1251
1252 if (dirty)
1253 cmd_buffer_emit_descriptor_pointers(cmd_buffer, dirty);
1254
1255 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
1256 gen8_cmd_buffer_emit_viewport(cmd_buffer);
1257
1258 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT |
1259 ANV_CMD_DIRTY_PIPELINE)) {
1260 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer,
1261 pipeline->depth_clamp_enable);
1262 }
1263
1264 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
1265 gen7_cmd_buffer_emit_scissor(cmd_buffer);
1266
1267 genX(cmd_buffer_flush_dynamic_state)(cmd_buffer);
1268
1269 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
1270 }
1271
1272 static void
1273 emit_base_vertex_instance_bo(struct anv_cmd_buffer *cmd_buffer,
1274 struct anv_bo *bo, uint32_t offset)
1275 {
1276 uint32_t *p = anv_batch_emitn(&cmd_buffer->batch, 5,
1277 GENX(3DSTATE_VERTEX_BUFFERS));
1278
1279 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, p + 1,
1280 &(struct GENX(VERTEX_BUFFER_STATE)) {
1281 .VertexBufferIndex = 32, /* Reserved for this */
1282 .AddressModifyEnable = true,
1283 .BufferPitch = 0,
1284 #if (GEN_GEN >= 8)
1285 .MemoryObjectControlState = GENX(MOCS),
1286 .BufferStartingAddress = { bo, offset },
1287 .BufferSize = 8
1288 #else
1289 .VertexBufferMemoryObjectControlState = GENX(MOCS),
1290 .BufferStartingAddress = { bo, offset },
1291 .EndAddress = { bo, offset + 8 },
1292 #endif
1293 });
1294 }
1295
1296 static void
1297 emit_base_vertex_instance(struct anv_cmd_buffer *cmd_buffer,
1298 uint32_t base_vertex, uint32_t base_instance)
1299 {
1300 struct anv_state id_state =
1301 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 8, 4);
1302
1303 ((uint32_t *)id_state.map)[0] = base_vertex;
1304 ((uint32_t *)id_state.map)[1] = base_instance;
1305
1306 if (!cmd_buffer->device->info.has_llc)
1307 anv_state_clflush(id_state);
1308
1309 emit_base_vertex_instance_bo(cmd_buffer,
1310 &cmd_buffer->device->dynamic_state_block_pool.bo, id_state.offset);
1311 }
1312
1313 void genX(CmdDraw)(
1314 VkCommandBuffer commandBuffer,
1315 uint32_t vertexCount,
1316 uint32_t instanceCount,
1317 uint32_t firstVertex,
1318 uint32_t firstInstance)
1319 {
1320 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1321 struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
1322 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
1323
1324 genX(cmd_buffer_flush_state)(cmd_buffer);
1325
1326 if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
1327 emit_base_vertex_instance(cmd_buffer, firstVertex, firstInstance);
1328
1329 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
1330 prim.VertexAccessType = SEQUENTIAL;
1331 prim.PrimitiveTopologyType = pipeline->topology;
1332 prim.VertexCountPerInstance = vertexCount;
1333 prim.StartVertexLocation = firstVertex;
1334 prim.InstanceCount = instanceCount;
1335 prim.StartInstanceLocation = firstInstance;
1336 prim.BaseVertexLocation = 0;
1337 }
1338 }
1339
1340 void genX(CmdDrawIndexed)(
1341 VkCommandBuffer commandBuffer,
1342 uint32_t indexCount,
1343 uint32_t instanceCount,
1344 uint32_t firstIndex,
1345 int32_t vertexOffset,
1346 uint32_t firstInstance)
1347 {
1348 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1349 struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
1350 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
1351
1352 genX(cmd_buffer_flush_state)(cmd_buffer);
1353
1354 if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
1355 emit_base_vertex_instance(cmd_buffer, vertexOffset, firstInstance);
1356
1357 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
1358 prim.VertexAccessType = RANDOM;
1359 prim.PrimitiveTopologyType = pipeline->topology;
1360 prim.VertexCountPerInstance = indexCount;
1361 prim.StartVertexLocation = firstIndex;
1362 prim.InstanceCount = instanceCount;
1363 prim.StartInstanceLocation = firstInstance;
1364 prim.BaseVertexLocation = vertexOffset;
1365 }
1366 }
1367
1368 /* Auto-Draw / Indirect Registers */
1369 #define GEN7_3DPRIM_END_OFFSET 0x2420
1370 #define GEN7_3DPRIM_START_VERTEX 0x2430
1371 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1372 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1373 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1374 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1375
1376 void genX(CmdDrawIndirect)(
1377 VkCommandBuffer commandBuffer,
1378 VkBuffer _buffer,
1379 VkDeviceSize offset,
1380 uint32_t drawCount,
1381 uint32_t stride)
1382 {
1383 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1384 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
1385 struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
1386 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
1387 struct anv_bo *bo = buffer->bo;
1388 uint32_t bo_offset = buffer->offset + offset;
1389
1390 genX(cmd_buffer_flush_state)(cmd_buffer);
1391
1392 if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
1393 emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset + 8);
1394
1395 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
1396 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
1397 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
1398 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 12);
1399 emit_lri(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, 0);
1400
1401 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
1402 prim.IndirectParameterEnable = true;
1403 prim.VertexAccessType = SEQUENTIAL;
1404 prim.PrimitiveTopologyType = pipeline->topology;
1405 }
1406 }
1407
1408 void genX(CmdDrawIndexedIndirect)(
1409 VkCommandBuffer commandBuffer,
1410 VkBuffer _buffer,
1411 VkDeviceSize offset,
1412 uint32_t drawCount,
1413 uint32_t stride)
1414 {
1415 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1416 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
1417 struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
1418 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
1419 struct anv_bo *bo = buffer->bo;
1420 uint32_t bo_offset = buffer->offset + offset;
1421
1422 genX(cmd_buffer_flush_state)(cmd_buffer);
1423
1424 /* TODO: We need to stomp base vertex to 0 somehow */
1425 if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
1426 emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset + 12);
1427
1428 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
1429 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
1430 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
1431 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, bo, bo_offset + 12);
1432 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 16);
1433
1434 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
1435 prim.IndirectParameterEnable = true;
1436 prim.VertexAccessType = RANDOM;
1437 prim.PrimitiveTopologyType = pipeline->topology;
1438 }
1439 }
1440
1441 static VkResult
1442 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
1443 {
1444 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1445 struct anv_state surfaces = { 0, }, samplers = { 0, };
1446 VkResult result;
1447
1448 result = emit_samplers(cmd_buffer, MESA_SHADER_COMPUTE, &samplers);
1449 if (result != VK_SUCCESS)
1450 return result;
1451 result = emit_binding_table(cmd_buffer, MESA_SHADER_COMPUTE, &surfaces);
1452 if (result != VK_SUCCESS)
1453 return result;
1454
1455 struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
1456
1457 if (push_state.alloc_size) {
1458 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
1459 curbe.CURBETotalDataLength = push_state.alloc_size;
1460 curbe.CURBEDataStartAddress = push_state.offset;
1461 }
1462 }
1463
1464 uint32_t iface_desc_data_dw[GENX(INTERFACE_DESCRIPTOR_DATA_length)];
1465 struct GENX(INTERFACE_DESCRIPTOR_DATA) desc = {
1466 .BindingTablePointer = surfaces.offset,
1467 .SamplerStatePointer = samplers.offset,
1468 };
1469 GENX(INTERFACE_DESCRIPTOR_DATA_pack)(NULL, iface_desc_data_dw, &desc);
1470
1471 struct anv_state state =
1472 anv_cmd_buffer_merge_dynamic(cmd_buffer, iface_desc_data_dw,
1473 pipeline->interface_descriptor_data,
1474 GENX(INTERFACE_DESCRIPTOR_DATA_length),
1475 64);
1476
1477 uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
1478 anv_batch_emit(&cmd_buffer->batch,
1479 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
1480 mid.InterfaceDescriptorTotalLength = size;
1481 mid.InterfaceDescriptorDataStartAddress = state.offset;
1482 }
1483
1484 return VK_SUCCESS;
1485 }
1486
1487 void
1488 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
1489 {
1490 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1491 MAYBE_UNUSED VkResult result;
1492
1493 assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
1494
1495 genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->urb.l3_config);
1496
1497 genX(flush_pipeline_select_gpgpu)(cmd_buffer);
1498
1499 if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
1500 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
1501
1502 if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
1503 (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
1504 /* FIXME: figure out descriptors for gen7 */
1505 result = flush_compute_descriptor_set(cmd_buffer);
1506 assert(result == VK_SUCCESS);
1507 cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
1508 }
1509
1510 cmd_buffer->state.compute_dirty = 0;
1511
1512 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
1513 }
1514
1515 #if GEN_GEN == 7
1516
1517 static bool
1518 verify_cmd_parser(const struct anv_device *device,
1519 int required_version,
1520 const char *function)
1521 {
1522 if (device->instance->physicalDevice.cmd_parser_version < required_version) {
1523 vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT,
1524 "cmd parser version %d is required for %s",
1525 required_version, function);
1526 return false;
1527 } else {
1528 return true;
1529 }
1530 }
1531
1532 #endif
1533
1534 void genX(CmdDispatch)(
1535 VkCommandBuffer commandBuffer,
1536 uint32_t x,
1537 uint32_t y,
1538 uint32_t z)
1539 {
1540 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1541 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1542 const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
1543
1544 if (prog_data->uses_num_work_groups) {
1545 struct anv_state state =
1546 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 12, 4);
1547 uint32_t *sizes = state.map;
1548 sizes[0] = x;
1549 sizes[1] = y;
1550 sizes[2] = z;
1551 if (!cmd_buffer->device->info.has_llc)
1552 anv_state_clflush(state);
1553 cmd_buffer->state.num_workgroups_offset = state.offset;
1554 cmd_buffer->state.num_workgroups_bo =
1555 &cmd_buffer->device->dynamic_state_block_pool.bo;
1556 }
1557
1558 genX(cmd_buffer_flush_compute_state)(cmd_buffer);
1559
1560 anv_batch_emit(&cmd_buffer->batch, GENX(GPGPU_WALKER), ggw) {
1561 ggw.SIMDSize = prog_data->simd_size / 16;
1562 ggw.ThreadDepthCounterMaximum = 0;
1563 ggw.ThreadHeightCounterMaximum = 0;
1564 ggw.ThreadWidthCounterMaximum = prog_data->threads - 1;
1565 ggw.ThreadGroupIDXDimension = x;
1566 ggw.ThreadGroupIDYDimension = y;
1567 ggw.ThreadGroupIDZDimension = z;
1568 ggw.RightExecutionMask = pipeline->cs_right_mask;
1569 ggw.BottomExecutionMask = 0xffffffff;
1570 }
1571
1572 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_STATE_FLUSH), msf);
1573 }
1574
1575 #define GPGPU_DISPATCHDIMX 0x2500
1576 #define GPGPU_DISPATCHDIMY 0x2504
1577 #define GPGPU_DISPATCHDIMZ 0x2508
1578
1579 #define MI_PREDICATE_SRC0 0x2400
1580 #define MI_PREDICATE_SRC1 0x2408
1581
1582 void genX(CmdDispatchIndirect)(
1583 VkCommandBuffer commandBuffer,
1584 VkBuffer _buffer,
1585 VkDeviceSize offset)
1586 {
1587 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1588 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
1589 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1590 const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
1591 struct anv_bo *bo = buffer->bo;
1592 uint32_t bo_offset = buffer->offset + offset;
1593 struct anv_batch *batch = &cmd_buffer->batch;
1594
1595 #if GEN_GEN == 7
1596 /* Linux 4.4 added command parser version 5 which allows the GPGPU
1597 * indirect dispatch registers to be written.
1598 */
1599 if (!verify_cmd_parser(cmd_buffer->device, 5, "vkCmdDispatchIndirect"))
1600 return;
1601 #endif
1602
1603 if (prog_data->uses_num_work_groups) {
1604 cmd_buffer->state.num_workgroups_offset = bo_offset;
1605 cmd_buffer->state.num_workgroups_bo = bo;
1606 }
1607
1608 genX(cmd_buffer_flush_compute_state)(cmd_buffer);
1609
1610 emit_lrm(batch, GPGPU_DISPATCHDIMX, bo, bo_offset);
1611 emit_lrm(batch, GPGPU_DISPATCHDIMY, bo, bo_offset + 4);
1612 emit_lrm(batch, GPGPU_DISPATCHDIMZ, bo, bo_offset + 8);
1613
1614 #if GEN_GEN <= 7
1615 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
1616 emit_lri(batch, MI_PREDICATE_SRC0 + 4, 0);
1617 emit_lri(batch, MI_PREDICATE_SRC1 + 0, 0);
1618 emit_lri(batch, MI_PREDICATE_SRC1 + 4, 0);
1619
1620 /* Load compute_dispatch_indirect_x_size into SRC0 */
1621 emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 0);
1622
1623 /* predicate = (compute_dispatch_indirect_x_size == 0); */
1624 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
1625 mip.LoadOperation = LOAD_LOAD;
1626 mip.CombineOperation = COMBINE_SET;
1627 mip.CompareOperation = COMPARE_SRCS_EQUAL;
1628 }
1629
1630 /* Load compute_dispatch_indirect_y_size into SRC0 */
1631 emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 4);
1632
1633 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
1634 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
1635 mip.LoadOperation = LOAD_LOAD;
1636 mip.CombineOperation = COMBINE_OR;
1637 mip.CompareOperation = COMPARE_SRCS_EQUAL;
1638 }
1639
1640 /* Load compute_dispatch_indirect_z_size into SRC0 */
1641 emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 8);
1642
1643 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
1644 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
1645 mip.LoadOperation = LOAD_LOAD;
1646 mip.CombineOperation = COMBINE_OR;
1647 mip.CompareOperation = COMPARE_SRCS_EQUAL;
1648 }
1649
1650 /* predicate = !predicate; */
1651 #define COMPARE_FALSE 1
1652 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
1653 mip.LoadOperation = LOAD_LOADINV;
1654 mip.CombineOperation = COMBINE_OR;
1655 mip.CompareOperation = COMPARE_FALSE;
1656 }
1657 #endif
1658
1659 anv_batch_emit(batch, GENX(GPGPU_WALKER), ggw) {
1660 ggw.IndirectParameterEnable = true;
1661 ggw.PredicateEnable = GEN_GEN <= 7;
1662 ggw.SIMDSize = prog_data->simd_size / 16;
1663 ggw.ThreadDepthCounterMaximum = 0;
1664 ggw.ThreadHeightCounterMaximum = 0;
1665 ggw.ThreadWidthCounterMaximum = prog_data->threads - 1;
1666 ggw.RightExecutionMask = pipeline->cs_right_mask;
1667 ggw.BottomExecutionMask = 0xffffffff;
1668 }
1669
1670 anv_batch_emit(batch, GENX(MEDIA_STATE_FLUSH), msf);
1671 }
1672
1673 static void
1674 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer *cmd_buffer,
1675 uint32_t pipeline)
1676 {
1677 #if GEN_GEN >= 8 && GEN_GEN < 10
1678 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
1679 *
1680 * Software must clear the COLOR_CALC_STATE Valid field in
1681 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
1682 * with Pipeline Select set to GPGPU.
1683 *
1684 * The internal hardware docs recommend the same workaround for Gen9
1685 * hardware too.
1686 */
1687 if (pipeline == GPGPU)
1688 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
1689 #elif GEN_GEN <= 7
1690 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
1691 * PIPELINE_SELECT [DevBWR+]":
1692 *
1693 * Project: DEVSNB+
1694 *
1695 * Software must ensure all the write caches are flushed through a
1696 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
1697 * command to invalidate read only caches prior to programming
1698 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
1699 */
1700 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1701 pc.RenderTargetCacheFlushEnable = true;
1702 pc.DepthCacheFlushEnable = true;
1703 pc.DCFlushEnable = true;
1704 pc.PostSyncOperation = NoWrite;
1705 pc.CommandStreamerStallEnable = true;
1706 }
1707
1708 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1709 pc.TextureCacheInvalidationEnable = true;
1710 pc.ConstantCacheInvalidationEnable = true;
1711 pc.StateCacheInvalidationEnable = true;
1712 pc.InstructionCacheInvalidateEnable = true;
1713 pc.PostSyncOperation = NoWrite;
1714 }
1715 #endif
1716 }
1717
1718 void
1719 genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer)
1720 {
1721 if (cmd_buffer->state.current_pipeline != _3D) {
1722 flush_pipeline_before_pipeline_select(cmd_buffer, _3D);
1723
1724 anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {
1725 #if GEN_GEN >= 9
1726 ps.MaskBits = 3;
1727 #endif
1728 ps.PipelineSelection = _3D;
1729 }
1730
1731 cmd_buffer->state.current_pipeline = _3D;
1732 }
1733 }
1734
1735 void
1736 genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer)
1737 {
1738 if (cmd_buffer->state.current_pipeline != GPGPU) {
1739 flush_pipeline_before_pipeline_select(cmd_buffer, GPGPU);
1740
1741 anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {
1742 #if GEN_GEN >= 9
1743 ps.MaskBits = 3;
1744 #endif
1745 ps.PipelineSelection = GPGPU;
1746 }
1747
1748 cmd_buffer->state.current_pipeline = GPGPU;
1749 }
1750 }
1751
1752 static void
1753 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
1754 {
1755 struct anv_device *device = cmd_buffer->device;
1756 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1757 const struct anv_image_view *iview =
1758 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
1759 const struct anv_image *image = iview ? iview->image : NULL;
1760 const bool has_depth = image && (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
1761 const bool has_hiz = image != NULL && anv_image_has_hiz(image);
1762 const bool has_stencil =
1763 image && (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
1764
1765 /* FIXME: Implement the PMA stall W/A */
1766 /* FIXME: Width and Height are wrong */
1767
1768 /* Emit 3DSTATE_DEPTH_BUFFER */
1769 if (has_depth) {
1770 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER), db) {
1771 db.SurfaceType = SURFTYPE_2D;
1772 db.DepthWriteEnable = true;
1773 db.StencilWriteEnable = has_stencil;
1774
1775 if (cmd_buffer->state.pass->subpass_count == 1) {
1776 db.HierarchicalDepthBufferEnable = has_hiz;
1777 } else {
1778 anv_finishme("Multiple-subpass HiZ not implemented");
1779 }
1780
1781 db.SurfaceFormat = isl_surf_get_depth_format(&device->isl_dev,
1782 &image->depth_surface.isl);
1783
1784 db.SurfaceBaseAddress = (struct anv_address) {
1785 .bo = image->bo,
1786 .offset = image->offset + image->depth_surface.offset,
1787 };
1788 db.DepthBufferObjectControlState = GENX(MOCS);
1789
1790 db.SurfacePitch = image->depth_surface.isl.row_pitch - 1;
1791 db.Height = image->extent.height - 1;
1792 db.Width = image->extent.width - 1;
1793 db.LOD = iview->isl.base_level;
1794 db.Depth = image->array_size - 1; /* FIXME: 3-D */
1795 db.MinimumArrayElement = iview->isl.base_array_layer;
1796
1797 #if GEN_GEN >= 8
1798 db.SurfaceQPitch =
1799 isl_surf_get_array_pitch_el_rows(&image->depth_surface.isl) >> 2;
1800 #endif
1801 db.RenderTargetViewExtent = 1 - 1;
1802 }
1803 } else {
1804 /* Even when no depth buffer is present, the hardware requires that
1805 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
1806 *
1807 * If a null depth buffer is bound, the driver must instead bind depth as:
1808 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
1809 * 3DSTATE_DEPTH.Width = 1
1810 * 3DSTATE_DEPTH.Height = 1
1811 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
1812 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
1813 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
1814 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
1815 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
1816 *
1817 * The PRM is wrong, though. The width and height must be programmed to
1818 * actual framebuffer's width and height, even when neither depth buffer
1819 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
1820 * be combined with a stencil buffer so we use D32_FLOAT instead.
1821 */
1822 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER), db) {
1823 db.SurfaceType = SURFTYPE_2D;
1824 db.SurfaceFormat = D32_FLOAT;
1825 db.Width = fb->width - 1;
1826 db.Height = fb->height - 1;
1827 db.StencilWriteEnable = has_stencil;
1828 }
1829 }
1830
1831 if (has_hiz) {
1832 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HIER_DEPTH_BUFFER), hdb) {
1833 hdb.HierarchicalDepthBufferObjectControlState = GENX(MOCS);
1834 hdb.SurfacePitch = image->hiz_surface.isl.row_pitch - 1;
1835 hdb.SurfaceBaseAddress = (struct anv_address) {
1836 .bo = image->bo,
1837 .offset = image->offset + image->hiz_surface.offset,
1838 };
1839 #if GEN_GEN >= 8
1840 /* From the SKL PRM Vol2a:
1841 *
1842 * The interpretation of this field is dependent on Surface Type
1843 * as follows:
1844 * - SURFTYPE_1D: distance in pixels between array slices
1845 * - SURFTYPE_2D/CUBE: distance in rows between array slices
1846 * - SURFTYPE_3D: distance in rows between R - slices
1847 */
1848 hdb.SurfaceQPitch =
1849 image->hiz_surface.isl.dim == ISL_SURF_DIM_1D ?
1850 isl_surf_get_array_pitch_el(&image->hiz_surface.isl) >> 2 :
1851 isl_surf_get_array_pitch_el_rows(&image->hiz_surface.isl) >> 2;
1852 #endif
1853 }
1854 } else {
1855 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HIER_DEPTH_BUFFER), hdb);
1856 }
1857
1858 /* Emit 3DSTATE_STENCIL_BUFFER */
1859 if (has_stencil) {
1860 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER), sb) {
1861 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1862 sb.StencilBufferEnable = true;
1863 #endif
1864 sb.StencilBufferObjectControlState = GENX(MOCS);
1865
1866 sb.SurfacePitch = image->stencil_surface.isl.row_pitch - 1;
1867
1868 #if GEN_GEN >= 8
1869 sb.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->stencil_surface.isl) >> 2;
1870 #endif
1871 sb.SurfaceBaseAddress = (struct anv_address) {
1872 .bo = image->bo,
1873 .offset = image->offset + image->stencil_surface.offset,
1874 };
1875 }
1876 } else {
1877 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER), sb);
1878 }
1879
1880 /* From the IVB PRM Vol2P1, 11.5.5.4 3DSTATE_CLEAR_PARAMS:
1881 *
1882 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along with
1883 * the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
1884 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)
1885 *
1886 * Testing also shows that some variant of this restriction may exist HSW+.
1887 * On BDW+, it is not possible to emit 2 of these packets consecutively when
1888 * both have DepthClearValueValid set. An analysis of such state programming
1889 * on SKL showed that the GPU doesn't register the latter packet's clear
1890 * value.
1891 */
1892 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CLEAR_PARAMS), cp) {
1893 if (has_hiz) {
1894 cp.DepthClearValueValid = true;
1895 const uint32_t ds =
1896 cmd_buffer->state.subpass->depth_stencil_attachment;
1897 cp.DepthClearValue =
1898 cmd_buffer->state.attachments[ds].clear_value.depthStencil.depth;
1899 }
1900 }
1901 }
1902
1903 static void
1904 genX(cmd_buffer_set_subpass)(struct anv_cmd_buffer *cmd_buffer,
1905 struct anv_subpass *subpass)
1906 {
1907 cmd_buffer->state.subpass = subpass;
1908
1909 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
1910
1911 cmd_buffer_emit_depth_stencil(cmd_buffer);
1912 genX(cmd_buffer_emit_hz_op)(cmd_buffer, BLORP_HIZ_OP_HIZ_RESOLVE);
1913 genX(cmd_buffer_emit_hz_op)(cmd_buffer, BLORP_HIZ_OP_DEPTH_CLEAR);
1914
1915 anv_cmd_buffer_clear_subpass(cmd_buffer);
1916 }
1917
1918 void genX(CmdBeginRenderPass)(
1919 VkCommandBuffer commandBuffer,
1920 const VkRenderPassBeginInfo* pRenderPassBegin,
1921 VkSubpassContents contents)
1922 {
1923 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1924 ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
1925 ANV_FROM_HANDLE(anv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
1926
1927 cmd_buffer->state.framebuffer = framebuffer;
1928 cmd_buffer->state.pass = pass;
1929 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
1930 genX(cmd_buffer_setup_attachments)(cmd_buffer, pass, framebuffer,
1931 pRenderPassBegin->pClearValues);
1932
1933 genX(flush_pipeline_select_3d)(cmd_buffer);
1934
1935 genX(cmd_buffer_set_subpass)(cmd_buffer, pass->subpasses);
1936 }
1937
1938 void genX(CmdNextSubpass)(
1939 VkCommandBuffer commandBuffer,
1940 VkSubpassContents contents)
1941 {
1942 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1943
1944 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1945
1946 anv_cmd_buffer_resolve_subpass(cmd_buffer);
1947 genX(cmd_buffer_set_subpass)(cmd_buffer, cmd_buffer->state.subpass + 1);
1948 }
1949
1950 void genX(CmdEndRenderPass)(
1951 VkCommandBuffer commandBuffer)
1952 {
1953 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1954
1955 genX(cmd_buffer_emit_hz_op)(cmd_buffer, BLORP_HIZ_OP_DEPTH_RESOLVE);
1956 anv_cmd_buffer_resolve_subpass(cmd_buffer);
1957
1958 #ifndef NDEBUG
1959 anv_dump_add_framebuffer(cmd_buffer, cmd_buffer->state.framebuffer);
1960 #endif
1961 }
1962
1963 static void
1964 emit_ps_depth_count(struct anv_cmd_buffer *cmd_buffer,
1965 struct anv_bo *bo, uint32_t offset)
1966 {
1967 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1968 pc.DestinationAddressType = DAT_PPGTT;
1969 pc.PostSyncOperation = WritePSDepthCount;
1970 pc.DepthStallEnable = true;
1971 pc.Address = (struct anv_address) { bo, offset };
1972
1973 if (GEN_GEN == 9 && cmd_buffer->device->info.gt == 4)
1974 pc.CommandStreamerStallEnable = true;
1975 }
1976 }
1977
1978 static void
1979 emit_query_availability(struct anv_cmd_buffer *cmd_buffer,
1980 struct anv_bo *bo, uint32_t offset)
1981 {
1982 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1983 pc.DestinationAddressType = DAT_PPGTT;
1984 pc.PostSyncOperation = WriteImmediateData;
1985 pc.Address = (struct anv_address) { bo, offset };
1986 pc.ImmediateData = 1;
1987 }
1988 }
1989
1990 void genX(CmdBeginQuery)(
1991 VkCommandBuffer commandBuffer,
1992 VkQueryPool queryPool,
1993 uint32_t query,
1994 VkQueryControlFlags flags)
1995 {
1996 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1997 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
1998
1999 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
2000 * that the pipelining of the depth write breaks. What we see is that
2001 * samples from the render pass clear leaks into the first query
2002 * immediately after the clear. Doing a pipecontrol with a post-sync
2003 * operation and DepthStallEnable seems to work around the issue.
2004 */
2005 if (cmd_buffer->state.need_query_wa) {
2006 cmd_buffer->state.need_query_wa = false;
2007 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
2008 pc.DepthCacheFlushEnable = true;
2009 pc.DepthStallEnable = true;
2010 }
2011 }
2012
2013 switch (pool->type) {
2014 case VK_QUERY_TYPE_OCCLUSION:
2015 emit_ps_depth_count(cmd_buffer, &pool->bo,
2016 query * sizeof(struct anv_query_pool_slot));
2017 break;
2018
2019 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
2020 default:
2021 unreachable("");
2022 }
2023 }
2024
2025 void genX(CmdEndQuery)(
2026 VkCommandBuffer commandBuffer,
2027 VkQueryPool queryPool,
2028 uint32_t query)
2029 {
2030 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
2031 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
2032
2033 switch (pool->type) {
2034 case VK_QUERY_TYPE_OCCLUSION:
2035 emit_ps_depth_count(cmd_buffer, &pool->bo,
2036 query * sizeof(struct anv_query_pool_slot) + 8);
2037
2038 emit_query_availability(cmd_buffer, &pool->bo,
2039 query * sizeof(struct anv_query_pool_slot) + 16);
2040 break;
2041
2042 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
2043 default:
2044 unreachable("");
2045 }
2046 }
2047
2048 #define TIMESTAMP 0x2358
2049
2050 void genX(CmdWriteTimestamp)(
2051 VkCommandBuffer commandBuffer,
2052 VkPipelineStageFlagBits pipelineStage,
2053 VkQueryPool queryPool,
2054 uint32_t query)
2055 {
2056 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
2057 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
2058 uint32_t offset = query * sizeof(struct anv_query_pool_slot);
2059
2060 assert(pool->type == VK_QUERY_TYPE_TIMESTAMP);
2061
2062 switch (pipelineStage) {
2063 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
2064 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) {
2065 srm.RegisterAddress = TIMESTAMP;
2066 srm.MemoryAddress = (struct anv_address) { &pool->bo, offset };
2067 }
2068 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) {
2069 srm.RegisterAddress = TIMESTAMP + 4;
2070 srm.MemoryAddress = (struct anv_address) { &pool->bo, offset + 4 };
2071 }
2072 break;
2073
2074 default:
2075 /* Everything else is bottom-of-pipe */
2076 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
2077 pc.DestinationAddressType = DAT_PPGTT;
2078 pc.PostSyncOperation = WriteTimestamp;
2079 pc.Address = (struct anv_address) { &pool->bo, offset };
2080
2081 if (GEN_GEN == 9 && cmd_buffer->device->info.gt == 4)
2082 pc.CommandStreamerStallEnable = true;
2083 }
2084 break;
2085 }
2086
2087 emit_query_availability(cmd_buffer, &pool->bo, query + 16);
2088 }
2089
2090 #if GEN_GEN > 7 || GEN_IS_HASWELL
2091
2092 #define alu_opcode(v) __gen_uint((v), 20, 31)
2093 #define alu_operand1(v) __gen_uint((v), 10, 19)
2094 #define alu_operand2(v) __gen_uint((v), 0, 9)
2095 #define alu(opcode, operand1, operand2) \
2096 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
2097
2098 #define OPCODE_NOOP 0x000
2099 #define OPCODE_LOAD 0x080
2100 #define OPCODE_LOADINV 0x480
2101 #define OPCODE_LOAD0 0x081
2102 #define OPCODE_LOAD1 0x481
2103 #define OPCODE_ADD 0x100
2104 #define OPCODE_SUB 0x101
2105 #define OPCODE_AND 0x102
2106 #define OPCODE_OR 0x103
2107 #define OPCODE_XOR 0x104
2108 #define OPCODE_STORE 0x180
2109 #define OPCODE_STOREINV 0x580
2110
2111 #define OPERAND_R0 0x00
2112 #define OPERAND_R1 0x01
2113 #define OPERAND_R2 0x02
2114 #define OPERAND_R3 0x03
2115 #define OPERAND_R4 0x04
2116 #define OPERAND_SRCA 0x20
2117 #define OPERAND_SRCB 0x21
2118 #define OPERAND_ACCU 0x31
2119 #define OPERAND_ZF 0x32
2120 #define OPERAND_CF 0x33
2121
2122 #define CS_GPR(n) (0x2600 + (n) * 8)
2123
2124 static void
2125 emit_load_alu_reg_u64(struct anv_batch *batch, uint32_t reg,
2126 struct anv_bo *bo, uint32_t offset)
2127 {
2128 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
2129 lrm.RegisterAddress = reg,
2130 lrm.MemoryAddress = (struct anv_address) { bo, offset };
2131 }
2132 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
2133 lrm.RegisterAddress = reg + 4;
2134 lrm.MemoryAddress = (struct anv_address) { bo, offset + 4 };
2135 }
2136 }
2137
2138 static void
2139 store_query_result(struct anv_batch *batch, uint32_t reg,
2140 struct anv_bo *bo, uint32_t offset, VkQueryResultFlags flags)
2141 {
2142 anv_batch_emit(batch, GENX(MI_STORE_REGISTER_MEM), srm) {
2143 srm.RegisterAddress = reg;
2144 srm.MemoryAddress = (struct anv_address) { bo, offset };
2145 }
2146
2147 if (flags & VK_QUERY_RESULT_64_BIT) {
2148 anv_batch_emit(batch, GENX(MI_STORE_REGISTER_MEM), srm) {
2149 srm.RegisterAddress = reg + 4;
2150 srm.MemoryAddress = (struct anv_address) { bo, offset + 4 };
2151 }
2152 }
2153 }
2154
2155 void genX(CmdCopyQueryPoolResults)(
2156 VkCommandBuffer commandBuffer,
2157 VkQueryPool queryPool,
2158 uint32_t firstQuery,
2159 uint32_t queryCount,
2160 VkBuffer destBuffer,
2161 VkDeviceSize destOffset,
2162 VkDeviceSize destStride,
2163 VkQueryResultFlags flags)
2164 {
2165 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
2166 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
2167 ANV_FROM_HANDLE(anv_buffer, buffer, destBuffer);
2168 uint32_t slot_offset, dst_offset;
2169
2170 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
2171 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
2172 pc.CommandStreamerStallEnable = true;
2173 pc.StallAtPixelScoreboard = true;
2174 }
2175 }
2176
2177 dst_offset = buffer->offset + destOffset;
2178 for (uint32_t i = 0; i < queryCount; i++) {
2179
2180 slot_offset = (firstQuery + i) * sizeof(struct anv_query_pool_slot);
2181 switch (pool->type) {
2182 case VK_QUERY_TYPE_OCCLUSION:
2183 emit_load_alu_reg_u64(&cmd_buffer->batch,
2184 CS_GPR(0), &pool->bo, slot_offset);
2185 emit_load_alu_reg_u64(&cmd_buffer->batch,
2186 CS_GPR(1), &pool->bo, slot_offset + 8);
2187
2188 /* FIXME: We need to clamp the result for 32 bit. */
2189
2190 uint32_t *dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(MI_MATH));
2191 dw[1] = alu(OPCODE_LOAD, OPERAND_SRCA, OPERAND_R1);
2192 dw[2] = alu(OPCODE_LOAD, OPERAND_SRCB, OPERAND_R0);
2193 dw[3] = alu(OPCODE_SUB, 0, 0);
2194 dw[4] = alu(OPCODE_STORE, OPERAND_R2, OPERAND_ACCU);
2195 break;
2196
2197 case VK_QUERY_TYPE_TIMESTAMP:
2198 emit_load_alu_reg_u64(&cmd_buffer->batch,
2199 CS_GPR(2), &pool->bo, slot_offset);
2200 break;
2201
2202 default:
2203 unreachable("unhandled query type");
2204 }
2205
2206 store_query_result(&cmd_buffer->batch,
2207 CS_GPR(2), buffer->bo, dst_offset, flags);
2208
2209 if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
2210 emit_load_alu_reg_u64(&cmd_buffer->batch, CS_GPR(0),
2211 &pool->bo, slot_offset + 16);
2212 if (flags & VK_QUERY_RESULT_64_BIT)
2213 store_query_result(&cmd_buffer->batch,
2214 CS_GPR(0), buffer->bo, dst_offset + 8, flags);
2215 else
2216 store_query_result(&cmd_buffer->batch,
2217 CS_GPR(0), buffer->bo, dst_offset + 4, flags);
2218 }
2219
2220 dst_offset += destStride;
2221 }
2222 }
2223
2224 #else
2225 void genX(CmdCopyQueryPoolResults)(
2226 VkCommandBuffer commandBuffer,
2227 VkQueryPool queryPool,
2228 uint32_t firstQuery,
2229 uint32_t queryCount,
2230 VkBuffer destBuffer,
2231 VkDeviceSize destOffset,
2232 VkDeviceSize destStride,
2233 VkQueryResultFlags flags)
2234 {
2235 anv_finishme("Queries not yet supported on Ivy Bridge");
2236 }
2237 #endif