2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "common/gen_l3_config.h"
31 #include "genxml/gen_macros.h"
32 #include "genxml/genX_pack.h"
35 emit_lrm(struct anv_batch
*batch
,
36 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
54 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
56 struct anv_device
*device
= cmd_buffer
->device
;
58 /* XXX: Do we need this on more than just BDW? */
60 /* Emit a render target cache flush.
62 * This isn't documented anywhere in the PRM. However, it seems to be
63 * necessary prior to changing the surface state base adress. Without
64 * this, we get GPU hangs when using multi-level command buffers which
65 * clear depth, reset state base address, and then go render stuff.
67 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
68 pc
.RenderTargetCacheFlushEnable
= true;
72 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
73 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
74 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
75 sba
.GeneralStateBaseAddressModifyEnable
= true;
77 sba
.SurfaceStateBaseAddress
=
78 anv_cmd_buffer_surface_base_address(cmd_buffer
);
79 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
80 sba
.SurfaceStateBaseAddressModifyEnable
= true;
82 sba
.DynamicStateBaseAddress
=
83 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
84 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
85 sba
.DynamicStateBaseAddressModifyEnable
= true;
87 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
88 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
89 sba
.IndirectObjectBaseAddressModifyEnable
= true;
91 sba
.InstructionBaseAddress
=
92 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
93 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
94 sba
.InstructionBaseAddressModifyEnable
= true;
97 /* Broadwell requires that we specify a buffer size for a bunch of
98 * these fields. However, since we will be growing the BO's live, we
99 * just set them all to the maximum.
101 sba
.GeneralStateBufferSize
= 0xfffff;
102 sba
.GeneralStateBufferSizeModifyEnable
= true;
103 sba
.DynamicStateBufferSize
= 0xfffff;
104 sba
.DynamicStateBufferSizeModifyEnable
= true;
105 sba
.IndirectObjectBufferSize
= 0xfffff;
106 sba
.IndirectObjectBufferSizeModifyEnable
= true;
107 sba
.InstructionBufferSize
= 0xfffff;
108 sba
.InstructionBuffersizeModifyEnable
= true;
112 /* After re-setting the surface state base address, we have to do some
113 * cache flusing so that the sampler engine will pick up the new
114 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
115 * Shared Function > 3D Sampler > State > State Caching (page 96):
117 * Coherency with system memory in the state cache, like the texture
118 * cache is handled partially by software. It is expected that the
119 * command stream or shader will issue Cache Flush operation or
120 * Cache_Flush sampler message to ensure that the L1 cache remains
121 * coherent with system memory.
125 * Whenever the value of the Dynamic_State_Base_Addr,
126 * Surface_State_Base_Addr are altered, the L1 state cache must be
127 * invalidated to ensure the new surface or sampler state is fetched
128 * from system memory.
130 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
131 * which, according the PIPE_CONTROL instruction documentation in the
134 * Setting this bit is independent of any other bit in this packet.
135 * This bit controls the invalidation of the L1 and L2 state caches
136 * at the top of the pipe i.e. at the parsing time.
138 * Unfortunately, experimentation seems to indicate that state cache
139 * invalidation through a PIPE_CONTROL does nothing whatsoever in
140 * regards to surface state and binding tables. In stead, it seems that
141 * invalidating the texture cache is what is actually needed.
143 * XXX: As far as we have been able to determine through
144 * experimentation, shows that flush the texture cache appears to be
145 * sufficient. The theory here is that all of the sampling/rendering
146 * units cache the binding table in the texture cache. However, we have
147 * yet to be able to actually confirm this.
149 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
150 pc
.TextureCacheInvalidationEnable
= true;
155 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
156 struct anv_state state
,
157 struct anv_bo
*bo
, uint32_t offset
)
159 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
161 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
162 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
166 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
167 const struct anv_image_view
*iview
,
168 enum isl_aux_usage aux_usage
,
169 struct anv_state state
)
171 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
173 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
174 state
.offset
+ isl_dev
->ss
.addr_offset
,
175 iview
->bo
, iview
->offset
);
177 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
178 uint32_t aux_offset
= iview
->offset
+ iview
->image
->aux_surface
.offset
;
180 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
181 * used to store other information. This should be ok, however, because
182 * surface buffer addresses are always 4K page alinged.
184 assert((aux_offset
& 0xfff) == 0);
185 uint32_t *aux_addr_dw
= state
.map
+ isl_dev
->ss
.aux_addr_offset
;
186 aux_offset
+= *aux_addr_dw
& 0xfff;
188 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
189 state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
190 iview
->bo
, aux_offset
);
195 color_is_zero_one(VkClearColorValue value
, enum isl_format format
)
197 if (isl_format_has_int_channel(format
)) {
198 for (unsigned i
= 0; i
< 4; i
++) {
199 if (value
.int32
[i
] != 0 && value
.int32
[i
] != 1)
203 for (unsigned i
= 0; i
< 4; i
++) {
204 if (value
.float32
[i
] != 0.0f
&& value
.float32
[i
] != 1.0f
)
213 color_attachment_compute_aux_usage(struct anv_device
*device
,
214 struct anv_attachment_state
*att_state
,
215 struct anv_image_view
*iview
,
216 VkRect2D render_area
,
217 union isl_color_value
*fast_clear_color
)
219 if (iview
->image
->aux_surface
.isl
.size
== 0) {
220 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
221 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
222 att_state
->fast_clear
= false;
226 assert(iview
->image
->aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
228 att_state
->clear_color_is_zero_one
=
229 color_is_zero_one(att_state
->clear_value
.color
, iview
->isl
.format
);
231 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
232 /* Start off assuming fast clears are possible */
233 att_state
->fast_clear
= true;
235 /* Potentially, we could do partial fast-clears but doing so has crazy
236 * alignment restrictions. It's easier to just restrict to full size
237 * fast clears for now.
239 if (render_area
.offset
.x
!= 0 ||
240 render_area
.offset
.y
!= 0 ||
241 render_area
.extent
.width
!= iview
->extent
.width
||
242 render_area
.extent
.height
!= iview
->extent
.height
)
243 att_state
->fast_clear
= false;
246 /* On gen7, we can't do multi-LOD or multi-layer fast-clears. We
247 * technically can, but it comes with crazy restrictions that we
248 * don't want to deal with now.
250 if (iview
->isl
.base_level
> 0 ||
251 iview
->isl
.base_array_layer
> 0 ||
252 iview
->isl
.array_len
> 1)
253 att_state
->fast_clear
= false;
256 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
257 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
258 att_state
->fast_clear
= false;
260 if (att_state
->fast_clear
) {
261 memcpy(fast_clear_color
->u32
, att_state
->clear_value
.color
.uint32
,
262 sizeof(fast_clear_color
->u32
));
265 att_state
->fast_clear
= false;
268 if (isl_format_supports_lossless_compression(&device
->info
,
269 iview
->isl
.format
)) {
270 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
271 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_E
;
272 } else if (att_state
->fast_clear
) {
273 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
275 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
277 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
278 * setting is only allowed if Surface Format supported for Fast
279 * Clear. In addition, if the surface is bound to the sampling
280 * engine, Surface Format must be supported for Render Target
281 * Compression for surfaces bound to the sampling engine."
283 * In other words, we can't sample from a fast-cleared image if it
284 * doesn't also support color compression.
286 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
287 } else if (GEN_GEN
== 8) {
288 /* Broadwell can sample from fast-cleared images */
289 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
291 /* Ivy Bridge and Haswell cannot */
292 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
295 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
296 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
301 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
303 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
306 /* We only allocate input attachment states for color and depth surfaces.
307 * Stencil doesn't allow compression so we can just use the texture surface
308 * state from the view
310 return vk_format_is_color(att
->format
) || vk_format_has_depth(att
->format
);
313 static enum isl_aux_usage
314 layout_to_hiz_usage(VkImageLayout layout
)
317 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
318 return ISL_AUX_USAGE_HIZ
;
320 return ISL_AUX_USAGE_NONE
;
324 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
325 * the initial layout is undefined, the HiZ buffer and depth buffer will
326 * represent the same data at the end of this operation.
329 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
330 const struct anv_image
*image
,
331 VkImageLayout initial_layout
,
332 VkImageLayout final_layout
)
336 if (image
->aux_usage
!= ISL_AUX_USAGE_HIZ
)
339 const bool hiz_enabled
= layout_to_hiz_usage(initial_layout
) ==
341 const bool enable_hiz
= layout_to_hiz_usage(final_layout
) ==
344 /* We've already initialized the aux HiZ buffer at BindImageMemory time,
345 * so there's no need to perform a HIZ resolve or clear to avoid GPU hangs.
346 * This initial layout indicates that the user doesn't care about the data
347 * that's currently in the buffer, so no resolves are necessary.
349 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
)
352 if (hiz_enabled
== enable_hiz
) {
353 /* The same buffer will be used, no resolves are necessary */
354 } else if (hiz_enabled
&& !enable_hiz
) {
355 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, BLORP_HIZ_OP_DEPTH_RESOLVE
);
357 assert(!hiz_enabled
&& enable_hiz
);
358 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, BLORP_HIZ_OP_HIZ_RESOLVE
);
364 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
367 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
368 struct anv_render_pass
*pass
,
369 const VkRenderPassBeginInfo
*begin
)
371 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
372 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
374 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
376 if (pass
->attachment_count
== 0) {
377 state
->attachments
= NULL
;
381 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
382 pass
->attachment_count
*
383 sizeof(state
->attachments
[0]),
384 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
385 if (state
->attachments
== NULL
) {
386 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
390 bool need_null_state
= false;
391 unsigned num_states
= 0;
392 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
393 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
396 /* We need a null state for any depth-stencil-only subpasses.
397 * Importantly, this includes depth/stencil clears so we create one
398 * whenever we have depth or stencil
400 need_null_state
= true;
403 if (need_input_attachment_state(&pass
->attachments
[i
]))
406 num_states
+= need_null_state
;
408 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
409 state
->render_pass_states
=
410 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
411 num_states
* ss_stride
, isl_dev
->ss
.align
);
413 struct anv_state next_state
= state
->render_pass_states
;
414 next_state
.alloc_size
= isl_dev
->ss
.size
;
416 if (need_null_state
) {
417 state
->null_surface_state
= next_state
;
418 next_state
.offset
+= ss_stride
;
419 next_state
.map
+= ss_stride
;
422 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
423 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
424 state
->attachments
[i
].color_rt_state
= next_state
;
425 next_state
.offset
+= ss_stride
;
426 next_state
.map
+= ss_stride
;
429 if (need_input_attachment_state(&pass
->attachments
[i
])) {
430 state
->attachments
[i
].input_att_state
= next_state
;
431 next_state
.offset
+= ss_stride
;
432 next_state
.map
+= ss_stride
;
435 assert(next_state
.offset
== state
->render_pass_states
.offset
+
436 state
->render_pass_states
.alloc_size
);
439 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
440 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
442 if (need_null_state
) {
443 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
444 .SurfaceType
= SURFTYPE_NULL
,
445 .SurfaceArray
= framebuffer
->layers
> 0,
446 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
450 .TiledSurface
= true,
452 .Width
= framebuffer
->width
- 1,
453 .Height
= framebuffer
->height
- 1,
454 .Depth
= framebuffer
->layers
- 1,
455 .RenderTargetViewExtent
= framebuffer
->layers
- 1,
457 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
->null_surface_state
.map
,
461 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
462 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
463 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
464 VkImageAspectFlags clear_aspects
= 0;
466 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
467 /* color attachment */
468 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
469 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
472 /* depthstencil attachment */
473 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
474 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
475 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
477 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
478 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
479 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
483 state
->attachments
[i
].current_layout
= att
->initial_layout
;
484 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
486 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
488 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
489 assert(iview
->vk_format
== att
->format
);
491 union isl_color_value clear_color
= { .u32
= { 0, } };
492 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
493 color_attachment_compute_aux_usage(cmd_buffer
->device
,
494 &state
->attachments
[i
],
495 iview
, begin
->renderArea
,
498 struct isl_view view
= iview
->isl
;
499 view
.usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
500 isl_surf_fill_state(isl_dev
,
501 state
->attachments
[i
].color_rt_state
.map
,
502 .surf
= &iview
->image
->color_surface
.isl
,
504 .aux_surf
= &iview
->image
->aux_surface
.isl
,
505 .aux_usage
= state
->attachments
[i
].aux_usage
,
506 .clear_color
= clear_color
,
507 .mocs
= cmd_buffer
->device
->default_mocs
);
509 add_image_view_relocs(cmd_buffer
, iview
,
510 state
->attachments
[i
].aux_usage
,
511 state
->attachments
[i
].color_rt_state
);
513 state
->attachments
[i
].aux_usage
= iview
->image
->aux_usage
;
514 state
->attachments
[i
].input_aux_usage
= ISL_AUX_USAGE_NONE
;
517 if (need_input_attachment_state(&pass
->attachments
[i
])) {
518 const struct isl_surf
*surf
;
519 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
520 surf
= &iview
->image
->color_surface
.isl
;
522 surf
= &iview
->image
->depth_surface
.isl
;
525 struct isl_view view
= iview
->isl
;
526 view
.usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
527 isl_surf_fill_state(isl_dev
,
528 state
->attachments
[i
].input_att_state
.map
,
531 .aux_surf
= &iview
->image
->aux_surface
.isl
,
532 .aux_usage
= state
->attachments
[i
].input_aux_usage
,
533 .clear_color
= clear_color
,
534 .mocs
= cmd_buffer
->device
->default_mocs
);
536 add_image_view_relocs(cmd_buffer
, iview
,
537 state
->attachments
[i
].input_aux_usage
,
538 state
->attachments
[i
].input_att_state
);
542 if (!cmd_buffer
->device
->info
.has_llc
)
543 anv_state_clflush(state
->render_pass_states
);
548 genX(BeginCommandBuffer
)(
549 VkCommandBuffer commandBuffer
,
550 const VkCommandBufferBeginInfo
* pBeginInfo
)
552 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
554 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
555 * command buffer's state. Otherwise, we must *reset* its state. In both
558 * From the Vulkan 1.0 spec:
560 * If a command buffer is in the executable state and the command buffer
561 * was allocated from a command pool with the
562 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
563 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
564 * as if vkResetCommandBuffer had been called with
565 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
566 * the command buffer in the recording state.
568 anv_cmd_buffer_reset(cmd_buffer
);
570 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
572 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
573 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
575 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
577 if (cmd_buffer
->usage_flags
&
578 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
579 cmd_buffer
->state
.pass
=
580 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
581 cmd_buffer
->state
.subpass
=
582 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
583 cmd_buffer
->state
.framebuffer
= NULL
;
585 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, cmd_buffer
->state
.pass
,
588 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
595 genX(EndCommandBuffer
)(
596 VkCommandBuffer commandBuffer
)
598 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
600 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
602 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
608 genX(CmdExecuteCommands
)(
609 VkCommandBuffer commandBuffer
,
610 uint32_t commandBufferCount
,
611 const VkCommandBuffer
* pCmdBuffers
)
613 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
615 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
617 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
618 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
620 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
622 if (secondary
->usage_flags
&
623 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
624 /* If we're continuing a render pass from the primary, we need to
625 * copy the surface states for the current subpass into the storage
626 * we allocated for them in BeginCommandBuffer.
628 struct anv_bo
*ss_bo
= &primary
->device
->surface_state_block_pool
.bo
;
629 struct anv_state src_state
= primary
->state
.render_pass_states
;
630 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
631 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
633 genX(cmd_buffer_gpu_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
634 ss_bo
, src_state
.offset
,
635 src_state
.alloc_size
);
638 anv_cmd_buffer_add_secondary(primary
, secondary
);
641 /* Each of the secondary command buffers will use its own state base
642 * address. We need to re-emit state base address for the primary after
643 * all of the secondaries are done.
645 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
648 genX(cmd_buffer_emit_state_base_address
)(primary
);
651 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
652 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
653 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
656 * Program the hardware to use the specified L3 configuration.
659 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
660 const struct gen_l3_config
*cfg
)
663 if (cfg
== cmd_buffer
->state
.current_l3_config
)
666 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
667 fprintf(stderr
, "L3 config transition: ");
668 gen_dump_l3_config(cfg
, stderr
);
671 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
673 /* According to the hardware docs, the L3 partitioning can only be changed
674 * while the pipeline is completely drained and the caches are flushed,
675 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
677 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
678 pc
.DCFlushEnable
= true;
679 pc
.PostSyncOperation
= NoWrite
;
680 pc
.CommandStreamerStallEnable
= true;
683 /* ...followed by a second pipelined PIPE_CONTROL that initiates
684 * invalidation of the relevant caches. Note that because RO invalidation
685 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
686 * command is processed by the CS) we cannot combine it with the previous
687 * stalling flush as the hardware documentation suggests, because that
688 * would cause the CS to stall on previous rendering *after* RO
689 * invalidation and wouldn't prevent the RO caches from being polluted by
690 * concurrent rendering before the stall completes. This intentionally
691 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
692 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
693 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
694 * already guarantee that there is no concurrent GPGPU kernel execution
695 * (see SKL HSD 2132585).
697 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
698 pc
.TextureCacheInvalidationEnable
= true;
699 pc
.ConstantCacheInvalidationEnable
= true;
700 pc
.InstructionCacheInvalidateEnable
= true;
701 pc
.StateCacheInvalidationEnable
= true;
702 pc
.PostSyncOperation
= NoWrite
;
705 /* Now send a third stalling flush to make sure that invalidation is
706 * complete when the L3 configuration registers are modified.
708 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
709 pc
.DCFlushEnable
= true;
710 pc
.PostSyncOperation
= NoWrite
;
711 pc
.CommandStreamerStallEnable
= true;
716 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
719 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
720 .SLMEnable
= has_slm
,
721 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
722 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
723 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
724 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
726 /* Set up the L3 partitioning. */
727 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
731 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
732 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
734 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
736 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
739 assert(!cfg
->n
[GEN_L3P_ALL
]);
741 /* When enabled SLM only uses a portion of the L3 on half of the banks,
742 * the matching space on the remaining banks has to be allocated to a
743 * client (URB for all validated configurations) set to the
744 * lower-bandwidth 2-bank address hashing mode.
746 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
747 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
748 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
750 /* Minimum number of ways that can be allocated to the URB. */
751 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
752 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
754 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
755 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
756 .ConvertDC_UC
= !has_dc
,
757 .ConvertIS_UC
= !has_is
,
758 .ConvertC_UC
= !has_c
,
759 .ConvertT_UC
= !has_t
);
761 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
762 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
763 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
765 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
766 .SLMEnable
= has_slm
,
767 .URBLowBandwidth
= urb_low_bw
,
768 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
770 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
772 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
773 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
775 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
776 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
778 .CAllocation
= cfg
->n
[GEN_L3P_C
],
780 .TAllocation
= cfg
->n
[GEN_L3P_T
],
783 /* Set up the L3 partitioning. */
784 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
785 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
786 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
789 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
790 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
791 * them disabled to avoid crashing the system hard.
793 uint32_t scratch1
, chicken3
;
794 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
795 .L3AtomicDisable
= !has_dc
);
796 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
797 .L3AtomicDisableMask
= true,
798 .L3AtomicDisable
= !has_dc
);
799 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
800 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
806 cmd_buffer
->state
.current_l3_config
= cfg
;
810 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
812 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
814 /* Flushes are pipelined while invalidations are handled immediately.
815 * Therefore, if we're flushing anything then we need to schedule a stall
816 * before any invalidations can happen.
818 if (bits
& ANV_PIPE_FLUSH_BITS
)
819 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
821 /* If we're going to do an invalidate and we have a pending CS stall that
822 * has yet to be resolved, we do the CS stall now.
824 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
825 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
826 bits
|= ANV_PIPE_CS_STALL_BIT
;
827 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
830 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
831 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
832 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
833 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
834 pipe
.RenderTargetCacheFlushEnable
=
835 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
837 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
838 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
839 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
842 * According to the Broadwell documentation, any PIPE_CONTROL with the
843 * "Command Streamer Stall" bit set must also have another bit set,
844 * with five different options:
846 * - Render Target Cache Flush
847 * - Depth Cache Flush
848 * - Stall at Pixel Scoreboard
849 * - Post-Sync Operation
853 * I chose "Stall at Pixel Scoreboard" since that's what we use in
854 * mesa and it seems to work fine. The choice is fairly arbitrary.
856 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
857 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
858 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
859 pipe
.StallAtPixelScoreboard
= true;
862 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
865 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
866 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
867 pipe
.StateCacheInvalidationEnable
=
868 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
869 pipe
.ConstantCacheInvalidationEnable
=
870 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
871 pipe
.VFCacheInvalidationEnable
=
872 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
873 pipe
.TextureCacheInvalidationEnable
=
874 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
875 pipe
.InstructionCacheInvalidateEnable
=
876 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
879 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
882 cmd_buffer
->state
.pending_pipe_bits
= bits
;
885 void genX(CmdPipelineBarrier
)(
886 VkCommandBuffer commandBuffer
,
887 VkPipelineStageFlags srcStageMask
,
888 VkPipelineStageFlags destStageMask
,
890 uint32_t memoryBarrierCount
,
891 const VkMemoryBarrier
* pMemoryBarriers
,
892 uint32_t bufferMemoryBarrierCount
,
893 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
894 uint32_t imageMemoryBarrierCount
,
895 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
897 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
900 /* XXX: Right now, we're really dumb and just flush whatever categories
901 * the app asks for. One of these days we may make this a bit better
902 * but right now that's all the hardware allows for in most areas.
904 VkAccessFlags src_flags
= 0;
905 VkAccessFlags dst_flags
= 0;
907 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
908 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
909 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
912 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
913 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
914 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
917 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
918 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
919 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
922 enum anv_pipe_bits pipe_bits
= 0;
924 for_each_bit(b
, src_flags
) {
925 switch ((VkAccessFlagBits
)(1 << b
)) {
926 case VK_ACCESS_SHADER_WRITE_BIT
:
927 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
929 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
930 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
932 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
933 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
935 case VK_ACCESS_TRANSFER_WRITE_BIT
:
936 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
937 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
940 break; /* Nothing to do */
944 for_each_bit(b
, dst_flags
) {
945 switch ((VkAccessFlagBits
)(1 << b
)) {
946 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
947 case VK_ACCESS_INDEX_READ_BIT
:
948 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
949 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
951 case VK_ACCESS_UNIFORM_READ_BIT
:
952 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
953 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
955 case VK_ACCESS_SHADER_READ_BIT
:
956 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
957 case VK_ACCESS_TRANSFER_READ_BIT
:
958 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
961 break; /* Nothing to do */
965 cmd_buffer
->state
.pending_pipe_bits
|= pipe_bits
;
969 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
971 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
973 /* In order to avoid thrash, we assume that vertex and fragment stages
974 * always exist. In the rare case where one is missing *and* the other
975 * uses push concstants, this may be suboptimal. However, avoiding stalls
976 * seems more important.
978 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
980 if (stages
== cmd_buffer
->state
.push_constant_stages
)
984 const unsigned push_constant_kb
= 32;
986 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
988 const unsigned push_constant_kb
= 16;
991 const unsigned num_stages
=
992 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
993 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
995 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
996 * units of 2KB. Incidentally, these are the same platforms that have
997 * 32KB worth of push constant space.
999 if (push_constant_kb
== 32)
1000 size_per_stage
&= ~1u;
1002 uint32_t kb_used
= 0;
1003 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1004 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1005 anv_batch_emit(&cmd_buffer
->batch
,
1006 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1007 alloc
._3DCommandSubOpcode
= 18 + i
;
1008 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1009 alloc
.ConstantBufferSize
= push_size
;
1011 kb_used
+= push_size
;
1014 anv_batch_emit(&cmd_buffer
->batch
,
1015 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1016 alloc
.ConstantBufferOffset
= kb_used
;
1017 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1020 cmd_buffer
->state
.push_constant_stages
= stages
;
1022 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1024 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1025 * the next 3DPRIMITIVE command after programming the
1026 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1028 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1029 * pipeline setup, we need to dirty push constants.
1031 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1035 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1036 gl_shader_stage stage
,
1037 struct anv_state
*bt_state
)
1039 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1040 struct anv_pipeline
*pipeline
;
1041 uint32_t bias
, state_offset
;
1044 case MESA_SHADER_COMPUTE
:
1045 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1049 pipeline
= cmd_buffer
->state
.pipeline
;
1054 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1055 *bt_state
= (struct anv_state
) { 0, };
1059 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1060 if (bias
+ map
->surface_count
== 0) {
1061 *bt_state
= (struct anv_state
) { 0, };
1065 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1066 bias
+ map
->surface_count
,
1068 uint32_t *bt_map
= bt_state
->map
;
1070 if (bt_state
->map
== NULL
)
1071 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1073 if (stage
== MESA_SHADER_COMPUTE
&&
1074 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
1075 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
1076 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
1078 struct anv_state surface_state
;
1080 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1082 const enum isl_format format
=
1083 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1084 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1085 format
, bo_offset
, 12, 1);
1087 bt_map
[0] = surface_state
.offset
+ state_offset
;
1088 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1091 if (map
->surface_count
== 0)
1094 if (map
->image_count
> 0) {
1096 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1097 if (result
!= VK_SUCCESS
)
1100 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1104 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1105 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1107 struct anv_state surface_state
;
1109 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1110 /* Color attachment binding */
1111 assert(stage
== MESA_SHADER_FRAGMENT
);
1112 assert(binding
->binding
== 0);
1113 if (binding
->index
< subpass
->color_count
) {
1114 const unsigned att
= subpass
->color_attachments
[binding
->index
];
1115 surface_state
= cmd_buffer
->state
.attachments
[att
].color_rt_state
;
1117 surface_state
= cmd_buffer
->state
.null_surface_state
;
1120 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1124 struct anv_descriptor_set
*set
=
1125 cmd_buffer
->state
.descriptors
[binding
->set
];
1126 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1127 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1129 switch (desc
->type
) {
1130 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1131 /* Nothing for us to do here */
1134 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1135 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
1136 surface_state
= desc
->image_view
->sampler_surface_state
;
1137 assert(surface_state
.alloc_size
);
1138 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1139 desc
->image_view
->image
->aux_usage
,
1143 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1144 assert(stage
== MESA_SHADER_FRAGMENT
);
1145 if (desc
->image_view
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
1146 /* For stencil input attachments, we treat it like any old texture
1147 * that a user may have bound.
1149 surface_state
= desc
->image_view
->sampler_surface_state
;
1150 assert(surface_state
.alloc_size
);
1151 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1152 desc
->image_view
->image
->aux_usage
,
1155 /* For depth and color input attachments, we create the surface
1156 * state at vkBeginRenderPass time so that we can include aux
1157 * and clear color information.
1159 assert(binding
->input_attachment_index
< subpass
->input_count
);
1160 const unsigned subpass_att
= binding
->input_attachment_index
;
1161 const unsigned att
= subpass
->input_attachments
[subpass_att
];
1162 surface_state
= cmd_buffer
->state
.attachments
[att
].input_att_state
;
1166 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1167 surface_state
= desc
->image_view
->storage_surface_state
;
1168 assert(surface_state
.alloc_size
);
1169 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1170 desc
->image_view
->image
->aux_usage
,
1173 struct brw_image_param
*image_param
=
1174 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1176 *image_param
= desc
->image_view
->storage_image_param
;
1177 image_param
->surface_idx
= bias
+ s
;
1181 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
1182 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
1183 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
1184 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
1185 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
1186 surface_state
= desc
->buffer_view
->surface_state
;
1187 assert(surface_state
.alloc_size
);
1188 add_surface_state_reloc(cmd_buffer
, surface_state
,
1189 desc
->buffer_view
->bo
,
1190 desc
->buffer_view
->offset
);
1193 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
1194 surface_state
= desc
->buffer_view
->storage_surface_state
;
1195 assert(surface_state
.alloc_size
);
1196 add_surface_state_reloc(cmd_buffer
, surface_state
,
1197 desc
->buffer_view
->bo
,
1198 desc
->buffer_view
->offset
);
1200 struct brw_image_param
*image_param
=
1201 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1203 *image_param
= desc
->buffer_view
->storage_image_param
;
1204 image_param
->surface_idx
= bias
+ s
;
1208 assert(!"Invalid descriptor type");
1212 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1214 assert(image
== map
->image_count
);
1217 if (!cmd_buffer
->device
->info
.has_llc
)
1218 anv_state_clflush(*bt_state
);
1224 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1225 gl_shader_stage stage
,
1226 struct anv_state
*state
)
1228 struct anv_pipeline
*pipeline
;
1230 if (stage
== MESA_SHADER_COMPUTE
)
1231 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1233 pipeline
= cmd_buffer
->state
.pipeline
;
1235 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1236 *state
= (struct anv_state
) { 0, };
1240 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1241 if (map
->sampler_count
== 0) {
1242 *state
= (struct anv_state
) { 0, };
1246 uint32_t size
= map
->sampler_count
* 16;
1247 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1249 if (state
->map
== NULL
)
1250 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1252 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1253 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1254 struct anv_descriptor_set
*set
=
1255 cmd_buffer
->state
.descriptors
[binding
->set
];
1256 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1257 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1259 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1260 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1263 struct anv_sampler
*sampler
= desc
->sampler
;
1265 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1266 * happens to be zero.
1268 if (sampler
== NULL
)
1271 memcpy(state
->map
+ (s
* 16),
1272 sampler
->state
, sizeof(sampler
->state
));
1275 if (!cmd_buffer
->device
->info
.has_llc
)
1276 anv_state_clflush(*state
);
1282 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1284 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1285 cmd_buffer
->state
.pipeline
->active_stages
;
1287 VkResult result
= VK_SUCCESS
;
1288 anv_foreach_stage(s
, dirty
) {
1289 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1290 if (result
!= VK_SUCCESS
)
1292 result
= emit_binding_table(cmd_buffer
, s
,
1293 &cmd_buffer
->state
.binding_tables
[s
]);
1294 if (result
!= VK_SUCCESS
)
1298 if (result
!= VK_SUCCESS
) {
1299 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1301 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1302 assert(result
== VK_SUCCESS
);
1304 /* Re-emit state base addresses so we get the new surface state base
1305 * address before we start emitting binding tables etc.
1307 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1309 /* Re-emit all active binding tables */
1310 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
1311 anv_foreach_stage(s
, dirty
) {
1312 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1313 if (result
!= VK_SUCCESS
)
1315 result
= emit_binding_table(cmd_buffer
, s
,
1316 &cmd_buffer
->state
.binding_tables
[s
]);
1317 if (result
!= VK_SUCCESS
)
1322 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1328 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1331 static const uint32_t sampler_state_opcodes
[] = {
1332 [MESA_SHADER_VERTEX
] = 43,
1333 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1334 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1335 [MESA_SHADER_GEOMETRY
] = 46,
1336 [MESA_SHADER_FRAGMENT
] = 47,
1337 [MESA_SHADER_COMPUTE
] = 0,
1340 static const uint32_t binding_table_opcodes
[] = {
1341 [MESA_SHADER_VERTEX
] = 38,
1342 [MESA_SHADER_TESS_CTRL
] = 39,
1343 [MESA_SHADER_TESS_EVAL
] = 40,
1344 [MESA_SHADER_GEOMETRY
] = 41,
1345 [MESA_SHADER_FRAGMENT
] = 42,
1346 [MESA_SHADER_COMPUTE
] = 0,
1349 anv_foreach_stage(s
, stages
) {
1350 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1351 anv_batch_emit(&cmd_buffer
->batch
,
1352 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1353 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1354 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1358 /* Always emit binding table pointers if we're asked to, since on SKL
1359 * this is what flushes push constants. */
1360 anv_batch_emit(&cmd_buffer
->batch
,
1361 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1362 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1363 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1369 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1371 static const uint32_t push_constant_opcodes
[] = {
1372 [MESA_SHADER_VERTEX
] = 21,
1373 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1374 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1375 [MESA_SHADER_GEOMETRY
] = 22,
1376 [MESA_SHADER_FRAGMENT
] = 23,
1377 [MESA_SHADER_COMPUTE
] = 0,
1380 VkShaderStageFlags flushed
= 0;
1382 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
1383 if (stage
== MESA_SHADER_COMPUTE
)
1386 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1388 if (state
.offset
== 0) {
1389 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1390 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1392 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1393 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1394 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1396 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
1397 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1399 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
1400 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1406 flushed
|= mesa_to_vk_shader_stage(stage
);
1409 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1415 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1417 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1420 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1422 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1424 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1426 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1429 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1430 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1432 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1433 GENX(3DSTATE_VERTEX_BUFFERS
));
1435 for_each_bit(vb
, vb_emit
) {
1436 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1437 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1439 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1440 .VertexBufferIndex
= vb
,
1443 .MemoryObjectControlState
= GENX(MOCS
),
1445 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1446 .InstanceDataStepRate
= 1,
1447 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1450 .AddressModifyEnable
= true,
1451 .BufferPitch
= pipeline
->binding_stride
[vb
],
1452 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1455 .BufferSize
= buffer
->size
- offset
1457 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1461 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1466 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1468 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1469 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1471 /* The exact descriptor layout is pulled from the pipeline, so we need
1472 * to re-emit binding tables on every pipeline change.
1474 cmd_buffer
->state
.descriptors_dirty
|=
1475 cmd_buffer
->state
.pipeline
->active_stages
;
1477 /* If the pipeline changed, we may need to re-allocate push constant
1480 cmd_buffer_alloc_push_constants(cmd_buffer
);
1484 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1485 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1486 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1488 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1489 * stall needs to be sent just prior to any 3DSTATE_VS,
1490 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1491 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1492 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1493 * PIPE_CONTROL needs to be sent before any combination of VS
1494 * associated 3DSTATE."
1496 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1497 pc
.DepthStallEnable
= true;
1498 pc
.PostSyncOperation
= WriteImmediateData
;
1500 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1505 /* Render targets live in the same binding table as fragment descriptors */
1506 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1507 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1509 /* We emit the binding tables and sampler tables first, then emit push
1510 * constants and then finally emit binding table and sampler table
1511 * pointers. It has to happen in this order, since emitting the binding
1512 * tables may change the push constants (in case of storage images). After
1513 * emitting push constants, on SKL+ we have to emit the corresponding
1514 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1517 if (cmd_buffer
->state
.descriptors_dirty
)
1518 dirty
= flush_descriptor_sets(cmd_buffer
);
1520 if (cmd_buffer
->state
.push_constants_dirty
) {
1522 /* On Sky Lake and later, the binding table pointers commands are
1523 * what actually flush the changes to push constant state so we need
1524 * to dirty them so they get re-emitted below.
1526 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1528 cmd_buffer_flush_push_constants(cmd_buffer
);
1533 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1535 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1536 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1538 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1539 ANV_CMD_DIRTY_PIPELINE
)) {
1540 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1541 pipeline
->depth_clamp_enable
);
1544 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1545 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1547 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1549 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1553 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1554 struct anv_bo
*bo
, uint32_t offset
)
1556 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1557 GENX(3DSTATE_VERTEX_BUFFERS
));
1559 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1560 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1561 .VertexBufferIndex
= 32, /* Reserved for this */
1562 .AddressModifyEnable
= true,
1565 .MemoryObjectControlState
= GENX(MOCS
),
1566 .BufferStartingAddress
= { bo
, offset
},
1569 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1570 .BufferStartingAddress
= { bo
, offset
},
1571 .EndAddress
= { bo
, offset
+ 8 },
1577 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1578 uint32_t base_vertex
, uint32_t base_instance
)
1580 struct anv_state id_state
=
1581 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1583 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1584 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1586 if (!cmd_buffer
->device
->info
.has_llc
)
1587 anv_state_clflush(id_state
);
1589 emit_base_vertex_instance_bo(cmd_buffer
,
1590 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
1594 VkCommandBuffer commandBuffer
,
1595 uint32_t vertexCount
,
1596 uint32_t instanceCount
,
1597 uint32_t firstVertex
,
1598 uint32_t firstInstance
)
1600 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1601 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1602 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1604 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1606 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1607 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1609 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1610 prim
.VertexAccessType
= SEQUENTIAL
;
1611 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1612 prim
.VertexCountPerInstance
= vertexCount
;
1613 prim
.StartVertexLocation
= firstVertex
;
1614 prim
.InstanceCount
= instanceCount
;
1615 prim
.StartInstanceLocation
= firstInstance
;
1616 prim
.BaseVertexLocation
= 0;
1620 void genX(CmdDrawIndexed
)(
1621 VkCommandBuffer commandBuffer
,
1622 uint32_t indexCount
,
1623 uint32_t instanceCount
,
1624 uint32_t firstIndex
,
1625 int32_t vertexOffset
,
1626 uint32_t firstInstance
)
1628 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1629 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1630 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1632 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1634 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1635 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1637 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1638 prim
.VertexAccessType
= RANDOM
;
1639 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1640 prim
.VertexCountPerInstance
= indexCount
;
1641 prim
.StartVertexLocation
= firstIndex
;
1642 prim
.InstanceCount
= instanceCount
;
1643 prim
.StartInstanceLocation
= firstInstance
;
1644 prim
.BaseVertexLocation
= vertexOffset
;
1648 /* Auto-Draw / Indirect Registers */
1649 #define GEN7_3DPRIM_END_OFFSET 0x2420
1650 #define GEN7_3DPRIM_START_VERTEX 0x2430
1651 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1652 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1653 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1654 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1656 void genX(CmdDrawIndirect
)(
1657 VkCommandBuffer commandBuffer
,
1659 VkDeviceSize offset
,
1663 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1664 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1665 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1666 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1667 struct anv_bo
*bo
= buffer
->bo
;
1668 uint32_t bo_offset
= buffer
->offset
+ offset
;
1670 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1672 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1673 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
1675 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1676 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1677 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1678 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
1679 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
1681 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1682 prim
.IndirectParameterEnable
= true;
1683 prim
.VertexAccessType
= SEQUENTIAL
;
1684 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1688 void genX(CmdDrawIndexedIndirect
)(
1689 VkCommandBuffer commandBuffer
,
1691 VkDeviceSize offset
,
1695 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1696 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1697 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1698 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1699 struct anv_bo
*bo
= buffer
->bo
;
1700 uint32_t bo_offset
= buffer
->offset
+ offset
;
1702 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1704 /* TODO: We need to stomp base vertex to 0 somehow */
1705 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1706 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
1708 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1709 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1710 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1711 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
1712 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
1714 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1715 prim
.IndirectParameterEnable
= true;
1716 prim
.VertexAccessType
= RANDOM
;
1717 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1722 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
1724 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1725 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
1728 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1729 if (result
!= VK_SUCCESS
) {
1730 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1731 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1732 assert(result
== VK_SUCCESS
);
1734 /* Re-emit state base addresses so we get the new surface state base
1735 * address before we start emitting binding tables etc.
1737 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1739 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1740 assert(result
== VK_SUCCESS
);
1743 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
1744 assert(result
== VK_SUCCESS
);
1746 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
1747 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1748 .BindingTablePointer
= surfaces
.offset
,
1749 .SamplerStatePointer
= samplers
.offset
,
1751 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
1753 struct anv_state state
=
1754 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
1755 pipeline
->interface_descriptor_data
,
1756 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
1759 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
1760 anv_batch_emit(&cmd_buffer
->batch
,
1761 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
1762 mid
.InterfaceDescriptorTotalLength
= size
;
1763 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
1770 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1772 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1773 MAYBE_UNUSED VkResult result
;
1775 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
1777 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1779 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
1781 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1782 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
1784 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
1785 * the only bits that are changed are scoreboard related: Scoreboard
1786 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
1787 * these scoreboard related states, a MEDIA_STATE_FLUSH is
1790 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1791 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1793 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1796 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
1797 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
1798 /* FIXME: figure out descriptors for gen7 */
1799 result
= flush_compute_descriptor_set(cmd_buffer
);
1800 assert(result
== VK_SUCCESS
);
1801 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
1804 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
1805 struct anv_state push_state
=
1806 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
1808 if (push_state
.alloc_size
) {
1809 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
1810 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
1811 curbe
.CURBEDataStartAddress
= push_state
.offset
;
1816 cmd_buffer
->state
.compute_dirty
= 0;
1818 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1824 verify_cmd_parser(const struct anv_device
*device
,
1825 int required_version
,
1826 const char *function
)
1828 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
1829 vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
1830 "cmd parser version %d is required for %s",
1831 required_version
, function
);
1840 void genX(CmdDispatch
)(
1841 VkCommandBuffer commandBuffer
,
1846 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1847 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1848 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1850 if (prog_data
->uses_num_work_groups
) {
1851 struct anv_state state
=
1852 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
1853 uint32_t *sizes
= state
.map
;
1857 if (!cmd_buffer
->device
->info
.has_llc
)
1858 anv_state_clflush(state
);
1859 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
1860 cmd_buffer
->state
.num_workgroups_bo
=
1861 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
1864 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1866 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
1867 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1868 ggw
.ThreadDepthCounterMaximum
= 0;
1869 ggw
.ThreadHeightCounterMaximum
= 0;
1870 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1871 ggw
.ThreadGroupIDXDimension
= x
;
1872 ggw
.ThreadGroupIDYDimension
= y
;
1873 ggw
.ThreadGroupIDZDimension
= z
;
1874 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1875 ggw
.BottomExecutionMask
= 0xffffffff;
1878 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1881 #define GPGPU_DISPATCHDIMX 0x2500
1882 #define GPGPU_DISPATCHDIMY 0x2504
1883 #define GPGPU_DISPATCHDIMZ 0x2508
1885 #define MI_PREDICATE_SRC0 0x2400
1886 #define MI_PREDICATE_SRC1 0x2408
1888 void genX(CmdDispatchIndirect
)(
1889 VkCommandBuffer commandBuffer
,
1891 VkDeviceSize offset
)
1893 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1894 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1895 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1896 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1897 struct anv_bo
*bo
= buffer
->bo
;
1898 uint32_t bo_offset
= buffer
->offset
+ offset
;
1899 struct anv_batch
*batch
= &cmd_buffer
->batch
;
1902 /* Linux 4.4 added command parser version 5 which allows the GPGPU
1903 * indirect dispatch registers to be written.
1905 if (!verify_cmd_parser(cmd_buffer
->device
, 5, "vkCmdDispatchIndirect"))
1909 if (prog_data
->uses_num_work_groups
) {
1910 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
1911 cmd_buffer
->state
.num_workgroups_bo
= bo
;
1914 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1916 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
1917 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
1918 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
1921 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
1922 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
1923 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
1924 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
1926 /* Load compute_dispatch_indirect_x_size into SRC0 */
1927 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
1929 /* predicate = (compute_dispatch_indirect_x_size == 0); */
1930 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1931 mip
.LoadOperation
= LOAD_LOAD
;
1932 mip
.CombineOperation
= COMBINE_SET
;
1933 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1936 /* Load compute_dispatch_indirect_y_size into SRC0 */
1937 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
1939 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
1940 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1941 mip
.LoadOperation
= LOAD_LOAD
;
1942 mip
.CombineOperation
= COMBINE_OR
;
1943 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1946 /* Load compute_dispatch_indirect_z_size into SRC0 */
1947 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
1949 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
1950 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1951 mip
.LoadOperation
= LOAD_LOAD
;
1952 mip
.CombineOperation
= COMBINE_OR
;
1953 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1956 /* predicate = !predicate; */
1957 #define COMPARE_FALSE 1
1958 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1959 mip
.LoadOperation
= LOAD_LOADINV
;
1960 mip
.CombineOperation
= COMBINE_OR
;
1961 mip
.CompareOperation
= COMPARE_FALSE
;
1965 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
1966 ggw
.IndirectParameterEnable
= true;
1967 ggw
.PredicateEnable
= GEN_GEN
<= 7;
1968 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1969 ggw
.ThreadDepthCounterMaximum
= 0;
1970 ggw
.ThreadHeightCounterMaximum
= 0;
1971 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1972 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1973 ggw
.BottomExecutionMask
= 0xffffffff;
1976 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1980 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
1983 #if GEN_GEN >= 8 && GEN_GEN < 10
1984 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
1986 * Software must clear the COLOR_CALC_STATE Valid field in
1987 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
1988 * with Pipeline Select set to GPGPU.
1990 * The internal hardware docs recommend the same workaround for Gen9
1993 if (pipeline
== GPGPU
)
1994 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
1996 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
1997 * PIPELINE_SELECT [DevBWR+]":
2001 * Software must ensure all the write caches are flushed through a
2002 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
2003 * command to invalidate read only caches prior to programming
2004 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
2006 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2007 pc
.RenderTargetCacheFlushEnable
= true;
2008 pc
.DepthCacheFlushEnable
= true;
2009 pc
.DCFlushEnable
= true;
2010 pc
.PostSyncOperation
= NoWrite
;
2011 pc
.CommandStreamerStallEnable
= true;
2014 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2015 pc
.TextureCacheInvalidationEnable
= true;
2016 pc
.ConstantCacheInvalidationEnable
= true;
2017 pc
.StateCacheInvalidationEnable
= true;
2018 pc
.InstructionCacheInvalidateEnable
= true;
2019 pc
.PostSyncOperation
= NoWrite
;
2025 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
2027 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
2028 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
2030 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2034 ps
.PipelineSelection
= _3D
;
2037 cmd_buffer
->state
.current_pipeline
= _3D
;
2042 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
2044 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
2045 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
2047 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2051 ps
.PipelineSelection
= GPGPU
;
2054 cmd_buffer
->state
.current_pipeline
= GPGPU
;
2059 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
2064 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
2066 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
2067 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
2068 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
2069 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
2070 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
2071 * Depth Flush Bit set, followed by another pipelined depth stall
2072 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
2073 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
2074 * via a preceding MI_FLUSH)."
2076 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2077 pipe
.DepthStallEnable
= true;
2079 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2080 pipe
.DepthCacheFlushEnable
= true;
2082 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2083 pipe
.DepthStallEnable
= true;
2088 depth_stencil_surface_type(enum isl_surf_dim dim
)
2091 case ISL_SURF_DIM_1D
:
2093 /* From the Sky Lake PRM, 3DSTATAE_DEPTH_BUFFER::SurfaceType
2095 * Programming Notes:
2096 * The Surface Type of the depth buffer must be the same as the
2097 * Surface Type of the render target(s) (defined in
2098 * SURFACE_STATE), unless either the depth buffer or render
2099 * targets are SURFTYPE_NULL (see exception below for SKL). 1D
2100 * surface type not allowed for depth surface and stencil surface.
2103 * If depth/stencil is enabled with 1D render target,
2104 * depth/stencil surface type needs to be set to 2D surface type
2105 * and height set to 1. Depth will use (legacy) TileY and stencil
2106 * will use TileW. For this case only, the Surface Type of the
2107 * depth buffer can be 2D while the Surface Type of the render
2108 * target(s) are 1D, representing an exception to a programming
2115 case ISL_SURF_DIM_2D
:
2117 case ISL_SURF_DIM_3D
:
2119 /* The Sky Lake docs list the value for 3D as "Reserved". However,
2120 * they have the exact same layout as 2D arrays on gen9+, so we can
2128 unreachable("Invalid surface dimension");
2133 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
2135 struct anv_device
*device
= cmd_buffer
->device
;
2136 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
2137 const struct anv_image_view
*iview
=
2138 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2139 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
2140 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
2141 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2142 const bool has_hiz
= image
!= NULL
&&
2143 cmd_buffer
->state
.attachments
[ds
].aux_usage
== ISL_AUX_USAGE_HIZ
;
2144 const bool has_stencil
=
2145 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
2147 /* FIXME: Implement the PMA stall W/A */
2148 /* FIXME: Width and Height are wrong */
2150 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
2152 /* Emit 3DSTATE_DEPTH_BUFFER */
2154 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2156 depth_stencil_surface_type(image
->depth_surface
.isl
.dim
);
2157 db
.DepthWriteEnable
= true;
2158 db
.StencilWriteEnable
= has_stencil
;
2159 db
.HierarchicalDepthBufferEnable
= has_hiz
;
2161 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
2162 &image
->depth_surface
.isl
);
2164 db
.SurfaceBaseAddress
= (struct anv_address
) {
2166 .offset
= image
->offset
+ image
->depth_surface
.offset
,
2168 db
.DepthBufferObjectControlState
= GENX(MOCS
);
2170 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
2171 db
.Height
= image
->extent
.height
- 1;
2172 db
.Width
= image
->extent
.width
- 1;
2173 db
.LOD
= iview
->isl
.base_level
;
2174 db
.MinimumArrayElement
= iview
->isl
.base_array_layer
;
2176 assert(image
->depth_surface
.isl
.dim
!= ISL_SURF_DIM_3D
);
2178 db
.RenderTargetViewExtent
=
2179 iview
->isl
.array_len
- iview
->isl
.base_array_layer
- 1;
2183 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2;
2187 /* Even when no depth buffer is present, the hardware requires that
2188 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
2190 * If a null depth buffer is bound, the driver must instead bind depth as:
2191 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
2192 * 3DSTATE_DEPTH.Width = 1
2193 * 3DSTATE_DEPTH.Height = 1
2194 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
2195 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
2196 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
2197 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
2198 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
2200 * The PRM is wrong, though. The width and height must be programmed to
2201 * actual framebuffer's width and height, even when neither depth buffer
2202 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
2203 * be combined with a stencil buffer so we use D32_FLOAT instead.
2205 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2208 depth_stencil_surface_type(image
->stencil_surface
.isl
.dim
);
2210 db
.SurfaceType
= SURFTYPE_2D
;
2212 db
.SurfaceFormat
= D32_FLOAT
;
2213 db
.Width
= MAX2(fb
->width
, 1) - 1;
2214 db
.Height
= MAX2(fb
->height
, 1) - 1;
2215 db
.StencilWriteEnable
= has_stencil
;
2220 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
) {
2221 hdb
.HierarchicalDepthBufferObjectControlState
= GENX(MOCS
);
2222 hdb
.SurfacePitch
= image
->aux_surface
.isl
.row_pitch
- 1;
2223 hdb
.SurfaceBaseAddress
= (struct anv_address
) {
2225 .offset
= image
->offset
+ image
->aux_surface
.offset
,
2228 /* From the SKL PRM Vol2a:
2230 * The interpretation of this field is dependent on Surface Type
2232 * - SURFTYPE_1D: distance in pixels between array slices
2233 * - SURFTYPE_2D/CUBE: distance in rows between array slices
2234 * - SURFTYPE_3D: distance in rows between R - slices
2236 * Unfortunately, the docs aren't 100% accurate here. They fail to
2237 * mention that the 1-D rule only applies to linear 1-D images.
2238 * Since depth and HiZ buffers are always tiled, they are treated as
2239 * 2-D images. Prior to Sky Lake, this field is always in rows.
2242 isl_surf_get_array_pitch_sa_rows(&image
->aux_surface
.isl
) >> 2;
2246 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
);
2249 /* Emit 3DSTATE_STENCIL_BUFFER */
2251 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
2252 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2253 sb
.StencilBufferEnable
= true;
2255 sb
.StencilBufferObjectControlState
= GENX(MOCS
);
2257 sb
.SurfacePitch
= image
->stencil_surface
.isl
.row_pitch
- 1;
2260 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2;
2262 sb
.SurfaceBaseAddress
= (struct anv_address
) {
2264 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
2268 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
2271 /* From the IVB PRM Vol2P1, 11.5.5.4 3DSTATE_CLEAR_PARAMS:
2273 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along with
2274 * the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
2275 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)
2277 * Testing also shows that some variant of this restriction may exist HSW+.
2278 * On BDW+, it is not possible to emit 2 of these packets consecutively when
2279 * both have DepthClearValueValid set. An analysis of such state programming
2280 * on SKL showed that the GPU doesn't register the latter packet's clear
2283 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
) {
2285 cp
.DepthClearValueValid
= true;
2286 cp
.DepthClearValue
= ANV_HZ_FC_VAL
;
2292 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
2293 struct anv_subpass
*subpass
)
2295 cmd_buffer
->state
.subpass
= subpass
;
2297 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
2299 const struct anv_image_view
*iview
=
2300 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2303 anv_gen8_hiz_op_resolve(cmd_buffer
, iview
->image
,
2304 BLORP_HIZ_OP_HIZ_RESOLVE
);
2307 cmd_buffer_emit_depth_stencil(cmd_buffer
);
2309 anv_cmd_buffer_clear_subpass(cmd_buffer
);
2312 void genX(CmdBeginRenderPass
)(
2313 VkCommandBuffer commandBuffer
,
2314 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2315 VkSubpassContents contents
)
2317 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2318 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2319 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2321 cmd_buffer
->state
.framebuffer
= framebuffer
;
2322 cmd_buffer
->state
.pass
= pass
;
2323 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2324 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
2326 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2328 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
2331 void genX(CmdNextSubpass
)(
2332 VkCommandBuffer commandBuffer
,
2333 VkSubpassContents contents
)
2335 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2337 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2339 const struct anv_image_view
*iview
=
2340 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2343 anv_gen8_hiz_op_resolve(cmd_buffer
, iview
->image
,
2344 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2347 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2348 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
2351 void genX(CmdEndRenderPass
)(
2352 VkCommandBuffer commandBuffer
)
2354 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2356 const struct anv_image_view
*iview
=
2357 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2360 anv_gen8_hiz_op_resolve(cmd_buffer
, iview
->image
,
2361 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2364 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2367 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
2372 emit_ps_depth_count(struct anv_cmd_buffer
*cmd_buffer
,
2373 struct anv_bo
*bo
, uint32_t offset
)
2375 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2376 pc
.DestinationAddressType
= DAT_PPGTT
;
2377 pc
.PostSyncOperation
= WritePSDepthCount
;
2378 pc
.DepthStallEnable
= true;
2379 pc
.Address
= (struct anv_address
) { bo
, offset
};
2381 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2382 pc
.CommandStreamerStallEnable
= true;
2387 emit_query_availability(struct anv_cmd_buffer
*cmd_buffer
,
2388 struct anv_bo
*bo
, uint32_t offset
)
2390 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2391 pc
.DestinationAddressType
= DAT_PPGTT
;
2392 pc
.PostSyncOperation
= WriteImmediateData
;
2393 pc
.Address
= (struct anv_address
) { bo
, offset
};
2394 pc
.ImmediateData
= 1;
2398 void genX(CmdBeginQuery
)(
2399 VkCommandBuffer commandBuffer
,
2400 VkQueryPool queryPool
,
2402 VkQueryControlFlags flags
)
2404 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2405 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2407 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
2408 * that the pipelining of the depth write breaks. What we see is that
2409 * samples from the render pass clear leaks into the first query
2410 * immediately after the clear. Doing a pipecontrol with a post-sync
2411 * operation and DepthStallEnable seems to work around the issue.
2413 if (cmd_buffer
->state
.need_query_wa
) {
2414 cmd_buffer
->state
.need_query_wa
= false;
2415 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2416 pc
.DepthCacheFlushEnable
= true;
2417 pc
.DepthStallEnable
= true;
2421 switch (pool
->type
) {
2422 case VK_QUERY_TYPE_OCCLUSION
:
2423 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2424 query
* sizeof(struct anv_query_pool_slot
));
2427 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2433 void genX(CmdEndQuery
)(
2434 VkCommandBuffer commandBuffer
,
2435 VkQueryPool queryPool
,
2438 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2439 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2441 switch (pool
->type
) {
2442 case VK_QUERY_TYPE_OCCLUSION
:
2443 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2444 query
* sizeof(struct anv_query_pool_slot
) + 8);
2446 emit_query_availability(cmd_buffer
, &pool
->bo
,
2447 query
* sizeof(struct anv_query_pool_slot
) + 16);
2450 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2456 #define TIMESTAMP 0x2358
2458 void genX(CmdWriteTimestamp
)(
2459 VkCommandBuffer commandBuffer
,
2460 VkPipelineStageFlagBits pipelineStage
,
2461 VkQueryPool queryPool
,
2464 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2465 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2466 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
2468 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
2470 switch (pipelineStage
) {
2471 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
2472 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2473 srm
.RegisterAddress
= TIMESTAMP
;
2474 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
};
2476 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2477 srm
.RegisterAddress
= TIMESTAMP
+ 4;
2478 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
+ 4 };
2483 /* Everything else is bottom-of-pipe */
2484 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2485 pc
.DestinationAddressType
= DAT_PPGTT
;
2486 pc
.PostSyncOperation
= WriteTimestamp
;
2487 pc
.Address
= (struct anv_address
) { &pool
->bo
, offset
};
2489 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2490 pc
.CommandStreamerStallEnable
= true;
2495 emit_query_availability(cmd_buffer
, &pool
->bo
, query
+ 16);
2498 #if GEN_GEN > 7 || GEN_IS_HASWELL
2500 #define alu_opcode(v) __gen_uint((v), 20, 31)
2501 #define alu_operand1(v) __gen_uint((v), 10, 19)
2502 #define alu_operand2(v) __gen_uint((v), 0, 9)
2503 #define alu(opcode, operand1, operand2) \
2504 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
2506 #define OPCODE_NOOP 0x000
2507 #define OPCODE_LOAD 0x080
2508 #define OPCODE_LOADINV 0x480
2509 #define OPCODE_LOAD0 0x081
2510 #define OPCODE_LOAD1 0x481
2511 #define OPCODE_ADD 0x100
2512 #define OPCODE_SUB 0x101
2513 #define OPCODE_AND 0x102
2514 #define OPCODE_OR 0x103
2515 #define OPCODE_XOR 0x104
2516 #define OPCODE_STORE 0x180
2517 #define OPCODE_STOREINV 0x580
2519 #define OPERAND_R0 0x00
2520 #define OPERAND_R1 0x01
2521 #define OPERAND_R2 0x02
2522 #define OPERAND_R3 0x03
2523 #define OPERAND_R4 0x04
2524 #define OPERAND_SRCA 0x20
2525 #define OPERAND_SRCB 0x21
2526 #define OPERAND_ACCU 0x31
2527 #define OPERAND_ZF 0x32
2528 #define OPERAND_CF 0x33
2530 #define CS_GPR(n) (0x2600 + (n) * 8)
2533 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
2534 struct anv_bo
*bo
, uint32_t offset
)
2536 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2537 lrm
.RegisterAddress
= reg
,
2538 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2540 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2541 lrm
.RegisterAddress
= reg
+ 4;
2542 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2547 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
2548 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
2550 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2551 srm
.RegisterAddress
= reg
;
2552 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2555 if (flags
& VK_QUERY_RESULT_64_BIT
) {
2556 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2557 srm
.RegisterAddress
= reg
+ 4;
2558 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2563 void genX(CmdCopyQueryPoolResults
)(
2564 VkCommandBuffer commandBuffer
,
2565 VkQueryPool queryPool
,
2566 uint32_t firstQuery
,
2567 uint32_t queryCount
,
2568 VkBuffer destBuffer
,
2569 VkDeviceSize destOffset
,
2570 VkDeviceSize destStride
,
2571 VkQueryResultFlags flags
)
2573 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2574 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2575 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
2576 uint32_t slot_offset
, dst_offset
;
2578 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
2579 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2580 pc
.CommandStreamerStallEnable
= true;
2581 pc
.StallAtPixelScoreboard
= true;
2585 dst_offset
= buffer
->offset
+ destOffset
;
2586 for (uint32_t i
= 0; i
< queryCount
; i
++) {
2588 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
2589 switch (pool
->type
) {
2590 case VK_QUERY_TYPE_OCCLUSION
:
2591 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2592 CS_GPR(0), &pool
->bo
, slot_offset
);
2593 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2594 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
2596 /* FIXME: We need to clamp the result for 32 bit. */
2598 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
2599 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
2600 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
2601 dw
[3] = alu(OPCODE_SUB
, 0, 0);
2602 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
2605 case VK_QUERY_TYPE_TIMESTAMP
:
2606 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2607 CS_GPR(2), &pool
->bo
, slot_offset
);
2611 unreachable("unhandled query type");
2614 store_query_result(&cmd_buffer
->batch
,
2615 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
2617 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
2618 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
2619 &pool
->bo
, slot_offset
+ 16);
2620 if (flags
& VK_QUERY_RESULT_64_BIT
)
2621 store_query_result(&cmd_buffer
->batch
,
2622 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
2624 store_query_result(&cmd_buffer
->batch
,
2625 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
2628 dst_offset
+= destStride
;
2633 void genX(CmdCopyQueryPoolResults
)(
2634 VkCommandBuffer commandBuffer
,
2635 VkQueryPool queryPool
,
2636 uint32_t firstQuery
,
2637 uint32_t queryCount
,
2638 VkBuffer destBuffer
,
2639 VkDeviceSize destOffset
,
2640 VkDeviceSize destStride
,
2641 VkQueryResultFlags flags
)
2643 anv_finishme("Queries not yet supported on Ivy Bridge");