2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
37 /* We reserve GPR 14 and 15 for conditional rendering */
38 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
39 #define __gen_get_batch_dwords anv_batch_emit_dwords
40 #define __gen_address_offset anv_address_add
41 #include "common/gen_mi_builder.h"
43 static void genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
47 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
49 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
50 lri
.RegisterOffset
= reg
;
56 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
58 struct anv_device
*device
= cmd_buffer
->device
;
59 UNUSED
const struct gen_device_info
*devinfo
= &device
->info
;
60 uint32_t mocs
= device
->isl_dev
.mocs
.internal
;
62 /* If we are emitting a new state base address we probably need to re-emit
65 cmd_buffer
->state
.descriptors_dirty
|= ~0;
67 /* Emit a render target cache flush.
69 * This isn't documented anywhere in the PRM. However, it seems to be
70 * necessary prior to changing the surface state base adress. Without
71 * this, we get GPU hangs when using multi-level command buffers which
72 * clear depth, reset state base address, and then go render stuff.
74 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
75 pc
.DCFlushEnable
= true;
76 pc
.RenderTargetCacheFlushEnable
= true;
77 pc
.CommandStreamerStallEnable
= true;
79 pc
.TileCacheFlushEnable
= true;
82 /* GEN:BUG:1606662791:
84 * Software must program PIPE_CONTROL command with "HDC Pipeline
85 * Flush" prior to programming of the below two non-pipeline state :
86 * * STATE_BASE_ADDRESS
87 * * 3DSTATE_BINDING_TABLE_POOL_ALLOC
89 if (devinfo
->revision
== 0 /* A0 */)
90 pc
.HDCPipelineFlushEnable
= true;
95 /* GEN:BUG:1607854226:
97 * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
98 * mode by putting the pipeline temporarily in 3D mode.
100 uint32_t gen12_wa_pipeline
= cmd_buffer
->state
.current_pipeline
;
101 genX(flush_pipeline_select_3d
)(cmd_buffer
);
104 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
105 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
106 sba
.GeneralStateMOCS
= mocs
;
107 sba
.GeneralStateBaseAddressModifyEnable
= true;
109 sba
.StatelessDataPortAccessMOCS
= mocs
;
111 sba
.SurfaceStateBaseAddress
=
112 anv_cmd_buffer_surface_base_address(cmd_buffer
);
113 sba
.SurfaceStateMOCS
= mocs
;
114 sba
.SurfaceStateBaseAddressModifyEnable
= true;
116 sba
.DynamicStateBaseAddress
=
117 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
118 sba
.DynamicStateMOCS
= mocs
;
119 sba
.DynamicStateBaseAddressModifyEnable
= true;
121 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
122 sba
.IndirectObjectMOCS
= mocs
;
123 sba
.IndirectObjectBaseAddressModifyEnable
= true;
125 sba
.InstructionBaseAddress
=
126 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
127 sba
.InstructionMOCS
= mocs
;
128 sba
.InstructionBaseAddressModifyEnable
= true;
131 /* Broadwell requires that we specify a buffer size for a bunch of
132 * these fields. However, since we will be growing the BO's live, we
133 * just set them all to the maximum.
135 sba
.GeneralStateBufferSize
= 0xfffff;
136 sba
.IndirectObjectBufferSize
= 0xfffff;
137 if (device
->physical
->use_softpin
) {
138 /* With softpin, we use fixed addresses so we actually know how big
139 * our base addresses are.
141 sba
.DynamicStateBufferSize
= DYNAMIC_STATE_POOL_SIZE
/ 4096;
142 sba
.InstructionBufferSize
= INSTRUCTION_STATE_POOL_SIZE
/ 4096;
144 sba
.DynamicStateBufferSize
= 0xfffff;
145 sba
.InstructionBufferSize
= 0xfffff;
147 sba
.GeneralStateBufferSizeModifyEnable
= true;
148 sba
.IndirectObjectBufferSizeModifyEnable
= true;
149 sba
.DynamicStateBufferSizeModifyEnable
= true;
150 sba
.InstructionBuffersizeModifyEnable
= true;
152 /* On gen7, we have upper bounds instead. According to the docs,
153 * setting an upper bound of zero means that no bounds checking is
154 * performed so, in theory, we should be able to leave them zero.
155 * However, border color is broken and the GPU bounds-checks anyway.
156 * To avoid this and other potential problems, we may as well set it
159 sba
.GeneralStateAccessUpperBound
=
160 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
161 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
162 sba
.DynamicStateAccessUpperBound
=
163 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
164 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
165 sba
.InstructionAccessUpperBound
=
166 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
167 sba
.InstructionAccessUpperBoundModifyEnable
= true;
170 if (cmd_buffer
->device
->physical
->use_softpin
) {
171 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
172 .bo
= device
->surface_state_pool
.block_pool
.bo
,
175 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
177 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
178 sba
.BindlessSurfaceStateSize
= 0;
180 sba
.BindlessSurfaceStateMOCS
= mocs
;
181 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
184 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
185 sba
.BindlessSamplerStateMOCS
= mocs
;
186 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
187 sba
.BindlessSamplerStateBufferSize
= 0;
192 /* GEN:BUG:1607854226:
194 * Put the pipeline back into its current mode.
196 if (gen12_wa_pipeline
!= UINT32_MAX
)
197 genX(flush_pipeline_select
)(cmd_buffer
, gen12_wa_pipeline
);
200 /* After re-setting the surface state base address, we have to do some
201 * cache flusing so that the sampler engine will pick up the new
202 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
203 * Shared Function > 3D Sampler > State > State Caching (page 96):
205 * Coherency with system memory in the state cache, like the texture
206 * cache is handled partially by software. It is expected that the
207 * command stream or shader will issue Cache Flush operation or
208 * Cache_Flush sampler message to ensure that the L1 cache remains
209 * coherent with system memory.
213 * Whenever the value of the Dynamic_State_Base_Addr,
214 * Surface_State_Base_Addr are altered, the L1 state cache must be
215 * invalidated to ensure the new surface or sampler state is fetched
216 * from system memory.
218 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
219 * which, according the PIPE_CONTROL instruction documentation in the
222 * Setting this bit is independent of any other bit in this packet.
223 * This bit controls the invalidation of the L1 and L2 state caches
224 * at the top of the pipe i.e. at the parsing time.
226 * Unfortunately, experimentation seems to indicate that state cache
227 * invalidation through a PIPE_CONTROL does nothing whatsoever in
228 * regards to surface state and binding tables. In stead, it seems that
229 * invalidating the texture cache is what is actually needed.
231 * XXX: As far as we have been able to determine through
232 * experimentation, shows that flush the texture cache appears to be
233 * sufficient. The theory here is that all of the sampling/rendering
234 * units cache the binding table in the texture cache. However, we have
235 * yet to be able to actually confirm this.
237 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
238 pc
.TextureCacheInvalidationEnable
= true;
239 pc
.ConstantCacheInvalidationEnable
= true;
240 pc
.StateCacheInvalidationEnable
= true;
245 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
246 struct anv_state state
, struct anv_address addr
)
248 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
251 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
252 state
.offset
+ isl_dev
->ss
.addr_offset
,
253 addr
.bo
, addr
.offset
, NULL
);
254 if (result
!= VK_SUCCESS
)
255 anv_batch_set_error(&cmd_buffer
->batch
, result
);
259 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
260 struct anv_surface_state state
)
262 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
264 assert(!anv_address_is_null(state
.address
));
265 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
267 if (!anv_address_is_null(state
.aux_address
)) {
269 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
270 &cmd_buffer
->pool
->alloc
,
271 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
272 state
.aux_address
.bo
,
273 state
.aux_address
.offset
,
275 if (result
!= VK_SUCCESS
)
276 anv_batch_set_error(&cmd_buffer
->batch
, result
);
279 if (!anv_address_is_null(state
.clear_address
)) {
281 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
282 &cmd_buffer
->pool
->alloc
,
284 isl_dev
->ss
.clear_color_state_offset
,
285 state
.clear_address
.bo
,
286 state
.clear_address
.offset
,
288 if (result
!= VK_SUCCESS
)
289 anv_batch_set_error(&cmd_buffer
->batch
, result
);
294 color_attachment_compute_aux_usage(struct anv_device
* device
,
295 struct anv_cmd_state
* cmd_state
,
296 uint32_t att
, VkRect2D render_area
)
298 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
299 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
301 assert(iview
->n_planes
== 1);
303 if (iview
->planes
[0].isl
.base_array_layer
>=
304 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
305 iview
->planes
[0].isl
.base_level
)) {
306 /* There is no aux buffer which corresponds to the level and layer(s)
309 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
310 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
311 att_state
->fast_clear
= false;
315 att_state
->aux_usage
=
316 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
317 VK_IMAGE_ASPECT_COLOR_BIT
,
318 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
,
319 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
321 /* If we don't have aux, then we should have returned early in the layer
322 * check above. If we got here, we must have something.
324 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
326 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
327 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
328 att_state
->input_aux_usage
= att_state
->aux_usage
;
330 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
332 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
333 * setting is only allowed if Surface Format supported for Fast
334 * Clear. In addition, if the surface is bound to the sampling
335 * engine, Surface Format must be supported for Render Target
336 * Compression for surfaces bound to the sampling engine."
338 * In other words, we can only sample from a fast-cleared image if it
339 * also supports color compression.
341 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
) &&
342 isl_format_supports_ccs_d(&device
->info
, iview
->planes
[0].isl
.format
)) {
343 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
345 /* While fast-clear resolves and partial resolves are fairly cheap in the
346 * case where you render to most of the pixels, full resolves are not
347 * because they potentially involve reading and writing the entire
348 * framebuffer. If we can't texture with CCS_E, we should leave it off and
349 * limit ourselves to fast clears.
351 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
352 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
353 anv_perf_warn(device
, iview
->image
,
354 "Not temporarily enabling CCS_E.");
357 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
361 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
362 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
364 union isl_color_value clear_color
= {};
365 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
367 att_state
->clear_color_is_zero_one
=
368 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
369 att_state
->clear_color_is_zero
=
370 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
372 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
373 /* Start by getting the fast clear type. We use the first subpass
374 * layout here because we don't want to fast-clear if the first subpass
375 * to use the attachment can't handle fast-clears.
377 enum anv_fast_clear_type fast_clear_type
=
378 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
379 VK_IMAGE_ASPECT_COLOR_BIT
,
380 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
381 switch (fast_clear_type
) {
382 case ANV_FAST_CLEAR_NONE
:
383 att_state
->fast_clear
= false;
385 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
386 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
388 case ANV_FAST_CLEAR_ANY
:
389 att_state
->fast_clear
= true;
393 /* Potentially, we could do partial fast-clears but doing so has crazy
394 * alignment restrictions. It's easier to just restrict to full size
395 * fast clears for now.
397 if (render_area
.offset
.x
!= 0 ||
398 render_area
.offset
.y
!= 0 ||
399 render_area
.extent
.width
!= iview
->extent
.width
||
400 render_area
.extent
.height
!= iview
->extent
.height
)
401 att_state
->fast_clear
= false;
403 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
404 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
405 att_state
->fast_clear
= false;
407 /* We only allow fast clears to the first slice of an image (level 0,
408 * layer 0) and only for the entire slice. This guarantees us that, at
409 * any given time, there is only one clear color on any given image at
410 * any given time. At the time of our testing (Jan 17, 2018), there
411 * were no known applications which would benefit from fast-clearing
412 * more than just the first slice.
414 if (att_state
->fast_clear
&&
415 (iview
->planes
[0].isl
.base_level
> 0 ||
416 iview
->planes
[0].isl
.base_array_layer
> 0)) {
417 anv_perf_warn(device
, iview
->image
,
418 "Rendering with multi-lod or multi-layer framebuffer "
419 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
420 "baseArrayLayer > 0. Not fast clearing.");
421 att_state
->fast_clear
= false;
422 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
423 anv_perf_warn(device
, iview
->image
,
424 "Rendering to a multi-layer framebuffer with "
425 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
428 att_state
->fast_clear
= false;
433 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
434 struct anv_cmd_state
*cmd_state
,
435 uint32_t att
, VkRect2D render_area
)
437 struct anv_render_pass_attachment
*pass_att
=
438 &cmd_state
->pass
->attachments
[att
];
439 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
440 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
442 /* These will be initialized after the first subpass transition. */
443 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
444 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
446 /* This is unused for depth/stencil but valgrind complains if it
449 att_state
->clear_color_is_zero_one
= false;
452 /* We don't do any HiZ or depth fast-clears on gen7 yet */
453 att_state
->fast_clear
= false;
457 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
458 /* If we're just clearing stencil, we can always HiZ clear */
459 att_state
->fast_clear
= true;
463 /* Default to false for now */
464 att_state
->fast_clear
= false;
466 /* We must have depth in order to have HiZ */
467 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
470 const enum isl_aux_usage first_subpass_aux_usage
=
471 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
472 VK_IMAGE_ASPECT_DEPTH_BIT
,
473 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
474 pass_att
->first_subpass_layout
);
475 if (!blorp_can_hiz_clear_depth(&device
->info
,
476 &iview
->image
->planes
[0].surface
.isl
,
477 first_subpass_aux_usage
,
478 iview
->planes
[0].isl
.base_level
,
479 iview
->planes
[0].isl
.base_array_layer
,
480 render_area
.offset
.x
,
481 render_area
.offset
.y
,
482 render_area
.offset
.x
+
483 render_area
.extent
.width
,
484 render_area
.offset
.y
+
485 render_area
.extent
.height
))
488 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
491 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
492 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
493 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
494 * only supports returning 0.0f. Gens prior to gen8 do not support this
500 /* If we got here, then we can fast clear */
501 att_state
->fast_clear
= true;
505 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
507 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
510 /* We only allocate input attachment states for color surfaces. Compression
511 * is not yet enabled for depth textures and stencil doesn't allow
512 * compression so we can just use the texture surface state from the view.
514 return vk_format_is_color(att
->format
);
517 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
521 anv_image_init_aux_tt(struct anv_cmd_buffer
*cmd_buffer
,
522 const struct anv_image
*image
,
523 VkImageAspectFlagBits aspect
,
524 uint32_t base_level
, uint32_t level_count
,
525 uint32_t base_layer
, uint32_t layer_count
)
527 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
529 uint64_t base_address
=
530 anv_address_physical(image
->planes
[plane
].address
);
532 const struct isl_surf
*isl_surf
= &image
->planes
[plane
].surface
.isl
;
533 uint64_t format_bits
= gen_aux_map_format_bits_for_isl_surf(isl_surf
);
535 /* We're about to live-update the AUX-TT. We really don't want anyone else
536 * trying to read it while we're doing this. We could probably get away
537 * with not having this stall in some cases if we were really careful but
538 * it's better to play it safe. Full stall the GPU.
540 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
541 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
543 struct gen_mi_builder b
;
544 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
546 for (uint32_t a
= 0; a
< layer_count
; a
++) {
547 const uint32_t layer
= base_layer
+ a
;
549 uint64_t start_offset_B
= UINT64_MAX
, end_offset_B
= 0;
550 for (uint32_t l
= 0; l
< level_count
; l
++) {
551 const uint32_t level
= base_level
+ l
;
553 uint32_t logical_array_layer
, logical_z_offset_px
;
554 if (image
->type
== VK_IMAGE_TYPE_3D
) {
555 logical_array_layer
= 0;
557 /* If the given miplevel does not have this layer, then any higher
558 * miplevels won't either because miplevels only get smaller the
561 assert(layer
< image
->extent
.depth
);
562 if (layer
>= anv_minify(image
->extent
.depth
, level
))
564 logical_z_offset_px
= layer
;
566 assert(layer
< image
->array_size
);
567 logical_array_layer
= layer
;
568 logical_z_offset_px
= 0;
571 uint32_t slice_start_offset_B
, slice_end_offset_B
;
572 isl_surf_get_image_range_B_tile(isl_surf
, level
,
575 &slice_start_offset_B
,
576 &slice_end_offset_B
);
578 start_offset_B
= MIN2(start_offset_B
, slice_start_offset_B
);
579 end_offset_B
= MAX2(end_offset_B
, slice_end_offset_B
);
582 /* Aux operates 64K at a time */
583 start_offset_B
= align_down_u64(start_offset_B
, 64 * 1024);
584 end_offset_B
= align_u64(end_offset_B
, 64 * 1024);
586 for (uint64_t offset
= start_offset_B
;
587 offset
< end_offset_B
; offset
+= 64 * 1024) {
588 uint64_t address
= base_address
+ offset
;
590 uint64_t aux_entry_addr64
, *aux_entry_map
;
591 aux_entry_map
= gen_aux_map_get_entry(cmd_buffer
->device
->aux_map_ctx
,
592 address
, &aux_entry_addr64
);
594 assert(cmd_buffer
->device
->physical
->use_softpin
);
595 struct anv_address aux_entry_address
= {
597 .offset
= aux_entry_addr64
,
600 const uint64_t old_aux_entry
= READ_ONCE(*aux_entry_map
);
601 uint64_t new_aux_entry
=
602 (old_aux_entry
& GEN_AUX_MAP_ADDRESS_MASK
) | format_bits
;
604 if (isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
))
605 new_aux_entry
|= GEN_AUX_MAP_ENTRY_VALID_BIT
;
607 gen_mi_store(&b
, gen_mi_mem64(aux_entry_address
),
608 gen_mi_imm(new_aux_entry
));
612 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
614 #endif /* GEN_GEN == 12 */
616 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
617 * the initial layout is undefined, the HiZ buffer and depth buffer will
618 * represent the same data at the end of this operation.
621 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
622 const struct anv_image
*image
,
623 uint32_t base_layer
, uint32_t layer_count
,
624 VkImageLayout initial_layout
,
625 VkImageLayout final_layout
)
627 uint32_t depth_plane
=
628 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
629 if (image
->planes
[depth_plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
633 if ((initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
634 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) &&
635 cmd_buffer
->device
->physical
->has_implicit_ccs
&&
636 cmd_buffer
->device
->info
.has_aux_map
) {
637 anv_image_init_aux_tt(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
642 const enum isl_aux_state initial_state
=
643 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
644 VK_IMAGE_ASPECT_DEPTH_BIT
,
646 const enum isl_aux_state final_state
=
647 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
648 VK_IMAGE_ASPECT_DEPTH_BIT
,
651 const bool initial_depth_valid
=
652 isl_aux_state_has_valid_primary(initial_state
);
653 const bool initial_hiz_valid
=
654 isl_aux_state_has_valid_aux(initial_state
);
655 const bool final_needs_depth
=
656 isl_aux_state_has_valid_primary(final_state
);
657 const bool final_needs_hiz
=
658 isl_aux_state_has_valid_aux(final_state
);
660 /* Getting into the pass-through state for Depth is tricky and involves
661 * both a resolve and an ambiguate. We don't handle that state right now
662 * as anv_layout_to_aux_state never returns it.
664 assert(final_state
!= ISL_AUX_STATE_PASS_THROUGH
);
666 if (final_needs_depth
&& !initial_depth_valid
) {
667 assert(initial_hiz_valid
);
668 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
669 0, base_layer
, layer_count
, ISL_AUX_OP_FULL_RESOLVE
);
670 } else if (final_needs_hiz
&& !initial_hiz_valid
) {
671 assert(initial_depth_valid
);
672 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
673 0, base_layer
, layer_count
, ISL_AUX_OP_AMBIGUATE
);
678 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
680 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
681 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
||
682 layout
== VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
;
685 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
686 * the initial layout is undefined, the HiZ buffer and depth buffer will
687 * represent the same data at the end of this operation.
690 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
691 const struct anv_image
*image
,
692 uint32_t base_level
, uint32_t level_count
,
693 uint32_t base_layer
, uint32_t layer_count
,
694 VkImageLayout initial_layout
,
695 VkImageLayout final_layout
)
698 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
699 VK_IMAGE_ASPECT_STENCIL_BIT
);
701 /* On gen7, we have to store a texturable version of the stencil buffer in
702 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
703 * forth at strategic points. Stencil writes are only allowed in following
706 * - VK_IMAGE_LAYOUT_GENERAL
707 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
708 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
709 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
710 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
712 * For general, we have no nice opportunity to transition so we do the copy
713 * to the shadow unconditionally at the end of the subpass. For transfer
714 * destinations, we can update it as part of the transfer op. For the other
715 * layouts, we delay the copy until a transition into some other layout.
717 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
718 vk_image_layout_stencil_write_optimal(initial_layout
) &&
719 !vk_image_layout_stencil_write_optimal(final_layout
)) {
720 anv_image_copy_to_shadow(cmd_buffer
, image
,
721 VK_IMAGE_ASPECT_STENCIL_BIT
,
722 base_level
, level_count
,
723 base_layer
, layer_count
);
725 #endif /* GEN_GEN == 7 */
728 #define MI_PREDICATE_SRC0 0x2400
729 #define MI_PREDICATE_SRC1 0x2408
730 #define MI_PREDICATE_RESULT 0x2418
733 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
734 const struct anv_image
*image
,
735 VkImageAspectFlagBits aspect
,
737 uint32_t base_layer
, uint32_t layer_count
,
740 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
742 /* We only have compression tracking for CCS_E */
743 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
746 for (uint32_t a
= 0; a
< layer_count
; a
++) {
747 uint32_t layer
= base_layer
+ a
;
748 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
749 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
752 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
758 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
759 const struct anv_image
*image
,
760 VkImageAspectFlagBits aspect
,
761 enum anv_fast_clear_type fast_clear
)
763 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
764 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
766 sdi
.ImmediateData
= fast_clear
;
769 /* Whenever we have fast-clear, we consider that slice to be compressed.
770 * This makes building predicates much easier.
772 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
773 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
776 /* This is only really practical on haswell and above because it requires
777 * MI math in order to get it correct.
779 #if GEN_GEN >= 8 || GEN_IS_HASWELL
781 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
782 const struct anv_image
*image
,
783 VkImageAspectFlagBits aspect
,
784 uint32_t level
, uint32_t array_layer
,
785 enum isl_aux_op resolve_op
,
786 enum anv_fast_clear_type fast_clear_supported
)
788 struct gen_mi_builder b
;
789 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
791 const struct gen_mi_value fast_clear_type
=
792 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
795 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
796 /* In this case, we're doing a full resolve which means we want the
797 * resolve to happen if any compression (including fast-clears) is
800 * In order to simplify the logic a bit, we make the assumption that,
801 * if the first slice has been fast-cleared, it is also marked as
802 * compressed. See also set_image_fast_clear_state.
804 const struct gen_mi_value compression_state
=
805 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
807 level
, array_layer
));
808 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
810 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
812 if (level
== 0 && array_layer
== 0) {
813 /* If the predicate is true, we want to write 0 to the fast clear type
814 * and, if it's false, leave it alone. We can do this by writing
816 * clear_type = clear_type & ~predicate;
818 struct gen_mi_value new_fast_clear_type
=
819 gen_mi_iand(&b
, fast_clear_type
,
820 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
821 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
823 } else if (level
== 0 && array_layer
== 0) {
824 /* In this case, we are doing a partial resolve to get rid of fast-clear
825 * colors. We don't care about the compression state but we do care
826 * about how much fast clear is allowed by the final layout.
828 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
829 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
831 /* We need to compute (fast_clear_supported < image->fast_clear) */
832 struct gen_mi_value pred
=
833 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
834 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
835 gen_mi_value_ref(&b
, pred
));
837 /* If the predicate is true, we want to write 0 to the fast clear type
838 * and, if it's false, leave it alone. We can do this by writing
840 * clear_type = clear_type & ~predicate;
842 struct gen_mi_value new_fast_clear_type
=
843 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
844 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
846 /* In this case, we're trying to do a partial resolve on a slice that
847 * doesn't have clear color. There's nothing to do.
849 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
853 /* Set src1 to 0 and use a != condition */
854 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
856 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
857 mip
.LoadOperation
= LOAD_LOADINV
;
858 mip
.CombineOperation
= COMBINE_SET
;
859 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
862 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
866 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
867 const struct anv_image
*image
,
868 VkImageAspectFlagBits aspect
,
869 uint32_t level
, uint32_t array_layer
,
870 enum isl_aux_op resolve_op
,
871 enum anv_fast_clear_type fast_clear_supported
)
873 struct gen_mi_builder b
;
874 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
876 struct gen_mi_value fast_clear_type_mem
=
877 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
880 /* This only works for partial resolves and only when the clear color is
881 * all or nothing. On the upside, this emits less command streamer code
882 * and works on Ivybridge and Bay Trail.
884 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
885 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
887 /* We don't support fast clears on anything other than the first slice. */
888 if (level
> 0 || array_layer
> 0)
891 /* On gen8, we don't have a concept of default clear colors because we
892 * can't sample from CCS surfaces. It's enough to just load the fast clear
893 * state into the predicate register.
895 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
896 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
897 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
899 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
900 mip
.LoadOperation
= LOAD_LOADINV
;
901 mip
.CombineOperation
= COMBINE_SET
;
902 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
905 #endif /* GEN_GEN <= 8 */
908 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
909 const struct anv_image
*image
,
910 enum isl_format format
,
911 struct isl_swizzle swizzle
,
912 VkImageAspectFlagBits aspect
,
913 uint32_t level
, uint32_t array_layer
,
914 enum isl_aux_op resolve_op
,
915 enum anv_fast_clear_type fast_clear_supported
)
917 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
920 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
921 aspect
, level
, array_layer
,
922 resolve_op
, fast_clear_supported
);
923 #else /* GEN_GEN <= 8 */
924 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
925 aspect
, level
, array_layer
,
926 resolve_op
, fast_clear_supported
);
929 /* CCS_D only supports full resolves and BLORP will assert on us if we try
930 * to do a partial resolve on a CCS_D surface.
932 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
933 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_D
)
934 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
936 anv_image_ccs_op(cmd_buffer
, image
, format
, swizzle
, aspect
,
937 level
, array_layer
, 1, resolve_op
, NULL
, true);
941 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
942 const struct anv_image
*image
,
943 enum isl_format format
,
944 struct isl_swizzle swizzle
,
945 VkImageAspectFlagBits aspect
,
946 uint32_t array_layer
,
947 enum isl_aux_op resolve_op
,
948 enum anv_fast_clear_type fast_clear_supported
)
950 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
951 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
953 #if GEN_GEN >= 8 || GEN_IS_HASWELL
954 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
955 aspect
, 0, array_layer
,
956 resolve_op
, fast_clear_supported
);
958 anv_image_mcs_op(cmd_buffer
, image
, format
, swizzle
, aspect
,
959 array_layer
, 1, resolve_op
, NULL
, true);
961 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
966 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
967 const struct anv_image
*image
,
968 VkImageAspectFlagBits aspect
,
969 enum isl_aux_usage aux_usage
,
972 uint32_t layer_count
)
974 /* The aspect must be exactly one of the image aspects. */
975 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
977 /* The only compression types with more than just fast-clears are MCS,
978 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
979 * track the current fast-clear and compression state. This leaves us
980 * with just MCS and CCS_E.
982 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
983 aux_usage
!= ISL_AUX_USAGE_MCS
)
986 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
987 level
, base_layer
, layer_count
, true);
991 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
992 const struct anv_image
*image
,
993 VkImageAspectFlagBits aspect
)
995 assert(cmd_buffer
&& image
);
996 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
998 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
999 ANV_FAST_CLEAR_NONE
);
1001 /* Initialize the struct fields that are accessed for fast-clears so that
1002 * the HW restrictions on the field values are satisfied.
1004 struct anv_address addr
=
1005 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
1008 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1009 const unsigned num_dwords
= GEN_GEN
>= 10 ?
1010 isl_dev
->ss
.clear_color_state_size
/ 4 :
1011 isl_dev
->ss
.clear_value_size
/ 4;
1012 for (unsigned i
= 0; i
< num_dwords
; i
++) {
1013 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1015 sdi
.Address
.offset
+= i
* 4;
1016 sdi
.ImmediateData
= 0;
1020 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1022 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
1023 /* Pre-SKL, the dword containing the clear values also contains
1024 * other fields, so we need to initialize those fields to match the
1025 * values that would be in a color attachment.
1027 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
1028 ISL_CHANNEL_SELECT_GREEN
<< 22 |
1029 ISL_CHANNEL_SELECT_BLUE
<< 19 |
1030 ISL_CHANNEL_SELECT_ALPHA
<< 16;
1031 } else if (GEN_GEN
== 7) {
1032 /* On IVB, the dword containing the clear values also contains
1033 * other fields that must be zero or can be zero.
1035 sdi
.ImmediateData
= 0;
1041 /* Copy the fast-clear value dword(s) between a surface state object and an
1042 * image's fast clear state buffer.
1045 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
1046 struct anv_state surface_state
,
1047 const struct anv_image
*image
,
1048 VkImageAspectFlagBits aspect
,
1049 bool copy_from_surface_state
)
1051 assert(cmd_buffer
&& image
);
1052 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
1054 struct anv_address ss_clear_addr
= {
1055 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
1056 .offset
= surface_state
.offset
+
1057 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
1059 const struct anv_address entry_addr
=
1060 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
1061 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
1064 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
1065 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
1066 * in-flight when they are issued even if the memory touched is not
1067 * currently active for rendering. The weird bit is that it is not the
1068 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
1069 * rendering hangs such that the next stalling command after the
1070 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
1072 * It is unclear exactly why this hang occurs. Both MI commands come with
1073 * warnings about the 3D pipeline but that doesn't seem to fully explain
1074 * it. My (Jason's) best theory is that it has something to do with the
1075 * fact that we're using a GPU state register as our temporary and that
1076 * something with reading/writing it is causing problems.
1078 * In order to work around this issue, we emit a PIPE_CONTROL with the
1079 * command streamer stall bit set.
1081 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1082 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1085 struct gen_mi_builder b
;
1086 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
1088 if (copy_from_surface_state
) {
1089 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
1091 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
1093 /* Updating a surface state object may require that the state cache be
1094 * invalidated. From the SKL PRM, Shared Functions -> State -> State
1097 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
1098 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
1099 * modified [...], the L1 state cache must be invalidated to ensure
1100 * the new surface or sampler state is fetched from system memory.
1102 * In testing, SKL doesn't actually seem to need this, but HSW does.
1104 cmd_buffer
->state
.pending_pipe_bits
|=
1105 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1110 * @brief Transitions a color buffer from one layout to another.
1112 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
1115 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
1116 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
1117 * this represents the maximum layers to transition at each
1118 * specified miplevel.
1121 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
1122 const struct anv_image
*image
,
1123 VkImageAspectFlagBits aspect
,
1124 const uint32_t base_level
, uint32_t level_count
,
1125 uint32_t base_layer
, uint32_t layer_count
,
1126 VkImageLayout initial_layout
,
1127 VkImageLayout final_layout
)
1129 struct anv_device
*device
= cmd_buffer
->device
;
1130 const struct gen_device_info
*devinfo
= &device
->info
;
1131 /* Validate the inputs. */
1133 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
1134 /* These values aren't supported for simplicity's sake. */
1135 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
1136 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
1137 /* Ensure the subresource range is valid. */
1138 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
1139 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
1140 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
1141 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
1142 assert(last_level_num
<= image
->levels
);
1143 /* The spec disallows these final layouts. */
1144 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
1145 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
1147 /* No work is necessary if the layout stays the same or if this subresource
1148 * range lacks auxiliary data.
1150 if (initial_layout
== final_layout
)
1153 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1155 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
1156 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
1157 /* This surface is a linear compressed image with a tiled shadow surface
1158 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
1159 * we need to ensure the shadow copy is up-to-date.
1161 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1162 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
1163 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1164 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
1166 anv_image_copy_to_shadow(cmd_buffer
, image
,
1167 VK_IMAGE_ASPECT_COLOR_BIT
,
1168 base_level
, level_count
,
1169 base_layer
, layer_count
);
1172 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
1175 assert(image
->planes
[plane
].surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1177 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1178 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1180 if (device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
) {
1181 anv_image_init_aux_tt(cmd_buffer
, image
, aspect
,
1182 base_level
, level_count
,
1183 base_layer
, layer_count
);
1186 assert(!(device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
));
1189 /* A subresource in the undefined layout may have been aliased and
1190 * populated with any arrangement of bits. Therefore, we must initialize
1191 * the related aux buffer and clear buffer entry with desirable values.
1192 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1193 * images with VK_IMAGE_TILING_OPTIMAL.
1195 * Initialize the relevant clear buffer entries.
1197 if (base_level
== 0 && base_layer
== 0)
1198 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1200 /* Initialize the aux buffers to enable correct rendering. In order to
1201 * ensure that things such as storage images work correctly, aux buffers
1202 * need to be initialized to valid data.
1204 * Having an aux buffer with invalid data is a problem for two reasons:
1206 * 1) Having an invalid value in the buffer can confuse the hardware.
1207 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1208 * invalid and leads to the hardware doing strange things. It
1209 * doesn't hang as far as we can tell but rendering corruption can
1212 * 2) If this transition is into the GENERAL layout and we then use the
1213 * image as a storage image, then we must have the aux buffer in the
1214 * pass-through state so that, if we then go to texture from the
1215 * image, we get the results of our storage image writes and not the
1216 * fast clear color or other random data.
1218 * For CCS both of the problems above are real demonstrable issues. In
1219 * that case, the only thing we can do is to perform an ambiguate to
1220 * transition the aux surface into the pass-through state.
1222 * For MCS, (2) is never an issue because we don't support multisampled
1223 * storage images. In theory, issue (1) is a problem with MCS but we've
1224 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1225 * theory, be interpreted as something but we don't know that all bit
1226 * patterns are actually valid. For 2x and 8x, you could easily end up
1227 * with the MCS referring to an invalid plane because not all bits of
1228 * the MCS value are actually used. Even though we've never seen issues
1229 * in the wild, it's best to play it safe and initialize the MCS. We
1230 * can use a fast-clear for MCS because we only ever touch from render
1231 * and texture (no image load store).
1233 if (image
->samples
== 1) {
1234 for (uint32_t l
= 0; l
< level_count
; l
++) {
1235 const uint32_t level
= base_level
+ l
;
1237 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1238 if (base_layer
>= aux_layers
)
1239 break; /* We will only get fewer layers as level increases */
1240 uint32_t level_layer_count
=
1241 MIN2(layer_count
, aux_layers
- base_layer
);
1243 anv_image_ccs_op(cmd_buffer
, image
,
1244 image
->planes
[plane
].surface
.isl
.format
,
1245 ISL_SWIZZLE_IDENTITY
,
1246 aspect
, level
, base_layer
, level_layer_count
,
1247 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1249 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1250 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1251 level
, base_layer
, level_layer_count
,
1256 if (image
->samples
== 4 || image
->samples
== 16) {
1257 anv_perf_warn(cmd_buffer
->device
, image
,
1258 "Doing a potentially unnecessary fast-clear to "
1259 "define an MCS buffer.");
1262 assert(base_level
== 0 && level_count
== 1);
1263 anv_image_mcs_op(cmd_buffer
, image
,
1264 image
->planes
[plane
].surface
.isl
.format
,
1265 ISL_SWIZZLE_IDENTITY
,
1266 aspect
, base_layer
, layer_count
,
1267 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1272 const enum isl_aux_usage initial_aux_usage
=
1273 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, initial_layout
);
1274 const enum isl_aux_usage final_aux_usage
=
1275 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, final_layout
);
1277 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1278 * We can handle transitions between CCS_D/E to and from NONE. What we
1279 * don't yet handle is switching between CCS_E and CCS_D within a given
1280 * image. Doing so in a performant way requires more detailed aux state
1281 * tracking such as what is done in i965. For now, just assume that we
1282 * only have one type of compression.
1284 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1285 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1286 initial_aux_usage
== final_aux_usage
);
1288 /* If initial aux usage is NONE, there is nothing to resolve */
1289 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1292 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1294 /* If the initial layout supports more fast clear than the final layout
1295 * then we need at least a partial resolve.
1297 const enum anv_fast_clear_type initial_fast_clear
=
1298 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1299 const enum anv_fast_clear_type final_fast_clear
=
1300 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1301 if (final_fast_clear
< initial_fast_clear
)
1302 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1304 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1305 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1306 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1308 if (resolve_op
== ISL_AUX_OP_NONE
)
1311 /* Perform a resolve to synchronize data between the main and aux buffer.
1312 * Before we begin, we must satisfy the cache flushing requirement specified
1313 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1315 * Any transition from any value in {Clear, Render, Resolve} to a
1316 * different value in {Clear, Render, Resolve} requires end of pipe
1319 * We perform a flush of the write cache before and after the clear and
1320 * resolve operations to meet this requirement.
1322 * Unlike other drawing, fast clear operations are not properly
1323 * synchronized. The first PIPE_CONTROL here likely ensures that the
1324 * contents of the previous render or clear hit the render target before we
1325 * resolve and the second likely ensures that the resolve is complete before
1326 * we do any more rendering or clearing.
1328 cmd_buffer
->state
.pending_pipe_bits
|=
1329 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1331 for (uint32_t l
= 0; l
< level_count
; l
++) {
1332 uint32_t level
= base_level
+ l
;
1334 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1335 if (base_layer
>= aux_layers
)
1336 break; /* We will only get fewer layers as level increases */
1337 uint32_t level_layer_count
=
1338 MIN2(layer_count
, aux_layers
- base_layer
);
1340 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1341 uint32_t array_layer
= base_layer
+ a
;
1342 if (image
->samples
== 1) {
1343 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1344 image
->planes
[plane
].surface
.isl
.format
,
1345 ISL_SWIZZLE_IDENTITY
,
1346 aspect
, level
, array_layer
, resolve_op
,
1349 /* We only support fast-clear on the first layer so partial
1350 * resolves should not be used on other layers as they will use
1351 * the clear color stored in memory that is only valid for layer0.
1353 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1357 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1358 image
->planes
[plane
].surface
.isl
.format
,
1359 ISL_SWIZZLE_IDENTITY
,
1360 aspect
, array_layer
, resolve_op
,
1366 cmd_buffer
->state
.pending_pipe_bits
|=
1367 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1371 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1374 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1375 struct anv_render_pass
*pass
,
1376 const VkRenderPassBeginInfo
*begin
)
1378 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1379 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1380 struct anv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1382 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1384 if (pass
->attachment_count
> 0) {
1385 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1386 pass
->attachment_count
*
1387 sizeof(state
->attachments
[0]),
1388 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1389 if (state
->attachments
== NULL
) {
1390 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1391 return anv_batch_set_error(&cmd_buffer
->batch
,
1392 VK_ERROR_OUT_OF_HOST_MEMORY
);
1395 state
->attachments
= NULL
;
1398 /* Reserve one for the NULL state. */
1399 unsigned num_states
= 1;
1400 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1401 if (vk_format_is_color(pass
->attachments
[i
].format
))
1404 if (need_input_attachment_state(&pass
->attachments
[i
]))
1408 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1409 state
->render_pass_states
=
1410 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1411 num_states
* ss_stride
, isl_dev
->ss
.align
);
1412 if (state
->render_pass_states
.map
== NULL
) {
1413 return anv_batch_set_error(&cmd_buffer
->batch
,
1414 VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1417 struct anv_state next_state
= state
->render_pass_states
;
1418 next_state
.alloc_size
= isl_dev
->ss
.size
;
1420 state
->null_surface_state
= next_state
;
1421 next_state
.offset
+= ss_stride
;
1422 next_state
.map
+= ss_stride
;
1424 const VkRenderPassAttachmentBeginInfoKHR
*begin_attachment
=
1425 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1427 if (begin
&& !begin_attachment
)
1428 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1430 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1431 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1432 state
->attachments
[i
].color
.state
= next_state
;
1433 next_state
.offset
+= ss_stride
;
1434 next_state
.map
+= ss_stride
;
1437 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1438 state
->attachments
[i
].input
.state
= next_state
;
1439 next_state
.offset
+= ss_stride
;
1440 next_state
.map
+= ss_stride
;
1443 if (begin_attachment
&& begin_attachment
->attachmentCount
!= 0) {
1444 assert(begin_attachment
->attachmentCount
== pass
->attachment_count
);
1445 ANV_FROM_HANDLE(anv_image_view
, iview
, begin_attachment
->pAttachments
[i
]);
1446 cmd_buffer
->state
.attachments
[i
].image_view
= iview
;
1447 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1448 cmd_buffer
->state
.attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1451 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1452 state
->render_pass_states
.alloc_size
);
1455 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1456 isl_extent3d(framebuffer
->width
,
1457 framebuffer
->height
,
1458 framebuffer
->layers
));
1460 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1461 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1462 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1463 VkImageAspectFlags clear_aspects
= 0;
1464 VkImageAspectFlags load_aspects
= 0;
1466 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1467 /* color attachment */
1468 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1469 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1470 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1471 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1474 /* depthstencil attachment */
1475 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1476 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1477 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1478 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1479 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1482 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1483 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1484 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1485 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1486 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1491 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1492 state
->attachments
[i
].current_stencil_layout
= att
->stencil_initial_layout
;
1493 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1494 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1496 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1498 struct anv_image_view
*iview
= cmd_buffer
->state
.attachments
[i
].image_view
;
1499 anv_assert(iview
->vk_format
== att
->format
);
1501 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1502 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1504 union isl_color_value clear_color
= { .u32
= { 0, } };
1505 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1506 anv_assert(iview
->n_planes
== 1);
1507 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1508 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1509 state
, i
, begin
->renderArea
);
1510 if (state
->attachments
[i
].fast_clear
) {
1511 anv_clear_color_from_att_state(&clear_color
,
1512 &state
->attachments
[i
], iview
);
1515 anv_image_fill_surface_state(cmd_buffer
->device
,
1517 VK_IMAGE_ASPECT_COLOR_BIT
,
1518 &iview
->planes
[0].isl
,
1519 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1520 state
->attachments
[i
].aux_usage
,
1523 &state
->attachments
[i
].color
,
1526 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1528 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1533 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1534 anv_image_fill_surface_state(cmd_buffer
->device
,
1536 VK_IMAGE_ASPECT_COLOR_BIT
,
1537 &iview
->planes
[0].isl
,
1538 ISL_SURF_USAGE_TEXTURE_BIT
,
1539 state
->attachments
[i
].input_aux_usage
,
1542 &state
->attachments
[i
].input
,
1545 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1554 genX(BeginCommandBuffer
)(
1555 VkCommandBuffer commandBuffer
,
1556 const VkCommandBufferBeginInfo
* pBeginInfo
)
1558 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1560 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1561 * command buffer's state. Otherwise, we must *reset* its state. In both
1562 * cases we reset it.
1564 * From the Vulkan 1.0 spec:
1566 * If a command buffer is in the executable state and the command buffer
1567 * was allocated from a command pool with the
1568 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1569 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1570 * as if vkResetCommandBuffer had been called with
1571 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1572 * the command buffer in the recording state.
1574 anv_cmd_buffer_reset(cmd_buffer
);
1576 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1578 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1579 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1581 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1583 /* We sometimes store vertex data in the dynamic state buffer for blorp
1584 * operations and our dynamic state stream may re-use data from previous
1585 * command buffers. In order to prevent stale cache data, we flush the VF
1586 * cache. We could do this on every blorp call but that's not really
1587 * needed as all of the data will get written by the CPU prior to the GPU
1588 * executing anything. The chances are fairly high that they will use
1589 * blorp at least once per primary command buffer so it shouldn't be
1592 * There is also a workaround on gen8 which requires us to invalidate the
1593 * VF cache occasionally. It's easier if we can assume we start with a
1594 * fresh cache (See also genX(cmd_buffer_set_binding_for_gen8_vb_flush).)
1596 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1598 /* Re-emit the aux table register in every command buffer. This way we're
1599 * ensured that we have the table even if this command buffer doesn't
1600 * initialize any images.
1602 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
1604 /* We send an "Indirect State Pointers Disable" packet at
1605 * EndCommandBuffer, so all push contant packets are ignored during a
1606 * context restore. Documentation says after that command, we need to
1607 * emit push constants again before any rendering operation. So we
1608 * flag them dirty here to make sure they get emitted.
1610 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1612 VkResult result
= VK_SUCCESS
;
1613 if (cmd_buffer
->usage_flags
&
1614 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1615 assert(pBeginInfo
->pInheritanceInfo
);
1616 ANV_FROM_HANDLE(anv_render_pass
, pass
,
1617 pBeginInfo
->pInheritanceInfo
->renderPass
);
1618 struct anv_subpass
*subpass
=
1619 &pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1620 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
,
1621 pBeginInfo
->pInheritanceInfo
->framebuffer
);
1623 cmd_buffer
->state
.pass
= pass
;
1624 cmd_buffer
->state
.subpass
= subpass
;
1626 /* This is optional in the inheritance info. */
1627 cmd_buffer
->state
.framebuffer
= framebuffer
;
1629 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1630 cmd_buffer
->state
.pass
, NULL
);
1632 /* Record that HiZ is enabled if we can. */
1633 if (cmd_buffer
->state
.framebuffer
) {
1634 const struct anv_image_view
* const iview
=
1635 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1638 VkImageLayout layout
=
1639 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1641 enum isl_aux_usage aux_usage
=
1642 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1643 VK_IMAGE_ASPECT_DEPTH_BIT
,
1644 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
1647 cmd_buffer
->state
.hiz_enabled
= isl_aux_usage_has_hiz(aux_usage
);
1651 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1654 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1655 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1656 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1657 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1659 /* If secondary buffer supports conditional rendering
1660 * we should emit commands as if conditional rendering is enabled.
1662 cmd_buffer
->state
.conditional_render_enabled
=
1663 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1670 /* From the PRM, Volume 2a:
1672 * "Indirect State Pointers Disable
1674 * At the completion of the post-sync operation associated with this pipe
1675 * control packet, the indirect state pointers in the hardware are
1676 * considered invalid; the indirect pointers are not saved in the context.
1677 * If any new indirect state commands are executed in the command stream
1678 * while the pipe control is pending, the new indirect state commands are
1681 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1682 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1683 * commands are only considered as Indirect State Pointers. Once ISP is
1684 * issued in a context, SW must initialize by programming push constant
1685 * commands for all the shaders (at least to zero length) before attempting
1686 * any rendering operation for the same context."
1688 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1689 * even though they point to a BO that has been already unreferenced at
1690 * the end of the previous batch buffer. This has been fine so far since
1691 * we are protected by these scratch page (every address not covered by
1692 * a BO should be pointing to the scratch page). But on CNL, it is
1693 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1696 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1697 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1698 * context restore, so the mentioned hang doesn't happen. However,
1699 * software must program push constant commands for all stages prior to
1700 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1702 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1703 * constants have been loaded into the EUs prior to disable the push constants
1704 * so that it doesn't hang a previous 3DPRIMITIVE.
1707 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1709 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1710 pc
.StallAtPixelScoreboard
= true;
1711 pc
.CommandStreamerStallEnable
= true;
1713 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1714 pc
.IndirectStatePointersDisable
= true;
1715 pc
.CommandStreamerStallEnable
= true;
1720 genX(EndCommandBuffer
)(
1721 VkCommandBuffer commandBuffer
)
1723 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1725 if (anv_batch_has_error(&cmd_buffer
->batch
))
1726 return cmd_buffer
->batch
.status
;
1728 /* We want every command buffer to start with the PMA fix in a known state,
1729 * so we disable it at the end of the command buffer.
1731 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1733 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1735 emit_isp_disable(cmd_buffer
);
1737 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1743 genX(CmdExecuteCommands
)(
1744 VkCommandBuffer commandBuffer
,
1745 uint32_t commandBufferCount
,
1746 const VkCommandBuffer
* pCmdBuffers
)
1748 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1750 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1752 if (anv_batch_has_error(&primary
->batch
))
1755 /* The secondary command buffers will assume that the PMA fix is disabled
1756 * when they begin executing. Make sure this is true.
1758 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1760 /* The secondary command buffer doesn't know which textures etc. have been
1761 * flushed prior to their execution. Apply those flushes now.
1763 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1765 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1766 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1768 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1769 assert(!anv_batch_has_error(&secondary
->batch
));
1771 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1772 if (secondary
->state
.conditional_render_enabled
) {
1773 if (!primary
->state
.conditional_render_enabled
) {
1774 /* Secondary buffer is constructed as if it will be executed
1775 * with conditional rendering, we should satisfy this dependency
1776 * regardless of conditional rendering being enabled in primary.
1778 struct gen_mi_builder b
;
1779 gen_mi_builder_init(&b
, &primary
->batch
);
1780 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1781 gen_mi_imm(UINT64_MAX
));
1786 if (secondary
->usage_flags
&
1787 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1788 /* If we're continuing a render pass from the primary, we need to
1789 * copy the surface states for the current subpass into the storage
1790 * we allocated for them in BeginCommandBuffer.
1792 struct anv_bo
*ss_bo
=
1793 primary
->device
->surface_state_pool
.block_pool
.bo
;
1794 struct anv_state src_state
= primary
->state
.render_pass_states
;
1795 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1796 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1798 genX(cmd_buffer_so_memcpy
)(primary
,
1799 (struct anv_address
) {
1801 .offset
= dst_state
.offset
,
1803 (struct anv_address
) {
1805 .offset
= src_state
.offset
,
1807 src_state
.alloc_size
);
1810 anv_cmd_buffer_add_secondary(primary
, secondary
);
1813 /* The secondary isn't counted in our VF cache tracking so we need to
1814 * invalidate the whole thing.
1816 if (GEN_GEN
>= 8 && GEN_GEN
<= 9) {
1817 primary
->state
.pending_pipe_bits
|=
1818 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1821 /* The secondary may have selected a different pipeline (3D or compute) and
1822 * may have changed the current L3$ configuration. Reset our tracking
1823 * variables to invalid values to ensure that we re-emit these in the case
1824 * where we do any draws or compute dispatches from the primary after the
1825 * secondary has returned.
1827 primary
->state
.current_pipeline
= UINT32_MAX
;
1828 primary
->state
.current_l3_config
= NULL
;
1829 primary
->state
.current_hash_scale
= 0;
1831 /* Each of the secondary command buffers will use its own state base
1832 * address. We need to re-emit state base address for the primary after
1833 * all of the secondaries are done.
1835 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1838 genX(cmd_buffer_emit_state_base_address
)(primary
);
1841 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1842 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1843 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1846 * Program the hardware to use the specified L3 configuration.
1849 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1850 const struct gen_l3_config
*cfg
)
1853 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1856 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1857 intel_logd("L3 config transition: ");
1858 gen_dump_l3_config(cfg
, stderr
);
1861 UNUSED
const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1863 /* According to the hardware docs, the L3 partitioning can only be changed
1864 * while the pipeline is completely drained and the caches are flushed,
1865 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1867 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1868 pc
.DCFlushEnable
= true;
1869 pc
.PostSyncOperation
= NoWrite
;
1870 pc
.CommandStreamerStallEnable
= true;
1873 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1874 * invalidation of the relevant caches. Note that because RO invalidation
1875 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1876 * command is processed by the CS) we cannot combine it with the previous
1877 * stalling flush as the hardware documentation suggests, because that
1878 * would cause the CS to stall on previous rendering *after* RO
1879 * invalidation and wouldn't prevent the RO caches from being polluted by
1880 * concurrent rendering before the stall completes. This intentionally
1881 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1882 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1883 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1884 * already guarantee that there is no concurrent GPGPU kernel execution
1885 * (see SKL HSD 2132585).
1887 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1888 pc
.TextureCacheInvalidationEnable
= true;
1889 pc
.ConstantCacheInvalidationEnable
= true;
1890 pc
.InstructionCacheInvalidateEnable
= true;
1891 pc
.StateCacheInvalidationEnable
= true;
1892 pc
.PostSyncOperation
= NoWrite
;
1895 /* Now send a third stalling flush to make sure that invalidation is
1896 * complete when the L3 configuration registers are modified.
1898 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1899 pc
.DCFlushEnable
= true;
1900 pc
.PostSyncOperation
= NoWrite
;
1901 pc
.CommandStreamerStallEnable
= true;
1906 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1909 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1910 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1912 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1913 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1917 anv_pack_struct(&l3cr
, L3_ALLOCATION_REG
,
1919 .SLMEnable
= has_slm
,
1922 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1923 * in L3CNTLREG register. The default setting of the bit is not the
1924 * desirable behavior.
1926 .ErrorDetectionBehaviorControl
= true,
1927 .UseFullWays
= true,
1929 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1930 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1931 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1932 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1934 /* Set up the L3 partitioning. */
1935 emit_lri(&cmd_buffer
->batch
, L3_ALLOCATION_REG_num
, l3cr
);
1939 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1940 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1941 cfg
->n
[GEN_L3P_ALL
];
1942 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1943 cfg
->n
[GEN_L3P_ALL
];
1944 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1945 cfg
->n
[GEN_L3P_ALL
];
1947 assert(!cfg
->n
[GEN_L3P_ALL
]);
1949 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1950 * the matching space on the remaining banks has to be allocated to a
1951 * client (URB for all validated configurations) set to the
1952 * lower-bandwidth 2-bank address hashing mode.
1954 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1955 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1956 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1958 /* Minimum number of ways that can be allocated to the URB. */
1959 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1960 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1962 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1963 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1964 .ConvertDC_UC
= !has_dc
,
1965 .ConvertIS_UC
= !has_is
,
1966 .ConvertC_UC
= !has_c
,
1967 .ConvertT_UC
= !has_t
);
1969 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1970 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1971 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1973 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1974 .SLMEnable
= has_slm
,
1975 .URBLowBandwidth
= urb_low_bw
,
1976 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1978 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1980 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1981 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1983 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1984 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1985 .ISLowBandwidth
= 0,
1986 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1988 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1989 .TLowBandwidth
= 0);
1991 /* Set up the L3 partitioning. */
1992 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1993 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1994 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1997 if (cmd_buffer
->device
->physical
->cmd_parser_version
>= 4) {
1998 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1999 * them disabled to avoid crashing the system hard.
2001 uint32_t scratch1
, chicken3
;
2002 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
2003 .L3AtomicDisable
= !has_dc
);
2004 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
2005 .L3AtomicDisableMask
= true,
2006 .L3AtomicDisable
= !has_dc
);
2007 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
2008 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
2014 cmd_buffer
->state
.current_l3_config
= cfg
;
2018 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
2020 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
2021 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
2023 if (cmd_buffer
->device
->physical
->always_flush_cache
)
2024 bits
|= ANV_PIPE_FLUSH_BITS
| ANV_PIPE_INVALIDATE_BITS
;
2027 * From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization":
2029 * Write synchronization is a special case of end-of-pipe
2030 * synchronization that requires that the render cache and/or depth
2031 * related caches are flushed to memory, where the data will become
2032 * globally visible. This type of synchronization is required prior to
2033 * SW (CPU) actually reading the result data from memory, or initiating
2034 * an operation that will use as a read surface (such as a texture
2035 * surface) a previous render target and/or depth/stencil buffer
2038 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
2040 * Exercising the write cache flush bits (Render Target Cache Flush
2041 * Enable, Depth Cache Flush Enable, DC Flush) in PIPE_CONTROL only
2042 * ensures the write caches are flushed and doesn't guarantee the data
2043 * is globally visible.
2045 * SW can track the completion of the end-of-pipe-synchronization by
2046 * using "Notify Enable" and "PostSync Operation - Write Immediate
2047 * Data" in the PIPE_CONTROL command.
2049 * In other words, flushes are pipelined while invalidations are handled
2050 * immediately. Therefore, if we're flushing anything then we need to
2051 * schedule an end-of-pipe sync before any invalidations can happen.
2053 if (bits
& ANV_PIPE_FLUSH_BITS
)
2054 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2057 /* HSD 1209978178: docs say that before programming the aux table:
2059 * "Driver must ensure that the engine is IDLE but ensure it doesn't
2060 * add extra flushes in the case it knows that the engine is already
2063 if (GEN_GEN
== 12 && (bits
& ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
))
2064 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2066 /* If we're going to do an invalidate and we have a pending end-of-pipe
2067 * sync that has yet to be resolved, we do the end-of-pipe sync now.
2069 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
2070 (bits
& ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
)) {
2071 bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
2072 bits
&= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2075 if (GEN_GEN
>= 12 &&
2076 ((bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
) ||
2077 (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
))) {
2078 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
2081 * Unified Cache (Tile Cache Disabled):
2083 * When the Color and Depth (Z) streams are enabled to be cached in
2084 * the DC space of L2, Software must use "Render Target Cache Flush
2085 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
2086 * Flush" for getting the color and depth (Z) write data to be
2087 * globally observable. In this mode of operation it is not required
2088 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
2090 bits
|= ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2093 /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
2094 * invalidates the instruction cache
2096 if (GEN_GEN
== 12 && (bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
))
2097 bits
|= ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2099 if ((GEN_GEN
>= 8 && GEN_GEN
<= 9) &&
2100 (bits
& ANV_PIPE_CS_STALL_BIT
) &&
2101 (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
)) {
2102 /* If we are doing a VF cache invalidate AND a CS stall (it must be
2103 * both) then we can reset our vertex cache tracking.
2105 memset(cmd_buffer
->state
.gfx
.vb_dirty_ranges
, 0,
2106 sizeof(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
2107 memset(&cmd_buffer
->state
.gfx
.ib_dirty_range
, 0,
2108 sizeof(cmd_buffer
->state
.gfx
.ib_dirty_range
));
2111 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2113 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2114 * programmed prior to programming a PIPECONTROL command with "LRI
2115 * Post Sync Operation" in GPGPU mode of operation (i.e when
2116 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2118 * The same text exists a few rows below for Post Sync Op.
2120 * On Gen12 this is GEN:BUG:1607156449.
2122 if (bits
& ANV_PIPE_POST_SYNC_BIT
) {
2123 if ((GEN_GEN
== 9 || (GEN_GEN
== 12 && devinfo
->revision
== 0 /* A0 */)) &&
2124 cmd_buffer
->state
.current_pipeline
== GPGPU
)
2125 bits
|= ANV_PIPE_CS_STALL_BIT
;
2126 bits
&= ~ANV_PIPE_POST_SYNC_BIT
;
2129 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2130 ANV_PIPE_END_OF_PIPE_SYNC_BIT
)) {
2131 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2133 pipe
.TileCacheFlushEnable
= bits
& ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2135 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2136 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2137 pipe
.RenderTargetCacheFlushEnable
=
2138 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2140 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
2141 * be set with any PIPE_CONTROL with Depth Flush Enable bit set.
2144 pipe
.DepthStallEnable
=
2145 pipe
.DepthCacheFlushEnable
|| (bits
& ANV_PIPE_DEPTH_STALL_BIT
);
2147 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
2150 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
2151 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2153 /* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory":
2155 * "The most common action to perform upon reaching a
2156 * synchronization point is to write a value out to memory. An
2157 * immediate value (included with the synchronization command) may
2161 * From Broadwell PRM, volume 7, "End-of-Pipe Synchronization":
2163 * "In case the data flushed out by the render engine is to be
2164 * read back in to the render engine in coherent manner, then the
2165 * render engine has to wait for the fence completion before
2166 * accessing the flushed data. This can be achieved by following
2167 * means on various products: PIPE_CONTROL command with CS Stall
2168 * and the required write caches flushed with Post-Sync-Operation
2169 * as Write Immediate Data.
2172 * - Workload-1 (3D/GPGPU/MEDIA)
2173 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2174 * Immediate Data, Required Write Cache Flush bits set)
2175 * - Workload-2 (Can use the data produce or output by
2178 if (bits
& ANV_PIPE_END_OF_PIPE_SYNC_BIT
) {
2179 pipe
.CommandStreamerStallEnable
= true;
2180 pipe
.PostSyncOperation
= WriteImmediateData
;
2181 pipe
.Address
= (struct anv_address
) {
2182 .bo
= cmd_buffer
->device
->workaround_bo
,
2188 * According to the Broadwell documentation, any PIPE_CONTROL with the
2189 * "Command Streamer Stall" bit set must also have another bit set,
2190 * with five different options:
2192 * - Render Target Cache Flush
2193 * - Depth Cache Flush
2194 * - Stall at Pixel Scoreboard
2195 * - Post-Sync Operation
2199 * I chose "Stall at Pixel Scoreboard" since that's what we use in
2200 * mesa and it seems to work fine. The choice is fairly arbitrary.
2202 if (pipe
.CommandStreamerStallEnable
&&
2203 !pipe
.RenderTargetCacheFlushEnable
&&
2204 !pipe
.DepthCacheFlushEnable
&&
2205 !pipe
.StallAtPixelScoreboard
&&
2206 !pipe
.PostSyncOperation
&&
2207 !pipe
.DepthStallEnable
&&
2208 !pipe
.DCFlushEnable
)
2209 pipe
.StallAtPixelScoreboard
= true;
2212 /* If a render target flush was emitted, then we can toggle off the bit
2213 * saying that render target writes are ongoing.
2215 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
2216 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
2218 if (GEN_IS_HASWELL
) {
2219 /* Haswell needs addition work-arounds:
2221 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
2224 * PIPE_CONTROL command with the CS Stall and the required write
2225 * caches flushed with Post-SyncOperation as Write Immediate Data
2226 * followed by eight dummy MI_STORE_DATA_IMM (write to scratch
2231 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2232 * Immediate Data, Required Write Cache Flush bits set)
2233 * - MI_STORE_DATA_IMM (8 times) (Dummy data, Scratch Address)
2234 * - Workload-2 (Can use the data produce or output by
2237 * Unfortunately, both the PRMs and the internal docs are a bit
2238 * out-of-date in this regard. What the windows driver does (and
2239 * this appears to actually work) is to emit a register read from the
2240 * memory address written by the pipe control above.
2242 * What register we load into doesn't matter. We choose an indirect
2243 * rendering register because we know it always exists and it's one
2244 * of the first registers the command parser allows us to write. If
2245 * you don't have command parser support in your kernel (pre-4.2),
2246 * this will get turned into MI_NOOP and you won't get the
2247 * workaround. Unfortunately, there's just not much we can do in
2248 * that case. This register is perfectly safe to write since we
2249 * always re-load all of the indirect draw registers right before
2250 * 3DPRIMITIVE when needed anyway.
2252 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2253 lrm
.RegisterAddress
= 0x243C; /* GEN7_3DPRIM_START_INSTANCE */
2254 lrm
.MemoryAddress
= (struct anv_address
) {
2255 .bo
= cmd_buffer
->device
->workaround_bo
,
2261 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2262 ANV_PIPE_END_OF_PIPE_SYNC_BIT
);
2265 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
2266 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2268 * "If the VF Cache Invalidation Enable is set to a 1 in a
2269 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
2270 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
2271 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
2274 * This appears to hang Broadwell, so we restrict it to just gen9.
2276 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
2277 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
2279 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2280 pipe
.StateCacheInvalidationEnable
=
2281 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
2282 pipe
.ConstantCacheInvalidationEnable
=
2283 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2284 pipe
.VFCacheInvalidationEnable
=
2285 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2286 pipe
.TextureCacheInvalidationEnable
=
2287 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2288 pipe
.InstructionCacheInvalidateEnable
=
2289 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
2291 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2293 * "When VF Cache Invalidate is set “Post Sync Operation” must be
2294 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
2295 * “Write Timestamp”.
2297 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
2298 pipe
.PostSyncOperation
= WriteImmediateData
;
2300 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
2305 if ((bits
& ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
) &&
2306 cmd_buffer
->device
->info
.has_aux_map
) {
2307 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2308 lri
.RegisterOffset
= GENX(GFX_CCS_AUX_INV_num
);
2314 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
2317 cmd_buffer
->state
.pending_pipe_bits
= bits
;
2320 void genX(CmdPipelineBarrier
)(
2321 VkCommandBuffer commandBuffer
,
2322 VkPipelineStageFlags srcStageMask
,
2323 VkPipelineStageFlags destStageMask
,
2325 uint32_t memoryBarrierCount
,
2326 const VkMemoryBarrier
* pMemoryBarriers
,
2327 uint32_t bufferMemoryBarrierCount
,
2328 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
2329 uint32_t imageMemoryBarrierCount
,
2330 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
2332 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2334 /* XXX: Right now, we're really dumb and just flush whatever categories
2335 * the app asks for. One of these days we may make this a bit better
2336 * but right now that's all the hardware allows for in most areas.
2338 VkAccessFlags src_flags
= 0;
2339 VkAccessFlags dst_flags
= 0;
2341 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
2342 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
2343 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
2346 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
2347 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
2348 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
2351 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
2352 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
2353 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
2354 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
2355 const VkImageSubresourceRange
*range
=
2356 &pImageMemoryBarriers
[i
].subresourceRange
;
2358 uint32_t base_layer
, layer_count
;
2359 if (image
->type
== VK_IMAGE_TYPE_3D
) {
2361 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
2363 base_layer
= range
->baseArrayLayer
;
2364 layer_count
= anv_get_layerCount(image
, range
);
2367 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
2368 transition_depth_buffer(cmd_buffer
, image
,
2369 base_layer
, layer_count
,
2370 pImageMemoryBarriers
[i
].oldLayout
,
2371 pImageMemoryBarriers
[i
].newLayout
);
2374 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
2375 transition_stencil_buffer(cmd_buffer
, image
,
2376 range
->baseMipLevel
,
2377 anv_get_levelCount(image
, range
),
2378 base_layer
, layer_count
,
2379 pImageMemoryBarriers
[i
].oldLayout
,
2380 pImageMemoryBarriers
[i
].newLayout
);
2383 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2384 VkImageAspectFlags color_aspects
=
2385 anv_image_expand_aspects(image
, range
->aspectMask
);
2386 uint32_t aspect_bit
;
2387 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
2388 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
2389 range
->baseMipLevel
,
2390 anv_get_levelCount(image
, range
),
2391 base_layer
, layer_count
,
2392 pImageMemoryBarriers
[i
].oldLayout
,
2393 pImageMemoryBarriers
[i
].newLayout
);
2398 cmd_buffer
->state
.pending_pipe_bits
|=
2399 anv_pipe_flush_bits_for_access_flags(src_flags
) |
2400 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
2404 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
2406 VkShaderStageFlags stages
=
2407 cmd_buffer
->state
.gfx
.pipeline
->active_stages
;
2409 /* In order to avoid thrash, we assume that vertex and fragment stages
2410 * always exist. In the rare case where one is missing *and* the other
2411 * uses push concstants, this may be suboptimal. However, avoiding stalls
2412 * seems more important.
2414 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
2416 if (stages
== cmd_buffer
->state
.push_constant_stages
)
2420 const unsigned push_constant_kb
= 32;
2421 #elif GEN_IS_HASWELL
2422 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2424 const unsigned push_constant_kb
= 16;
2427 const unsigned num_stages
=
2428 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2429 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2431 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2432 * units of 2KB. Incidentally, these are the same platforms that have
2433 * 32KB worth of push constant space.
2435 if (push_constant_kb
== 32)
2436 size_per_stage
&= ~1u;
2438 uint32_t kb_used
= 0;
2439 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2440 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2441 anv_batch_emit(&cmd_buffer
->batch
,
2442 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2443 alloc
._3DCommandSubOpcode
= 18 + i
;
2444 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2445 alloc
.ConstantBufferSize
= push_size
;
2447 kb_used
+= push_size
;
2450 anv_batch_emit(&cmd_buffer
->batch
,
2451 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2452 alloc
.ConstantBufferOffset
= kb_used
;
2453 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2456 cmd_buffer
->state
.push_constant_stages
= stages
;
2458 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2460 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2461 * the next 3DPRIMITIVE command after programming the
2462 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2464 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2465 * pipeline setup, we need to dirty push constants.
2467 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2470 static struct anv_address
2471 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2472 struct anv_descriptor_set
*set
)
2475 /* This is a normal descriptor set */
2476 return (struct anv_address
) {
2477 .bo
= set
->pool
->bo
,
2478 .offset
= set
->desc_mem
.offset
,
2481 /* This is a push descriptor set. We have to flag it as used on the GPU
2482 * so that the next time we push descriptors, we grab a new memory.
2484 struct anv_push_descriptor_set
*push_set
=
2485 (struct anv_push_descriptor_set
*)set
;
2486 push_set
->set_used_on_gpu
= true;
2488 return (struct anv_address
) {
2489 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2490 .offset
= set
->desc_mem
.offset
,
2496 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2497 struct anv_cmd_pipeline_state
*pipe_state
,
2498 struct anv_shader_bin
*shader
,
2499 struct anv_state
*bt_state
)
2501 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2502 uint32_t state_offset
;
2504 struct anv_pipeline_bind_map
*map
= &shader
->bind_map
;
2505 if (map
->surface_count
== 0) {
2506 *bt_state
= (struct anv_state
) { 0, };
2510 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2513 uint32_t *bt_map
= bt_state
->map
;
2515 if (bt_state
->map
== NULL
)
2516 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2518 /* We only need to emit relocs if we're not using softpin. If we are using
2519 * softpin then we always keep all user-allocated memory objects resident.
2521 const bool need_client_mem_relocs
=
2522 !cmd_buffer
->device
->physical
->use_softpin
;
2524 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2525 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2527 struct anv_state surface_state
;
2529 switch (binding
->set
) {
2530 case ANV_DESCRIPTOR_SET_NULL
:
2534 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
:
2535 /* Color attachment binding */
2536 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
2537 if (binding
->index
< subpass
->color_count
) {
2538 const unsigned att
=
2539 subpass
->color_attachments
[binding
->index
].attachment
;
2541 /* From the Vulkan 1.0.46 spec:
2543 * "If any color or depth/stencil attachments are
2544 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2547 if (att
== VK_ATTACHMENT_UNUSED
) {
2548 surface_state
= cmd_buffer
->state
.null_surface_state
;
2550 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2553 surface_state
= cmd_buffer
->state
.null_surface_state
;
2556 assert(surface_state
.map
);
2557 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2560 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
: {
2561 struct anv_state surface_state
=
2562 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2564 struct anv_address constant_data
= {
2565 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2566 .offset
= shader
->constant_data
.offset
,
2568 unsigned constant_data_size
= shader
->constant_data_size
;
2570 const enum isl_format format
=
2571 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2572 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2573 surface_state
, format
,
2574 constant_data
, constant_data_size
, 1);
2576 assert(surface_state
.map
);
2577 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2578 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2582 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
: {
2583 /* This is always the first binding for compute shaders */
2584 assert(shader
->stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2586 struct anv_state surface_state
=
2587 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2589 const enum isl_format format
=
2590 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2591 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2593 cmd_buffer
->state
.compute
.num_workgroups
,
2596 assert(surface_state
.map
);
2597 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2598 if (need_client_mem_relocs
) {
2599 add_surface_reloc(cmd_buffer
, surface_state
,
2600 cmd_buffer
->state
.compute
.num_workgroups
);
2605 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2606 /* This is a descriptor set buffer so the set index is actually
2607 * given by binding->binding. (Yes, that's confusing.)
2609 struct anv_descriptor_set
*set
=
2610 pipe_state
->descriptors
[binding
->index
];
2611 assert(set
->desc_mem
.alloc_size
);
2612 assert(set
->desc_surface_state
.alloc_size
);
2613 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2614 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2615 anv_descriptor_set_address(cmd_buffer
, set
));
2620 assert(binding
->set
< MAX_SETS
);
2621 const struct anv_descriptor
*desc
=
2622 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2624 switch (desc
->type
) {
2625 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2626 /* Nothing for us to do here */
2629 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2630 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2631 struct anv_surface_state sstate
=
2632 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2633 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2634 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2635 surface_state
= sstate
.state
;
2636 assert(surface_state
.alloc_size
);
2637 if (need_client_mem_relocs
)
2638 add_surface_state_relocs(cmd_buffer
, sstate
);
2641 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2642 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
2643 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2644 /* For depth and stencil input attachments, we treat it like any
2645 * old texture that a user may have bound.
2647 assert(desc
->image_view
->n_planes
== 1);
2648 struct anv_surface_state sstate
=
2649 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2650 desc
->image_view
->planes
[0].general_sampler_surface_state
:
2651 desc
->image_view
->planes
[0].optimal_sampler_surface_state
;
2652 surface_state
= sstate
.state
;
2653 assert(surface_state
.alloc_size
);
2654 if (need_client_mem_relocs
)
2655 add_surface_state_relocs(cmd_buffer
, sstate
);
2657 /* For color input attachments, we create the surface state at
2658 * vkBeginRenderPass time so that we can include aux and clear
2659 * color information.
2661 assert(binding
->input_attachment_index
< subpass
->input_count
);
2662 const unsigned subpass_att
= binding
->input_attachment_index
;
2663 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2664 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2668 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2669 struct anv_surface_state sstate
= (binding
->write_only
)
2670 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2671 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2672 surface_state
= sstate
.state
;
2673 assert(surface_state
.alloc_size
);
2674 if (need_client_mem_relocs
)
2675 add_surface_state_relocs(cmd_buffer
, sstate
);
2679 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2680 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2681 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2682 surface_state
= desc
->buffer_view
->surface_state
;
2683 assert(surface_state
.alloc_size
);
2684 if (need_client_mem_relocs
) {
2685 add_surface_reloc(cmd_buffer
, surface_state
,
2686 desc
->buffer_view
->address
);
2690 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2691 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2692 /* Compute the offset within the buffer */
2693 struct anv_push_constants
*push
=
2694 &cmd_buffer
->state
.push_constants
[shader
->stage
];
2696 uint32_t dynamic_offset
=
2697 push
->dynamic_offsets
[binding
->dynamic_offset_index
];
2698 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2699 /* Clamp to the buffer size */
2700 offset
= MIN2(offset
, desc
->buffer
->size
);
2701 /* Clamp the range to the buffer size */
2702 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2704 /* Align the range for consistency */
2705 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
)
2706 range
= align_u32(range
, ANV_UBO_BOUNDS_CHECK_ALIGNMENT
);
2708 struct anv_address address
=
2709 anv_address_add(desc
->buffer
->address
, offset
);
2712 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2713 enum isl_format format
=
2714 anv_isl_format_for_descriptor_type(desc
->type
);
2716 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2717 format
, address
, range
, 1);
2718 if (need_client_mem_relocs
)
2719 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2723 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2724 surface_state
= (binding
->write_only
)
2725 ? desc
->buffer_view
->writeonly_storage_surface_state
2726 : desc
->buffer_view
->storage_surface_state
;
2727 assert(surface_state
.alloc_size
);
2728 if (need_client_mem_relocs
) {
2729 add_surface_reloc(cmd_buffer
, surface_state
,
2730 desc
->buffer_view
->address
);
2735 assert(!"Invalid descriptor type");
2738 assert(surface_state
.map
);
2739 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2749 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2750 struct anv_cmd_pipeline_state
*pipe_state
,
2751 struct anv_shader_bin
*shader
,
2752 struct anv_state
*state
)
2754 struct anv_pipeline_bind_map
*map
= &shader
->bind_map
;
2755 if (map
->sampler_count
== 0) {
2756 *state
= (struct anv_state
) { 0, };
2760 uint32_t size
= map
->sampler_count
* 16;
2761 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2763 if (state
->map
== NULL
)
2764 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2766 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2767 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2768 const struct anv_descriptor
*desc
=
2769 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2771 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2772 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2775 struct anv_sampler
*sampler
= desc
->sampler
;
2777 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2778 * happens to be zero.
2780 if (sampler
== NULL
)
2783 memcpy(state
->map
+ (s
* 16),
2784 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2791 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
,
2792 struct anv_cmd_pipeline_state
*pipe_state
,
2793 struct anv_shader_bin
**shaders
,
2794 uint32_t num_shaders
)
2796 const VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
;
2797 VkShaderStageFlags flushed
= 0;
2799 VkResult result
= VK_SUCCESS
;
2800 for (uint32_t i
= 0; i
< num_shaders
; i
++) {
2804 gl_shader_stage stage
= shaders
[i
]->stage
;
2805 VkShaderStageFlags vk_stage
= mesa_to_vk_shader_stage(stage
);
2806 if ((vk_stage
& dirty
) == 0)
2809 result
= emit_samplers(cmd_buffer
, pipe_state
, shaders
[i
],
2810 &cmd_buffer
->state
.samplers
[stage
]);
2811 if (result
!= VK_SUCCESS
)
2813 result
= emit_binding_table(cmd_buffer
, pipe_state
, shaders
[i
],
2814 &cmd_buffer
->state
.binding_tables
[stage
]);
2815 if (result
!= VK_SUCCESS
)
2818 flushed
|= vk_stage
;
2821 if (result
!= VK_SUCCESS
) {
2822 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2824 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2825 if (result
!= VK_SUCCESS
)
2828 /* Re-emit state base addresses so we get the new surface state base
2829 * address before we start emitting binding tables etc.
2831 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2833 /* Re-emit all active binding tables */
2836 for (uint32_t i
= 0; i
< num_shaders
; i
++) {
2840 gl_shader_stage stage
= shaders
[i
]->stage
;
2842 result
= emit_samplers(cmd_buffer
, pipe_state
, shaders
[i
],
2843 &cmd_buffer
->state
.samplers
[stage
]);
2844 if (result
!= VK_SUCCESS
) {
2845 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2848 result
= emit_binding_table(cmd_buffer
, pipe_state
, shaders
[i
],
2849 &cmd_buffer
->state
.binding_tables
[stage
]);
2850 if (result
!= VK_SUCCESS
) {
2851 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2855 flushed
|= mesa_to_vk_shader_stage(stage
);
2859 cmd_buffer
->state
.descriptors_dirty
&= ~flushed
;
2865 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2868 static const uint32_t sampler_state_opcodes
[] = {
2869 [MESA_SHADER_VERTEX
] = 43,
2870 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2871 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2872 [MESA_SHADER_GEOMETRY
] = 46,
2873 [MESA_SHADER_FRAGMENT
] = 47,
2874 [MESA_SHADER_COMPUTE
] = 0,
2877 static const uint32_t binding_table_opcodes
[] = {
2878 [MESA_SHADER_VERTEX
] = 38,
2879 [MESA_SHADER_TESS_CTRL
] = 39,
2880 [MESA_SHADER_TESS_EVAL
] = 40,
2881 [MESA_SHADER_GEOMETRY
] = 41,
2882 [MESA_SHADER_FRAGMENT
] = 42,
2883 [MESA_SHADER_COMPUTE
] = 0,
2886 anv_foreach_stage(s
, stages
) {
2887 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2888 assert(binding_table_opcodes
[s
] > 0);
2890 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2891 anv_batch_emit(&cmd_buffer
->batch
,
2892 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2893 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2894 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2898 /* Always emit binding table pointers if we're asked to, since on SKL
2899 * this is what flushes push constants. */
2900 anv_batch_emit(&cmd_buffer
->batch
,
2901 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2902 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2903 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2908 static struct anv_address
2909 get_push_range_address(struct anv_cmd_buffer
*cmd_buffer
,
2910 gl_shader_stage stage
,
2911 const struct anv_push_range
*range
)
2913 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2914 switch (range
->set
) {
2915 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2916 /* This is a descriptor set buffer so the set index is
2917 * actually given by binding->binding. (Yes, that's
2920 struct anv_descriptor_set
*set
=
2921 gfx_state
->base
.descriptors
[range
->index
];
2922 return anv_descriptor_set_address(cmd_buffer
, set
);
2925 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
: {
2926 struct anv_state state
=
2927 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2928 return (struct anv_address
) {
2929 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2930 .offset
= state
.offset
,
2935 assert(range
->set
< MAX_SETS
);
2936 struct anv_descriptor_set
*set
=
2937 gfx_state
->base
.descriptors
[range
->set
];
2938 const struct anv_descriptor
*desc
=
2939 &set
->descriptors
[range
->index
];
2941 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2942 return desc
->buffer_view
->address
;
2944 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2945 struct anv_push_constants
*push
=
2946 &cmd_buffer
->state
.push_constants
[stage
];
2947 uint32_t dynamic_offset
=
2948 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2949 return anv_address_add(desc
->buffer
->address
,
2950 desc
->offset
+ dynamic_offset
);
2957 /** Returns the size in bytes of the bound buffer
2959 * The range is relative to the start of the buffer, not the start of the
2960 * range. The returned range may be smaller than
2962 * (range->start + range->length) * 32;
2965 get_push_range_bound_size(struct anv_cmd_buffer
*cmd_buffer
,
2966 gl_shader_stage stage
,
2967 const struct anv_push_range
*range
)
2969 assert(stage
!= MESA_SHADER_COMPUTE
);
2970 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2971 switch (range
->set
) {
2972 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2973 struct anv_descriptor_set
*set
=
2974 gfx_state
->base
.descriptors
[range
->index
];
2975 assert(range
->start
* 32 < set
->desc_mem
.alloc_size
);
2976 assert((range
->start
+ range
->length
) * 32 <= set
->desc_mem
.alloc_size
);
2977 return set
->desc_mem
.alloc_size
;
2980 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
:
2981 return (range
->start
+ range
->length
) * 32;
2984 assert(range
->set
< MAX_SETS
);
2985 struct anv_descriptor_set
*set
=
2986 gfx_state
->base
.descriptors
[range
->set
];
2987 const struct anv_descriptor
*desc
=
2988 &set
->descriptors
[range
->index
];
2990 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2991 return desc
->buffer_view
->range
;
2993 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2994 /* Compute the offset within the buffer */
2995 struct anv_push_constants
*push
=
2996 &cmd_buffer
->state
.push_constants
[stage
];
2997 uint32_t dynamic_offset
=
2998 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2999 uint64_t offset
= desc
->offset
+ dynamic_offset
;
3000 /* Clamp to the buffer size */
3001 offset
= MIN2(offset
, desc
->buffer
->size
);
3002 /* Clamp the range to the buffer size */
3003 uint32_t bound_range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
3005 /* Align the range for consistency */
3006 bound_range
= align_u32(bound_range
, ANV_UBO_BOUNDS_CHECK_ALIGNMENT
);
3015 cmd_buffer_emit_push_constant(struct anv_cmd_buffer
*cmd_buffer
,
3016 gl_shader_stage stage
,
3017 struct anv_address
*buffers
,
3018 unsigned buffer_count
)
3020 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3021 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3023 static const uint32_t push_constant_opcodes
[] = {
3024 [MESA_SHADER_VERTEX
] = 21,
3025 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3026 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3027 [MESA_SHADER_GEOMETRY
] = 22,
3028 [MESA_SHADER_FRAGMENT
] = 23,
3029 [MESA_SHADER_COMPUTE
] = 0,
3032 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3033 assert(push_constant_opcodes
[stage
] > 0);
3035 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
3036 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3038 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3039 const struct anv_pipeline_bind_map
*bind_map
=
3040 &pipeline
->shaders
[stage
]->bind_map
;
3043 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3046 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3047 /* The Skylake PRM contains the following restriction:
3049 * "The driver must ensure The following case does not occur
3050 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3051 * buffer 3 read length equal to zero committed followed by a
3052 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3055 * To avoid this, we program the buffers in the highest slots.
3056 * This way, slot 0 is only used if slot 3 is also used.
3058 assert(buffer_count
<= 4);
3059 const unsigned shift
= 4 - buffer_count
;
3060 for (unsigned i
= 0; i
< buffer_count
; i
++) {
3061 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3063 /* At this point we only have non-empty ranges */
3064 assert(range
->length
> 0);
3066 /* For Ivy Bridge, make sure we only set the first range (actual
3069 assert((GEN_GEN
>= 8 || GEN_IS_HASWELL
) || i
== 0);
3071 c
.ConstantBody
.ReadLength
[i
+ shift
] = range
->length
;
3072 c
.ConstantBody
.Buffer
[i
+ shift
] =
3073 anv_address_add(buffers
[i
], range
->start
* 32);
3076 /* For Ivy Bridge, push constants are relative to dynamic state
3077 * base address and we only ever push actual push constants.
3079 if (bind_map
->push_ranges
[0].length
> 0) {
3080 assert(buffer_count
== 1);
3081 assert(bind_map
->push_ranges
[0].set
==
3082 ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
);
3083 assert(buffers
[0].bo
==
3084 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
);
3085 c
.ConstantBody
.ReadLength
[0] = bind_map
->push_ranges
[0].length
;
3086 c
.ConstantBody
.Buffer
[0].bo
= NULL
;
3087 c
.ConstantBody
.Buffer
[0].offset
= buffers
[0].offset
;
3089 assert(bind_map
->push_ranges
[1].length
== 0);
3090 assert(bind_map
->push_ranges
[2].length
== 0);
3091 assert(bind_map
->push_ranges
[3].length
== 0);
3099 cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer
*cmd_buffer
,
3100 uint32_t shader_mask
,
3101 struct anv_address
*buffers
,
3102 uint32_t buffer_count
)
3104 if (buffer_count
== 0) {
3105 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_ALL
), c
) {
3106 c
.ShaderUpdateEnable
= shader_mask
;
3107 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3112 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3113 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3115 static const uint32_t push_constant_opcodes
[] = {
3116 [MESA_SHADER_VERTEX
] = 21,
3117 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3118 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3119 [MESA_SHADER_GEOMETRY
] = 22,
3120 [MESA_SHADER_FRAGMENT
] = 23,
3121 [MESA_SHADER_COMPUTE
] = 0,
3124 gl_shader_stage stage
= vk_to_mesa_shader_stage(shader_mask
);
3125 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3126 assert(push_constant_opcodes
[stage
] > 0);
3128 const struct anv_pipeline_bind_map
*bind_map
=
3129 &pipeline
->shaders
[stage
]->bind_map
;
3132 const uint32_t buffer_mask
= (1 << buffer_count
) - 1;
3133 const uint32_t num_dwords
= 2 + 2 * buffer_count
;
3135 dw
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3136 GENX(3DSTATE_CONSTANT_ALL
),
3137 .ShaderUpdateEnable
= shader_mask
,
3138 .PointerBufferMask
= buffer_mask
,
3139 .MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
);
3141 for (int i
= 0; i
< buffer_count
; i
++) {
3142 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3143 GENX(3DSTATE_CONSTANT_ALL_DATA_pack
)(
3144 &cmd_buffer
->batch
, dw
+ 2 + i
* 2,
3145 &(struct GENX(3DSTATE_CONSTANT_ALL_DATA
)) {
3146 .PointerToConstantBuffer
=
3147 anv_address_add(buffers
[i
], range
->start
* 32),
3148 .ConstantBufferReadLength
= range
->length
,
3155 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
3156 VkShaderStageFlags dirty_stages
)
3158 VkShaderStageFlags flushed
= 0;
3159 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3160 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3163 uint32_t nobuffer_stages
= 0;
3166 anv_foreach_stage(stage
, dirty_stages
) {
3167 unsigned buffer_count
= 0;
3168 flushed
|= mesa_to_vk_shader_stage(stage
);
3169 UNUSED
uint32_t max_push_range
= 0;
3171 struct anv_address buffers
[4] = {};
3172 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3173 const struct anv_pipeline_bind_map
*bind_map
=
3174 &pipeline
->shaders
[stage
]->bind_map
;
3175 struct anv_push_constants
*push
=
3176 &cmd_buffer
->state
.push_constants
[stage
];
3178 if (cmd_buffer
->device
->robust_buffer_access
) {
3179 push
->push_reg_mask
= 0;
3180 /* Start of the current range in the shader, relative to the start
3181 * of push constants in the shader.
3183 unsigned range_start_reg
= 0;
3184 for (unsigned i
= 0; i
< 4; i
++) {
3185 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3186 if (range
->length
== 0)
3189 unsigned bound_size
=
3190 get_push_range_bound_size(cmd_buffer
, stage
, range
);
3191 if (bound_size
>= range
->start
* 32) {
3192 unsigned bound_regs
=
3193 MIN2(DIV_ROUND_UP(bound_size
, 32) - range
->start
,
3195 assert(range_start_reg
+ bound_regs
<= 64);
3196 push
->push_reg_mask
|= BITFIELD64_RANGE(range_start_reg
,
3200 cmd_buffer
->state
.push_constants_dirty
|=
3201 mesa_to_vk_shader_stage(stage
);
3203 range_start_reg
+= range
->length
;
3207 /* We have to gather buffer addresses as a second step because the
3208 * loop above puts data into the push constant area and the call to
3209 * get_push_range_address is what locks our push constants and copies
3210 * them into the actual GPU buffer. If we did the two loops at the
3211 * same time, we'd risk only having some of the sizes in the push
3212 * constant buffer when we did the copy.
3214 for (unsigned i
= 0; i
< 4; i
++) {
3215 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3216 if (range
->length
== 0)
3219 buffers
[i
] = get_push_range_address(cmd_buffer
, stage
, range
);
3220 max_push_range
= MAX2(max_push_range
, range
->length
);
3224 /* We have at most 4 buffers but they should be tightly packed */
3225 for (unsigned i
= buffer_count
; i
< 4; i
++)
3226 assert(bind_map
->push_ranges
[i
].length
== 0);
3230 /* If this stage doesn't have any push constants, emit it later in a
3231 * single CONSTANT_ALL packet.
3233 if (buffer_count
== 0) {
3234 nobuffer_stages
|= 1 << stage
;
3238 /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
3239 * contains only 5 bits, so we can only use it for buffers smaller than
3242 if (max_push_range
< 32) {
3243 cmd_buffer_emit_push_constant_all(cmd_buffer
, 1 << stage
,
3244 buffers
, buffer_count
);
3249 cmd_buffer_emit_push_constant(cmd_buffer
, stage
, buffers
, buffer_count
);
3253 if (nobuffer_stages
)
3254 cmd_buffer_emit_push_constant_all(cmd_buffer
, nobuffer_stages
, NULL
, 0);
3257 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
3261 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3263 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3266 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
3268 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->base
.l3_config
);
3270 genX(cmd_buffer_emit_hashing_mode
)(cmd_buffer
, UINT_MAX
, UINT_MAX
, 1);
3272 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3274 /* Apply any pending pipeline flushes we may have. We want to apply them
3275 * now because, if any of those flushes are for things like push constants,
3276 * the GPU will read the state at weird times.
3278 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3280 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
3281 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
3282 vb_emit
|= pipeline
->vb_used
;
3285 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
3286 const uint32_t num_dwords
= 1 + num_buffers
* 4;
3288 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3289 GENX(3DSTATE_VERTEX_BUFFERS
));
3291 for_each_bit(vb
, vb_emit
) {
3292 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
3293 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
3295 struct GENX(VERTEX_BUFFER_STATE
) state
= {
3296 .VertexBufferIndex
= vb
,
3298 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
3300 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
3301 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
3304 .AddressModifyEnable
= true,
3305 .BufferPitch
= pipeline
->vb
[vb
].stride
,
3306 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
3309 .BufferSize
= buffer
->size
- offset
3311 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
3315 #if GEN_GEN >= 8 && GEN_GEN <= 9
3316 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
, vb
,
3317 state
.BufferStartingAddress
,
3321 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
3326 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
3329 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
3330 /* We don't need any per-buffer dirty tracking because you're not
3331 * allowed to bind different XFB buffers while XFB is enabled.
3333 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3334 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
3335 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3337 sob
.SOBufferIndex
= idx
;
3339 sob
._3DCommandOpcode
= 0;
3340 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ idx
;
3343 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
3344 sob
.SOBufferEnable
= true;
3345 sob
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
,
3346 sob
.StreamOffsetWriteEnable
= false;
3347 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
3349 /* Size is in DWords - 1 */
3350 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
3355 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
3357 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3361 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
3362 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->base
.batch
);
3364 /* If the pipeline changed, we may need to re-allocate push constant
3367 cmd_buffer_alloc_push_constants(cmd_buffer
);
3371 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
3372 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
3373 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
3375 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
3376 * stall needs to be sent just prior to any 3DSTATE_VS,
3377 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
3378 * 3DSTATE_BINDING_TABLE_POINTER_VS,
3379 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
3380 * PIPE_CONTROL needs to be sent before any combination of VS
3381 * associated 3DSTATE."
3383 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3384 pc
.DepthStallEnable
= true;
3385 pc
.PostSyncOperation
= WriteImmediateData
;
3387 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
3392 /* Render targets live in the same binding table as fragment descriptors */
3393 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
3394 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
3396 /* We emit the binding tables and sampler tables first, then emit push
3397 * constants and then finally emit binding table and sampler table
3398 * pointers. It has to happen in this order, since emitting the binding
3399 * tables may change the push constants (in case of storage images). After
3400 * emitting push constants, on SKL+ we have to emit the corresponding
3401 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
3404 if (cmd_buffer
->state
.descriptors_dirty
) {
3405 dirty
= flush_descriptor_sets(cmd_buffer
,
3406 &cmd_buffer
->state
.gfx
.base
,
3408 ARRAY_SIZE(pipeline
->shaders
));
3411 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
3412 /* Because we're pushing UBOs, we have to push whenever either
3413 * descriptors or push constants is dirty.
3415 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
3416 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
3417 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
3421 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
3423 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
3424 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
3426 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
3427 ANV_CMD_DIRTY_PIPELINE
)) {
3428 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
3429 pipeline
->depth_clamp_enable
);
3432 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
3433 ANV_CMD_DIRTY_RENDER_TARGETS
))
3434 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
3436 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
3440 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
3441 struct anv_address addr
,
3442 uint32_t size
, uint32_t index
)
3444 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
3445 GENX(3DSTATE_VERTEX_BUFFERS
));
3447 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
3448 &(struct GENX(VERTEX_BUFFER_STATE
)) {
3449 .VertexBufferIndex
= index
,
3450 .AddressModifyEnable
= true,
3452 .MOCS
= addr
.bo
? anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
) : 0,
3453 .NullVertexBuffer
= size
== 0,
3455 .BufferStartingAddress
= addr
,
3458 .BufferStartingAddress
= addr
,
3459 .EndAddress
= anv_address_add(addr
, size
),
3463 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
,
3468 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
3469 struct anv_address addr
)
3471 emit_vertex_bo(cmd_buffer
, addr
, addr
.bo
? 8 : 0, ANV_SVGS_VB_INDEX
);
3475 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
3476 uint32_t base_vertex
, uint32_t base_instance
)
3478 if (base_vertex
== 0 && base_instance
== 0) {
3479 emit_base_vertex_instance_bo(cmd_buffer
, ANV_NULL_ADDRESS
);
3481 struct anv_state id_state
=
3482 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
3484 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
3485 ((uint32_t *)id_state
.map
)[1] = base_instance
;
3487 struct anv_address addr
= {
3488 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3489 .offset
= id_state
.offset
,
3492 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
3497 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
3499 struct anv_state state
=
3500 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
3502 ((uint32_t *)state
.map
)[0] = draw_index
;
3504 struct anv_address addr
= {
3505 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3506 .offset
= state
.offset
,
3509 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
3513 update_dirty_vbs_for_gen8_vb_flush(struct anv_cmd_buffer
*cmd_buffer
,
3514 uint32_t access_type
)
3516 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3517 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3519 uint64_t vb_used
= pipeline
->vb_used
;
3520 if (vs_prog_data
->uses_firstvertex
||
3521 vs_prog_data
->uses_baseinstance
)
3522 vb_used
|= 1ull << ANV_SVGS_VB_INDEX
;
3523 if (vs_prog_data
->uses_drawid
)
3524 vb_used
|= 1ull << ANV_DRAWID_VB_INDEX
;
3526 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(cmd_buffer
,
3527 access_type
== RANDOM
,
3532 VkCommandBuffer commandBuffer
,
3533 uint32_t vertexCount
,
3534 uint32_t instanceCount
,
3535 uint32_t firstVertex
,
3536 uint32_t firstInstance
)
3538 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3539 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3540 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3542 if (anv_batch_has_error(&cmd_buffer
->batch
))
3545 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3547 if (cmd_buffer
->state
.conditional_render_enabled
)
3548 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3550 if (vs_prog_data
->uses_firstvertex
||
3551 vs_prog_data
->uses_baseinstance
)
3552 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3553 if (vs_prog_data
->uses_drawid
)
3554 emit_draw_index(cmd_buffer
, 0);
3556 /* Emitting draw index or vertex index BOs may result in needing
3557 * additional VF cache flushes.
3559 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3561 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3562 * different views. We need to multiply instanceCount by the view count.
3564 if (!pipeline
->use_primitive_replication
)
3565 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3567 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3568 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3569 prim
.VertexAccessType
= SEQUENTIAL
;
3570 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3571 prim
.VertexCountPerInstance
= vertexCount
;
3572 prim
.StartVertexLocation
= firstVertex
;
3573 prim
.InstanceCount
= instanceCount
;
3574 prim
.StartInstanceLocation
= firstInstance
;
3575 prim
.BaseVertexLocation
= 0;
3578 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3581 void genX(CmdDrawIndexed
)(
3582 VkCommandBuffer commandBuffer
,
3583 uint32_t indexCount
,
3584 uint32_t instanceCount
,
3585 uint32_t firstIndex
,
3586 int32_t vertexOffset
,
3587 uint32_t firstInstance
)
3589 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3590 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3591 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3593 if (anv_batch_has_error(&cmd_buffer
->batch
))
3596 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3598 if (cmd_buffer
->state
.conditional_render_enabled
)
3599 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3601 if (vs_prog_data
->uses_firstvertex
||
3602 vs_prog_data
->uses_baseinstance
)
3603 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
3604 if (vs_prog_data
->uses_drawid
)
3605 emit_draw_index(cmd_buffer
, 0);
3607 /* Emitting draw index or vertex index BOs may result in needing
3608 * additional VF cache flushes.
3610 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3612 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3613 * different views. We need to multiply instanceCount by the view count.
3615 if (!pipeline
->use_primitive_replication
)
3616 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3618 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3619 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3620 prim
.VertexAccessType
= RANDOM
;
3621 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3622 prim
.VertexCountPerInstance
= indexCount
;
3623 prim
.StartVertexLocation
= firstIndex
;
3624 prim
.InstanceCount
= instanceCount
;
3625 prim
.StartInstanceLocation
= firstInstance
;
3626 prim
.BaseVertexLocation
= vertexOffset
;
3629 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3632 /* Auto-Draw / Indirect Registers */
3633 #define GEN7_3DPRIM_END_OFFSET 0x2420
3634 #define GEN7_3DPRIM_START_VERTEX 0x2430
3635 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3636 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3637 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3638 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3640 void genX(CmdDrawIndirectByteCountEXT
)(
3641 VkCommandBuffer commandBuffer
,
3642 uint32_t instanceCount
,
3643 uint32_t firstInstance
,
3644 VkBuffer counterBuffer
,
3645 VkDeviceSize counterBufferOffset
,
3646 uint32_t counterOffset
,
3647 uint32_t vertexStride
)
3649 #if GEN_IS_HASWELL || GEN_GEN >= 8
3650 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3651 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3652 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3653 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3655 /* firstVertex is always zero for this draw function */
3656 const uint32_t firstVertex
= 0;
3658 if (anv_batch_has_error(&cmd_buffer
->batch
))
3661 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3663 if (vs_prog_data
->uses_firstvertex
||
3664 vs_prog_data
->uses_baseinstance
)
3665 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3666 if (vs_prog_data
->uses_drawid
)
3667 emit_draw_index(cmd_buffer
, 0);
3669 /* Emitting draw index or vertex index BOs may result in needing
3670 * additional VF cache flushes.
3672 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3674 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3675 * different views. We need to multiply instanceCount by the view count.
3677 if (!pipeline
->use_primitive_replication
)
3678 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3680 struct gen_mi_builder b
;
3681 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3682 struct gen_mi_value count
=
3683 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3684 counterBufferOffset
));
3686 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3687 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3688 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3690 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3691 gen_mi_imm(firstVertex
));
3692 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3693 gen_mi_imm(instanceCount
));
3694 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3695 gen_mi_imm(firstInstance
));
3696 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3698 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3699 prim
.IndirectParameterEnable
= true;
3700 prim
.VertexAccessType
= SEQUENTIAL
;
3701 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3704 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3705 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3709 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3710 struct anv_address addr
,
3713 struct gen_mi_builder b
;
3714 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3716 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3717 gen_mi_mem32(anv_address_add(addr
, 0)));
3719 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3720 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3721 if (view_count
> 1) {
3722 #if GEN_IS_HASWELL || GEN_GEN >= 8
3723 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3725 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3726 "MI_MATH is not supported on Ivy Bridge");
3729 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3731 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3732 gen_mi_mem32(anv_address_add(addr
, 8)));
3735 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3736 gen_mi_mem32(anv_address_add(addr
, 12)));
3737 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3738 gen_mi_mem32(anv_address_add(addr
, 16)));
3740 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3741 gen_mi_mem32(anv_address_add(addr
, 12)));
3742 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3746 void genX(CmdDrawIndirect
)(
3747 VkCommandBuffer commandBuffer
,
3749 VkDeviceSize offset
,
3753 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3754 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3755 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3756 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3758 if (anv_batch_has_error(&cmd_buffer
->batch
))
3761 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3763 if (cmd_buffer
->state
.conditional_render_enabled
)
3764 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3766 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3767 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3769 if (vs_prog_data
->uses_firstvertex
||
3770 vs_prog_data
->uses_baseinstance
)
3771 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3772 if (vs_prog_data
->uses_drawid
)
3773 emit_draw_index(cmd_buffer
, i
);
3775 /* Emitting draw index or vertex index BOs may result in needing
3776 * additional VF cache flushes.
3778 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3780 load_indirect_parameters(cmd_buffer
, draw
, false);
3782 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3783 prim
.IndirectParameterEnable
= true;
3784 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3785 prim
.VertexAccessType
= SEQUENTIAL
;
3786 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3789 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3795 void genX(CmdDrawIndexedIndirect
)(
3796 VkCommandBuffer commandBuffer
,
3798 VkDeviceSize offset
,
3802 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3803 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3804 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3805 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3807 if (anv_batch_has_error(&cmd_buffer
->batch
))
3810 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3812 if (cmd_buffer
->state
.conditional_render_enabled
)
3813 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3815 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3816 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3818 /* TODO: We need to stomp base vertex to 0 somehow */
3819 if (vs_prog_data
->uses_firstvertex
||
3820 vs_prog_data
->uses_baseinstance
)
3821 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3822 if (vs_prog_data
->uses_drawid
)
3823 emit_draw_index(cmd_buffer
, i
);
3825 /* Emitting draw index or vertex index BOs may result in needing
3826 * additional VF cache flushes.
3828 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3830 load_indirect_parameters(cmd_buffer
, draw
, true);
3832 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3833 prim
.IndirectParameterEnable
= true;
3834 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3835 prim
.VertexAccessType
= RANDOM
;
3836 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3839 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3845 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3848 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3849 struct anv_address count_address
,
3850 const bool conditional_render_enabled
)
3852 struct gen_mi_builder b
;
3853 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3855 if (conditional_render_enabled
) {
3856 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3857 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3858 gen_mi_mem32(count_address
));
3861 /* Upload the current draw count from the draw parameters buffer to
3862 * MI_PREDICATE_SRC0.
3864 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3865 gen_mi_mem32(count_address
));
3867 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3872 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3873 uint32_t draw_index
)
3875 struct gen_mi_builder b
;
3876 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3878 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3879 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3881 if (draw_index
== 0) {
3882 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3883 mip
.LoadOperation
= LOAD_LOADINV
;
3884 mip
.CombineOperation
= COMBINE_SET
;
3885 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3888 /* While draw_index < draw_count the predicate's result will be
3889 * (draw_index == draw_count) ^ TRUE = TRUE
3890 * When draw_index == draw_count the result is
3891 * (TRUE) ^ TRUE = FALSE
3892 * After this all results will be:
3893 * (FALSE) ^ FALSE = FALSE
3895 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3896 mip
.LoadOperation
= LOAD_LOAD
;
3897 mip
.CombineOperation
= COMBINE_XOR
;
3898 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3903 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3905 emit_draw_count_predicate_with_conditional_render(
3906 struct anv_cmd_buffer
*cmd_buffer
,
3907 uint32_t draw_index
)
3909 struct gen_mi_builder b
;
3910 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3912 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3913 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3914 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3917 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3919 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3920 * so we emit MI_PREDICATE to set it.
3923 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3924 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3926 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3927 mip
.LoadOperation
= LOAD_LOADINV
;
3928 mip
.CombineOperation
= COMBINE_SET
;
3929 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3935 void genX(CmdDrawIndirectCount
)(
3936 VkCommandBuffer commandBuffer
,
3938 VkDeviceSize offset
,
3939 VkBuffer _countBuffer
,
3940 VkDeviceSize countBufferOffset
,
3941 uint32_t maxDrawCount
,
3944 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3945 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3946 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3947 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3948 struct anv_graphics_pipeline
*pipeline
= cmd_state
->gfx
.pipeline
;
3949 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3951 if (anv_batch_has_error(&cmd_buffer
->batch
))
3954 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3956 struct anv_address count_address
=
3957 anv_address_add(count_buffer
->address
, countBufferOffset
);
3959 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3960 cmd_state
->conditional_render_enabled
);
3962 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3963 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3965 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3966 if (cmd_state
->conditional_render_enabled
) {
3967 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3969 emit_draw_count_predicate(cmd_buffer
, i
);
3972 emit_draw_count_predicate(cmd_buffer
, i
);
3975 if (vs_prog_data
->uses_firstvertex
||
3976 vs_prog_data
->uses_baseinstance
)
3977 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3978 if (vs_prog_data
->uses_drawid
)
3979 emit_draw_index(cmd_buffer
, i
);
3981 /* Emitting draw index or vertex index BOs may result in needing
3982 * additional VF cache flushes.
3984 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3986 load_indirect_parameters(cmd_buffer
, draw
, false);
3988 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3989 prim
.IndirectParameterEnable
= true;
3990 prim
.PredicateEnable
= true;
3991 prim
.VertexAccessType
= SEQUENTIAL
;
3992 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3995 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
4001 void genX(CmdDrawIndexedIndirectCount
)(
4002 VkCommandBuffer commandBuffer
,
4004 VkDeviceSize offset
,
4005 VkBuffer _countBuffer
,
4006 VkDeviceSize countBufferOffset
,
4007 uint32_t maxDrawCount
,
4010 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4011 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
4012 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
4013 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4014 struct anv_graphics_pipeline
*pipeline
= cmd_state
->gfx
.pipeline
;
4015 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
4017 if (anv_batch_has_error(&cmd_buffer
->batch
))
4020 genX(cmd_buffer_flush_state
)(cmd_buffer
);
4022 struct anv_address count_address
=
4023 anv_address_add(count_buffer
->address
, countBufferOffset
);
4025 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
4026 cmd_state
->conditional_render_enabled
);
4028 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
4029 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
4031 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4032 if (cmd_state
->conditional_render_enabled
) {
4033 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
4035 emit_draw_count_predicate(cmd_buffer
, i
);
4038 emit_draw_count_predicate(cmd_buffer
, i
);
4041 /* TODO: We need to stomp base vertex to 0 somehow */
4042 if (vs_prog_data
->uses_firstvertex
||
4043 vs_prog_data
->uses_baseinstance
)
4044 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
4045 if (vs_prog_data
->uses_drawid
)
4046 emit_draw_index(cmd_buffer
, i
);
4048 /* Emitting draw index or vertex index BOs may result in needing
4049 * additional VF cache flushes.
4051 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4053 load_indirect_parameters(cmd_buffer
, draw
, true);
4055 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
4056 prim
.IndirectParameterEnable
= true;
4057 prim
.PredicateEnable
= true;
4058 prim
.VertexAccessType
= RANDOM
;
4059 prim
.PrimitiveTopologyType
= pipeline
->topology
;
4062 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
4068 void genX(CmdBeginTransformFeedbackEXT
)(
4069 VkCommandBuffer commandBuffer
,
4070 uint32_t firstCounterBuffer
,
4071 uint32_t counterBufferCount
,
4072 const VkBuffer
* pCounterBuffers
,
4073 const VkDeviceSize
* pCounterBufferOffsets
)
4075 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4077 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
4078 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4079 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4081 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4083 * "Ssoftware must ensure that no HW stream output operations can be in
4084 * process or otherwise pending at the point that the MI_LOAD/STORE
4085 * commands are processed. This will likely require a pipeline flush."
4087 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4088 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4090 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
4091 /* If we have a counter buffer, this is a resume so we need to load the
4092 * value into the streamout offset register. Otherwise, this is a begin
4093 * and we need to reset it to zero.
4095 if (pCounterBuffers
&&
4096 idx
>= firstCounterBuffer
&&
4097 idx
- firstCounterBuffer
< counterBufferCount
&&
4098 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
4099 uint32_t cb_idx
= idx
- firstCounterBuffer
;
4100 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4101 uint64_t offset
= pCounterBufferOffsets
?
4102 pCounterBufferOffsets
[cb_idx
] : 0;
4104 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4105 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4106 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4110 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4111 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4117 cmd_buffer
->state
.xfb_enabled
= true;
4118 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4121 void genX(CmdEndTransformFeedbackEXT
)(
4122 VkCommandBuffer commandBuffer
,
4123 uint32_t firstCounterBuffer
,
4124 uint32_t counterBufferCount
,
4125 const VkBuffer
* pCounterBuffers
,
4126 const VkDeviceSize
* pCounterBufferOffsets
)
4128 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4130 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
4131 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4132 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4134 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4136 * "Ssoftware must ensure that no HW stream output operations can be in
4137 * process or otherwise pending at the point that the MI_LOAD/STORE
4138 * commands are processed. This will likely require a pipeline flush."
4140 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4141 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4143 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
4144 unsigned idx
= firstCounterBuffer
+ cb_idx
;
4146 /* If we have a counter buffer, this is a resume so we need to load the
4147 * value into the streamout offset register. Otherwise, this is a begin
4148 * and we need to reset it to zero.
4150 if (pCounterBuffers
&&
4151 cb_idx
< counterBufferCount
&&
4152 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
4153 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4154 uint64_t offset
= pCounterBufferOffsets
?
4155 pCounterBufferOffsets
[cb_idx
] : 0;
4157 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
4158 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4160 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4165 cmd_buffer
->state
.xfb_enabled
= false;
4166 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4170 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
4172 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4174 assert(pipeline
->cs
);
4176 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->base
.l3_config
);
4178 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
4180 /* Apply any pending pipeline flushes we may have. We want to apply them
4181 * now because, if any of those flushes are for things like push constants,
4182 * the GPU will read the state at weird times.
4184 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4186 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
4187 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
4189 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4190 * the only bits that are changed are scoreboard related: Scoreboard
4191 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4192 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4195 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4196 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4198 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->base
.batch
);
4200 /* The workgroup size of the pipeline affects our push constant layout
4201 * so flag push constants as dirty if we change the pipeline.
4203 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4206 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
4207 cmd_buffer
->state
.compute
.pipeline_dirty
) {
4208 flush_descriptor_sets(cmd_buffer
,
4209 &cmd_buffer
->state
.compute
.base
,
4212 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4213 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
4214 .BindingTablePointer
=
4215 cmd_buffer
->state
.binding_tables
[MESA_SHADER_COMPUTE
].offset
,
4216 .SamplerStatePointer
=
4217 cmd_buffer
->state
.samplers
[MESA_SHADER_COMPUTE
].offset
,
4219 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
4221 struct anv_state state
=
4222 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
4223 pipeline
->interface_descriptor_data
,
4224 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
4227 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4228 anv_batch_emit(&cmd_buffer
->batch
,
4229 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
4230 mid
.InterfaceDescriptorTotalLength
= size
;
4231 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
4235 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
4236 struct anv_state push_state
=
4237 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
4239 if (push_state
.alloc_size
) {
4240 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4241 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
4242 curbe
.CURBEDataStartAddress
= push_state
.offset
;
4246 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
4249 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
4251 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4257 verify_cmd_parser(const struct anv_device
*device
,
4258 int required_version
,
4259 const char *function
)
4261 if (device
->physical
->cmd_parser_version
< required_version
) {
4262 return vk_errorf(device
, device
->physical
,
4263 VK_ERROR_FEATURE_NOT_PRESENT
,
4264 "cmd parser version %d is required for %s",
4265 required_version
, function
);
4274 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
4275 uint32_t baseGroupX
,
4276 uint32_t baseGroupY
,
4277 uint32_t baseGroupZ
)
4279 if (anv_batch_has_error(&cmd_buffer
->batch
))
4282 struct anv_push_constants
*push
=
4283 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
4284 if (push
->cs
.base_work_group_id
[0] != baseGroupX
||
4285 push
->cs
.base_work_group_id
[1] != baseGroupY
||
4286 push
->cs
.base_work_group_id
[2] != baseGroupZ
) {
4287 push
->cs
.base_work_group_id
[0] = baseGroupX
;
4288 push
->cs
.base_work_group_id
[1] = baseGroupY
;
4289 push
->cs
.base_work_group_id
[2] = baseGroupZ
;
4291 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4295 void genX(CmdDispatch
)(
4296 VkCommandBuffer commandBuffer
,
4301 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
4304 void genX(CmdDispatchBase
)(
4305 VkCommandBuffer commandBuffer
,
4306 uint32_t baseGroupX
,
4307 uint32_t baseGroupY
,
4308 uint32_t baseGroupZ
,
4309 uint32_t groupCountX
,
4310 uint32_t groupCountY
,
4311 uint32_t groupCountZ
)
4313 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4314 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4315 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4317 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
4318 baseGroupY
, baseGroupZ
);
4320 if (anv_batch_has_error(&cmd_buffer
->batch
))
4323 if (prog_data
->uses_num_work_groups
) {
4324 struct anv_state state
=
4325 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
4326 uint32_t *sizes
= state
.map
;
4327 sizes
[0] = groupCountX
;
4328 sizes
[1] = groupCountY
;
4329 sizes
[2] = groupCountZ
;
4330 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
4331 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4332 .offset
= state
.offset
,
4335 /* The num_workgroups buffer goes in the binding table */
4336 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4339 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4341 if (cmd_buffer
->state
.conditional_render_enabled
)
4342 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4344 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
4345 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
4346 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
4347 ggw
.ThreadDepthCounterMaximum
= 0;
4348 ggw
.ThreadHeightCounterMaximum
= 0;
4349 ggw
.ThreadWidthCounterMaximum
= anv_cs_threads(pipeline
) - 1;
4350 ggw
.ThreadGroupIDXDimension
= groupCountX
;
4351 ggw
.ThreadGroupIDYDimension
= groupCountY
;
4352 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
4353 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4354 ggw
.BottomExecutionMask
= 0xffffffff;
4357 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4360 #define GPGPU_DISPATCHDIMX 0x2500
4361 #define GPGPU_DISPATCHDIMY 0x2504
4362 #define GPGPU_DISPATCHDIMZ 0x2508
4364 void genX(CmdDispatchIndirect
)(
4365 VkCommandBuffer commandBuffer
,
4367 VkDeviceSize offset
)
4369 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4370 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
4371 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4372 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4373 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
4374 struct anv_batch
*batch
= &cmd_buffer
->batch
;
4376 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
4379 /* Linux 4.4 added command parser version 5 which allows the GPGPU
4380 * indirect dispatch registers to be written.
4382 if (verify_cmd_parser(cmd_buffer
->device
, 5,
4383 "vkCmdDispatchIndirect") != VK_SUCCESS
)
4387 if (prog_data
->uses_num_work_groups
) {
4388 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
4390 /* The num_workgroups buffer goes in the binding table */
4391 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4394 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4396 struct gen_mi_builder b
;
4397 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4399 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
4400 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
4401 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
4403 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
4404 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
4405 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
4408 /* predicate = (compute_dispatch_indirect_x_size == 0); */
4409 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
4410 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4411 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4412 mip
.LoadOperation
= LOAD_LOAD
;
4413 mip
.CombineOperation
= COMBINE_SET
;
4414 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4417 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
4418 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
4419 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4420 mip
.LoadOperation
= LOAD_LOAD
;
4421 mip
.CombineOperation
= COMBINE_OR
;
4422 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4425 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
4426 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
4427 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4428 mip
.LoadOperation
= LOAD_LOAD
;
4429 mip
.CombineOperation
= COMBINE_OR
;
4430 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4433 /* predicate = !predicate; */
4434 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4435 mip
.LoadOperation
= LOAD_LOADINV
;
4436 mip
.CombineOperation
= COMBINE_OR
;
4437 mip
.CompareOperation
= COMPARE_FALSE
;
4441 if (cmd_buffer
->state
.conditional_render_enabled
) {
4442 /* predicate &= !(conditional_rendering_predicate == 0); */
4443 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
4444 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4445 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4446 mip
.LoadOperation
= LOAD_LOADINV
;
4447 mip
.CombineOperation
= COMBINE_AND
;
4448 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4453 #else /* GEN_GEN > 7 */
4454 if (cmd_buffer
->state
.conditional_render_enabled
)
4455 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4458 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
4459 ggw
.IndirectParameterEnable
= true;
4460 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
4461 cmd_buffer
->state
.conditional_render_enabled
;
4462 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
4463 ggw
.ThreadDepthCounterMaximum
= 0;
4464 ggw
.ThreadHeightCounterMaximum
= 0;
4465 ggw
.ThreadWidthCounterMaximum
= anv_cs_threads(pipeline
) - 1;
4466 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4467 ggw
.BottomExecutionMask
= 0xffffffff;
4470 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4474 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
4477 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4479 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
4482 #if GEN_GEN >= 8 && GEN_GEN < 10
4483 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
4485 * Software must clear the COLOR_CALC_STATE Valid field in
4486 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
4487 * with Pipeline Select set to GPGPU.
4489 * The internal hardware docs recommend the same workaround for Gen9
4492 if (pipeline
== GPGPU
)
4493 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
4497 if (pipeline
== _3D
) {
4498 /* There is a mid-object preemption workaround which requires you to
4499 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
4500 * even without preemption, we have issues with geometry flickering when
4501 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
4504 const uint32_t subslices
=
4505 MAX2(cmd_buffer
->device
->physical
->subslice_total
, 1);
4506 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4507 vfe
.MaximumNumberofThreads
=
4508 devinfo
->max_cs_threads
* subslices
- 1;
4509 vfe
.NumberofURBEntries
= 2;
4510 vfe
.URBEntryAllocationSize
= 2;
4513 /* We just emitted a dummy MEDIA_VFE_STATE so now that packet is
4514 * invalid. Set the compute pipeline to dirty to force a re-emit of the
4515 * pipeline in case we get back-to-back dispatch calls with the same
4516 * pipeline and a PIPELINE_SELECT in between.
4518 cmd_buffer
->state
.compute
.pipeline_dirty
= true;
4522 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
4523 * PIPELINE_SELECT [DevBWR+]":
4527 * Software must ensure all the write caches are flushed through a
4528 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
4529 * command to invalidate read only caches prior to programming
4530 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
4532 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4533 pc
.RenderTargetCacheFlushEnable
= true;
4534 pc
.DepthCacheFlushEnable
= true;
4535 pc
.DCFlushEnable
= true;
4536 pc
.PostSyncOperation
= NoWrite
;
4537 pc
.CommandStreamerStallEnable
= true;
4539 pc
.TileCacheFlushEnable
= true;
4541 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be
4542 * set with any PIPE_CONTROL with Depth Flush Enable bit set.
4544 pc
.DepthStallEnable
= true;
4548 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4549 pc
.TextureCacheInvalidationEnable
= true;
4550 pc
.ConstantCacheInvalidationEnable
= true;
4551 pc
.StateCacheInvalidationEnable
= true;
4552 pc
.InstructionCacheInvalidateEnable
= true;
4553 pc
.PostSyncOperation
= NoWrite
;
4555 pc
.TileCacheFlushEnable
= true;
4559 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
4563 ps
.PipelineSelection
= pipeline
;
4567 if (devinfo
->is_geminilake
) {
4570 * "This chicken bit works around a hardware issue with barrier logic
4571 * encountered when switching between GPGPU and 3D pipelines. To
4572 * workaround the issue, this mode bit should be set after a pipeline
4576 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
4578 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
4579 : GLK_BARRIER_MODE_3D_HULL
,
4580 .GLKBarrierModeMask
= 1);
4581 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
4585 cmd_buffer
->state
.current_pipeline
= pipeline
;
4589 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
4591 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
4595 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
4597 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
4601 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
4606 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
4608 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
4609 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
4610 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
4611 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
4612 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
4613 * Depth Flush Bit set, followed by another pipelined depth stall
4614 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
4615 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
4616 * via a preceding MI_FLUSH)."
4618 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4619 pipe
.DepthStallEnable
= true;
4621 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4622 pipe
.DepthCacheFlushEnable
= true;
4624 pipe
.TileCacheFlushEnable
= true;
4627 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4628 pipe
.DepthStallEnable
= true;
4632 /* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
4634 * "The VF cache needs to be invalidated before binding and then using
4635 * Vertex Buffers that overlap with any previously bound Vertex Buffer
4636 * (at a 64B granularity) since the last invalidation. A VF cache
4637 * invalidate is performed by setting the "VF Cache Invalidation Enable"
4638 * bit in PIPE_CONTROL."
4640 * This is implemented by carefully tracking all vertex and index buffer
4641 * bindings and flushing if the cache ever ends up with a range in the cache
4642 * that would exceed 4 GiB. This is implemented in three parts:
4644 * 1. genX(cmd_buffer_set_binding_for_gen8_vb_flush)() which must be called
4645 * every time a 3DSTATE_VERTEX_BUFFER packet is emitted and informs the
4646 * tracking code of the new binding. If this new binding would cause
4647 * the cache to have a too-large range on the next draw call, a pipeline
4648 * stall and VF cache invalidate are added to pending_pipeline_bits.
4650 * 2. genX(cmd_buffer_apply_pipe_flushes)() resets the cache tracking to
4651 * empty whenever we emit a VF invalidate.
4653 * 3. genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)() must be called
4654 * after every 3DPRIMITIVE and copies the bound range into the dirty
4655 * range for each used buffer. This has to be a separate step because
4656 * we don't always re-bind all buffers and so 1. can't know which
4657 * buffers are actually bound.
4660 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4662 struct anv_address vb_address
,
4665 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4666 !cmd_buffer
->device
->physical
->use_softpin
)
4669 struct anv_vb_cache_range
*bound
, *dirty
;
4670 if (vb_index
== -1) {
4671 bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4672 dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4674 assert(vb_index
>= 0);
4675 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4676 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4677 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[vb_index
];
4678 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[vb_index
];
4687 assert(vb_address
.bo
&& (vb_address
.bo
->flags
& EXEC_OBJECT_PINNED
));
4688 bound
->start
= gen_48b_address(anv_address_physical(vb_address
));
4689 bound
->end
= bound
->start
+ vb_size
;
4690 assert(bound
->end
> bound
->start
); /* No overflow */
4692 /* Align everything to a cache line */
4693 bound
->start
&= ~(64ull - 1ull);
4694 bound
->end
= align_u64(bound
->end
, 64);
4696 /* Compute the dirty range */
4697 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4698 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4700 /* If our range is larger than 32 bits, we have to flush */
4701 assert(bound
->end
- bound
->start
<= (1ull << 32));
4702 if (dirty
->end
- dirty
->start
> (1ull << 32)) {
4703 cmd_buffer
->state
.pending_pipe_bits
|=
4704 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
4709 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4710 uint32_t access_type
,
4713 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4714 !cmd_buffer
->device
->physical
->use_softpin
)
4717 if (access_type
== RANDOM
) {
4718 /* We have an index buffer */
4719 struct anv_vb_cache_range
*bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4720 struct anv_vb_cache_range
*dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4722 if (bound
->end
> bound
->start
) {
4723 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4724 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4728 uint64_t mask
= vb_used
;
4730 int i
= u_bit_scan64(&mask
);
4732 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4733 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4735 struct anv_vb_cache_range
*bound
, *dirty
;
4736 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[i
];
4737 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[i
];
4739 if (bound
->end
> bound
->start
) {
4740 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4741 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4747 * Update the pixel hashing modes that determine the balancing of PS threads
4748 * across subslices and slices.
4750 * \param width Width bound of the rendering area (already scaled down if \p
4751 * scale is greater than 1).
4752 * \param height Height bound of the rendering area (already scaled down if \p
4753 * scale is greater than 1).
4754 * \param scale The number of framebuffer samples that could potentially be
4755 * affected by an individual channel of the PS thread. This is
4756 * typically one for single-sampled rendering, but for operations
4757 * like CCS resolves and fast clears a single PS invocation may
4758 * update a huge number of pixels, in which case a finer
4759 * balancing is desirable in order to maximally utilize the
4760 * bandwidth available. UINT_MAX can be used as shorthand for
4761 * "finest hashing mode available".
4764 genX(cmd_buffer_emit_hashing_mode
)(struct anv_cmd_buffer
*cmd_buffer
,
4765 unsigned width
, unsigned height
,
4769 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4770 const unsigned slice_hashing
[] = {
4771 /* Because all Gen9 platforms with more than one slice require
4772 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4773 * block is guaranteed to suffer from substantial imbalance, with one
4774 * subslice receiving twice as much work as the other two in the
4777 * The performance impact of that would be particularly severe when
4778 * three-way hashing is also in use for slice balancing (which is the
4779 * case for all Gen9 GT4 platforms), because one of the slices
4780 * receives one every three 16x16 blocks in either direction, which
4781 * is roughly the periodicity of the underlying subslice imbalance
4782 * pattern ("roughly" because in reality the hardware's
4783 * implementation of three-way hashing doesn't do exact modulo 3
4784 * arithmetic, which somewhat decreases the magnitude of this effect
4785 * in practice). This leads to a systematic subslice imbalance
4786 * within that slice regardless of the size of the primitive. The
4787 * 32x32 hashing mode guarantees that the subslice imbalance within a
4788 * single slice hashing block is minimal, largely eliminating this
4792 /* Finest slice hashing mode available. */
4795 const unsigned subslice_hashing
[] = {
4796 /* 16x16 would provide a slight cache locality benefit especially
4797 * visible in the sampler L1 cache efficiency of low-bandwidth
4798 * non-LLC platforms, but it comes at the cost of greater subslice
4799 * imbalance for primitives of dimensions approximately intermediate
4800 * between 16x4 and 16x16.
4803 /* Finest subslice hashing mode available. */
4806 /* Dimensions of the smallest hashing block of a given hashing mode. If
4807 * the rendering area is smaller than this there can't possibly be any
4808 * benefit from switching to this mode, so we optimize out the
4811 const unsigned min_size
[][2] = {
4815 const unsigned idx
= scale
> 1;
4817 if (cmd_buffer
->state
.current_hash_scale
!= scale
&&
4818 (width
> min_size
[idx
][0] || height
> min_size
[idx
][1])) {
4821 anv_pack_struct(>_mode
, GENX(GT_MODE
),
4822 .SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0),
4823 .SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0),
4824 .SubsliceHashing
= subslice_hashing
[idx
],
4825 .SubsliceHashingMask
= -1);
4827 cmd_buffer
->state
.pending_pipe_bits
|=
4828 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
4829 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4831 emit_lri(&cmd_buffer
->batch
, GENX(GT_MODE_num
), gt_mode
);
4833 cmd_buffer
->state
.current_hash_scale
= scale
;
4839 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4841 struct anv_device
*device
= cmd_buffer
->device
;
4842 const struct anv_image_view
*iview
=
4843 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4844 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4846 /* FIXME: Width and Height are wrong */
4848 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4850 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4851 device
->isl_dev
.ds
.size
/ 4);
4855 struct isl_depth_stencil_hiz_emit_info info
= { };
4858 info
.view
= &iview
->planes
[0].isl
;
4860 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4861 uint32_t depth_plane
=
4862 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4863 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4865 info
.depth_surf
= &surface
->isl
;
4867 info
.depth_address
=
4868 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4869 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4870 image
->planes
[depth_plane
].address
.bo
,
4871 image
->planes
[depth_plane
].address
.offset
+
4874 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4877 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4878 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4879 if (info
.hiz_usage
!= ISL_AUX_USAGE_NONE
) {
4880 assert(isl_aux_usage_has_hiz(info
.hiz_usage
));
4881 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4884 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4885 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4886 image
->planes
[depth_plane
].address
.bo
,
4887 image
->planes
[depth_plane
].address
.offset
+
4888 image
->planes
[depth_plane
].aux_surface
.offset
);
4890 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4894 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4895 uint32_t stencil_plane
=
4896 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4897 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4899 info
.stencil_surf
= &surface
->isl
;
4901 info
.stencil_address
=
4902 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4903 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4904 image
->planes
[stencil_plane
].address
.bo
,
4905 image
->planes
[stencil_plane
].address
.offset
+
4908 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4911 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4913 if (GEN_GEN
>= 12) {
4914 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
4915 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4917 /* GEN:BUG:1408224581
4919 * Workaround: Gen12LP Astep only An additional pipe control with
4920 * post-sync = store dword operation would be required.( w/a is to
4921 * have an additional pipe control after the stencil state whenever
4922 * the surface state bits of this state is changing).
4924 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4925 pc
.PostSyncOperation
= WriteImmediateData
;
4927 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
4930 cmd_buffer
->state
.hiz_enabled
= isl_aux_usage_has_hiz(info
.hiz_usage
);
4934 * This ANDs the view mask of the current subpass with the pending clear
4935 * views in the attachment to get the mask of views active in the subpass
4936 * that still need to be cleared.
4938 static inline uint32_t
4939 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4940 const struct anv_attachment_state
*att_state
)
4942 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4946 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4947 const struct anv_attachment_state
*att_state
)
4949 if (!cmd_state
->subpass
->view_mask
)
4952 uint32_t pending_clear_mask
=
4953 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4955 return pending_clear_mask
& 1;
4959 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4962 const uint32_t last_subpass_idx
=
4963 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4964 const struct anv_subpass
*last_subpass
=
4965 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4966 return last_subpass
== cmd_state
->subpass
;
4970 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4971 uint32_t subpass_id
)
4973 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4974 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4975 cmd_state
->subpass
= subpass
;
4977 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4979 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4980 * different views. If the client asks for instancing, we need to use the
4981 * Instance Data Step Rate to ensure that we repeat the client's
4982 * per-instance data once for each view. Since this bit is in
4983 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4987 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4989 /* It is possible to start a render pass with an old pipeline. Because the
4990 * render pass and subpass index are both baked into the pipeline, this is
4991 * highly unlikely. In order to do so, it requires that you have a render
4992 * pass with a single subpass and that you use that render pass twice
4993 * back-to-back and use the same pipeline at the start of the second render
4994 * pass as at the end of the first. In order to avoid unpredictable issues
4995 * with this edge case, we just dirty the pipeline at the start of every
4998 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
5000 /* Accumulate any subpass flushes that need to happen before the subpass */
5001 cmd_buffer
->state
.pending_pipe_bits
|=
5002 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
5004 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5005 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
5007 bool is_multiview
= subpass
->view_mask
!= 0;
5009 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5010 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5011 if (a
== VK_ATTACHMENT_UNUSED
)
5014 assert(a
< cmd_state
->pass
->attachment_count
);
5015 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5017 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
5018 const struct anv_image
*image
= iview
->image
;
5020 /* A resolve is necessary before use as an input attachment if the clear
5021 * color or auxiliary buffer usage isn't supported by the sampler.
5023 const bool input_needs_resolve
=
5024 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
5025 att_state
->input_aux_usage
!= att_state
->aux_usage
;
5027 VkImageLayout target_layout
;
5028 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
5029 !input_needs_resolve
) {
5030 /* Layout transitions before the final only help to enable sampling
5031 * as an input attachment. If the input attachment supports sampling
5032 * using the auxiliary surface, we can skip such transitions by
5033 * making the target layout one that is CCS-aware.
5035 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
5037 target_layout
= subpass
->attachments
[i
].layout
;
5040 VkImageLayout target_stencil_layout
=
5041 subpass
->attachments
[i
].stencil_layout
;
5043 uint32_t base_layer
, layer_count
;
5044 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5046 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5047 iview
->planes
[0].isl
.base_level
);
5049 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5050 layer_count
= fb
->layers
;
5053 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5054 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5055 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5056 iview
->planes
[0].isl
.base_level
, 1,
5057 base_layer
, layer_count
,
5058 att_state
->current_layout
, target_layout
);
5061 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5062 transition_depth_buffer(cmd_buffer
, image
,
5063 base_layer
, layer_count
,
5064 att_state
->current_layout
, target_layout
);
5065 att_state
->aux_usage
=
5066 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
5067 VK_IMAGE_ASPECT_DEPTH_BIT
,
5068 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
5072 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5073 transition_stencil_buffer(cmd_buffer
, image
,
5074 iview
->planes
[0].isl
.base_level
, 1,
5075 base_layer
, layer_count
,
5076 att_state
->current_stencil_layout
,
5077 target_stencil_layout
);
5079 att_state
->current_layout
= target_layout
;
5080 att_state
->current_stencil_layout
= target_stencil_layout
;
5082 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
5083 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5085 /* Multi-planar images are not supported as attachments */
5086 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5087 assert(image
->n_planes
== 1);
5089 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
5090 uint32_t clear_layer_count
= fb
->layers
;
5092 if (att_state
->fast_clear
&&
5093 do_first_layer_clear(cmd_state
, att_state
)) {
5094 /* We only support fast-clears on the first layer */
5095 assert(iview
->planes
[0].isl
.base_level
== 0);
5096 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
5098 union isl_color_value clear_color
= {};
5099 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
5100 if (iview
->image
->samples
== 1) {
5101 anv_image_ccs_op(cmd_buffer
, image
,
5102 iview
->planes
[0].isl
.format
,
5103 iview
->planes
[0].isl
.swizzle
,
5104 VK_IMAGE_ASPECT_COLOR_BIT
,
5105 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
5109 anv_image_mcs_op(cmd_buffer
, image
,
5110 iview
->planes
[0].isl
.format
,
5111 iview
->planes
[0].isl
.swizzle
,
5112 VK_IMAGE_ASPECT_COLOR_BIT
,
5113 0, 1, ISL_AUX_OP_FAST_CLEAR
,
5118 clear_layer_count
--;
5120 att_state
->pending_clear_views
&= ~1;
5122 if (att_state
->clear_color_is_zero
) {
5123 /* This image has the auxiliary buffer enabled. We can mark the
5124 * subresource as not needing a resolve because the clear color
5125 * will match what's in every RENDER_SURFACE_STATE object when
5126 * it's being used for sampling.
5128 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
5129 VK_IMAGE_ASPECT_COLOR_BIT
,
5130 ANV_FAST_CLEAR_DEFAULT_VALUE
);
5132 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
5133 VK_IMAGE_ASPECT_COLOR_BIT
,
5134 ANV_FAST_CLEAR_ANY
);
5138 /* From the VkFramebufferCreateInfo spec:
5140 * "If the render pass uses multiview, then layers must be one and each
5141 * attachment requires a number of layers that is greater than the
5142 * maximum bit index set in the view mask in the subpasses in which it
5145 * So if multiview is active we ignore the number of layers in the
5146 * framebuffer and instead we honor the view mask from the subpass.
5149 assert(image
->n_planes
== 1);
5150 uint32_t pending_clear_mask
=
5151 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5154 for_each_bit(layer_idx
, pending_clear_mask
) {
5156 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5158 anv_image_clear_color(cmd_buffer
, image
,
5159 VK_IMAGE_ASPECT_COLOR_BIT
,
5160 att_state
->aux_usage
,
5161 iview
->planes
[0].isl
.format
,
5162 iview
->planes
[0].isl
.swizzle
,
5163 iview
->planes
[0].isl
.base_level
,
5166 vk_to_isl_color(att_state
->clear_value
.color
));
5169 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5170 } else if (clear_layer_count
> 0) {
5171 assert(image
->n_planes
== 1);
5172 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5173 att_state
->aux_usage
,
5174 iview
->planes
[0].isl
.format
,
5175 iview
->planes
[0].isl
.swizzle
,
5176 iview
->planes
[0].isl
.base_level
,
5177 base_clear_layer
, clear_layer_count
,
5179 vk_to_isl_color(att_state
->clear_value
.color
));
5181 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
5182 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
5183 if (att_state
->fast_clear
&& !is_multiview
) {
5184 /* We currently only support HiZ for single-LOD images */
5185 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5186 assert(isl_aux_usage_has_hiz(iview
->image
->planes
[0].aux_usage
));
5187 assert(iview
->planes
[0].isl
.base_level
== 0);
5190 anv_image_hiz_clear(cmd_buffer
, image
,
5191 att_state
->pending_clear_aspects
,
5192 iview
->planes
[0].isl
.base_level
,
5193 iview
->planes
[0].isl
.base_array_layer
,
5194 fb
->layers
, render_area
,
5195 att_state
->clear_value
.depthStencil
.stencil
);
5196 } else if (is_multiview
) {
5197 uint32_t pending_clear_mask
=
5198 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5201 for_each_bit(layer_idx
, pending_clear_mask
) {
5203 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5205 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5206 att_state
->pending_clear_aspects
,
5207 att_state
->aux_usage
,
5208 iview
->planes
[0].isl
.base_level
,
5211 att_state
->clear_value
.depthStencil
.depth
,
5212 att_state
->clear_value
.depthStencil
.stencil
);
5215 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5217 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5218 att_state
->pending_clear_aspects
,
5219 att_state
->aux_usage
,
5220 iview
->planes
[0].isl
.base_level
,
5221 iview
->planes
[0].isl
.base_array_layer
,
5222 fb
->layers
, render_area
,
5223 att_state
->clear_value
.depthStencil
.depth
,
5224 att_state
->clear_value
.depthStencil
.stencil
);
5227 assert(att_state
->pending_clear_aspects
== 0);
5231 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
5232 image
->planes
[0].aux_usage
!= ISL_AUX_USAGE_NONE
&&
5233 iview
->planes
[0].isl
.base_level
== 0 &&
5234 iview
->planes
[0].isl
.base_array_layer
== 0) {
5235 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
5236 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
5237 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5238 false /* copy to ss */);
5241 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
5242 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
5243 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
5244 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5245 false /* copy to ss */);
5249 /* If multiview is enabled, then we are only done clearing when we no
5250 * longer have pending layers to clear, or when we have processed the
5251 * last subpass that uses this attachment.
5253 if (!is_multiview
||
5254 att_state
->pending_clear_views
== 0 ||
5255 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
5256 att_state
->pending_clear_aspects
= 0;
5259 att_state
->pending_load_aspects
= 0;
5263 /* The PIPE_CONTROL command description says:
5265 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
5266 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
5267 * Target Cache Flush by enabling this bit. When render target flush
5268 * is set due to new association of BTI, PS Scoreboard Stall bit must
5269 * be set in this packet."
5271 cmd_buffer
->state
.pending_pipe_bits
|=
5272 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
|
5273 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
5277 /* GEN:BUG:14010455700
5279 * ISL will change some CHICKEN registers depending on the depth surface
5280 * format, along with emitting the depth and stencil packets. In that case,
5281 * we want to do a depth flush and stall, so the pipeline is not using these
5282 * settings while we change the registers.
5284 cmd_buffer
->state
.pending_pipe_bits
|=
5285 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
|
5286 ANV_PIPE_DEPTH_STALL_BIT
|
5287 ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
5288 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5291 cmd_buffer_emit_depth_stencil(cmd_buffer
);
5294 static enum blorp_filter
5295 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
5298 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
5299 return BLORP_FILTER_SAMPLE_0
;
5300 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
5301 return BLORP_FILTER_AVERAGE
;
5302 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
5303 return BLORP_FILTER_MIN_SAMPLE
;
5304 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
5305 return BLORP_FILTER_MAX_SAMPLE
;
5307 return BLORP_FILTER_NONE
;
5312 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
5314 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5315 struct anv_subpass
*subpass
= cmd_state
->subpass
;
5316 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
5317 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
5319 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5320 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5321 if (a
== VK_ATTACHMENT_UNUSED
)
5324 assert(a
< cmd_state
->pass
->attachment_count
);
5325 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5326 struct anv_image_view
*iview
= att_state
->image_view
;
5328 assert(util_bitcount(subpass
->attachments
[i
].usage
) == 1);
5329 if (subpass
->attachments
[i
].usage
==
5330 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
5331 /* We assume that if we're ending a subpass, we did do some rendering
5332 * so we may end up with compressed data.
5334 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5335 VK_IMAGE_ASPECT_COLOR_BIT
,
5336 att_state
->aux_usage
,
5337 iview
->planes
[0].isl
.base_level
,
5338 iview
->planes
[0].isl
.base_array_layer
,
5340 } else if (subpass
->attachments
[i
].usage
==
5341 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
5342 /* We may be writing depth or stencil so we need to mark the surface.
5343 * Unfortunately, there's no way to know at this point whether the
5344 * depth or stencil tests used will actually write to the surface.
5346 * Even though stencil may be plane 1, it always shares a base_level
5349 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
5350 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5351 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5352 VK_IMAGE_ASPECT_DEPTH_BIT
,
5353 att_state
->aux_usage
,
5354 ds_view
->base_level
,
5355 ds_view
->base_array_layer
,
5358 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5359 /* Even though stencil may be plane 1, it always shares a
5360 * base_level with depth.
5362 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5363 VK_IMAGE_ASPECT_STENCIL_BIT
,
5365 ds_view
->base_level
,
5366 ds_view
->base_array_layer
,
5372 if (subpass
->has_color_resolve
) {
5373 /* We are about to do some MSAA resolves. We need to flush so that the
5374 * result of writes to the MSAA color attachments show up in the sampler
5375 * when we blit to the single-sampled resolve target.
5377 cmd_buffer
->state
.pending_pipe_bits
|=
5378 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5379 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
5381 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
5382 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
5383 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
5385 if (dst_att
== VK_ATTACHMENT_UNUSED
)
5388 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5389 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5391 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5392 /* From the Vulkan 1.0 spec:
5394 * If the first use of an attachment in a render pass is as a
5395 * resolve attachment, then the loadOp is effectively ignored
5396 * as the resolve is guaranteed to overwrite all pixels in the
5399 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5402 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5403 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5405 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5407 enum isl_aux_usage src_aux_usage
=
5408 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
5409 enum isl_aux_usage dst_aux_usage
=
5410 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
5412 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
5413 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
5415 anv_image_msaa_resolve(cmd_buffer
,
5416 src_iview
->image
, src_aux_usage
,
5417 src_iview
->planes
[0].isl
.base_level
,
5418 src_iview
->planes
[0].isl
.base_array_layer
,
5419 dst_iview
->image
, dst_aux_usage
,
5420 dst_iview
->planes
[0].isl
.base_level
,
5421 dst_iview
->planes
[0].isl
.base_array_layer
,
5422 VK_IMAGE_ASPECT_COLOR_BIT
,
5423 render_area
.offset
.x
, render_area
.offset
.y
,
5424 render_area
.offset
.x
, render_area
.offset
.y
,
5425 render_area
.extent
.width
,
5426 render_area
.extent
.height
,
5427 fb
->layers
, BLORP_FILTER_NONE
);
5431 if (subpass
->ds_resolve_attachment
) {
5432 /* We are about to do some MSAA resolves. We need to flush so that the
5433 * result of writes to the MSAA depth attachments show up in the sampler
5434 * when we blit to the single-sampled resolve target.
5436 cmd_buffer
->state
.pending_pipe_bits
|=
5437 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5438 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
5440 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
5441 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
5443 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5444 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5446 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5447 /* From the Vulkan 1.0 spec:
5449 * If the first use of an attachment in a render pass is as a
5450 * resolve attachment, then the loadOp is effectively ignored
5451 * as the resolve is guaranteed to overwrite all pixels in the
5454 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5457 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5458 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5460 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5462 struct anv_attachment_state
*src_state
=
5463 &cmd_state
->attachments
[src_att
];
5464 struct anv_attachment_state
*dst_state
=
5465 &cmd_state
->attachments
[dst_att
];
5467 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
5468 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5470 /* MSAA resolves sample from the source attachment. Transition the
5471 * depth attachment first to get rid of any HiZ that we may not be
5474 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
5475 src_iview
->planes
[0].isl
.base_array_layer
,
5477 src_state
->current_layout
,
5478 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5479 src_state
->aux_usage
=
5480 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
5481 VK_IMAGE_ASPECT_DEPTH_BIT
,
5482 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
,
5483 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5484 src_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5486 /* MSAA resolves write to the resolve attachment as if it were any
5487 * other transfer op. Transition the resolve attachment accordingly.
5489 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
5491 /* If our render area is the entire size of the image, we're going to
5492 * blow it all away so we can claim the initial layout is UNDEFINED
5493 * and we'll get a HiZ ambiguate instead of a resolve.
5495 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
5496 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
5497 render_area
.extent
.width
== dst_iview
->extent
.width
&&
5498 render_area
.extent
.height
== dst_iview
->extent
.height
)
5499 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
5501 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
5502 dst_iview
->planes
[0].isl
.base_array_layer
,
5505 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5506 dst_state
->aux_usage
=
5507 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
5508 VK_IMAGE_ASPECT_DEPTH_BIT
,
5509 VK_IMAGE_USAGE_TRANSFER_DST_BIT
,
5510 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5511 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5513 enum blorp_filter filter
=
5514 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
5516 anv_image_msaa_resolve(cmd_buffer
,
5517 src_iview
->image
, src_state
->aux_usage
,
5518 src_iview
->planes
[0].isl
.base_level
,
5519 src_iview
->planes
[0].isl
.base_array_layer
,
5520 dst_iview
->image
, dst_state
->aux_usage
,
5521 dst_iview
->planes
[0].isl
.base_level
,
5522 dst_iview
->planes
[0].isl
.base_array_layer
,
5523 VK_IMAGE_ASPECT_DEPTH_BIT
,
5524 render_area
.offset
.x
, render_area
.offset
.y
,
5525 render_area
.offset
.x
, render_area
.offset
.y
,
5526 render_area
.extent
.width
,
5527 render_area
.extent
.height
,
5528 fb
->layers
, filter
);
5531 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
5532 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5534 src_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5535 dst_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5537 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
5538 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
5540 enum blorp_filter filter
=
5541 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
5543 anv_image_msaa_resolve(cmd_buffer
,
5544 src_iview
->image
, src_aux_usage
,
5545 src_iview
->planes
[0].isl
.base_level
,
5546 src_iview
->planes
[0].isl
.base_array_layer
,
5547 dst_iview
->image
, dst_aux_usage
,
5548 dst_iview
->planes
[0].isl
.base_level
,
5549 dst_iview
->planes
[0].isl
.base_array_layer
,
5550 VK_IMAGE_ASPECT_STENCIL_BIT
,
5551 render_area
.offset
.x
, render_area
.offset
.y
,
5552 render_area
.offset
.x
, render_area
.offset
.y
,
5553 render_area
.extent
.width
,
5554 render_area
.extent
.height
,
5555 fb
->layers
, filter
);
5560 /* On gen7, we have to store a texturable version of the stencil buffer in
5561 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
5562 * forth at strategic points. Stencil writes are only allowed in following
5565 * - VK_IMAGE_LAYOUT_GENERAL
5566 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
5567 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
5568 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
5569 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
5571 * For general, we have no nice opportunity to transition so we do the copy
5572 * to the shadow unconditionally at the end of the subpass. For transfer
5573 * destinations, we can update it as part of the transfer op. For the other
5574 * layouts, we delay the copy until a transition into some other layout.
5576 if (subpass
->depth_stencil_attachment
) {
5577 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
5578 assert(a
!= VK_ATTACHMENT_UNUSED
);
5580 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5581 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
5582 const struct anv_image
*image
= iview
->image
;
5584 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5585 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
5586 VK_IMAGE_ASPECT_STENCIL_BIT
);
5588 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
5589 att_state
->current_stencil_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5590 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
5591 anv_image_copy_to_shadow(cmd_buffer
, image
,
5592 VK_IMAGE_ASPECT_STENCIL_BIT
,
5593 iview
->planes
[plane
].isl
.base_level
, 1,
5594 iview
->planes
[plane
].isl
.base_array_layer
,
5599 #endif /* GEN_GEN == 7 */
5601 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5602 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5603 if (a
== VK_ATTACHMENT_UNUSED
)
5606 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
5609 assert(a
< cmd_state
->pass
->attachment_count
);
5610 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5611 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
5612 const struct anv_image
*image
= iview
->image
;
5614 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
5615 image
->vk_format
!= iview
->vk_format
) {
5616 enum anv_fast_clear_type fast_clear_type
=
5617 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
5618 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5619 att_state
->current_layout
);
5621 /* If any clear color was used, flush it down the aux surfaces. If we
5622 * don't do it now using the view's format we might use the clear
5623 * color incorrectly in the following resolves (for example with an
5624 * SRGB view & a UNORM image).
5626 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
5627 anv_perf_warn(cmd_buffer
->device
, iview
,
5628 "Doing a partial resolve to get rid of clear color at the "
5629 "end of a renderpass due to an image/view format mismatch");
5631 uint32_t base_layer
, layer_count
;
5632 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5634 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5635 iview
->planes
[0].isl
.base_level
);
5637 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5638 layer_count
= fb
->layers
;
5641 for (uint32_t a
= 0; a
< layer_count
; a
++) {
5642 uint32_t array_layer
= base_layer
+ a
;
5643 if (image
->samples
== 1) {
5644 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
5645 iview
->planes
[0].isl
.format
,
5646 iview
->planes
[0].isl
.swizzle
,
5647 VK_IMAGE_ASPECT_COLOR_BIT
,
5648 iview
->planes
[0].isl
.base_level
,
5650 ISL_AUX_OP_PARTIAL_RESOLVE
,
5651 ANV_FAST_CLEAR_NONE
);
5653 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
5654 iview
->planes
[0].isl
.format
,
5655 iview
->planes
[0].isl
.swizzle
,
5656 VK_IMAGE_ASPECT_COLOR_BIT
,
5658 ISL_AUX_OP_PARTIAL_RESOLVE
,
5659 ANV_FAST_CLEAR_NONE
);
5665 /* Transition the image into the final layout for this render pass */
5666 VkImageLayout target_layout
=
5667 cmd_state
->pass
->attachments
[a
].final_layout
;
5668 VkImageLayout target_stencil_layout
=
5669 cmd_state
->pass
->attachments
[a
].stencil_final_layout
;
5671 uint32_t base_layer
, layer_count
;
5672 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5674 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5675 iview
->planes
[0].isl
.base_level
);
5677 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5678 layer_count
= fb
->layers
;
5681 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5682 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5683 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5684 iview
->planes
[0].isl
.base_level
, 1,
5685 base_layer
, layer_count
,
5686 att_state
->current_layout
, target_layout
);
5689 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5690 transition_depth_buffer(cmd_buffer
, image
,
5691 base_layer
, layer_count
,
5692 att_state
->current_layout
, target_layout
);
5695 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5696 transition_stencil_buffer(cmd_buffer
, image
,
5697 iview
->planes
[0].isl
.base_level
, 1,
5698 base_layer
, layer_count
,
5699 att_state
->current_stencil_layout
,
5700 target_stencil_layout
);
5704 /* Accumulate any subpass flushes that need to happen after the subpass.
5705 * Yes, they do get accumulated twice in the NextSubpass case but since
5706 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
5707 * ORing the bits in twice so it's harmless.
5709 cmd_buffer
->state
.pending_pipe_bits
|=
5710 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
5713 void genX(CmdBeginRenderPass
)(
5714 VkCommandBuffer commandBuffer
,
5715 const VkRenderPassBeginInfo
* pRenderPassBegin
,
5716 VkSubpassContents contents
)
5718 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5719 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
5720 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
5722 cmd_buffer
->state
.framebuffer
= framebuffer
;
5723 cmd_buffer
->state
.pass
= pass
;
5724 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
5726 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
5728 /* If we failed to setup the attachments we should not try to go further */
5729 if (result
!= VK_SUCCESS
) {
5730 assert(anv_batch_has_error(&cmd_buffer
->batch
));
5734 genX(flush_pipeline_select_3d
)(cmd_buffer
);
5736 cmd_buffer_begin_subpass(cmd_buffer
, 0);
5739 void genX(CmdBeginRenderPass2
)(
5740 VkCommandBuffer commandBuffer
,
5741 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
5742 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
5744 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
5745 pSubpassBeginInfo
->contents
);
5748 void genX(CmdNextSubpass
)(
5749 VkCommandBuffer commandBuffer
,
5750 VkSubpassContents contents
)
5752 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5754 if (anv_batch_has_error(&cmd_buffer
->batch
))
5757 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
5759 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
5760 cmd_buffer_end_subpass(cmd_buffer
);
5761 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
5764 void genX(CmdNextSubpass2
)(
5765 VkCommandBuffer commandBuffer
,
5766 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
5767 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5769 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
5772 void genX(CmdEndRenderPass
)(
5773 VkCommandBuffer commandBuffer
)
5775 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5777 if (anv_batch_has_error(&cmd_buffer
->batch
))
5780 cmd_buffer_end_subpass(cmd_buffer
);
5782 cmd_buffer
->state
.hiz_enabled
= false;
5785 anv_dump_add_attachments(cmd_buffer
);
5788 /* Remove references to render pass specific state. This enables us to
5789 * detect whether or not we're in a renderpass.
5791 cmd_buffer
->state
.framebuffer
= NULL
;
5792 cmd_buffer
->state
.pass
= NULL
;
5793 cmd_buffer
->state
.subpass
= NULL
;
5796 void genX(CmdEndRenderPass2
)(
5797 VkCommandBuffer commandBuffer
,
5798 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5800 genX(CmdEndRenderPass
)(commandBuffer
);
5804 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
5806 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5807 struct gen_mi_builder b
;
5808 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5810 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
5811 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
5812 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
5814 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
5815 mip
.LoadOperation
= LOAD_LOADINV
;
5816 mip
.CombineOperation
= COMBINE_SET
;
5817 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
5822 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5823 void genX(CmdBeginConditionalRenderingEXT
)(
5824 VkCommandBuffer commandBuffer
,
5825 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5827 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5828 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5829 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5830 struct anv_address value_address
=
5831 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
5833 const bool isInverted
= pConditionalRenderingBegin
->flags
&
5834 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
5836 cmd_state
->conditional_render_enabled
= true;
5838 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5840 struct gen_mi_builder b
;
5841 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5843 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5845 * If the value of the predicate in buffer memory changes
5846 * while conditional rendering is active, the rendering commands
5847 * may be discarded in an implementation-dependent way.
5848 * Some implementations may latch the value of the predicate
5849 * upon beginning conditional rendering while others
5850 * may read it before every rendering command.
5852 * So it's perfectly fine to read a value from the buffer once.
5854 struct gen_mi_value value
= gen_mi_mem32(value_address
);
5856 /* Precompute predicate result, it is necessary to support secondary
5857 * command buffers since it is unknown if conditional rendering is
5858 * inverted when populating them.
5860 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
5861 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
5862 gen_mi_ult(&b
, gen_mi_imm(0), value
));
5865 void genX(CmdEndConditionalRenderingEXT
)(
5866 VkCommandBuffer commandBuffer
)
5868 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5869 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5871 cmd_state
->conditional_render_enabled
= false;
5875 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5876 * command streamer for later execution.
5878 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5879 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5880 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5881 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5882 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5883 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5884 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5885 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5886 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5887 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5888 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5889 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5890 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5891 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5892 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5894 void genX(CmdSetEvent
)(
5895 VkCommandBuffer commandBuffer
,
5897 VkPipelineStageFlags stageMask
)
5899 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5900 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5902 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5903 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5905 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5906 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5907 pc
.StallAtPixelScoreboard
= true;
5908 pc
.CommandStreamerStallEnable
= true;
5911 pc
.DestinationAddressType
= DAT_PPGTT
,
5912 pc
.PostSyncOperation
= WriteImmediateData
,
5913 pc
.Address
= (struct anv_address
) {
5914 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5917 pc
.ImmediateData
= VK_EVENT_SET
;
5921 void genX(CmdResetEvent
)(
5922 VkCommandBuffer commandBuffer
,
5924 VkPipelineStageFlags stageMask
)
5926 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5927 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5929 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5930 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5932 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5933 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5934 pc
.StallAtPixelScoreboard
= true;
5935 pc
.CommandStreamerStallEnable
= true;
5938 pc
.DestinationAddressType
= DAT_PPGTT
;
5939 pc
.PostSyncOperation
= WriteImmediateData
;
5940 pc
.Address
= (struct anv_address
) {
5941 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5944 pc
.ImmediateData
= VK_EVENT_RESET
;
5948 void genX(CmdWaitEvents
)(
5949 VkCommandBuffer commandBuffer
,
5950 uint32_t eventCount
,
5951 const VkEvent
* pEvents
,
5952 VkPipelineStageFlags srcStageMask
,
5953 VkPipelineStageFlags destStageMask
,
5954 uint32_t memoryBarrierCount
,
5955 const VkMemoryBarrier
* pMemoryBarriers
,
5956 uint32_t bufferMemoryBarrierCount
,
5957 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5958 uint32_t imageMemoryBarrierCount
,
5959 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5962 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5964 for (uint32_t i
= 0; i
< eventCount
; i
++) {
5965 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
5967 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
5968 sem
.WaitMode
= PollingMode
,
5969 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
5970 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
5971 sem
.SemaphoreAddress
= (struct anv_address
) {
5972 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5978 anv_finishme("Implement events on gen7");
5981 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
5982 false, /* byRegion */
5983 memoryBarrierCount
, pMemoryBarriers
,
5984 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5985 imageMemoryBarrierCount
, pImageMemoryBarriers
);
5988 VkResult
genX(CmdSetPerformanceOverrideINTEL
)(
5989 VkCommandBuffer commandBuffer
,
5990 const VkPerformanceOverrideInfoINTEL
* pOverrideInfo
)
5992 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5994 switch (pOverrideInfo
->type
) {
5995 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL
: {
5999 anv_pack_struct(&dw
, GENX(CS_DEBUG_MODE2
),
6000 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
6001 .MediaInstructionDisable
= pOverrideInfo
->enable
,
6002 ._3DRenderingInstructionDisableMask
= true,
6003 .MediaInstructionDisableMask
= true);
6004 emit_lri(&cmd_buffer
->batch
, GENX(CS_DEBUG_MODE2_num
), dw
);
6006 anv_pack_struct(&dw
, GENX(INSTPM
),
6007 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
6008 .MediaInstructionDisable
= pOverrideInfo
->enable
,
6009 ._3DRenderingInstructionDisableMask
= true,
6010 .MediaInstructionDisableMask
= true);
6011 emit_lri(&cmd_buffer
->batch
, GENX(INSTPM_num
), dw
);
6016 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL
:
6017 if (pOverrideInfo
->enable
) {
6018 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
6019 cmd_buffer
->state
.pending_pipe_bits
|=
6020 ANV_PIPE_FLUSH_BITS
|
6021 ANV_PIPE_INVALIDATE_BITS
;
6022 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
6027 unreachable("Invalid override");
6033 VkResult
genX(CmdSetPerformanceStreamMarkerINTEL
)(
6034 VkCommandBuffer commandBuffer
,
6035 const VkPerformanceStreamMarkerInfoINTEL
* pMarkerInfo
)
6037 /* TODO: Waiting on the register to write, might depend on generation. */