2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
37 /* We reserve GPR 14 and 15 for conditional rendering */
38 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
39 #define __gen_get_batch_dwords anv_batch_emit_dwords
40 #define __gen_address_offset anv_address_add
41 #include "common/gen_mi_builder.h"
44 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
46 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
47 lri
.RegisterOffset
= reg
;
53 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
55 struct anv_device
*device
= cmd_buffer
->device
;
57 /* If we are emitting a new state base address we probably need to re-emit
60 cmd_buffer
->state
.descriptors_dirty
|= ~0;
62 /* Emit a render target cache flush.
64 * This isn't documented anywhere in the PRM. However, it seems to be
65 * necessary prior to changing the surface state base adress. Without
66 * this, we get GPU hangs when using multi-level command buffers which
67 * clear depth, reset state base address, and then go render stuff.
69 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
70 pc
.DCFlushEnable
= true;
71 pc
.RenderTargetCacheFlushEnable
= true;
72 pc
.CommandStreamerStallEnable
= true;
74 pc
.TileCacheFlushEnable
= true;
78 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
79 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
80 sba
.GeneralStateMOCS
= GENX(MOCS
);
81 sba
.GeneralStateBaseAddressModifyEnable
= true;
83 sba
.StatelessDataPortAccessMOCS
= GENX(MOCS
);
85 sba
.SurfaceStateBaseAddress
=
86 anv_cmd_buffer_surface_base_address(cmd_buffer
);
87 sba
.SurfaceStateMOCS
= GENX(MOCS
);
88 sba
.SurfaceStateBaseAddressModifyEnable
= true;
90 sba
.DynamicStateBaseAddress
=
91 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
92 sba
.DynamicStateMOCS
= GENX(MOCS
);
93 sba
.DynamicStateBaseAddressModifyEnable
= true;
95 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
96 sba
.IndirectObjectMOCS
= GENX(MOCS
);
97 sba
.IndirectObjectBaseAddressModifyEnable
= true;
99 sba
.InstructionBaseAddress
=
100 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
101 sba
.InstructionMOCS
= GENX(MOCS
);
102 sba
.InstructionBaseAddressModifyEnable
= true;
105 /* Broadwell requires that we specify a buffer size for a bunch of
106 * these fields. However, since we will be growing the BO's live, we
107 * just set them all to the maximum.
109 sba
.GeneralStateBufferSize
= 0xfffff;
110 sba
.GeneralStateBufferSizeModifyEnable
= true;
111 sba
.DynamicStateBufferSize
= 0xfffff;
112 sba
.DynamicStateBufferSizeModifyEnable
= true;
113 sba
.IndirectObjectBufferSize
= 0xfffff;
114 sba
.IndirectObjectBufferSizeModifyEnable
= true;
115 sba
.InstructionBufferSize
= 0xfffff;
116 sba
.InstructionBuffersizeModifyEnable
= true;
118 /* On gen7, we have upper bounds instead. According to the docs,
119 * setting an upper bound of zero means that no bounds checking is
120 * performed so, in theory, we should be able to leave them zero.
121 * However, border color is broken and the GPU bounds-checks anyway.
122 * To avoid this and other potential problems, we may as well set it
125 sba
.GeneralStateAccessUpperBound
=
126 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
127 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
128 sba
.DynamicStateAccessUpperBound
=
129 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
130 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
131 sba
.InstructionAccessUpperBound
=
132 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
133 sba
.InstructionAccessUpperBoundModifyEnable
= true;
136 if (cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
) {
137 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
138 .bo
= device
->surface_state_pool
.block_pool
.bo
,
141 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
143 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
144 sba
.BindlessSurfaceStateSize
= 0;
146 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
147 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
150 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
151 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
152 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
153 sba
.BindlessSamplerStateBufferSize
= 0;
157 /* After re-setting the surface state base address, we have to do some
158 * cache flusing so that the sampler engine will pick up the new
159 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
160 * Shared Function > 3D Sampler > State > State Caching (page 96):
162 * Coherency with system memory in the state cache, like the texture
163 * cache is handled partially by software. It is expected that the
164 * command stream or shader will issue Cache Flush operation or
165 * Cache_Flush sampler message to ensure that the L1 cache remains
166 * coherent with system memory.
170 * Whenever the value of the Dynamic_State_Base_Addr,
171 * Surface_State_Base_Addr are altered, the L1 state cache must be
172 * invalidated to ensure the new surface or sampler state is fetched
173 * from system memory.
175 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
176 * which, according the PIPE_CONTROL instruction documentation in the
179 * Setting this bit is independent of any other bit in this packet.
180 * This bit controls the invalidation of the L1 and L2 state caches
181 * at the top of the pipe i.e. at the parsing time.
183 * Unfortunately, experimentation seems to indicate that state cache
184 * invalidation through a PIPE_CONTROL does nothing whatsoever in
185 * regards to surface state and binding tables. In stead, it seems that
186 * invalidating the texture cache is what is actually needed.
188 * XXX: As far as we have been able to determine through
189 * experimentation, shows that flush the texture cache appears to be
190 * sufficient. The theory here is that all of the sampling/rendering
191 * units cache the binding table in the texture cache. However, we have
192 * yet to be able to actually confirm this.
194 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
195 pc
.TextureCacheInvalidationEnable
= true;
196 pc
.ConstantCacheInvalidationEnable
= true;
197 pc
.StateCacheInvalidationEnable
= true;
202 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
203 struct anv_state state
, struct anv_address addr
)
205 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
208 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
209 state
.offset
+ isl_dev
->ss
.addr_offset
,
210 addr
.bo
, addr
.offset
, NULL
);
211 if (result
!= VK_SUCCESS
)
212 anv_batch_set_error(&cmd_buffer
->batch
, result
);
216 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
217 struct anv_surface_state state
)
219 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
221 assert(!anv_address_is_null(state
.address
));
222 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
224 if (!anv_address_is_null(state
.aux_address
)) {
226 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
227 &cmd_buffer
->pool
->alloc
,
228 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
229 state
.aux_address
.bo
,
230 state
.aux_address
.offset
,
232 if (result
!= VK_SUCCESS
)
233 anv_batch_set_error(&cmd_buffer
->batch
, result
);
236 if (!anv_address_is_null(state
.clear_address
)) {
238 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
239 &cmd_buffer
->pool
->alloc
,
241 isl_dev
->ss
.clear_color_state_offset
,
242 state
.clear_address
.bo
,
243 state
.clear_address
.offset
,
245 if (result
!= VK_SUCCESS
)
246 anv_batch_set_error(&cmd_buffer
->batch
, result
);
251 color_attachment_compute_aux_usage(struct anv_device
* device
,
252 struct anv_cmd_state
* cmd_state
,
253 uint32_t att
, VkRect2D render_area
,
254 union isl_color_value
*fast_clear_color
)
256 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
257 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
259 assert(iview
->n_planes
== 1);
261 if (iview
->planes
[0].isl
.base_array_layer
>=
262 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
263 iview
->planes
[0].isl
.base_level
)) {
264 /* There is no aux buffer which corresponds to the level and layer(s)
267 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
268 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
269 att_state
->fast_clear
= false;
273 att_state
->aux_usage
=
274 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
275 VK_IMAGE_ASPECT_COLOR_BIT
,
276 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
278 /* If we don't have aux, then we should have returned early in the layer
279 * check above. If we got here, we must have something.
281 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
283 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
284 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
285 att_state
->input_aux_usage
= att_state
->aux_usage
;
287 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
289 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
290 * setting is only allowed if Surface Format supported for Fast
291 * Clear. In addition, if the surface is bound to the sampling
292 * engine, Surface Format must be supported for Render Target
293 * Compression for surfaces bound to the sampling engine."
295 * In other words, we can only sample from a fast-cleared image if it
296 * also supports color compression.
298 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
) &&
299 isl_format_supports_ccs_d(&device
->info
, iview
->planes
[0].isl
.format
)) {
300 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
302 /* While fast-clear resolves and partial resolves are fairly cheap in the
303 * case where you render to most of the pixels, full resolves are not
304 * because they potentially involve reading and writing the entire
305 * framebuffer. If we can't texture with CCS_E, we should leave it off and
306 * limit ourselves to fast clears.
308 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
309 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
310 anv_perf_warn(device
->instance
, iview
->image
,
311 "Not temporarily enabling CCS_E.");
314 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
318 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
319 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
321 union isl_color_value clear_color
= {};
322 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
324 att_state
->clear_color_is_zero_one
=
325 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
326 att_state
->clear_color_is_zero
=
327 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
329 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
330 /* Start by getting the fast clear type. We use the first subpass
331 * layout here because we don't want to fast-clear if the first subpass
332 * to use the attachment can't handle fast-clears.
334 enum anv_fast_clear_type fast_clear_type
=
335 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
336 VK_IMAGE_ASPECT_COLOR_BIT
,
337 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
338 switch (fast_clear_type
) {
339 case ANV_FAST_CLEAR_NONE
:
340 att_state
->fast_clear
= false;
342 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
343 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
345 case ANV_FAST_CLEAR_ANY
:
346 att_state
->fast_clear
= true;
350 /* Potentially, we could do partial fast-clears but doing so has crazy
351 * alignment restrictions. It's easier to just restrict to full size
352 * fast clears for now.
354 if (render_area
.offset
.x
!= 0 ||
355 render_area
.offset
.y
!= 0 ||
356 render_area
.extent
.width
!= iview
->extent
.width
||
357 render_area
.extent
.height
!= iview
->extent
.height
)
358 att_state
->fast_clear
= false;
360 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
361 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
362 att_state
->fast_clear
= false;
364 /* We only allow fast clears to the first slice of an image (level 0,
365 * layer 0) and only for the entire slice. This guarantees us that, at
366 * any given time, there is only one clear color on any given image at
367 * any given time. At the time of our testing (Jan 17, 2018), there
368 * were no known applications which would benefit from fast-clearing
369 * more than just the first slice.
371 if (att_state
->fast_clear
&&
372 (iview
->planes
[0].isl
.base_level
> 0 ||
373 iview
->planes
[0].isl
.base_array_layer
> 0)) {
374 anv_perf_warn(device
->instance
, iview
->image
,
375 "Rendering with multi-lod or multi-layer framebuffer "
376 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
377 "baseArrayLayer > 0. Not fast clearing.");
378 att_state
->fast_clear
= false;
379 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
380 anv_perf_warn(device
->instance
, iview
->image
,
381 "Rendering to a multi-layer framebuffer with "
382 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
385 if (att_state
->fast_clear
)
386 *fast_clear_color
= clear_color
;
388 att_state
->fast_clear
= false;
393 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
394 struct anv_cmd_state
*cmd_state
,
395 uint32_t att
, VkRect2D render_area
)
397 struct anv_render_pass_attachment
*pass_att
=
398 &cmd_state
->pass
->attachments
[att
];
399 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
400 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
402 /* These will be initialized after the first subpass transition. */
403 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
404 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
407 /* We don't do any HiZ or depth fast-clears on gen7 yet */
408 att_state
->fast_clear
= false;
412 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
413 /* If we're just clearing stencil, we can always HiZ clear */
414 att_state
->fast_clear
= true;
418 /* Default to false for now */
419 att_state
->fast_clear
= false;
421 /* We must have depth in order to have HiZ */
422 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
425 const enum isl_aux_usage first_subpass_aux_usage
=
426 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
427 VK_IMAGE_ASPECT_DEPTH_BIT
,
428 pass_att
->first_subpass_layout
);
429 if (!blorp_can_hiz_clear_depth(&device
->info
,
430 &iview
->image
->planes
[0].surface
.isl
,
431 first_subpass_aux_usage
,
432 iview
->planes
[0].isl
.base_level
,
433 iview
->planes
[0].isl
.base_array_layer
,
434 render_area
.offset
.x
,
435 render_area
.offset
.y
,
436 render_area
.offset
.x
+
437 render_area
.extent
.width
,
438 render_area
.offset
.y
+
439 render_area
.extent
.height
))
442 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
445 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
446 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
447 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
448 * only supports returning 0.0f. Gens prior to gen8 do not support this
454 /* If we got here, then we can fast clear */
455 att_state
->fast_clear
= true;
459 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
461 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
464 /* We only allocate input attachment states for color surfaces. Compression
465 * is not yet enabled for depth textures and stencil doesn't allow
466 * compression so we can just use the texture surface state from the view.
468 return vk_format_is_color(att
->format
);
471 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
472 * the initial layout is undefined, the HiZ buffer and depth buffer will
473 * represent the same data at the end of this operation.
476 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
477 const struct anv_image
*image
,
478 VkImageLayout initial_layout
,
479 VkImageLayout final_layout
)
481 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
482 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
483 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
484 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
485 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
486 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
488 enum isl_aux_op hiz_op
;
489 if (hiz_enabled
&& !enable_hiz
) {
490 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
491 } else if (!hiz_enabled
&& enable_hiz
) {
492 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
494 assert(hiz_enabled
== enable_hiz
);
495 /* If the same buffer will be used, no resolves are necessary. */
496 hiz_op
= ISL_AUX_OP_NONE
;
499 if (hiz_op
!= ISL_AUX_OP_NONE
)
500 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
505 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
507 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
508 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
||
509 layout
== VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
;
512 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
513 * the initial layout is undefined, the HiZ buffer and depth buffer will
514 * represent the same data at the end of this operation.
517 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
518 const struct anv_image
*image
,
519 uint32_t base_level
, uint32_t level_count
,
520 uint32_t base_layer
, uint32_t layer_count
,
521 VkImageLayout initial_layout
,
522 VkImageLayout final_layout
)
525 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
526 VK_IMAGE_ASPECT_STENCIL_BIT
);
528 /* On gen7, we have to store a texturable version of the stencil buffer in
529 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
530 * forth at strategic points. Stencil writes are only allowed in following
533 * - VK_IMAGE_LAYOUT_GENERAL
534 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
535 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
536 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
537 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
539 * For general, we have no nice opportunity to transition so we do the copy
540 * to the shadow unconditionally at the end of the subpass. For transfer
541 * destinations, we can update it as part of the transfer op. For the other
542 * layouts, we delay the copy until a transition into some other layout.
544 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
545 vk_image_layout_stencil_write_optimal(initial_layout
) &&
546 !vk_image_layout_stencil_write_optimal(final_layout
)) {
547 anv_image_copy_to_shadow(cmd_buffer
, image
,
548 VK_IMAGE_ASPECT_STENCIL_BIT
,
549 base_level
, level_count
,
550 base_layer
, layer_count
);
552 #endif /* GEN_GEN == 7 */
555 #define MI_PREDICATE_SRC0 0x2400
556 #define MI_PREDICATE_SRC1 0x2408
557 #define MI_PREDICATE_RESULT 0x2418
560 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
561 const struct anv_image
*image
,
562 VkImageAspectFlagBits aspect
,
564 uint32_t base_layer
, uint32_t layer_count
,
567 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
569 /* We only have compression tracking for CCS_E */
570 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
573 for (uint32_t a
= 0; a
< layer_count
; a
++) {
574 uint32_t layer
= base_layer
+ a
;
575 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
576 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
579 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
585 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
586 const struct anv_image
*image
,
587 VkImageAspectFlagBits aspect
,
588 enum anv_fast_clear_type fast_clear
)
590 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
591 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
593 sdi
.ImmediateData
= fast_clear
;
596 /* Whenever we have fast-clear, we consider that slice to be compressed.
597 * This makes building predicates much easier.
599 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
600 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
603 /* This is only really practical on haswell and above because it requires
604 * MI math in order to get it correct.
606 #if GEN_GEN >= 8 || GEN_IS_HASWELL
608 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
609 const struct anv_image
*image
,
610 VkImageAspectFlagBits aspect
,
611 uint32_t level
, uint32_t array_layer
,
612 enum isl_aux_op resolve_op
,
613 enum anv_fast_clear_type fast_clear_supported
)
615 struct gen_mi_builder b
;
616 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
618 const struct gen_mi_value fast_clear_type
=
619 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
622 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
623 /* In this case, we're doing a full resolve which means we want the
624 * resolve to happen if any compression (including fast-clears) is
627 * In order to simplify the logic a bit, we make the assumption that,
628 * if the first slice has been fast-cleared, it is also marked as
629 * compressed. See also set_image_fast_clear_state.
631 const struct gen_mi_value compression_state
=
632 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
634 level
, array_layer
));
635 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
637 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
639 if (level
== 0 && array_layer
== 0) {
640 /* If the predicate is true, we want to write 0 to the fast clear type
641 * and, if it's false, leave it alone. We can do this by writing
643 * clear_type = clear_type & ~predicate;
645 struct gen_mi_value new_fast_clear_type
=
646 gen_mi_iand(&b
, fast_clear_type
,
647 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
648 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
650 } else if (level
== 0 && array_layer
== 0) {
651 /* In this case, we are doing a partial resolve to get rid of fast-clear
652 * colors. We don't care about the compression state but we do care
653 * about how much fast clear is allowed by the final layout.
655 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
656 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
658 /* We need to compute (fast_clear_supported < image->fast_clear) */
659 struct gen_mi_value pred
=
660 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
661 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
662 gen_mi_value_ref(&b
, pred
));
664 /* If the predicate is true, we want to write 0 to the fast clear type
665 * and, if it's false, leave it alone. We can do this by writing
667 * clear_type = clear_type & ~predicate;
669 struct gen_mi_value new_fast_clear_type
=
670 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
671 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
673 /* In this case, we're trying to do a partial resolve on a slice that
674 * doesn't have clear color. There's nothing to do.
676 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
680 /* Set src1 to 0 and use a != condition */
681 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
683 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
684 mip
.LoadOperation
= LOAD_LOADINV
;
685 mip
.CombineOperation
= COMBINE_SET
;
686 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
689 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
693 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
694 const struct anv_image
*image
,
695 VkImageAspectFlagBits aspect
,
696 uint32_t level
, uint32_t array_layer
,
697 enum isl_aux_op resolve_op
,
698 enum anv_fast_clear_type fast_clear_supported
)
700 struct gen_mi_builder b
;
701 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
703 struct gen_mi_value fast_clear_type_mem
=
704 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
707 /* This only works for partial resolves and only when the clear color is
708 * all or nothing. On the upside, this emits less command streamer code
709 * and works on Ivybridge and Bay Trail.
711 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
712 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
714 /* We don't support fast clears on anything other than the first slice. */
715 if (level
> 0 || array_layer
> 0)
718 /* On gen8, we don't have a concept of default clear colors because we
719 * can't sample from CCS surfaces. It's enough to just load the fast clear
720 * state into the predicate register.
722 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
723 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
724 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
726 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
727 mip
.LoadOperation
= LOAD_LOADINV
;
728 mip
.CombineOperation
= COMBINE_SET
;
729 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
732 #endif /* GEN_GEN <= 8 */
735 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
736 const struct anv_image
*image
,
737 enum isl_format format
,
738 VkImageAspectFlagBits aspect
,
739 uint32_t level
, uint32_t array_layer
,
740 enum isl_aux_op resolve_op
,
741 enum anv_fast_clear_type fast_clear_supported
)
743 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
746 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
747 aspect
, level
, array_layer
,
748 resolve_op
, fast_clear_supported
);
749 #else /* GEN_GEN <= 8 */
750 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
751 aspect
, level
, array_layer
,
752 resolve_op
, fast_clear_supported
);
755 /* CCS_D only supports full resolves and BLORP will assert on us if we try
756 * to do a partial resolve on a CCS_D surface.
758 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
759 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
760 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
762 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
763 array_layer
, 1, resolve_op
, NULL
, true);
767 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
768 const struct anv_image
*image
,
769 enum isl_format format
,
770 VkImageAspectFlagBits aspect
,
771 uint32_t array_layer
,
772 enum isl_aux_op resolve_op
,
773 enum anv_fast_clear_type fast_clear_supported
)
775 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
776 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
778 #if GEN_GEN >= 8 || GEN_IS_HASWELL
779 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
780 aspect
, 0, array_layer
,
781 resolve_op
, fast_clear_supported
);
783 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
784 array_layer
, 1, resolve_op
, NULL
, true);
786 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
791 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
792 const struct anv_image
*image
,
793 VkImageAspectFlagBits aspect
,
794 enum isl_aux_usage aux_usage
,
797 uint32_t layer_count
)
799 /* The aspect must be exactly one of the image aspects. */
800 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
802 /* The only compression types with more than just fast-clears are MCS,
803 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
804 * track the current fast-clear and compression state. This leaves us
805 * with just MCS and CCS_E.
807 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
808 aux_usage
!= ISL_AUX_USAGE_MCS
)
811 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
812 level
, base_layer
, layer_count
, true);
816 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
817 const struct anv_image
*image
,
818 VkImageAspectFlagBits aspect
)
820 assert(cmd_buffer
&& image
);
821 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
823 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
824 ANV_FAST_CLEAR_NONE
);
826 /* Initialize the struct fields that are accessed for fast-clears so that
827 * the HW restrictions on the field values are satisfied.
829 struct anv_address addr
=
830 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
833 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
834 const unsigned num_dwords
= GEN_GEN
>= 10 ?
835 isl_dev
->ss
.clear_color_state_size
/ 4 :
836 isl_dev
->ss
.clear_value_size
/ 4;
837 for (unsigned i
= 0; i
< num_dwords
; i
++) {
838 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
840 sdi
.Address
.offset
+= i
* 4;
841 sdi
.ImmediateData
= 0;
845 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
847 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
848 /* Pre-SKL, the dword containing the clear values also contains
849 * other fields, so we need to initialize those fields to match the
850 * values that would be in a color attachment.
852 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
853 ISL_CHANNEL_SELECT_GREEN
<< 22 |
854 ISL_CHANNEL_SELECT_BLUE
<< 19 |
855 ISL_CHANNEL_SELECT_ALPHA
<< 16;
856 } else if (GEN_GEN
== 7) {
857 /* On IVB, the dword containing the clear values also contains
858 * other fields that must be zero or can be zero.
860 sdi
.ImmediateData
= 0;
866 /* Copy the fast-clear value dword(s) between a surface state object and an
867 * image's fast clear state buffer.
870 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
871 struct anv_state surface_state
,
872 const struct anv_image
*image
,
873 VkImageAspectFlagBits aspect
,
874 bool copy_from_surface_state
)
876 assert(cmd_buffer
&& image
);
877 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
879 struct anv_address ss_clear_addr
= {
880 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
881 .offset
= surface_state
.offset
+
882 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
884 const struct anv_address entry_addr
=
885 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
886 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
889 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
890 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
891 * in-flight when they are issued even if the memory touched is not
892 * currently active for rendering. The weird bit is that it is not the
893 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
894 * rendering hangs such that the next stalling command after the
895 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
897 * It is unclear exactly why this hang occurs. Both MI commands come with
898 * warnings about the 3D pipeline but that doesn't seem to fully explain
899 * it. My (Jason's) best theory is that it has something to do with the
900 * fact that we're using a GPU state register as our temporary and that
901 * something with reading/writing it is causing problems.
903 * In order to work around this issue, we emit a PIPE_CONTROL with the
904 * command streamer stall bit set.
906 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
907 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
910 struct gen_mi_builder b
;
911 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
913 if (copy_from_surface_state
) {
914 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
916 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
918 /* Updating a surface state object may require that the state cache be
919 * invalidated. From the SKL PRM, Shared Functions -> State -> State
922 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
923 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
924 * modified [...], the L1 state cache must be invalidated to ensure
925 * the new surface or sampler state is fetched from system memory.
927 * In testing, SKL doesn't actually seem to need this, but HSW does.
929 cmd_buffer
->state
.pending_pipe_bits
|=
930 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
935 * @brief Transitions a color buffer from one layout to another.
937 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
940 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
941 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
942 * this represents the maximum layers to transition at each
943 * specified miplevel.
946 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
947 const struct anv_image
*image
,
948 VkImageAspectFlagBits aspect
,
949 const uint32_t base_level
, uint32_t level_count
,
950 uint32_t base_layer
, uint32_t layer_count
,
951 VkImageLayout initial_layout
,
952 VkImageLayout final_layout
)
954 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
955 /* Validate the inputs. */
957 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
958 /* These values aren't supported for simplicity's sake. */
959 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
960 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
961 /* Ensure the subresource range is valid. */
962 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
963 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
964 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
965 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
966 assert(last_level_num
<= image
->levels
);
967 /* The spec disallows these final layouts. */
968 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
969 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
971 /* No work is necessary if the layout stays the same or if this subresource
972 * range lacks auxiliary data.
974 if (initial_layout
== final_layout
)
977 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
979 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
980 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
981 /* This surface is a linear compressed image with a tiled shadow surface
982 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
983 * we need to ensure the shadow copy is up-to-date.
985 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
986 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
987 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
988 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
990 anv_image_copy_to_shadow(cmd_buffer
, image
,
991 VK_IMAGE_ASPECT_COLOR_BIT
,
992 base_level
, level_count
,
993 base_layer
, layer_count
);
996 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
999 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
1001 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1002 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1003 /* A subresource in the undefined layout may have been aliased and
1004 * populated with any arrangement of bits. Therefore, we must initialize
1005 * the related aux buffer and clear buffer entry with desirable values.
1006 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1007 * images with VK_IMAGE_TILING_OPTIMAL.
1009 * Initialize the relevant clear buffer entries.
1011 if (base_level
== 0 && base_layer
== 0)
1012 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1014 /* Initialize the aux buffers to enable correct rendering. In order to
1015 * ensure that things such as storage images work correctly, aux buffers
1016 * need to be initialized to valid data.
1018 * Having an aux buffer with invalid data is a problem for two reasons:
1020 * 1) Having an invalid value in the buffer can confuse the hardware.
1021 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1022 * invalid and leads to the hardware doing strange things. It
1023 * doesn't hang as far as we can tell but rendering corruption can
1026 * 2) If this transition is into the GENERAL layout and we then use the
1027 * image as a storage image, then we must have the aux buffer in the
1028 * pass-through state so that, if we then go to texture from the
1029 * image, we get the results of our storage image writes and not the
1030 * fast clear color or other random data.
1032 * For CCS both of the problems above are real demonstrable issues. In
1033 * that case, the only thing we can do is to perform an ambiguate to
1034 * transition the aux surface into the pass-through state.
1036 * For MCS, (2) is never an issue because we don't support multisampled
1037 * storage images. In theory, issue (1) is a problem with MCS but we've
1038 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1039 * theory, be interpreted as something but we don't know that all bit
1040 * patterns are actually valid. For 2x and 8x, you could easily end up
1041 * with the MCS referring to an invalid plane because not all bits of
1042 * the MCS value are actually used. Even though we've never seen issues
1043 * in the wild, it's best to play it safe and initialize the MCS. We
1044 * can use a fast-clear for MCS because we only ever touch from render
1045 * and texture (no image load store).
1047 if (image
->samples
== 1) {
1048 for (uint32_t l
= 0; l
< level_count
; l
++) {
1049 const uint32_t level
= base_level
+ l
;
1051 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1052 if (base_layer
>= aux_layers
)
1053 break; /* We will only get fewer layers as level increases */
1054 uint32_t level_layer_count
=
1055 MIN2(layer_count
, aux_layers
- base_layer
);
1057 anv_image_ccs_op(cmd_buffer
, image
,
1058 image
->planes
[plane
].surface
.isl
.format
,
1059 aspect
, level
, base_layer
, level_layer_count
,
1060 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1062 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1063 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1064 level
, base_layer
, level_layer_count
,
1069 if (image
->samples
== 4 || image
->samples
== 16) {
1070 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1071 "Doing a potentially unnecessary fast-clear to "
1072 "define an MCS buffer.");
1075 assert(base_level
== 0 && level_count
== 1);
1076 anv_image_mcs_op(cmd_buffer
, image
,
1077 image
->planes
[plane
].surface
.isl
.format
,
1078 aspect
, base_layer
, layer_count
,
1079 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1084 const enum isl_aux_usage initial_aux_usage
=
1085 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1086 const enum isl_aux_usage final_aux_usage
=
1087 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1089 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1090 * We can handle transitions between CCS_D/E to and from NONE. What we
1091 * don't yet handle is switching between CCS_E and CCS_D within a given
1092 * image. Doing so in a performant way requires more detailed aux state
1093 * tracking such as what is done in i965. For now, just assume that we
1094 * only have one type of compression.
1096 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1097 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1098 initial_aux_usage
== final_aux_usage
);
1100 /* If initial aux usage is NONE, there is nothing to resolve */
1101 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1104 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1106 /* If the initial layout supports more fast clear than the final layout
1107 * then we need at least a partial resolve.
1109 const enum anv_fast_clear_type initial_fast_clear
=
1110 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1111 const enum anv_fast_clear_type final_fast_clear
=
1112 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1113 if (final_fast_clear
< initial_fast_clear
)
1114 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1116 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1117 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1118 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1120 if (resolve_op
== ISL_AUX_OP_NONE
)
1123 /* Perform a resolve to synchronize data between the main and aux buffer.
1124 * Before we begin, we must satisfy the cache flushing requirement specified
1125 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1127 * Any transition from any value in {Clear, Render, Resolve} to a
1128 * different value in {Clear, Render, Resolve} requires end of pipe
1131 * We perform a flush of the write cache before and after the clear and
1132 * resolve operations to meet this requirement.
1134 * Unlike other drawing, fast clear operations are not properly
1135 * synchronized. The first PIPE_CONTROL here likely ensures that the
1136 * contents of the previous render or clear hit the render target before we
1137 * resolve and the second likely ensures that the resolve is complete before
1138 * we do any more rendering or clearing.
1140 cmd_buffer
->state
.pending_pipe_bits
|=
1141 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1143 for (uint32_t l
= 0; l
< level_count
; l
++) {
1144 uint32_t level
= base_level
+ l
;
1146 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1147 if (base_layer
>= aux_layers
)
1148 break; /* We will only get fewer layers as level increases */
1149 uint32_t level_layer_count
=
1150 MIN2(layer_count
, aux_layers
- base_layer
);
1152 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1153 uint32_t array_layer
= base_layer
+ a
;
1154 if (image
->samples
== 1) {
1155 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1156 image
->planes
[plane
].surface
.isl
.format
,
1157 aspect
, level
, array_layer
, resolve_op
,
1160 /* We only support fast-clear on the first layer so partial
1161 * resolves should not be used on other layers as they will use
1162 * the clear color stored in memory that is only valid for layer0.
1164 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1168 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1169 image
->planes
[plane
].surface
.isl
.format
,
1170 aspect
, array_layer
, resolve_op
,
1176 cmd_buffer
->state
.pending_pipe_bits
|=
1177 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1181 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1184 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1185 struct anv_render_pass
*pass
,
1186 const VkRenderPassBeginInfo
*begin
)
1188 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1189 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1190 struct anv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1192 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1194 if (pass
->attachment_count
> 0) {
1195 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1196 pass
->attachment_count
*
1197 sizeof(state
->attachments
[0]),
1198 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1199 if (state
->attachments
== NULL
) {
1200 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1201 return anv_batch_set_error(&cmd_buffer
->batch
,
1202 VK_ERROR_OUT_OF_HOST_MEMORY
);
1205 state
->attachments
= NULL
;
1208 /* Reserve one for the NULL state. */
1209 unsigned num_states
= 1;
1210 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1211 if (vk_format_is_color(pass
->attachments
[i
].format
))
1214 if (need_input_attachment_state(&pass
->attachments
[i
]))
1218 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1219 state
->render_pass_states
=
1220 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1221 num_states
* ss_stride
, isl_dev
->ss
.align
);
1223 struct anv_state next_state
= state
->render_pass_states
;
1224 next_state
.alloc_size
= isl_dev
->ss
.size
;
1226 state
->null_surface_state
= next_state
;
1227 next_state
.offset
+= ss_stride
;
1228 next_state
.map
+= ss_stride
;
1230 const VkRenderPassAttachmentBeginInfoKHR
*begin_attachment
=
1231 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1233 if (begin
&& !begin_attachment
)
1234 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1236 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1237 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1238 state
->attachments
[i
].color
.state
= next_state
;
1239 next_state
.offset
+= ss_stride
;
1240 next_state
.map
+= ss_stride
;
1243 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1244 state
->attachments
[i
].input
.state
= next_state
;
1245 next_state
.offset
+= ss_stride
;
1246 next_state
.map
+= ss_stride
;
1249 if (begin_attachment
&& begin_attachment
->attachmentCount
!= 0) {
1250 assert(begin_attachment
->attachmentCount
== pass
->attachment_count
);
1251 ANV_FROM_HANDLE(anv_image_view
, iview
, begin_attachment
->pAttachments
[i
]);
1252 cmd_buffer
->state
.attachments
[i
].image_view
= iview
;
1253 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1254 cmd_buffer
->state
.attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1257 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1258 state
->render_pass_states
.alloc_size
);
1261 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1262 isl_extent3d(framebuffer
->width
,
1263 framebuffer
->height
,
1264 framebuffer
->layers
));
1266 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1267 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1268 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1269 VkImageAspectFlags clear_aspects
= 0;
1270 VkImageAspectFlags load_aspects
= 0;
1272 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1273 /* color attachment */
1274 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1275 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1276 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1277 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1280 /* depthstencil attachment */
1281 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1282 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1283 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1284 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1285 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1288 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1289 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1290 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1291 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1292 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1297 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1298 state
->attachments
[i
].current_stencil_layout
= att
->stencil_initial_layout
;
1299 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1300 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1302 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1304 struct anv_image_view
*iview
= cmd_buffer
->state
.attachments
[i
].image_view
;
1305 anv_assert(iview
->vk_format
== att
->format
);
1307 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1308 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1310 union isl_color_value clear_color
= { .u32
= { 0, } };
1311 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1312 anv_assert(iview
->n_planes
== 1);
1313 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1314 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1315 state
, i
, begin
->renderArea
,
1318 anv_image_fill_surface_state(cmd_buffer
->device
,
1320 VK_IMAGE_ASPECT_COLOR_BIT
,
1321 &iview
->planes
[0].isl
,
1322 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1323 state
->attachments
[i
].aux_usage
,
1326 &state
->attachments
[i
].color
,
1329 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1331 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1336 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1337 anv_image_fill_surface_state(cmd_buffer
->device
,
1339 VK_IMAGE_ASPECT_COLOR_BIT
,
1340 &iview
->planes
[0].isl
,
1341 ISL_SURF_USAGE_TEXTURE_BIT
,
1342 state
->attachments
[i
].input_aux_usage
,
1345 &state
->attachments
[i
].input
,
1348 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1357 genX(BeginCommandBuffer
)(
1358 VkCommandBuffer commandBuffer
,
1359 const VkCommandBufferBeginInfo
* pBeginInfo
)
1361 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1363 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1364 * command buffer's state. Otherwise, we must *reset* its state. In both
1365 * cases we reset it.
1367 * From the Vulkan 1.0 spec:
1369 * If a command buffer is in the executable state and the command buffer
1370 * was allocated from a command pool with the
1371 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1372 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1373 * as if vkResetCommandBuffer had been called with
1374 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1375 * the command buffer in the recording state.
1377 anv_cmd_buffer_reset(cmd_buffer
);
1379 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1381 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1382 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1384 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1386 /* We sometimes store vertex data in the dynamic state buffer for blorp
1387 * operations and our dynamic state stream may re-use data from previous
1388 * command buffers. In order to prevent stale cache data, we flush the VF
1389 * cache. We could do this on every blorp call but that's not really
1390 * needed as all of the data will get written by the CPU prior to the GPU
1391 * executing anything. The chances are fairly high that they will use
1392 * blorp at least once per primary command buffer so it shouldn't be
1395 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1396 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1398 /* We send an "Indirect State Pointers Disable" packet at
1399 * EndCommandBuffer, so all push contant packets are ignored during a
1400 * context restore. Documentation says after that command, we need to
1401 * emit push constants again before any rendering operation. So we
1402 * flag them dirty here to make sure they get emitted.
1404 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1406 VkResult result
= VK_SUCCESS
;
1407 if (cmd_buffer
->usage_flags
&
1408 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1409 assert(pBeginInfo
->pInheritanceInfo
);
1410 cmd_buffer
->state
.pass
=
1411 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1412 cmd_buffer
->state
.subpass
=
1413 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1415 /* This is optional in the inheritance info. */
1416 cmd_buffer
->state
.framebuffer
=
1417 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1419 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1420 cmd_buffer
->state
.pass
, NULL
);
1422 /* Record that HiZ is enabled if we can. */
1423 if (cmd_buffer
->state
.framebuffer
) {
1424 const struct anv_image_view
* const iview
=
1425 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1428 VkImageLayout layout
=
1429 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1431 enum isl_aux_usage aux_usage
=
1432 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1433 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1435 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1439 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1442 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1443 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1444 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1445 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1447 /* If secondary buffer supports conditional rendering
1448 * we should emit commands as if conditional rendering is enabled.
1450 cmd_buffer
->state
.conditional_render_enabled
=
1451 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1458 /* From the PRM, Volume 2a:
1460 * "Indirect State Pointers Disable
1462 * At the completion of the post-sync operation associated with this pipe
1463 * control packet, the indirect state pointers in the hardware are
1464 * considered invalid; the indirect pointers are not saved in the context.
1465 * If any new indirect state commands are executed in the command stream
1466 * while the pipe control is pending, the new indirect state commands are
1469 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1470 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1471 * commands are only considered as Indirect State Pointers. Once ISP is
1472 * issued in a context, SW must initialize by programming push constant
1473 * commands for all the shaders (at least to zero length) before attempting
1474 * any rendering operation for the same context."
1476 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1477 * even though they point to a BO that has been already unreferenced at
1478 * the end of the previous batch buffer. This has been fine so far since
1479 * we are protected by these scratch page (every address not covered by
1480 * a BO should be pointing to the scratch page). But on CNL, it is
1481 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1484 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1485 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1486 * context restore, so the mentioned hang doesn't happen. However,
1487 * software must program push constant commands for all stages prior to
1488 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1490 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1491 * constants have been loaded into the EUs prior to disable the push constants
1492 * so that it doesn't hang a previous 3DPRIMITIVE.
1495 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1497 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1498 pc
.StallAtPixelScoreboard
= true;
1499 pc
.CommandStreamerStallEnable
= true;
1501 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1502 pc
.IndirectStatePointersDisable
= true;
1503 pc
.CommandStreamerStallEnable
= true;
1508 genX(EndCommandBuffer
)(
1509 VkCommandBuffer commandBuffer
)
1511 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1513 if (anv_batch_has_error(&cmd_buffer
->batch
))
1514 return cmd_buffer
->batch
.status
;
1516 /* We want every command buffer to start with the PMA fix in a known state,
1517 * so we disable it at the end of the command buffer.
1519 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1521 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1523 emit_isp_disable(cmd_buffer
);
1525 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1531 genX(CmdExecuteCommands
)(
1532 VkCommandBuffer commandBuffer
,
1533 uint32_t commandBufferCount
,
1534 const VkCommandBuffer
* pCmdBuffers
)
1536 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1538 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1540 if (anv_batch_has_error(&primary
->batch
))
1543 /* The secondary command buffers will assume that the PMA fix is disabled
1544 * when they begin executing. Make sure this is true.
1546 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1548 /* The secondary command buffer doesn't know which textures etc. have been
1549 * flushed prior to their execution. Apply those flushes now.
1551 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1553 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1554 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1556 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1557 assert(!anv_batch_has_error(&secondary
->batch
));
1559 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1560 if (secondary
->state
.conditional_render_enabled
) {
1561 if (!primary
->state
.conditional_render_enabled
) {
1562 /* Secondary buffer is constructed as if it will be executed
1563 * with conditional rendering, we should satisfy this dependency
1564 * regardless of conditional rendering being enabled in primary.
1566 struct gen_mi_builder b
;
1567 gen_mi_builder_init(&b
, &primary
->batch
);
1568 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1569 gen_mi_imm(UINT64_MAX
));
1574 if (secondary
->usage_flags
&
1575 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1576 /* If we're continuing a render pass from the primary, we need to
1577 * copy the surface states for the current subpass into the storage
1578 * we allocated for them in BeginCommandBuffer.
1580 struct anv_bo
*ss_bo
=
1581 primary
->device
->surface_state_pool
.block_pool
.bo
;
1582 struct anv_state src_state
= primary
->state
.render_pass_states
;
1583 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1584 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1586 genX(cmd_buffer_so_memcpy
)(primary
,
1587 (struct anv_address
) {
1589 .offset
= dst_state
.offset
,
1591 (struct anv_address
) {
1593 .offset
= src_state
.offset
,
1595 src_state
.alloc_size
);
1598 anv_cmd_buffer_add_secondary(primary
, secondary
);
1601 /* The secondary may have selected a different pipeline (3D or compute) and
1602 * may have changed the current L3$ configuration. Reset our tracking
1603 * variables to invalid values to ensure that we re-emit these in the case
1604 * where we do any draws or compute dispatches from the primary after the
1605 * secondary has returned.
1607 primary
->state
.current_pipeline
= UINT32_MAX
;
1608 primary
->state
.current_l3_config
= NULL
;
1609 primary
->state
.current_hash_scale
= 0;
1611 /* Each of the secondary command buffers will use its own state base
1612 * address. We need to re-emit state base address for the primary after
1613 * all of the secondaries are done.
1615 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1618 genX(cmd_buffer_emit_state_base_address
)(primary
);
1621 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1622 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1623 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1626 * Program the hardware to use the specified L3 configuration.
1629 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1630 const struct gen_l3_config
*cfg
)
1633 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1636 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1637 intel_logd("L3 config transition: ");
1638 gen_dump_l3_config(cfg
, stderr
);
1641 UNUSED
const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1643 /* According to the hardware docs, the L3 partitioning can only be changed
1644 * while the pipeline is completely drained and the caches are flushed,
1645 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1647 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1648 pc
.DCFlushEnable
= true;
1649 pc
.PostSyncOperation
= NoWrite
;
1650 pc
.CommandStreamerStallEnable
= true;
1653 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1654 * invalidation of the relevant caches. Note that because RO invalidation
1655 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1656 * command is processed by the CS) we cannot combine it with the previous
1657 * stalling flush as the hardware documentation suggests, because that
1658 * would cause the CS to stall on previous rendering *after* RO
1659 * invalidation and wouldn't prevent the RO caches from being polluted by
1660 * concurrent rendering before the stall completes. This intentionally
1661 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1662 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1663 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1664 * already guarantee that there is no concurrent GPGPU kernel execution
1665 * (see SKL HSD 2132585).
1667 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1668 pc
.TextureCacheInvalidationEnable
= true;
1669 pc
.ConstantCacheInvalidationEnable
= true;
1670 pc
.InstructionCacheInvalidateEnable
= true;
1671 pc
.StateCacheInvalidationEnable
= true;
1672 pc
.PostSyncOperation
= NoWrite
;
1675 /* Now send a third stalling flush to make sure that invalidation is
1676 * complete when the L3 configuration registers are modified.
1678 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1679 pc
.DCFlushEnable
= true;
1680 pc
.PostSyncOperation
= NoWrite
;
1681 pc
.CommandStreamerStallEnable
= true;
1686 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1689 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1690 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1692 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1693 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1697 anv_pack_struct(&l3cr
, L3_ALLOCATION_REG
,
1699 .SLMEnable
= has_slm
,
1702 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1703 * in L3CNTLREG register. The default setting of the bit is not the
1704 * desirable behavior.
1706 .ErrorDetectionBehaviorControl
= true,
1707 .UseFullWays
= true,
1709 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1710 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1711 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1712 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1714 /* Set up the L3 partitioning. */
1715 emit_lri(&cmd_buffer
->batch
, L3_ALLOCATION_REG_num
, l3cr
);
1719 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1720 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1721 cfg
->n
[GEN_L3P_ALL
];
1722 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1723 cfg
->n
[GEN_L3P_ALL
];
1724 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1725 cfg
->n
[GEN_L3P_ALL
];
1727 assert(!cfg
->n
[GEN_L3P_ALL
]);
1729 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1730 * the matching space on the remaining banks has to be allocated to a
1731 * client (URB for all validated configurations) set to the
1732 * lower-bandwidth 2-bank address hashing mode.
1734 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1735 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1736 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1738 /* Minimum number of ways that can be allocated to the URB. */
1739 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1740 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1742 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1743 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1744 .ConvertDC_UC
= !has_dc
,
1745 .ConvertIS_UC
= !has_is
,
1746 .ConvertC_UC
= !has_c
,
1747 .ConvertT_UC
= !has_t
);
1749 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1750 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1751 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1753 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1754 .SLMEnable
= has_slm
,
1755 .URBLowBandwidth
= urb_low_bw
,
1756 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1758 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1760 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1761 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1763 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1764 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1765 .ISLowBandwidth
= 0,
1766 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1768 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1769 .TLowBandwidth
= 0);
1771 /* Set up the L3 partitioning. */
1772 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1773 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1774 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1777 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1778 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1779 * them disabled to avoid crashing the system hard.
1781 uint32_t scratch1
, chicken3
;
1782 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1783 .L3AtomicDisable
= !has_dc
);
1784 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1785 .L3AtomicDisableMask
= true,
1786 .L3AtomicDisable
= !has_dc
);
1787 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1788 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1794 cmd_buffer
->state
.current_l3_config
= cfg
;
1798 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1800 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1802 /* Flushes are pipelined while invalidations are handled immediately.
1803 * Therefore, if we're flushing anything then we need to schedule a stall
1804 * before any invalidations can happen.
1806 if (bits
& ANV_PIPE_FLUSH_BITS
)
1807 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1809 /* If we're going to do an invalidate and we have a pending CS stall that
1810 * has yet to be resolved, we do the CS stall now.
1812 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1813 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1814 bits
|= ANV_PIPE_CS_STALL_BIT
;
1815 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1818 if (GEN_GEN
>= 12 &&
1819 ((bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
) ||
1820 (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
))) {
1821 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
1824 * Unified Cache (Tile Cache Disabled):
1826 * When the Color and Depth (Z) streams are enabled to be cached in
1827 * the DC space of L2, Software must use "Render Target Cache Flush
1828 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
1829 * Flush" for getting the color and depth (Z) write data to be
1830 * globally observable. In this mode of operation it is not required
1831 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
1833 bits
|= ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
1836 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1837 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1839 pipe
.TileCacheFlushEnable
= bits
& ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
1841 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1842 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1843 pipe
.RenderTargetCacheFlushEnable
=
1844 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1846 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1847 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1848 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1851 * According to the Broadwell documentation, any PIPE_CONTROL with the
1852 * "Command Streamer Stall" bit set must also have another bit set,
1853 * with five different options:
1855 * - Render Target Cache Flush
1856 * - Depth Cache Flush
1857 * - Stall at Pixel Scoreboard
1858 * - Post-Sync Operation
1862 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1863 * mesa and it seems to work fine. The choice is fairly arbitrary.
1865 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1866 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1867 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1868 pipe
.StallAtPixelScoreboard
= true;
1871 /* If a render target flush was emitted, then we can toggle off the bit
1872 * saying that render target writes are ongoing.
1874 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1875 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1877 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1880 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1881 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1883 * "If the VF Cache Invalidation Enable is set to a 1 in a
1884 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1885 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1886 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1889 * This appears to hang Broadwell, so we restrict it to just gen9.
1891 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1892 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1894 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1895 pipe
.StateCacheInvalidationEnable
=
1896 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1897 pipe
.ConstantCacheInvalidationEnable
=
1898 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1899 pipe
.VFCacheInvalidationEnable
=
1900 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1901 pipe
.TextureCacheInvalidationEnable
=
1902 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1903 pipe
.InstructionCacheInvalidateEnable
=
1904 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1906 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1908 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1909 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1910 * “Write Timestamp”.
1912 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1913 pipe
.PostSyncOperation
= WriteImmediateData
;
1915 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
1919 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1922 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1925 void genX(CmdPipelineBarrier
)(
1926 VkCommandBuffer commandBuffer
,
1927 VkPipelineStageFlags srcStageMask
,
1928 VkPipelineStageFlags destStageMask
,
1930 uint32_t memoryBarrierCount
,
1931 const VkMemoryBarrier
* pMemoryBarriers
,
1932 uint32_t bufferMemoryBarrierCount
,
1933 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1934 uint32_t imageMemoryBarrierCount
,
1935 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1937 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1939 /* XXX: Right now, we're really dumb and just flush whatever categories
1940 * the app asks for. One of these days we may make this a bit better
1941 * but right now that's all the hardware allows for in most areas.
1943 VkAccessFlags src_flags
= 0;
1944 VkAccessFlags dst_flags
= 0;
1946 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1947 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1948 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1951 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1952 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1953 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1956 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1957 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1958 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1959 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1960 const VkImageSubresourceRange
*range
=
1961 &pImageMemoryBarriers
[i
].subresourceRange
;
1963 uint32_t base_layer
, layer_count
;
1964 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1966 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1968 base_layer
= range
->baseArrayLayer
;
1969 layer_count
= anv_get_layerCount(image
, range
);
1972 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1973 transition_depth_buffer(cmd_buffer
, image
,
1974 pImageMemoryBarriers
[i
].oldLayout
,
1975 pImageMemoryBarriers
[i
].newLayout
);
1978 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1979 transition_stencil_buffer(cmd_buffer
, image
,
1980 range
->baseMipLevel
,
1981 anv_get_levelCount(image
, range
),
1982 base_layer
, layer_count
,
1983 pImageMemoryBarriers
[i
].oldLayout
,
1984 pImageMemoryBarriers
[i
].newLayout
);
1987 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1988 VkImageAspectFlags color_aspects
=
1989 anv_image_expand_aspects(image
, range
->aspectMask
);
1990 uint32_t aspect_bit
;
1991 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1992 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1993 range
->baseMipLevel
,
1994 anv_get_levelCount(image
, range
),
1995 base_layer
, layer_count
,
1996 pImageMemoryBarriers
[i
].oldLayout
,
1997 pImageMemoryBarriers
[i
].newLayout
);
2002 cmd_buffer
->state
.pending_pipe_bits
|=
2003 anv_pipe_flush_bits_for_access_flags(src_flags
) |
2004 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
2008 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
2010 VkShaderStageFlags stages
=
2011 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
2013 /* In order to avoid thrash, we assume that vertex and fragment stages
2014 * always exist. In the rare case where one is missing *and* the other
2015 * uses push concstants, this may be suboptimal. However, avoiding stalls
2016 * seems more important.
2018 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
2020 if (stages
== cmd_buffer
->state
.push_constant_stages
)
2024 const unsigned push_constant_kb
= 32;
2025 #elif GEN_IS_HASWELL
2026 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2028 const unsigned push_constant_kb
= 16;
2031 const unsigned num_stages
=
2032 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2033 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2035 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2036 * units of 2KB. Incidentally, these are the same platforms that have
2037 * 32KB worth of push constant space.
2039 if (push_constant_kb
== 32)
2040 size_per_stage
&= ~1u;
2042 uint32_t kb_used
= 0;
2043 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2044 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2045 anv_batch_emit(&cmd_buffer
->batch
,
2046 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2047 alloc
._3DCommandSubOpcode
= 18 + i
;
2048 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2049 alloc
.ConstantBufferSize
= push_size
;
2051 kb_used
+= push_size
;
2054 anv_batch_emit(&cmd_buffer
->batch
,
2055 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2056 alloc
.ConstantBufferOffset
= kb_used
;
2057 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2060 cmd_buffer
->state
.push_constant_stages
= stages
;
2062 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2064 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2065 * the next 3DPRIMITIVE command after programming the
2066 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2068 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2069 * pipeline setup, we need to dirty push constants.
2071 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2074 static const struct anv_descriptor
*
2075 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2076 const struct anv_pipeline_binding
*binding
)
2078 assert(binding
->set
< MAX_SETS
);
2079 const struct anv_descriptor_set
*set
=
2080 pipe_state
->descriptors
[binding
->set
];
2081 const uint32_t offset
=
2082 set
->layout
->binding
[binding
->binding
].descriptor_index
;
2083 return &set
->descriptors
[offset
+ binding
->index
];
2087 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2088 const struct anv_pipeline_binding
*binding
)
2090 assert(binding
->set
< MAX_SETS
);
2091 const struct anv_descriptor_set
*set
=
2092 pipe_state
->descriptors
[binding
->set
];
2094 uint32_t dynamic_offset_idx
=
2095 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
2096 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
2099 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
2102 static struct anv_address
2103 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2104 struct anv_descriptor_set
*set
)
2107 /* This is a normal descriptor set */
2108 return (struct anv_address
) {
2109 .bo
= set
->pool
->bo
,
2110 .offset
= set
->desc_mem
.offset
,
2113 /* This is a push descriptor set. We have to flag it as used on the GPU
2114 * so that the next time we push descriptors, we grab a new memory.
2116 struct anv_push_descriptor_set
*push_set
=
2117 (struct anv_push_descriptor_set
*)set
;
2118 push_set
->set_used_on_gpu
= true;
2120 return (struct anv_address
) {
2121 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2122 .offset
= set
->desc_mem
.offset
,
2128 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2129 gl_shader_stage stage
,
2130 struct anv_state
*bt_state
)
2132 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2133 struct anv_cmd_pipeline_state
*pipe_state
;
2134 struct anv_pipeline
*pipeline
;
2135 uint32_t state_offset
;
2138 case MESA_SHADER_COMPUTE
:
2139 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2142 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2145 pipeline
= pipe_state
->pipeline
;
2147 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2148 *bt_state
= (struct anv_state
) { 0, };
2152 struct anv_shader_bin
*bin
= pipeline
->shaders
[stage
];
2153 struct anv_pipeline_bind_map
*map
= &bin
->bind_map
;
2154 if (map
->surface_count
== 0) {
2155 *bt_state
= (struct anv_state
) { 0, };
2159 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2162 uint32_t *bt_map
= bt_state
->map
;
2164 if (bt_state
->map
== NULL
)
2165 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2167 /* We only need to emit relocs if we're not using softpin. If we are using
2168 * softpin then we always keep all user-allocated memory objects resident.
2170 const bool need_client_mem_relocs
=
2171 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
;
2173 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2174 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2176 struct anv_state surface_state
;
2178 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2179 /* Color attachment binding */
2180 assert(stage
== MESA_SHADER_FRAGMENT
);
2181 assert(binding
->binding
== 0);
2182 if (binding
->index
< subpass
->color_count
) {
2183 const unsigned att
=
2184 subpass
->color_attachments
[binding
->index
].attachment
;
2186 /* From the Vulkan 1.0.46 spec:
2188 * "If any color or depth/stencil attachments are
2189 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2192 if (att
== VK_ATTACHMENT_UNUSED
) {
2193 surface_state
= cmd_buffer
->state
.null_surface_state
;
2195 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2198 surface_state
= cmd_buffer
->state
.null_surface_state
;
2201 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2203 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2204 struct anv_state surface_state
=
2205 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2207 struct anv_address constant_data
= {
2208 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2209 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2211 unsigned constant_data_size
=
2212 pipeline
->shaders
[stage
]->constant_data_size
;
2214 const enum isl_format format
=
2215 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2216 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2217 surface_state
, format
,
2218 constant_data
, constant_data_size
, 1);
2220 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2221 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2223 } else if (binding
->set
== ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
) {
2224 /* This is always the first binding for compute shaders */
2225 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2226 if (!get_cs_prog_data(pipeline
)->uses_num_work_groups
)
2229 struct anv_state surface_state
=
2230 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2232 const enum isl_format format
=
2233 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2234 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2236 cmd_buffer
->state
.compute
.num_workgroups
,
2238 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2239 if (need_client_mem_relocs
) {
2240 add_surface_reloc(cmd_buffer
, surface_state
,
2241 cmd_buffer
->state
.compute
.num_workgroups
);
2244 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2245 /* This is a descriptor set buffer so the set index is actually
2246 * given by binding->binding. (Yes, that's confusing.)
2248 struct anv_descriptor_set
*set
=
2249 pipe_state
->descriptors
[binding
->binding
];
2250 assert(set
->desc_mem
.alloc_size
);
2251 assert(set
->desc_surface_state
.alloc_size
);
2252 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2253 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2254 anv_descriptor_set_address(cmd_buffer
, set
));
2258 const struct anv_descriptor
*desc
=
2259 anv_descriptor_for_binding(pipe_state
, binding
);
2261 switch (desc
->type
) {
2262 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2263 /* Nothing for us to do here */
2266 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2267 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2268 struct anv_surface_state sstate
=
2269 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2270 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2271 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2272 surface_state
= sstate
.state
;
2273 assert(surface_state
.alloc_size
);
2274 if (need_client_mem_relocs
)
2275 add_surface_state_relocs(cmd_buffer
, sstate
);
2278 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2279 assert(stage
== MESA_SHADER_FRAGMENT
);
2280 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2281 /* For depth and stencil input attachments, we treat it like any
2282 * old texture that a user may have bound.
2284 struct anv_surface_state sstate
=
2285 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2286 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2287 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2288 surface_state
= sstate
.state
;
2289 assert(surface_state
.alloc_size
);
2290 if (need_client_mem_relocs
)
2291 add_surface_state_relocs(cmd_buffer
, sstate
);
2293 /* For color input attachments, we create the surface state at
2294 * vkBeginRenderPass time so that we can include aux and clear
2295 * color information.
2297 assert(binding
->input_attachment_index
< subpass
->input_count
);
2298 const unsigned subpass_att
= binding
->input_attachment_index
;
2299 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2300 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2304 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2305 struct anv_surface_state sstate
= (binding
->write_only
)
2306 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2307 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2308 surface_state
= sstate
.state
;
2309 assert(surface_state
.alloc_size
);
2310 if (need_client_mem_relocs
)
2311 add_surface_state_relocs(cmd_buffer
, sstate
);
2315 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2316 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2317 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2318 surface_state
= desc
->buffer_view
->surface_state
;
2319 assert(surface_state
.alloc_size
);
2320 if (need_client_mem_relocs
) {
2321 add_surface_reloc(cmd_buffer
, surface_state
,
2322 desc
->buffer_view
->address
);
2326 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2327 /* If the shader never does any UBO pulls (this is a fairly common
2328 * case) then we don't need to fill out those binding table entries.
2329 * The real cost savings here is that we don't have to build the
2330 * surface state for them which is surprisingly expensive when it's
2333 if (!bin
->prog_data
->has_ubo_pull
)
2337 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2338 /* Compute the offset within the buffer */
2339 uint32_t dynamic_offset
=
2340 dynamic_offset_for_binding(pipe_state
, binding
);
2341 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2342 /* Clamp to the buffer size */
2343 offset
= MIN2(offset
, desc
->buffer
->size
);
2344 /* Clamp the range to the buffer size */
2345 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2347 struct anv_address address
=
2348 anv_address_add(desc
->buffer
->address
, offset
);
2351 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2352 enum isl_format format
=
2353 anv_isl_format_for_descriptor_type(desc
->type
);
2355 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2356 format
, address
, range
, 1);
2357 if (need_client_mem_relocs
)
2358 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2362 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2363 surface_state
= (binding
->write_only
)
2364 ? desc
->buffer_view
->writeonly_storage_surface_state
2365 : desc
->buffer_view
->storage_surface_state
;
2366 assert(surface_state
.alloc_size
);
2367 if (need_client_mem_relocs
) {
2368 add_surface_reloc(cmd_buffer
, surface_state
,
2369 desc
->buffer_view
->address
);
2374 assert(!"Invalid descriptor type");
2378 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2385 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2386 gl_shader_stage stage
,
2387 struct anv_state
*state
)
2389 struct anv_cmd_pipeline_state
*pipe_state
=
2390 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2391 &cmd_buffer
->state
.gfx
.base
;
2392 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2394 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2395 *state
= (struct anv_state
) { 0, };
2399 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2400 if (map
->sampler_count
== 0) {
2401 *state
= (struct anv_state
) { 0, };
2405 uint32_t size
= map
->sampler_count
* 16;
2406 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2408 if (state
->map
== NULL
)
2409 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2411 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2412 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2413 const struct anv_descriptor
*desc
=
2414 anv_descriptor_for_binding(pipe_state
, binding
);
2416 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2417 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2420 struct anv_sampler
*sampler
= desc
->sampler
;
2422 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2423 * happens to be zero.
2425 if (sampler
== NULL
)
2428 memcpy(state
->map
+ (s
* 16),
2429 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2436 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2438 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2440 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2441 pipeline
->active_stages
;
2443 VkResult result
= VK_SUCCESS
;
2444 anv_foreach_stage(s
, dirty
) {
2445 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2446 if (result
!= VK_SUCCESS
)
2448 result
= emit_binding_table(cmd_buffer
, s
,
2449 &cmd_buffer
->state
.binding_tables
[s
]);
2450 if (result
!= VK_SUCCESS
)
2454 if (result
!= VK_SUCCESS
) {
2455 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2457 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2458 if (result
!= VK_SUCCESS
)
2461 /* Re-emit state base addresses so we get the new surface state base
2462 * address before we start emitting binding tables etc.
2464 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2466 /* Re-emit all active binding tables */
2467 dirty
|= pipeline
->active_stages
;
2468 anv_foreach_stage(s
, dirty
) {
2469 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2470 if (result
!= VK_SUCCESS
) {
2471 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2474 result
= emit_binding_table(cmd_buffer
, s
,
2475 &cmd_buffer
->state
.binding_tables
[s
]);
2476 if (result
!= VK_SUCCESS
) {
2477 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2483 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2489 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2492 static const uint32_t sampler_state_opcodes
[] = {
2493 [MESA_SHADER_VERTEX
] = 43,
2494 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2495 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2496 [MESA_SHADER_GEOMETRY
] = 46,
2497 [MESA_SHADER_FRAGMENT
] = 47,
2498 [MESA_SHADER_COMPUTE
] = 0,
2501 static const uint32_t binding_table_opcodes
[] = {
2502 [MESA_SHADER_VERTEX
] = 38,
2503 [MESA_SHADER_TESS_CTRL
] = 39,
2504 [MESA_SHADER_TESS_EVAL
] = 40,
2505 [MESA_SHADER_GEOMETRY
] = 41,
2506 [MESA_SHADER_FRAGMENT
] = 42,
2507 [MESA_SHADER_COMPUTE
] = 0,
2510 anv_foreach_stage(s
, stages
) {
2511 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2512 assert(binding_table_opcodes
[s
] > 0);
2514 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2515 anv_batch_emit(&cmd_buffer
->batch
,
2516 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2517 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2518 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2522 /* Always emit binding table pointers if we're asked to, since on SKL
2523 * this is what flushes push constants. */
2524 anv_batch_emit(&cmd_buffer
->batch
,
2525 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2526 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2527 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2533 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2534 VkShaderStageFlags dirty_stages
)
2536 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2537 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2539 static const uint32_t push_constant_opcodes
[] = {
2540 [MESA_SHADER_VERTEX
] = 21,
2541 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2542 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2543 [MESA_SHADER_GEOMETRY
] = 22,
2544 [MESA_SHADER_FRAGMENT
] = 23,
2545 [MESA_SHADER_COMPUTE
] = 0,
2548 VkShaderStageFlags flushed
= 0;
2550 anv_foreach_stage(stage
, dirty_stages
) {
2551 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2552 assert(push_constant_opcodes
[stage
] > 0);
2554 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2555 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2557 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2558 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2559 const struct brw_stage_prog_data
*prog_data
=
2560 pipeline
->shaders
[stage
]->prog_data
;
2561 const struct anv_pipeline_bind_map
*bind_map
=
2562 &pipeline
->shaders
[stage
]->bind_map
;
2564 /* The Skylake PRM contains the following restriction:
2566 * "The driver must ensure The following case does not occur
2567 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2568 * buffer 3 read length equal to zero committed followed by a
2569 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2572 * To avoid this, we program the buffers in the highest slots.
2573 * This way, slot 0 is only used if slot 3 is also used.
2577 for (int i
= 3; i
>= 0; i
--) {
2578 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2579 if (range
->length
== 0)
2582 const unsigned surface
=
2583 prog_data
->binding_table
.ubo_start
+ range
->block
;
2585 assert(surface
<= bind_map
->surface_count
);
2586 const struct anv_pipeline_binding
*binding
=
2587 &bind_map
->surface_to_descriptor
[surface
];
2589 struct anv_address read_addr
;
2591 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2592 struct anv_address constant_data
= {
2593 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2594 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2596 unsigned constant_data_size
=
2597 pipeline
->shaders
[stage
]->constant_data_size
;
2599 read_len
= MIN2(range
->length
,
2600 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2601 read_addr
= anv_address_add(constant_data
,
2603 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2604 /* This is a descriptor set buffer so the set index is
2605 * actually given by binding->binding. (Yes, that's
2608 struct anv_descriptor_set
*set
=
2609 gfx_state
->base
.descriptors
[binding
->binding
];
2610 struct anv_address desc_buffer_addr
=
2611 anv_descriptor_set_address(cmd_buffer
, set
);
2612 const unsigned desc_buffer_size
= set
->desc_mem
.alloc_size
;
2614 read_len
= MIN2(range
->length
,
2615 DIV_ROUND_UP(desc_buffer_size
, 32) - range
->start
);
2616 read_addr
= anv_address_add(desc_buffer_addr
,
2619 const struct anv_descriptor
*desc
=
2620 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2622 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2623 read_len
= MIN2(range
->length
,
2624 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2625 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2628 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2630 uint32_t dynamic_offset
=
2631 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2632 uint32_t buf_offset
=
2633 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2634 uint32_t buf_range
=
2635 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2637 read_len
= MIN2(range
->length
,
2638 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2639 read_addr
= anv_address_add(desc
->buffer
->address
,
2640 buf_offset
+ range
->start
* 32);
2645 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2646 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2651 struct anv_state state
=
2652 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2654 if (state
.alloc_size
> 0) {
2655 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2656 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2657 .offset
= state
.offset
,
2659 c
.ConstantBody
.ReadLength
[n
] =
2660 DIV_ROUND_UP(state
.alloc_size
, 32);
2663 /* For Ivy Bridge, the push constants packets have a different
2664 * rule that would require us to iterate in the other direction
2665 * and possibly mess around with dynamic state base address.
2666 * Don't bother; just emit regular push constants at n = 0.
2668 struct anv_state state
=
2669 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2671 if (state
.alloc_size
> 0) {
2672 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2673 c
.ConstantBody
.ReadLength
[0] =
2674 DIV_ROUND_UP(state
.alloc_size
, 32);
2680 flushed
|= mesa_to_vk_shader_stage(stage
);
2683 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2688 genX(cmd_buffer_aux_map_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2690 void *aux_map_ctx
= cmd_buffer
->device
->aux_map_ctx
;
2693 uint32_t aux_map_state_num
= gen_aux_map_get_state_num(aux_map_ctx
);
2694 if (cmd_buffer
->state
.last_aux_map_state
!= aux_map_state_num
) {
2695 /* If the aux-map state number increased, then we need to rewrite the
2696 * register. Rewriting the register is used to both set the aux-map
2697 * translation table address, and also to invalidate any previously
2698 * cached translations.
2700 uint64_t base_addr
= gen_aux_map_get_base(aux_map_ctx
);
2701 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2702 lri
.RegisterOffset
= GENX(GFX_AUX_TABLE_BASE_ADDR_num
);
2703 lri
.DataDWord
= base_addr
& 0xffffffff;
2705 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2706 lri
.RegisterOffset
= GENX(GFX_AUX_TABLE_BASE_ADDR_num
) + 4;
2707 lri
.DataDWord
= base_addr
>> 32;
2709 cmd_buffer
->state
.last_aux_map_state
= aux_map_state_num
;
2715 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2717 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2720 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2721 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2722 vb_emit
|= pipeline
->vb_used
;
2724 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2726 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2728 genX(cmd_buffer_emit_hashing_mode
)(cmd_buffer
, UINT_MAX
, UINT_MAX
, 1);
2730 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2733 genX(cmd_buffer_aux_map_state
)(cmd_buffer
);
2737 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2738 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2740 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2741 GENX(3DSTATE_VERTEX_BUFFERS
));
2743 for_each_bit(vb
, vb_emit
) {
2744 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2745 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2747 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2748 .VertexBufferIndex
= vb
,
2750 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2752 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2753 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2756 .AddressModifyEnable
= true,
2757 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2758 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2761 .BufferSize
= buffer
->size
- offset
2763 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2767 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2772 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2775 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2776 /* We don't need any per-buffer dirty tracking because you're not
2777 * allowed to bind different XFB buffers while XFB is enabled.
2779 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2780 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2781 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2783 sob
.SOBufferIndex
= idx
;
2785 sob
._3DCommandOpcode
= 0;
2786 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ idx
;
2789 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2790 sob
.SOBufferEnable
= true;
2791 sob
.MOCS
= cmd_buffer
->device
->default_mocs
,
2792 sob
.StreamOffsetWriteEnable
= false;
2793 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2795 /* Size is in DWords - 1 */
2796 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2801 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2803 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2807 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2808 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2810 /* The exact descriptor layout is pulled from the pipeline, so we need
2811 * to re-emit binding tables on every pipeline change.
2813 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2815 /* If the pipeline changed, we may need to re-allocate push constant
2818 cmd_buffer_alloc_push_constants(cmd_buffer
);
2822 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2823 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2824 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2826 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2827 * stall needs to be sent just prior to any 3DSTATE_VS,
2828 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2829 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2830 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2831 * PIPE_CONTROL needs to be sent before any combination of VS
2832 * associated 3DSTATE."
2834 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2835 pc
.DepthStallEnable
= true;
2836 pc
.PostSyncOperation
= WriteImmediateData
;
2838 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
2843 /* Render targets live in the same binding table as fragment descriptors */
2844 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2845 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2847 /* We emit the binding tables and sampler tables first, then emit push
2848 * constants and then finally emit binding table and sampler table
2849 * pointers. It has to happen in this order, since emitting the binding
2850 * tables may change the push constants (in case of storage images). After
2851 * emitting push constants, on SKL+ we have to emit the corresponding
2852 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2855 if (cmd_buffer
->state
.descriptors_dirty
)
2856 dirty
= flush_descriptor_sets(cmd_buffer
);
2858 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2859 /* Because we're pushing UBOs, we have to push whenever either
2860 * descriptors or push constants is dirty.
2862 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2863 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2864 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2868 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2870 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2871 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2873 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2874 ANV_CMD_DIRTY_PIPELINE
)) {
2875 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2876 pipeline
->depth_clamp_enable
);
2879 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2880 ANV_CMD_DIRTY_RENDER_TARGETS
))
2881 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2883 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2885 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2889 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2890 struct anv_address addr
,
2891 uint32_t size
, uint32_t index
)
2893 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2894 GENX(3DSTATE_VERTEX_BUFFERS
));
2896 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2897 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2898 .VertexBufferIndex
= index
,
2899 .AddressModifyEnable
= true,
2901 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2903 .BufferStartingAddress
= addr
,
2906 .BufferStartingAddress
= addr
,
2907 .EndAddress
= anv_address_add(addr
, size
),
2913 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2914 struct anv_address addr
)
2916 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2920 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2921 uint32_t base_vertex
, uint32_t base_instance
)
2923 struct anv_state id_state
=
2924 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2926 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2927 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2929 struct anv_address addr
= {
2930 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2931 .offset
= id_state
.offset
,
2934 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2938 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2940 struct anv_state state
=
2941 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2943 ((uint32_t *)state
.map
)[0] = draw_index
;
2945 struct anv_address addr
= {
2946 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2947 .offset
= state
.offset
,
2950 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2954 VkCommandBuffer commandBuffer
,
2955 uint32_t vertexCount
,
2956 uint32_t instanceCount
,
2957 uint32_t firstVertex
,
2958 uint32_t firstInstance
)
2960 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2961 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2962 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2964 if (anv_batch_has_error(&cmd_buffer
->batch
))
2967 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2969 if (cmd_buffer
->state
.conditional_render_enabled
)
2970 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2972 if (vs_prog_data
->uses_firstvertex
||
2973 vs_prog_data
->uses_baseinstance
)
2974 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2975 if (vs_prog_data
->uses_drawid
)
2976 emit_draw_index(cmd_buffer
, 0);
2978 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2979 * different views. We need to multiply instanceCount by the view count.
2981 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2983 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2984 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2985 prim
.VertexAccessType
= SEQUENTIAL
;
2986 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2987 prim
.VertexCountPerInstance
= vertexCount
;
2988 prim
.StartVertexLocation
= firstVertex
;
2989 prim
.InstanceCount
= instanceCount
;
2990 prim
.StartInstanceLocation
= firstInstance
;
2991 prim
.BaseVertexLocation
= 0;
2995 void genX(CmdDrawIndexed
)(
2996 VkCommandBuffer commandBuffer
,
2997 uint32_t indexCount
,
2998 uint32_t instanceCount
,
2999 uint32_t firstIndex
,
3000 int32_t vertexOffset
,
3001 uint32_t firstInstance
)
3003 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3004 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3005 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3007 if (anv_batch_has_error(&cmd_buffer
->batch
))
3010 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3012 if (cmd_buffer
->state
.conditional_render_enabled
)
3013 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3015 if (vs_prog_data
->uses_firstvertex
||
3016 vs_prog_data
->uses_baseinstance
)
3017 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
3018 if (vs_prog_data
->uses_drawid
)
3019 emit_draw_index(cmd_buffer
, 0);
3021 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3022 * different views. We need to multiply instanceCount by the view count.
3024 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3026 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3027 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3028 prim
.VertexAccessType
= RANDOM
;
3029 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3030 prim
.VertexCountPerInstance
= indexCount
;
3031 prim
.StartVertexLocation
= firstIndex
;
3032 prim
.InstanceCount
= instanceCount
;
3033 prim
.StartInstanceLocation
= firstInstance
;
3034 prim
.BaseVertexLocation
= vertexOffset
;
3038 /* Auto-Draw / Indirect Registers */
3039 #define GEN7_3DPRIM_END_OFFSET 0x2420
3040 #define GEN7_3DPRIM_START_VERTEX 0x2430
3041 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3042 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3043 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3044 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3046 void genX(CmdDrawIndirectByteCountEXT
)(
3047 VkCommandBuffer commandBuffer
,
3048 uint32_t instanceCount
,
3049 uint32_t firstInstance
,
3050 VkBuffer counterBuffer
,
3051 VkDeviceSize counterBufferOffset
,
3052 uint32_t counterOffset
,
3053 uint32_t vertexStride
)
3055 #if GEN_IS_HASWELL || GEN_GEN >= 8
3056 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3057 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3058 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3059 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3061 /* firstVertex is always zero for this draw function */
3062 const uint32_t firstVertex
= 0;
3064 if (anv_batch_has_error(&cmd_buffer
->batch
))
3067 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3069 if (vs_prog_data
->uses_firstvertex
||
3070 vs_prog_data
->uses_baseinstance
)
3071 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3072 if (vs_prog_data
->uses_drawid
)
3073 emit_draw_index(cmd_buffer
, 0);
3075 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3076 * different views. We need to multiply instanceCount by the view count.
3078 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3080 struct gen_mi_builder b
;
3081 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3082 struct gen_mi_value count
=
3083 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3084 counterBufferOffset
));
3086 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3087 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3088 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3090 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3091 gen_mi_imm(firstVertex
));
3092 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3093 gen_mi_imm(instanceCount
));
3094 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3095 gen_mi_imm(firstInstance
));
3096 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3098 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3099 prim
.IndirectParameterEnable
= true;
3100 prim
.VertexAccessType
= SEQUENTIAL
;
3101 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3103 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3107 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3108 struct anv_address addr
,
3111 struct gen_mi_builder b
;
3112 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3114 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3115 gen_mi_mem32(anv_address_add(addr
, 0)));
3117 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3118 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3119 if (view_count
> 1) {
3120 #if GEN_IS_HASWELL || GEN_GEN >= 8
3121 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3123 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3124 "MI_MATH is not supported on Ivy Bridge");
3127 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3129 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3130 gen_mi_mem32(anv_address_add(addr
, 8)));
3133 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3134 gen_mi_mem32(anv_address_add(addr
, 12)));
3135 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3136 gen_mi_mem32(anv_address_add(addr
, 16)));
3138 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3139 gen_mi_mem32(anv_address_add(addr
, 12)));
3140 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3144 void genX(CmdDrawIndirect
)(
3145 VkCommandBuffer commandBuffer
,
3147 VkDeviceSize offset
,
3151 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3152 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3153 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3154 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3156 if (anv_batch_has_error(&cmd_buffer
->batch
))
3159 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3161 if (cmd_buffer
->state
.conditional_render_enabled
)
3162 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3164 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3165 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3167 if (vs_prog_data
->uses_firstvertex
||
3168 vs_prog_data
->uses_baseinstance
)
3169 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3170 if (vs_prog_data
->uses_drawid
)
3171 emit_draw_index(cmd_buffer
, i
);
3173 load_indirect_parameters(cmd_buffer
, draw
, false);
3175 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3176 prim
.IndirectParameterEnable
= true;
3177 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3178 prim
.VertexAccessType
= SEQUENTIAL
;
3179 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3186 void genX(CmdDrawIndexedIndirect
)(
3187 VkCommandBuffer commandBuffer
,
3189 VkDeviceSize offset
,
3193 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3194 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3195 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3196 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3198 if (anv_batch_has_error(&cmd_buffer
->batch
))
3201 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3203 if (cmd_buffer
->state
.conditional_render_enabled
)
3204 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3206 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3207 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3209 /* TODO: We need to stomp base vertex to 0 somehow */
3210 if (vs_prog_data
->uses_firstvertex
||
3211 vs_prog_data
->uses_baseinstance
)
3212 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3213 if (vs_prog_data
->uses_drawid
)
3214 emit_draw_index(cmd_buffer
, i
);
3216 load_indirect_parameters(cmd_buffer
, draw
, true);
3218 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3219 prim
.IndirectParameterEnable
= true;
3220 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3221 prim
.VertexAccessType
= RANDOM
;
3222 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3229 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3232 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3233 struct anv_address count_address
,
3234 const bool conditional_render_enabled
)
3236 struct gen_mi_builder b
;
3237 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3239 if (conditional_render_enabled
) {
3240 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3241 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3242 gen_mi_mem32(count_address
));
3245 /* Upload the current draw count from the draw parameters buffer to
3246 * MI_PREDICATE_SRC0.
3248 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3249 gen_mi_mem32(count_address
));
3251 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3256 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3257 uint32_t draw_index
)
3259 struct gen_mi_builder b
;
3260 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3262 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3263 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3265 if (draw_index
== 0) {
3266 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3267 mip
.LoadOperation
= LOAD_LOADINV
;
3268 mip
.CombineOperation
= COMBINE_SET
;
3269 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3272 /* While draw_index < draw_count the predicate's result will be
3273 * (draw_index == draw_count) ^ TRUE = TRUE
3274 * When draw_index == draw_count the result is
3275 * (TRUE) ^ TRUE = FALSE
3276 * After this all results will be:
3277 * (FALSE) ^ FALSE = FALSE
3279 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3280 mip
.LoadOperation
= LOAD_LOAD
;
3281 mip
.CombineOperation
= COMBINE_XOR
;
3282 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3287 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3289 emit_draw_count_predicate_with_conditional_render(
3290 struct anv_cmd_buffer
*cmd_buffer
,
3291 uint32_t draw_index
)
3293 struct gen_mi_builder b
;
3294 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3296 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3297 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3298 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3301 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3303 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3304 * so we emit MI_PREDICATE to set it.
3307 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3308 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3310 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3311 mip
.LoadOperation
= LOAD_LOADINV
;
3312 mip
.CombineOperation
= COMBINE_SET
;
3313 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3319 void genX(CmdDrawIndirectCountKHR
)(
3320 VkCommandBuffer commandBuffer
,
3322 VkDeviceSize offset
,
3323 VkBuffer _countBuffer
,
3324 VkDeviceSize countBufferOffset
,
3325 uint32_t maxDrawCount
,
3328 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3329 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3330 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3331 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3332 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3333 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3335 if (anv_batch_has_error(&cmd_buffer
->batch
))
3338 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3340 struct anv_address count_address
=
3341 anv_address_add(count_buffer
->address
, countBufferOffset
);
3343 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3344 cmd_state
->conditional_render_enabled
);
3346 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3347 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3349 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3350 if (cmd_state
->conditional_render_enabled
) {
3351 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3353 emit_draw_count_predicate(cmd_buffer
, i
);
3356 emit_draw_count_predicate(cmd_buffer
, i
);
3359 if (vs_prog_data
->uses_firstvertex
||
3360 vs_prog_data
->uses_baseinstance
)
3361 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3362 if (vs_prog_data
->uses_drawid
)
3363 emit_draw_index(cmd_buffer
, i
);
3365 load_indirect_parameters(cmd_buffer
, draw
, false);
3367 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3368 prim
.IndirectParameterEnable
= true;
3369 prim
.PredicateEnable
= true;
3370 prim
.VertexAccessType
= SEQUENTIAL
;
3371 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3378 void genX(CmdDrawIndexedIndirectCountKHR
)(
3379 VkCommandBuffer commandBuffer
,
3381 VkDeviceSize offset
,
3382 VkBuffer _countBuffer
,
3383 VkDeviceSize countBufferOffset
,
3384 uint32_t maxDrawCount
,
3387 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3388 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3389 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3390 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3391 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3392 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3394 if (anv_batch_has_error(&cmd_buffer
->batch
))
3397 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3399 struct anv_address count_address
=
3400 anv_address_add(count_buffer
->address
, countBufferOffset
);
3402 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3403 cmd_state
->conditional_render_enabled
);
3405 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3406 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3408 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3409 if (cmd_state
->conditional_render_enabled
) {
3410 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3412 emit_draw_count_predicate(cmd_buffer
, i
);
3415 emit_draw_count_predicate(cmd_buffer
, i
);
3418 /* TODO: We need to stomp base vertex to 0 somehow */
3419 if (vs_prog_data
->uses_firstvertex
||
3420 vs_prog_data
->uses_baseinstance
)
3421 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3422 if (vs_prog_data
->uses_drawid
)
3423 emit_draw_index(cmd_buffer
, i
);
3425 load_indirect_parameters(cmd_buffer
, draw
, true);
3427 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3428 prim
.IndirectParameterEnable
= true;
3429 prim
.PredicateEnable
= true;
3430 prim
.VertexAccessType
= RANDOM
;
3431 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3438 void genX(CmdBeginTransformFeedbackEXT
)(
3439 VkCommandBuffer commandBuffer
,
3440 uint32_t firstCounterBuffer
,
3441 uint32_t counterBufferCount
,
3442 const VkBuffer
* pCounterBuffers
,
3443 const VkDeviceSize
* pCounterBufferOffsets
)
3445 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3447 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3448 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3449 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3451 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3453 * "Ssoftware must ensure that no HW stream output operations can be in
3454 * process or otherwise pending at the point that the MI_LOAD/STORE
3455 * commands are processed. This will likely require a pipeline flush."
3457 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3458 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3460 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3461 /* If we have a counter buffer, this is a resume so we need to load the
3462 * value into the streamout offset register. Otherwise, this is a begin
3463 * and we need to reset it to zero.
3465 if (pCounterBuffers
&&
3466 idx
>= firstCounterBuffer
&&
3467 idx
- firstCounterBuffer
< counterBufferCount
&&
3468 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3469 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3470 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3471 uint64_t offset
= pCounterBufferOffsets
?
3472 pCounterBufferOffsets
[cb_idx
] : 0;
3474 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3475 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3476 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3480 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3481 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3487 cmd_buffer
->state
.xfb_enabled
= true;
3488 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3491 void genX(CmdEndTransformFeedbackEXT
)(
3492 VkCommandBuffer commandBuffer
,
3493 uint32_t firstCounterBuffer
,
3494 uint32_t counterBufferCount
,
3495 const VkBuffer
* pCounterBuffers
,
3496 const VkDeviceSize
* pCounterBufferOffsets
)
3498 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3500 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3501 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3502 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3504 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3506 * "Ssoftware must ensure that no HW stream output operations can be in
3507 * process or otherwise pending at the point that the MI_LOAD/STORE
3508 * commands are processed. This will likely require a pipeline flush."
3510 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3511 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3513 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3514 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3516 /* If we have a counter buffer, this is a resume so we need to load the
3517 * value into the streamout offset register. Otherwise, this is a begin
3518 * and we need to reset it to zero.
3520 if (pCounterBuffers
&&
3521 cb_idx
< counterBufferCount
&&
3522 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3523 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3524 uint64_t offset
= pCounterBufferOffsets
?
3525 pCounterBufferOffsets
[cb_idx
] : 0;
3527 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3528 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3530 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3535 cmd_buffer
->state
.xfb_enabled
= false;
3536 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3540 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3542 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3543 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3546 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3547 if (result
!= VK_SUCCESS
) {
3548 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3550 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3551 if (result
!= VK_SUCCESS
)
3554 /* Re-emit state base addresses so we get the new surface state base
3555 * address before we start emitting binding tables etc.
3557 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3559 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3560 if (result
!= VK_SUCCESS
) {
3561 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3566 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3567 if (result
!= VK_SUCCESS
) {
3568 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3572 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3573 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3574 .BindingTablePointer
= surfaces
.offset
,
3575 .SamplerStatePointer
= samplers
.offset
,
3577 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3579 struct anv_state state
=
3580 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3581 pipeline
->interface_descriptor_data
,
3582 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3585 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3586 anv_batch_emit(&cmd_buffer
->batch
,
3587 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3588 mid
.InterfaceDescriptorTotalLength
= size
;
3589 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3596 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3598 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3601 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3603 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3605 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3608 genX(cmd_buffer_aux_map_state
)(cmd_buffer
);
3611 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3612 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3614 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3615 * the only bits that are changed are scoreboard related: Scoreboard
3616 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3617 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3620 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3621 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3623 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3626 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3627 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3628 /* FIXME: figure out descriptors for gen7 */
3629 result
= flush_compute_descriptor_set(cmd_buffer
);
3630 if (result
!= VK_SUCCESS
)
3633 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3636 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3637 struct anv_state push_state
=
3638 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3640 if (push_state
.alloc_size
) {
3641 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3642 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3643 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3647 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3650 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3652 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3658 verify_cmd_parser(const struct anv_device
*device
,
3659 int required_version
,
3660 const char *function
)
3662 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3663 return vk_errorf(device
->instance
, device
->instance
,
3664 VK_ERROR_FEATURE_NOT_PRESENT
,
3665 "cmd parser version %d is required for %s",
3666 required_version
, function
);
3675 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3676 uint32_t baseGroupX
,
3677 uint32_t baseGroupY
,
3678 uint32_t baseGroupZ
)
3680 if (anv_batch_has_error(&cmd_buffer
->batch
))
3683 struct anv_push_constants
*push
=
3684 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3685 if (push
->base_work_group_id
[0] != baseGroupX
||
3686 push
->base_work_group_id
[1] != baseGroupY
||
3687 push
->base_work_group_id
[2] != baseGroupZ
) {
3688 push
->base_work_group_id
[0] = baseGroupX
;
3689 push
->base_work_group_id
[1] = baseGroupY
;
3690 push
->base_work_group_id
[2] = baseGroupZ
;
3692 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3696 void genX(CmdDispatch
)(
3697 VkCommandBuffer commandBuffer
,
3702 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3705 void genX(CmdDispatchBase
)(
3706 VkCommandBuffer commandBuffer
,
3707 uint32_t baseGroupX
,
3708 uint32_t baseGroupY
,
3709 uint32_t baseGroupZ
,
3710 uint32_t groupCountX
,
3711 uint32_t groupCountY
,
3712 uint32_t groupCountZ
)
3714 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3715 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3716 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3718 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3719 baseGroupY
, baseGroupZ
);
3721 if (anv_batch_has_error(&cmd_buffer
->batch
))
3724 if (prog_data
->uses_num_work_groups
) {
3725 struct anv_state state
=
3726 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3727 uint32_t *sizes
= state
.map
;
3728 sizes
[0] = groupCountX
;
3729 sizes
[1] = groupCountY
;
3730 sizes
[2] = groupCountZ
;
3731 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3732 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3733 .offset
= state
.offset
,
3737 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3739 if (cmd_buffer
->state
.conditional_render_enabled
)
3740 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3742 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3743 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3744 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3745 ggw
.ThreadDepthCounterMaximum
= 0;
3746 ggw
.ThreadHeightCounterMaximum
= 0;
3747 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3748 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3749 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3750 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3751 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3752 ggw
.BottomExecutionMask
= 0xffffffff;
3755 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3758 #define GPGPU_DISPATCHDIMX 0x2500
3759 #define GPGPU_DISPATCHDIMY 0x2504
3760 #define GPGPU_DISPATCHDIMZ 0x2508
3762 void genX(CmdDispatchIndirect
)(
3763 VkCommandBuffer commandBuffer
,
3765 VkDeviceSize offset
)
3767 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3768 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3769 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3770 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3771 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3772 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3774 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3777 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3778 * indirect dispatch registers to be written.
3780 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3781 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3785 if (prog_data
->uses_num_work_groups
)
3786 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3788 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3790 struct gen_mi_builder b
;
3791 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3793 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
3794 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
3795 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
3797 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
3798 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
3799 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
3802 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3803 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
3804 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3805 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3806 mip
.LoadOperation
= LOAD_LOAD
;
3807 mip
.CombineOperation
= COMBINE_SET
;
3808 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3811 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3812 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
3813 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3814 mip
.LoadOperation
= LOAD_LOAD
;
3815 mip
.CombineOperation
= COMBINE_OR
;
3816 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3819 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3820 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
3821 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3822 mip
.LoadOperation
= LOAD_LOAD
;
3823 mip
.CombineOperation
= COMBINE_OR
;
3824 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3827 /* predicate = !predicate; */
3828 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3829 mip
.LoadOperation
= LOAD_LOADINV
;
3830 mip
.CombineOperation
= COMBINE_OR
;
3831 mip
.CompareOperation
= COMPARE_FALSE
;
3835 if (cmd_buffer
->state
.conditional_render_enabled
) {
3836 /* predicate &= !(conditional_rendering_predicate == 0); */
3837 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
3838 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
3839 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3840 mip
.LoadOperation
= LOAD_LOADINV
;
3841 mip
.CombineOperation
= COMBINE_AND
;
3842 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3847 #else /* GEN_GEN > 7 */
3848 if (cmd_buffer
->state
.conditional_render_enabled
)
3849 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3852 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3853 ggw
.IndirectParameterEnable
= true;
3854 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3855 cmd_buffer
->state
.conditional_render_enabled
;
3856 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3857 ggw
.ThreadDepthCounterMaximum
= 0;
3858 ggw
.ThreadHeightCounterMaximum
= 0;
3859 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3860 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3861 ggw
.BottomExecutionMask
= 0xffffffff;
3864 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3868 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3871 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3873 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3876 #if GEN_GEN >= 8 && GEN_GEN < 10
3877 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3879 * Software must clear the COLOR_CALC_STATE Valid field in
3880 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3881 * with Pipeline Select set to GPGPU.
3883 * The internal hardware docs recommend the same workaround for Gen9
3886 if (pipeline
== GPGPU
)
3887 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3891 if (pipeline
== _3D
) {
3892 /* There is a mid-object preemption workaround which requires you to
3893 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
3894 * even without preemption, we have issues with geometry flickering when
3895 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
3898 const uint32_t subslices
=
3899 MAX2(cmd_buffer
->device
->instance
->physicalDevice
.subslice_total
, 1);
3900 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
3901 vfe
.MaximumNumberofThreads
=
3902 devinfo
->max_cs_threads
* subslices
- 1;
3903 vfe
.NumberofURBEntries
= 2;
3904 vfe
.URBEntryAllocationSize
= 2;
3909 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3910 * PIPELINE_SELECT [DevBWR+]":
3914 * Software must ensure all the write caches are flushed through a
3915 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3916 * command to invalidate read only caches prior to programming
3917 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3919 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3920 pc
.RenderTargetCacheFlushEnable
= true;
3921 pc
.DepthCacheFlushEnable
= true;
3922 pc
.DCFlushEnable
= true;
3923 pc
.PostSyncOperation
= NoWrite
;
3924 pc
.CommandStreamerStallEnable
= true;
3926 pc
.TileCacheFlushEnable
= true;
3930 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3931 pc
.TextureCacheInvalidationEnable
= true;
3932 pc
.ConstantCacheInvalidationEnable
= true;
3933 pc
.StateCacheInvalidationEnable
= true;
3934 pc
.InstructionCacheInvalidateEnable
= true;
3935 pc
.PostSyncOperation
= NoWrite
;
3937 pc
.TileCacheFlushEnable
= true;
3941 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3945 ps
.PipelineSelection
= pipeline
;
3949 if (devinfo
->is_geminilake
) {
3952 * "This chicken bit works around a hardware issue with barrier logic
3953 * encountered when switching between GPGPU and 3D pipelines. To
3954 * workaround the issue, this mode bit should be set after a pipeline
3958 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3960 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3961 : GLK_BARRIER_MODE_3D_HULL
,
3962 .GLKBarrierModeMask
= 1);
3963 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3967 cmd_buffer
->state
.current_pipeline
= pipeline
;
3971 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3973 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3977 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3979 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3983 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3988 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3990 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3991 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3992 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3993 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3994 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3995 * Depth Flush Bit set, followed by another pipelined depth stall
3996 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3997 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3998 * via a preceding MI_FLUSH)."
4000 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4001 pipe
.DepthStallEnable
= true;
4003 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4004 pipe
.DepthCacheFlushEnable
= true;
4006 pipe
.TileCacheFlushEnable
= true;
4009 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4010 pipe
.DepthStallEnable
= true;
4015 * Update the pixel hashing modes that determine the balancing of PS threads
4016 * across subslices and slices.
4018 * \param width Width bound of the rendering area (already scaled down if \p
4019 * scale is greater than 1).
4020 * \param height Height bound of the rendering area (already scaled down if \p
4021 * scale is greater than 1).
4022 * \param scale The number of framebuffer samples that could potentially be
4023 * affected by an individual channel of the PS thread. This is
4024 * typically one for single-sampled rendering, but for operations
4025 * like CCS resolves and fast clears a single PS invocation may
4026 * update a huge number of pixels, in which case a finer
4027 * balancing is desirable in order to maximally utilize the
4028 * bandwidth available. UINT_MAX can be used as shorthand for
4029 * "finest hashing mode available".
4032 genX(cmd_buffer_emit_hashing_mode
)(struct anv_cmd_buffer
*cmd_buffer
,
4033 unsigned width
, unsigned height
,
4037 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4038 const unsigned slice_hashing
[] = {
4039 /* Because all Gen9 platforms with more than one slice require
4040 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4041 * block is guaranteed to suffer from substantial imbalance, with one
4042 * subslice receiving twice as much work as the other two in the
4045 * The performance impact of that would be particularly severe when
4046 * three-way hashing is also in use for slice balancing (which is the
4047 * case for all Gen9 GT4 platforms), because one of the slices
4048 * receives one every three 16x16 blocks in either direction, which
4049 * is roughly the periodicity of the underlying subslice imbalance
4050 * pattern ("roughly" because in reality the hardware's
4051 * implementation of three-way hashing doesn't do exact modulo 3
4052 * arithmetic, which somewhat decreases the magnitude of this effect
4053 * in practice). This leads to a systematic subslice imbalance
4054 * within that slice regardless of the size of the primitive. The
4055 * 32x32 hashing mode guarantees that the subslice imbalance within a
4056 * single slice hashing block is minimal, largely eliminating this
4060 /* Finest slice hashing mode available. */
4063 const unsigned subslice_hashing
[] = {
4064 /* 16x16 would provide a slight cache locality benefit especially
4065 * visible in the sampler L1 cache efficiency of low-bandwidth
4066 * non-LLC platforms, but it comes at the cost of greater subslice
4067 * imbalance for primitives of dimensions approximately intermediate
4068 * between 16x4 and 16x16.
4071 /* Finest subslice hashing mode available. */
4074 /* Dimensions of the smallest hashing block of a given hashing mode. If
4075 * the rendering area is smaller than this there can't possibly be any
4076 * benefit from switching to this mode, so we optimize out the
4079 const unsigned min_size
[][2] = {
4083 const unsigned idx
= scale
> 1;
4085 if (cmd_buffer
->state
.current_hash_scale
!= scale
&&
4086 (width
> min_size
[idx
][0] || height
> min_size
[idx
][1])) {
4089 anv_pack_struct(>_mode
, GENX(GT_MODE
),
4090 .SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0),
4091 .SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0),
4092 .SubsliceHashing
= subslice_hashing
[idx
],
4093 .SubsliceHashingMask
= -1);
4095 cmd_buffer
->state
.pending_pipe_bits
|=
4096 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
4097 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4099 emit_lri(&cmd_buffer
->batch
, GENX(GT_MODE_num
), gt_mode
);
4101 cmd_buffer
->state
.current_hash_scale
= scale
;
4107 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4109 struct anv_device
*device
= cmd_buffer
->device
;
4110 const struct anv_image_view
*iview
=
4111 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4112 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4114 /* FIXME: Width and Height are wrong */
4116 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4118 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4119 device
->isl_dev
.ds
.size
/ 4);
4123 struct isl_depth_stencil_hiz_emit_info info
= { };
4126 info
.view
= &iview
->planes
[0].isl
;
4128 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4129 uint32_t depth_plane
=
4130 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4131 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4133 info
.depth_surf
= &surface
->isl
;
4135 info
.depth_address
=
4136 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4137 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4138 image
->planes
[depth_plane
].address
.bo
,
4139 image
->planes
[depth_plane
].address
.offset
+
4142 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4145 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4146 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4147 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
4148 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4151 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4152 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4153 image
->planes
[depth_plane
].address
.bo
,
4154 image
->planes
[depth_plane
].address
.offset
+
4155 image
->planes
[depth_plane
].aux_surface
.offset
);
4157 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4161 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4162 uint32_t stencil_plane
=
4163 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4164 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4166 info
.stencil_surf
= &surface
->isl
;
4168 info
.stencil_address
=
4169 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4170 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4171 image
->planes
[stencil_plane
].address
.bo
,
4172 image
->planes
[stencil_plane
].address
.offset
+
4175 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4178 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4180 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
4184 * This ANDs the view mask of the current subpass with the pending clear
4185 * views in the attachment to get the mask of views active in the subpass
4186 * that still need to be cleared.
4188 static inline uint32_t
4189 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4190 const struct anv_attachment_state
*att_state
)
4192 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4196 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4197 const struct anv_attachment_state
*att_state
)
4199 if (!cmd_state
->subpass
->view_mask
)
4202 uint32_t pending_clear_mask
=
4203 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4205 return pending_clear_mask
& 1;
4209 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4212 const uint32_t last_subpass_idx
=
4213 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4214 const struct anv_subpass
*last_subpass
=
4215 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4216 return last_subpass
== cmd_state
->subpass
;
4220 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4221 uint32_t subpass_id
)
4223 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4224 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4225 cmd_state
->subpass
= subpass
;
4227 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4229 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4230 * different views. If the client asks for instancing, we need to use the
4231 * Instance Data Step Rate to ensure that we repeat the client's
4232 * per-instance data once for each view. Since this bit is in
4233 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4237 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4239 /* It is possible to start a render pass with an old pipeline. Because the
4240 * render pass and subpass index are both baked into the pipeline, this is
4241 * highly unlikely. In order to do so, it requires that you have a render
4242 * pass with a single subpass and that you use that render pass twice
4243 * back-to-back and use the same pipeline at the start of the second render
4244 * pass as at the end of the first. In order to avoid unpredictable issues
4245 * with this edge case, we just dirty the pipeline at the start of every
4248 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4250 /* Accumulate any subpass flushes that need to happen before the subpass */
4251 cmd_buffer
->state
.pending_pipe_bits
|=
4252 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4254 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4255 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4257 bool is_multiview
= subpass
->view_mask
!= 0;
4259 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4260 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4261 if (a
== VK_ATTACHMENT_UNUSED
)
4264 assert(a
< cmd_state
->pass
->attachment_count
);
4265 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4267 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4268 const struct anv_image
*image
= iview
->image
;
4270 /* A resolve is necessary before use as an input attachment if the clear
4271 * color or auxiliary buffer usage isn't supported by the sampler.
4273 const bool input_needs_resolve
=
4274 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4275 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4277 VkImageLayout target_layout
, target_stencil_layout
;
4278 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4279 !input_needs_resolve
) {
4280 /* Layout transitions before the final only help to enable sampling
4281 * as an input attachment. If the input attachment supports sampling
4282 * using the auxiliary surface, we can skip such transitions by
4283 * making the target layout one that is CCS-aware.
4285 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4287 target_layout
= subpass
->attachments
[i
].layout
;
4288 target_stencil_layout
= subpass
->attachments
[i
].stencil_layout
;
4291 uint32_t base_layer
, layer_count
;
4292 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4294 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4295 iview
->planes
[0].isl
.base_level
);
4297 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4298 layer_count
= fb
->layers
;
4301 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4302 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4303 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4304 iview
->planes
[0].isl
.base_level
, 1,
4305 base_layer
, layer_count
,
4306 att_state
->current_layout
, target_layout
);
4309 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4310 transition_depth_buffer(cmd_buffer
, image
,
4311 att_state
->current_layout
, target_layout
);
4312 att_state
->aux_usage
=
4313 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4314 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4317 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4318 transition_stencil_buffer(cmd_buffer
, image
,
4319 iview
->planes
[0].isl
.base_level
, 1,
4320 base_layer
, layer_count
,
4321 att_state
->current_stencil_layout
,
4322 target_stencil_layout
);
4324 att_state
->current_layout
= target_layout
;
4325 att_state
->current_stencil_layout
= target_stencil_layout
;
4327 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4328 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4330 /* Multi-planar images are not supported as attachments */
4331 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4332 assert(image
->n_planes
== 1);
4334 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4335 uint32_t clear_layer_count
= fb
->layers
;
4337 if (att_state
->fast_clear
&&
4338 do_first_layer_clear(cmd_state
, att_state
)) {
4339 /* We only support fast-clears on the first layer */
4340 assert(iview
->planes
[0].isl
.base_level
== 0);
4341 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4343 union isl_color_value clear_color
= {};
4344 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4345 if (iview
->image
->samples
== 1) {
4346 anv_image_ccs_op(cmd_buffer
, image
,
4347 iview
->planes
[0].isl
.format
,
4348 VK_IMAGE_ASPECT_COLOR_BIT
,
4349 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4353 anv_image_mcs_op(cmd_buffer
, image
,
4354 iview
->planes
[0].isl
.format
,
4355 VK_IMAGE_ASPECT_COLOR_BIT
,
4356 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4361 clear_layer_count
--;
4363 att_state
->pending_clear_views
&= ~1;
4365 if (att_state
->clear_color_is_zero
) {
4366 /* This image has the auxiliary buffer enabled. We can mark the
4367 * subresource as not needing a resolve because the clear color
4368 * will match what's in every RENDER_SURFACE_STATE object when
4369 * it's being used for sampling.
4371 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4372 VK_IMAGE_ASPECT_COLOR_BIT
,
4373 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4375 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4376 VK_IMAGE_ASPECT_COLOR_BIT
,
4377 ANV_FAST_CLEAR_ANY
);
4381 /* From the VkFramebufferCreateInfo spec:
4383 * "If the render pass uses multiview, then layers must be one and each
4384 * attachment requires a number of layers that is greater than the
4385 * maximum bit index set in the view mask in the subpasses in which it
4388 * So if multiview is active we ignore the number of layers in the
4389 * framebuffer and instead we honor the view mask from the subpass.
4392 assert(image
->n_planes
== 1);
4393 uint32_t pending_clear_mask
=
4394 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4397 for_each_bit(layer_idx
, pending_clear_mask
) {
4399 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4401 anv_image_clear_color(cmd_buffer
, image
,
4402 VK_IMAGE_ASPECT_COLOR_BIT
,
4403 att_state
->aux_usage
,
4404 iview
->planes
[0].isl
.format
,
4405 iview
->planes
[0].isl
.swizzle
,
4406 iview
->planes
[0].isl
.base_level
,
4409 vk_to_isl_color(att_state
->clear_value
.color
));
4412 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4413 } else if (clear_layer_count
> 0) {
4414 assert(image
->n_planes
== 1);
4415 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4416 att_state
->aux_usage
,
4417 iview
->planes
[0].isl
.format
,
4418 iview
->planes
[0].isl
.swizzle
,
4419 iview
->planes
[0].isl
.base_level
,
4420 base_clear_layer
, clear_layer_count
,
4422 vk_to_isl_color(att_state
->clear_value
.color
));
4424 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4425 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4426 if (att_state
->fast_clear
&& !is_multiview
) {
4427 /* We currently only support HiZ for single-layer images */
4428 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4429 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4430 assert(iview
->planes
[0].isl
.base_level
== 0);
4431 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4432 assert(fb
->layers
== 1);
4435 anv_image_hiz_clear(cmd_buffer
, image
,
4436 att_state
->pending_clear_aspects
,
4437 iview
->planes
[0].isl
.base_level
,
4438 iview
->planes
[0].isl
.base_array_layer
,
4439 fb
->layers
, render_area
,
4440 att_state
->clear_value
.depthStencil
.stencil
);
4441 } else if (is_multiview
) {
4442 uint32_t pending_clear_mask
=
4443 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4446 for_each_bit(layer_idx
, pending_clear_mask
) {
4448 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4450 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4451 att_state
->pending_clear_aspects
,
4452 att_state
->aux_usage
,
4453 iview
->planes
[0].isl
.base_level
,
4456 att_state
->clear_value
.depthStencil
.depth
,
4457 att_state
->clear_value
.depthStencil
.stencil
);
4460 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4462 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4463 att_state
->pending_clear_aspects
,
4464 att_state
->aux_usage
,
4465 iview
->planes
[0].isl
.base_level
,
4466 iview
->planes
[0].isl
.base_array_layer
,
4467 fb
->layers
, render_area
,
4468 att_state
->clear_value
.depthStencil
.depth
,
4469 att_state
->clear_value
.depthStencil
.stencil
);
4472 assert(att_state
->pending_clear_aspects
== 0);
4476 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4477 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4478 iview
->planes
[0].isl
.base_level
== 0 &&
4479 iview
->planes
[0].isl
.base_array_layer
== 0) {
4480 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4481 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4482 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4483 false /* copy to ss */);
4486 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4487 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4488 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4489 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4490 false /* copy to ss */);
4494 if (subpass
->attachments
[i
].usage
==
4495 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4496 /* We assume that if we're starting a subpass, we're going to do some
4497 * rendering so we may end up with compressed data.
4499 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4500 VK_IMAGE_ASPECT_COLOR_BIT
,
4501 att_state
->aux_usage
,
4502 iview
->planes
[0].isl
.base_level
,
4503 iview
->planes
[0].isl
.base_array_layer
,
4505 } else if (subpass
->attachments
[i
].usage
==
4506 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4507 /* We may be writing depth or stencil so we need to mark the surface.
4508 * Unfortunately, there's no way to know at this point whether the
4509 * depth or stencil tests used will actually write to the surface.
4511 * Even though stencil may be plane 1, it always shares a base_level
4514 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4515 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4516 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4517 VK_IMAGE_ASPECT_DEPTH_BIT
,
4518 att_state
->aux_usage
,
4519 ds_view
->base_level
,
4520 ds_view
->base_array_layer
,
4523 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4524 /* Even though stencil may be plane 1, it always shares a
4525 * base_level with depth.
4527 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4528 VK_IMAGE_ASPECT_STENCIL_BIT
,
4530 ds_view
->base_level
,
4531 ds_view
->base_array_layer
,
4536 /* If multiview is enabled, then we are only done clearing when we no
4537 * longer have pending layers to clear, or when we have processed the
4538 * last subpass that uses this attachment.
4540 if (!is_multiview
||
4541 att_state
->pending_clear_views
== 0 ||
4542 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4543 att_state
->pending_clear_aspects
= 0;
4546 att_state
->pending_load_aspects
= 0;
4549 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4552 /* The PIPE_CONTROL command description says:
4554 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
4555 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
4556 * Target Cache Flush by enabling this bit. When render target flush
4557 * is set due to new association of BTI, PS Scoreboard Stall bit must
4558 * be set in this packet."
4560 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4561 pc
.RenderTargetCacheFlushEnable
= true;
4562 pc
.StallAtPixelScoreboard
= true;
4564 pc
.TileCacheFlushEnable
= true;
4570 static enum blorp_filter
4571 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4574 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4575 return BLORP_FILTER_SAMPLE_0
;
4576 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4577 return BLORP_FILTER_AVERAGE
;
4578 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4579 return BLORP_FILTER_MIN_SAMPLE
;
4580 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4581 return BLORP_FILTER_MAX_SAMPLE
;
4583 return BLORP_FILTER_NONE
;
4588 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4590 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4591 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4592 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4593 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4595 if (subpass
->has_color_resolve
) {
4596 /* We are about to do some MSAA resolves. We need to flush so that the
4597 * result of writes to the MSAA color attachments show up in the sampler
4598 * when we blit to the single-sampled resolve target.
4600 cmd_buffer
->state
.pending_pipe_bits
|=
4601 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4602 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4604 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4605 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4606 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4608 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4611 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4612 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4614 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4615 /* From the Vulkan 1.0 spec:
4617 * If the first use of an attachment in a render pass is as a
4618 * resolve attachment, then the loadOp is effectively ignored
4619 * as the resolve is guaranteed to overwrite all pixels in the
4622 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4625 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
4626 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
4628 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4630 enum isl_aux_usage src_aux_usage
=
4631 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4632 enum isl_aux_usage dst_aux_usage
=
4633 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4635 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4636 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4638 anv_image_msaa_resolve(cmd_buffer
,
4639 src_iview
->image
, src_aux_usage
,
4640 src_iview
->planes
[0].isl
.base_level
,
4641 src_iview
->planes
[0].isl
.base_array_layer
,
4642 dst_iview
->image
, dst_aux_usage
,
4643 dst_iview
->planes
[0].isl
.base_level
,
4644 dst_iview
->planes
[0].isl
.base_array_layer
,
4645 VK_IMAGE_ASPECT_COLOR_BIT
,
4646 render_area
.offset
.x
, render_area
.offset
.y
,
4647 render_area
.offset
.x
, render_area
.offset
.y
,
4648 render_area
.extent
.width
,
4649 render_area
.extent
.height
,
4650 fb
->layers
, BLORP_FILTER_NONE
);
4654 if (subpass
->ds_resolve_attachment
) {
4655 /* We are about to do some MSAA resolves. We need to flush so that the
4656 * result of writes to the MSAA depth attachments show up in the sampler
4657 * when we blit to the single-sampled resolve target.
4659 cmd_buffer
->state
.pending_pipe_bits
|=
4660 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4661 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4663 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4664 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4666 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4667 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4669 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4670 /* From the Vulkan 1.0 spec:
4672 * If the first use of an attachment in a render pass is as a
4673 * resolve attachment, then the loadOp is effectively ignored
4674 * as the resolve is guaranteed to overwrite all pixels in the
4677 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4680 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
4681 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
4683 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4685 struct anv_attachment_state
*src_state
=
4686 &cmd_state
->attachments
[src_att
];
4687 struct anv_attachment_state
*dst_state
=
4688 &cmd_state
->attachments
[dst_att
];
4690 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4691 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4693 /* MSAA resolves sample from the source attachment. Transition the
4694 * depth attachment first to get rid of any HiZ that we may not be
4697 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4698 src_state
->current_layout
,
4699 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4700 src_state
->aux_usage
=
4701 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4702 VK_IMAGE_ASPECT_DEPTH_BIT
,
4703 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4704 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4706 /* MSAA resolves write to the resolve attachment as if it were any
4707 * other transfer op. Transition the resolve attachment accordingly.
4709 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4711 /* If our render area is the entire size of the image, we're going to
4712 * blow it all away so we can claim the initial layout is UNDEFINED
4713 * and we'll get a HiZ ambiguate instead of a resolve.
4715 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4716 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4717 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4718 render_area
.extent
.height
== dst_iview
->extent
.height
)
4719 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4721 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4723 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4724 dst_state
->aux_usage
=
4725 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4726 VK_IMAGE_ASPECT_DEPTH_BIT
,
4727 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4728 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4730 enum blorp_filter filter
=
4731 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4733 anv_image_msaa_resolve(cmd_buffer
,
4734 src_iview
->image
, src_state
->aux_usage
,
4735 src_iview
->planes
[0].isl
.base_level
,
4736 src_iview
->planes
[0].isl
.base_array_layer
,
4737 dst_iview
->image
, dst_state
->aux_usage
,
4738 dst_iview
->planes
[0].isl
.base_level
,
4739 dst_iview
->planes
[0].isl
.base_array_layer
,
4740 VK_IMAGE_ASPECT_DEPTH_BIT
,
4741 render_area
.offset
.x
, render_area
.offset
.y
,
4742 render_area
.offset
.x
, render_area
.offset
.y
,
4743 render_area
.extent
.width
,
4744 render_area
.extent
.height
,
4745 fb
->layers
, filter
);
4748 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4749 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4751 src_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4752 dst_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4754 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4755 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4757 enum blorp_filter filter
=
4758 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4760 anv_image_msaa_resolve(cmd_buffer
,
4761 src_iview
->image
, src_aux_usage
,
4762 src_iview
->planes
[0].isl
.base_level
,
4763 src_iview
->planes
[0].isl
.base_array_layer
,
4764 dst_iview
->image
, dst_aux_usage
,
4765 dst_iview
->planes
[0].isl
.base_level
,
4766 dst_iview
->planes
[0].isl
.base_array_layer
,
4767 VK_IMAGE_ASPECT_STENCIL_BIT
,
4768 render_area
.offset
.x
, render_area
.offset
.y
,
4769 render_area
.offset
.x
, render_area
.offset
.y
,
4770 render_area
.extent
.width
,
4771 render_area
.extent
.height
,
4772 fb
->layers
, filter
);
4777 /* On gen7, we have to store a texturable version of the stencil buffer in
4778 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
4779 * forth at strategic points. Stencil writes are only allowed in following
4782 * - VK_IMAGE_LAYOUT_GENERAL
4783 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
4784 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
4785 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
4786 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
4788 * For general, we have no nice opportunity to transition so we do the copy
4789 * to the shadow unconditionally at the end of the subpass. For transfer
4790 * destinations, we can update it as part of the transfer op. For the other
4791 * layouts, we delay the copy until a transition into some other layout.
4793 if (subpass
->depth_stencil_attachment
) {
4794 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
4795 assert(a
!= VK_ATTACHMENT_UNUSED
);
4797 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4798 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
4799 const struct anv_image
*image
= iview
->image
;
4801 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4802 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
4803 VK_IMAGE_ASPECT_STENCIL_BIT
);
4805 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
4806 att_state
->current_stencil_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
4807 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
4808 anv_image_copy_to_shadow(cmd_buffer
, image
,
4809 VK_IMAGE_ASPECT_STENCIL_BIT
,
4810 iview
->planes
[plane
].isl
.base_level
, 1,
4811 iview
->planes
[plane
].isl
.base_array_layer
,
4816 #endif /* GEN_GEN == 7 */
4818 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4819 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4820 if (a
== VK_ATTACHMENT_UNUSED
)
4823 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4826 assert(a
< cmd_state
->pass
->attachment_count
);
4827 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4828 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4829 const struct anv_image
*image
= iview
->image
;
4831 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4832 image
->vk_format
!= iview
->vk_format
) {
4833 enum anv_fast_clear_type fast_clear_type
=
4834 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4835 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4836 att_state
->current_layout
);
4838 /* If any clear color was used, flush it down the aux surfaces. If we
4839 * don't do it now using the view's format we might use the clear
4840 * color incorrectly in the following resolves (for example with an
4841 * SRGB view & a UNORM image).
4843 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4844 anv_perf_warn(cmd_buffer
->device
->instance
, iview
,
4845 "Doing a partial resolve to get rid of clear color at the "
4846 "end of a renderpass due to an image/view format mismatch");
4848 uint32_t base_layer
, layer_count
;
4849 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4851 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4852 iview
->planes
[0].isl
.base_level
);
4854 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4855 layer_count
= fb
->layers
;
4858 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4859 uint32_t array_layer
= base_layer
+ a
;
4860 if (image
->samples
== 1) {
4861 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4862 iview
->planes
[0].isl
.format
,
4863 VK_IMAGE_ASPECT_COLOR_BIT
,
4864 iview
->planes
[0].isl
.base_level
,
4866 ISL_AUX_OP_PARTIAL_RESOLVE
,
4867 ANV_FAST_CLEAR_NONE
);
4869 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4870 iview
->planes
[0].isl
.format
,
4871 VK_IMAGE_ASPECT_COLOR_BIT
,
4873 ISL_AUX_OP_PARTIAL_RESOLVE
,
4874 ANV_FAST_CLEAR_NONE
);
4880 /* Transition the image into the final layout for this render pass */
4881 VkImageLayout target_layout
=
4882 cmd_state
->pass
->attachments
[a
].final_layout
;
4883 VkImageLayout target_stencil_layout
=
4884 cmd_state
->pass
->attachments
[a
].stencil_final_layout
;
4886 uint32_t base_layer
, layer_count
;
4887 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4889 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4890 iview
->planes
[0].isl
.base_level
);
4892 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4893 layer_count
= fb
->layers
;
4896 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4897 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4898 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4899 iview
->planes
[0].isl
.base_level
, 1,
4900 base_layer
, layer_count
,
4901 att_state
->current_layout
, target_layout
);
4904 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4905 transition_depth_buffer(cmd_buffer
, image
,
4906 att_state
->current_layout
, target_layout
);
4909 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4910 transition_stencil_buffer(cmd_buffer
, image
,
4911 iview
->planes
[0].isl
.base_level
, 1,
4912 base_layer
, layer_count
,
4913 att_state
->current_stencil_layout
,
4914 target_stencil_layout
);
4918 /* Accumulate any subpass flushes that need to happen after the subpass.
4919 * Yes, they do get accumulated twice in the NextSubpass case but since
4920 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4921 * ORing the bits in twice so it's harmless.
4923 cmd_buffer
->state
.pending_pipe_bits
|=
4924 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4927 void genX(CmdBeginRenderPass
)(
4928 VkCommandBuffer commandBuffer
,
4929 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4930 VkSubpassContents contents
)
4932 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4933 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4934 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4936 cmd_buffer
->state
.framebuffer
= framebuffer
;
4937 cmd_buffer
->state
.pass
= pass
;
4938 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4940 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4942 /* If we failed to setup the attachments we should not try to go further */
4943 if (result
!= VK_SUCCESS
) {
4944 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4948 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4950 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4953 void genX(CmdBeginRenderPass2KHR
)(
4954 VkCommandBuffer commandBuffer
,
4955 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4956 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4958 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4959 pSubpassBeginInfo
->contents
);
4962 void genX(CmdNextSubpass
)(
4963 VkCommandBuffer commandBuffer
,
4964 VkSubpassContents contents
)
4966 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4968 if (anv_batch_has_error(&cmd_buffer
->batch
))
4971 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4973 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4974 cmd_buffer_end_subpass(cmd_buffer
);
4975 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4978 void genX(CmdNextSubpass2KHR
)(
4979 VkCommandBuffer commandBuffer
,
4980 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4981 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4983 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4986 void genX(CmdEndRenderPass
)(
4987 VkCommandBuffer commandBuffer
)
4989 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4991 if (anv_batch_has_error(&cmd_buffer
->batch
))
4994 cmd_buffer_end_subpass(cmd_buffer
);
4996 cmd_buffer
->state
.hiz_enabled
= false;
4999 anv_dump_add_attachments(cmd_buffer
);
5002 /* Remove references to render pass specific state. This enables us to
5003 * detect whether or not we're in a renderpass.
5005 cmd_buffer
->state
.framebuffer
= NULL
;
5006 cmd_buffer
->state
.pass
= NULL
;
5007 cmd_buffer
->state
.subpass
= NULL
;
5010 void genX(CmdEndRenderPass2KHR
)(
5011 VkCommandBuffer commandBuffer
,
5012 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5014 genX(CmdEndRenderPass
)(commandBuffer
);
5018 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
5020 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5021 struct gen_mi_builder b
;
5022 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5024 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
5025 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
5026 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
5028 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
5029 mip
.LoadOperation
= LOAD_LOADINV
;
5030 mip
.CombineOperation
= COMBINE_SET
;
5031 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
5036 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5037 void genX(CmdBeginConditionalRenderingEXT
)(
5038 VkCommandBuffer commandBuffer
,
5039 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5041 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5042 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5043 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5044 struct anv_address value_address
=
5045 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
5047 const bool isInverted
= pConditionalRenderingBegin
->flags
&
5048 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
5050 cmd_state
->conditional_render_enabled
= true;
5052 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5054 struct gen_mi_builder b
;
5055 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5057 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5059 * If the value of the predicate in buffer memory changes
5060 * while conditional rendering is active, the rendering commands
5061 * may be discarded in an implementation-dependent way.
5062 * Some implementations may latch the value of the predicate
5063 * upon beginning conditional rendering while others
5064 * may read it before every rendering command.
5066 * So it's perfectly fine to read a value from the buffer once.
5068 struct gen_mi_value value
= gen_mi_mem32(value_address
);
5070 /* Precompute predicate result, it is necessary to support secondary
5071 * command buffers since it is unknown if conditional rendering is
5072 * inverted when populating them.
5074 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
5075 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
5076 gen_mi_ult(&b
, gen_mi_imm(0), value
));
5079 void genX(CmdEndConditionalRenderingEXT
)(
5080 VkCommandBuffer commandBuffer
)
5082 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5083 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5085 cmd_state
->conditional_render_enabled
= false;
5089 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5090 * command streamer for later execution.
5092 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5093 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5094 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5095 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5096 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5097 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5098 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5099 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5100 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5101 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5102 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5103 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5104 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5105 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5106 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5108 void genX(CmdSetEvent
)(
5109 VkCommandBuffer commandBuffer
,
5111 VkPipelineStageFlags stageMask
)
5113 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5114 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5116 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5117 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5118 pc
.StallAtPixelScoreboard
= true;
5119 pc
.CommandStreamerStallEnable
= true;
5122 pc
.DestinationAddressType
= DAT_PPGTT
,
5123 pc
.PostSyncOperation
= WriteImmediateData
,
5124 pc
.Address
= (struct anv_address
) {
5125 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5128 pc
.ImmediateData
= VK_EVENT_SET
;
5132 void genX(CmdResetEvent
)(
5133 VkCommandBuffer commandBuffer
,
5135 VkPipelineStageFlags stageMask
)
5137 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5138 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5140 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5141 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5142 pc
.StallAtPixelScoreboard
= true;
5143 pc
.CommandStreamerStallEnable
= true;
5146 pc
.DestinationAddressType
= DAT_PPGTT
;
5147 pc
.PostSyncOperation
= WriteImmediateData
;
5148 pc
.Address
= (struct anv_address
) {
5149 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5152 pc
.ImmediateData
= VK_EVENT_RESET
;
5156 void genX(CmdWaitEvents
)(
5157 VkCommandBuffer commandBuffer
,
5158 uint32_t eventCount
,
5159 const VkEvent
* pEvents
,
5160 VkPipelineStageFlags srcStageMask
,
5161 VkPipelineStageFlags destStageMask
,
5162 uint32_t memoryBarrierCount
,
5163 const VkMemoryBarrier
* pMemoryBarriers
,
5164 uint32_t bufferMemoryBarrierCount
,
5165 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5166 uint32_t imageMemoryBarrierCount
,
5167 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5170 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5172 for (uint32_t i
= 0; i
< eventCount
; i
++) {
5173 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
5175 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
5176 sem
.WaitMode
= PollingMode
,
5177 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
5178 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
5179 sem
.SemaphoreAddress
= (struct anv_address
) {
5180 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5186 anv_finishme("Implement events on gen7");
5189 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
5190 false, /* byRegion */
5191 memoryBarrierCount
, pMemoryBarriers
,
5192 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5193 imageMemoryBarrierCount
, pImageMemoryBarriers
);
5196 VkResult
genX(CmdSetPerformanceOverrideINTEL
)(
5197 VkCommandBuffer commandBuffer
,
5198 const VkPerformanceOverrideInfoINTEL
* pOverrideInfo
)
5200 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5202 switch (pOverrideInfo
->type
) {
5203 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL
: {
5207 anv_pack_struct(&dw
, GENX(CS_DEBUG_MODE2
),
5208 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5209 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5210 ._3DRenderingInstructionDisableMask
= true,
5211 .MediaInstructionDisableMask
= true);
5212 emit_lri(&cmd_buffer
->batch
, GENX(CS_DEBUG_MODE2_num
), dw
);
5214 anv_pack_struct(&dw
, GENX(INSTPM
),
5215 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5216 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5217 ._3DRenderingInstructionDisableMask
= true,
5218 .MediaInstructionDisableMask
= true);
5219 emit_lri(&cmd_buffer
->batch
, GENX(INSTPM_num
), dw
);
5224 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL
:
5225 if (pOverrideInfo
->enable
) {
5226 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
5227 cmd_buffer
->state
.pending_pipe_bits
|=
5228 ANV_PIPE_FLUSH_BITS
|
5229 ANV_PIPE_INVALIDATE_BITS
;
5230 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5235 unreachable("Invalid override");
5241 VkResult
genX(CmdSetPerformanceStreamMarkerINTEL
)(
5242 VkCommandBuffer commandBuffer
,
5243 const VkPerformanceStreamMarkerInfoINTEL
* pMarkerInfo
)
5245 /* TODO: Waiting on the register to write, might depend on generation. */