2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "common/gen_l3_config.h"
31 #include "genxml/gen_macros.h"
32 #include "genxml/genX_pack.h"
35 emit_lrm(struct anv_batch
*batch
,
36 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
54 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
56 struct anv_device
*device
= cmd_buffer
->device
;
58 /* XXX: Do we need this on more than just BDW? */
60 /* Emit a render target cache flush.
62 * This isn't documented anywhere in the PRM. However, it seems to be
63 * necessary prior to changing the surface state base adress. Without
64 * this, we get GPU hangs when using multi-level command buffers which
65 * clear depth, reset state base address, and then go render stuff.
67 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
68 pc
.RenderTargetCacheFlushEnable
= true;
72 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
73 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
74 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
75 sba
.GeneralStateBaseAddressModifyEnable
= true;
77 sba
.SurfaceStateBaseAddress
=
78 anv_cmd_buffer_surface_base_address(cmd_buffer
);
79 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
80 sba
.SurfaceStateBaseAddressModifyEnable
= true;
82 sba
.DynamicStateBaseAddress
=
83 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
84 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
85 sba
.DynamicStateBaseAddressModifyEnable
= true;
87 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
88 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
89 sba
.IndirectObjectBaseAddressModifyEnable
= true;
91 sba
.InstructionBaseAddress
=
92 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
93 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
94 sba
.InstructionBaseAddressModifyEnable
= true;
97 /* Broadwell requires that we specify a buffer size for a bunch of
98 * these fields. However, since we will be growing the BO's live, we
99 * just set them all to the maximum.
101 sba
.GeneralStateBufferSize
= 0xfffff;
102 sba
.GeneralStateBufferSizeModifyEnable
= true;
103 sba
.DynamicStateBufferSize
= 0xfffff;
104 sba
.DynamicStateBufferSizeModifyEnable
= true;
105 sba
.IndirectObjectBufferSize
= 0xfffff;
106 sba
.IndirectObjectBufferSizeModifyEnable
= true;
107 sba
.InstructionBufferSize
= 0xfffff;
108 sba
.InstructionBuffersizeModifyEnable
= true;
112 /* After re-setting the surface state base address, we have to do some
113 * cache flusing so that the sampler engine will pick up the new
114 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
115 * Shared Function > 3D Sampler > State > State Caching (page 96):
117 * Coherency with system memory in the state cache, like the texture
118 * cache is handled partially by software. It is expected that the
119 * command stream or shader will issue Cache Flush operation or
120 * Cache_Flush sampler message to ensure that the L1 cache remains
121 * coherent with system memory.
125 * Whenever the value of the Dynamic_State_Base_Addr,
126 * Surface_State_Base_Addr are altered, the L1 state cache must be
127 * invalidated to ensure the new surface or sampler state is fetched
128 * from system memory.
130 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
131 * which, according the PIPE_CONTROL instruction documentation in the
134 * Setting this bit is independent of any other bit in this packet.
135 * This bit controls the invalidation of the L1 and L2 state caches
136 * at the top of the pipe i.e. at the parsing time.
138 * Unfortunately, experimentation seems to indicate that state cache
139 * invalidation through a PIPE_CONTROL does nothing whatsoever in
140 * regards to surface state and binding tables. In stead, it seems that
141 * invalidating the texture cache is what is actually needed.
143 * XXX: As far as we have been able to determine through
144 * experimentation, shows that flush the texture cache appears to be
145 * sufficient. The theory here is that all of the sampling/rendering
146 * units cache the binding table in the texture cache. However, we have
147 * yet to be able to actually confirm this.
149 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
150 pc
.TextureCacheInvalidationEnable
= true;
155 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
156 struct anv_state state
,
157 struct anv_bo
*bo
, uint32_t offset
)
159 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
161 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
162 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
166 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
167 const struct anv_image_view
*iview
,
168 struct anv_state state
)
170 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
172 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
173 state
.offset
+ isl_dev
->ss
.addr_offset
,
174 iview
->bo
, iview
->offset
);
178 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
181 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
182 struct anv_render_pass
*pass
,
183 struct anv_framebuffer
*framebuffer
,
184 const VkClearValue
*clear_values
)
186 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
187 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
189 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
191 if (pass
->attachment_count
== 0) {
192 state
->attachments
= NULL
;
196 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
197 pass
->attachment_count
*
198 sizeof(state
->attachments
[0]),
199 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
200 if (state
->attachments
== NULL
) {
201 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
205 bool need_null_state
= false;
206 unsigned num_states
= 0;
207 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
208 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
211 /* We need a null state for any depth-stencil-only subpasses.
212 * Importantly, this includes depth/stencil clears so we create one
213 * whenever we have depth or stencil
215 need_null_state
= true;
218 num_states
+= need_null_state
;
220 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
221 state
->render_pass_states
=
222 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
223 num_states
* ss_stride
, isl_dev
->ss
.align
);
225 struct anv_state next_state
= state
->render_pass_states
;
226 next_state
.alloc_size
= isl_dev
->ss
.size
;
228 if (need_null_state
) {
229 state
->null_surface_state
= next_state
;
230 next_state
.offset
+= ss_stride
;
231 next_state
.map
+= ss_stride
;
234 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
235 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
236 state
->attachments
[i
].color_rt_state
= next_state
;
237 next_state
.offset
+= ss_stride
;
238 next_state
.map
+= ss_stride
;
241 assert(next_state
.offset
== state
->render_pass_states
.offset
+
242 state
->render_pass_states
.alloc_size
);
245 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
247 if (need_null_state
) {
248 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
249 .SurfaceType
= SURFTYPE_NULL
,
250 .SurfaceArray
= framebuffer
->layers
> 0,
251 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
255 .TiledSurface
= true,
257 .Width
= framebuffer
->width
- 1,
258 .Height
= framebuffer
->height
- 1,
259 .Depth
= framebuffer
->layers
- 1,
260 .RenderTargetViewExtent
= framebuffer
->layers
- 1,
262 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
->null_surface_state
.map
,
266 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
267 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
268 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
269 VkImageAspectFlags clear_aspects
= 0;
271 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
272 /* color attachment */
273 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
274 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
277 /* depthstencil attachment */
278 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
279 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
280 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
282 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
283 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
284 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
288 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
290 state
->attachments
[i
].clear_value
= clear_values
[i
];
292 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
293 assert(iview
->vk_format
== att
->format
);
295 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
296 struct isl_view view
= iview
->isl
;
297 view
.usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
298 isl_surf_fill_state(isl_dev
,
299 state
->attachments
[i
].color_rt_state
.map
,
300 .surf
= &iview
->image
->color_surface
.isl
,
302 .mocs
= cmd_buffer
->device
->default_mocs
);
304 add_image_view_relocs(cmd_buffer
, iview
,
305 state
->attachments
[i
].color_rt_state
);
309 if (!cmd_buffer
->device
->info
.has_llc
)
310 anv_state_clflush(state
->render_pass_states
);
315 genX(BeginCommandBuffer
)(
316 VkCommandBuffer commandBuffer
,
317 const VkCommandBufferBeginInfo
* pBeginInfo
)
319 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
321 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
322 * command buffer's state. Otherwise, we must *reset* its state. In both
325 * From the Vulkan 1.0 spec:
327 * If a command buffer is in the executable state and the command buffer
328 * was allocated from a command pool with the
329 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
330 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
331 * as if vkResetCommandBuffer had been called with
332 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
333 * the command buffer in the recording state.
335 anv_cmd_buffer_reset(cmd_buffer
);
337 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
339 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
340 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
342 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
344 if (cmd_buffer
->usage_flags
&
345 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
346 cmd_buffer
->state
.pass
=
347 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
348 cmd_buffer
->state
.subpass
=
349 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
350 cmd_buffer
->state
.framebuffer
= NULL
;
352 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, cmd_buffer
->state
.pass
,
355 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
362 genX(EndCommandBuffer
)(
363 VkCommandBuffer commandBuffer
)
365 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
367 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
373 genX(CmdExecuteCommands
)(
374 VkCommandBuffer commandBuffer
,
375 uint32_t commandBufferCount
,
376 const VkCommandBuffer
* pCmdBuffers
)
378 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
380 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
382 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
383 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
385 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
387 if (secondary
->usage_flags
&
388 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
389 /* If we're continuing a render pass from the primary, we need to
390 * copy the surface states for the current subpass into the storage
391 * we allocated for them in BeginCommandBuffer.
393 struct anv_bo
*ss_bo
= &primary
->device
->surface_state_block_pool
.bo
;
394 struct anv_state src_state
= primary
->state
.render_pass_states
;
395 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
396 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
398 genX(cmd_buffer_gpu_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
399 ss_bo
, src_state
.offset
,
400 src_state
.alloc_size
);
403 anv_cmd_buffer_add_secondary(primary
, secondary
);
406 /* Each of the secondary command buffers will use its own state base
407 * address. We need to re-emit state base address for the primary after
408 * all of the secondaries are done.
410 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
413 genX(cmd_buffer_emit_state_base_address
)(primary
);
416 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
417 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
418 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
421 * Program the hardware to use the specified L3 configuration.
424 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
425 const struct gen_l3_config
*cfg
)
428 if (cfg
== cmd_buffer
->state
.current_l3_config
)
431 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
432 fprintf(stderr
, "L3 config transition: ");
433 gen_dump_l3_config(cfg
, stderr
);
436 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
438 /* According to the hardware docs, the L3 partitioning can only be changed
439 * while the pipeline is completely drained and the caches are flushed,
440 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
442 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
443 pc
.DCFlushEnable
= true;
444 pc
.PostSyncOperation
= NoWrite
;
445 pc
.CommandStreamerStallEnable
= true;
448 /* ...followed by a second pipelined PIPE_CONTROL that initiates
449 * invalidation of the relevant caches. Note that because RO invalidation
450 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
451 * command is processed by the CS) we cannot combine it with the previous
452 * stalling flush as the hardware documentation suggests, because that
453 * would cause the CS to stall on previous rendering *after* RO
454 * invalidation and wouldn't prevent the RO caches from being polluted by
455 * concurrent rendering before the stall completes. This intentionally
456 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
457 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
458 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
459 * already guarantee that there is no concurrent GPGPU kernel execution
460 * (see SKL HSD 2132585).
462 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
463 pc
.TextureCacheInvalidationEnable
= true;
464 pc
.ConstantCacheInvalidationEnable
= true;
465 pc
.InstructionCacheInvalidateEnable
= true;
466 pc
.StateCacheInvalidationEnable
= true;
467 pc
.PostSyncOperation
= NoWrite
;
470 /* Now send a third stalling flush to make sure that invalidation is
471 * complete when the L3 configuration registers are modified.
473 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
474 pc
.DCFlushEnable
= true;
475 pc
.PostSyncOperation
= NoWrite
;
476 pc
.CommandStreamerStallEnable
= true;
481 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
484 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
485 .SLMEnable
= has_slm
,
486 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
487 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
488 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
489 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
491 /* Set up the L3 partitioning. */
492 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
496 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
497 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
499 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
501 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
504 assert(!cfg
->n
[GEN_L3P_ALL
]);
506 /* When enabled SLM only uses a portion of the L3 on half of the banks,
507 * the matching space on the remaining banks has to be allocated to a
508 * client (URB for all validated configurations) set to the
509 * lower-bandwidth 2-bank address hashing mode.
511 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
512 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
513 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
515 /* Minimum number of ways that can be allocated to the URB. */
516 const unsigned n0_urb
= (devinfo
->is_baytrail
? 32 : 0);
517 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
519 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
520 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
521 .ConvertDC_UC
= !has_dc
,
522 .ConvertIS_UC
= !has_is
,
523 .ConvertC_UC
= !has_c
,
524 .ConvertT_UC
= !has_t
);
526 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
527 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
528 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
530 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
531 .SLMEnable
= has_slm
,
532 .URBLowBandwidth
= urb_low_bw
,
533 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
535 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
537 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
538 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
540 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
541 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
543 .CAllocation
= cfg
->n
[GEN_L3P_C
],
545 .TAllocation
= cfg
->n
[GEN_L3P_T
],
548 /* Set up the L3 partitioning. */
549 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
550 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
551 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
554 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
555 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
556 * them disabled to avoid crashing the system hard.
558 uint32_t scratch1
, chicken3
;
559 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
560 .L3AtomicDisable
= !has_dc
);
561 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
562 .L3AtomicDisableMask
= true,
563 .L3AtomicDisable
= !has_dc
);
564 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
565 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
571 cmd_buffer
->state
.current_l3_config
= cfg
;
575 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
577 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
579 /* Flushes are pipelined while invalidations are handled immediately.
580 * Therefore, if we're flushing anything then we need to schedule a stall
581 * before any invalidations can happen.
583 if (bits
& ANV_PIPE_FLUSH_BITS
)
584 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
586 /* If we're going to do an invalidate and we have a pending CS stall that
587 * has yet to be resolved, we do the CS stall now.
589 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
590 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
591 bits
|= ANV_PIPE_CS_STALL_BIT
;
592 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
595 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
596 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
597 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
598 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
599 pipe
.RenderTargetCacheFlushEnable
=
600 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
602 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
603 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
604 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
607 * According to the Broadwell documentation, any PIPE_CONTROL with the
608 * "Command Streamer Stall" bit set must also have another bit set,
609 * with five different options:
611 * - Render Target Cache Flush
612 * - Depth Cache Flush
613 * - Stall at Pixel Scoreboard
614 * - Post-Sync Operation
618 * I chose "Stall at Pixel Scoreboard" since that's what we use in
619 * mesa and it seems to work fine. The choice is fairly arbitrary.
621 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
622 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
623 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
624 pipe
.StallAtPixelScoreboard
= true;
627 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
630 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
631 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
632 pipe
.StateCacheInvalidationEnable
=
633 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
634 pipe
.ConstantCacheInvalidationEnable
=
635 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
636 pipe
.VFCacheInvalidationEnable
=
637 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
638 pipe
.TextureCacheInvalidationEnable
=
639 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
640 pipe
.InstructionCacheInvalidateEnable
=
641 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
644 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
647 cmd_buffer
->state
.pending_pipe_bits
= bits
;
650 void genX(CmdPipelineBarrier
)(
651 VkCommandBuffer commandBuffer
,
652 VkPipelineStageFlags srcStageMask
,
653 VkPipelineStageFlags destStageMask
,
655 uint32_t memoryBarrierCount
,
656 const VkMemoryBarrier
* pMemoryBarriers
,
657 uint32_t bufferMemoryBarrierCount
,
658 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
659 uint32_t imageMemoryBarrierCount
,
660 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
662 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
665 /* XXX: Right now, we're really dumb and just flush whatever categories
666 * the app asks for. One of these days we may make this a bit better
667 * but right now that's all the hardware allows for in most areas.
669 VkAccessFlags src_flags
= 0;
670 VkAccessFlags dst_flags
= 0;
672 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
673 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
674 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
677 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
678 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
679 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
682 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
683 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
684 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
687 enum anv_pipe_bits pipe_bits
= 0;
689 for_each_bit(b
, src_flags
) {
690 switch ((VkAccessFlagBits
)(1 << b
)) {
691 case VK_ACCESS_SHADER_WRITE_BIT
:
692 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
694 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
695 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
697 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
698 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
700 case VK_ACCESS_TRANSFER_WRITE_BIT
:
701 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
702 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
705 break; /* Nothing to do */
709 for_each_bit(b
, dst_flags
) {
710 switch ((VkAccessFlagBits
)(1 << b
)) {
711 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
712 case VK_ACCESS_INDEX_READ_BIT
:
713 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
714 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
716 case VK_ACCESS_UNIFORM_READ_BIT
:
717 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
718 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
720 case VK_ACCESS_SHADER_READ_BIT
:
721 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
722 case VK_ACCESS_TRANSFER_READ_BIT
:
723 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
726 break; /* Nothing to do */
730 cmd_buffer
->state
.pending_pipe_bits
|= pipe_bits
;
734 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
736 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
738 /* In order to avoid thrash, we assume that vertex and fragment stages
739 * always exist. In the rare case where one is missing *and* the other
740 * uses push concstants, this may be suboptimal. However, avoiding stalls
741 * seems more important.
743 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
745 if (stages
== cmd_buffer
->state
.push_constant_stages
)
749 const unsigned push_constant_kb
= 32;
751 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
753 const unsigned push_constant_kb
= 16;
756 const unsigned num_stages
=
757 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
758 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
760 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
761 * units of 2KB. Incidentally, these are the same platforms that have
762 * 32KB worth of push constant space.
764 if (push_constant_kb
== 32)
765 size_per_stage
&= ~1u;
767 uint32_t kb_used
= 0;
768 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
769 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
770 anv_batch_emit(&cmd_buffer
->batch
,
771 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
772 alloc
._3DCommandSubOpcode
= 18 + i
;
773 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
774 alloc
.ConstantBufferSize
= push_size
;
776 kb_used
+= push_size
;
779 anv_batch_emit(&cmd_buffer
->batch
,
780 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
781 alloc
.ConstantBufferOffset
= kb_used
;
782 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
785 cmd_buffer
->state
.push_constant_stages
= stages
;
787 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
789 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
790 * the next 3DPRIMITIVE command after programming the
791 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
793 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
794 * pipeline setup, we need to dirty push constants.
796 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
800 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
801 gl_shader_stage stage
,
802 struct anv_state
*bt_state
)
804 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
805 struct anv_pipeline
*pipeline
;
806 uint32_t bias
, state_offset
;
809 case MESA_SHADER_COMPUTE
:
810 pipeline
= cmd_buffer
->state
.compute_pipeline
;
814 pipeline
= cmd_buffer
->state
.pipeline
;
819 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
820 *bt_state
= (struct anv_state
) { 0, };
824 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
825 if (bias
+ map
->surface_count
== 0) {
826 *bt_state
= (struct anv_state
) { 0, };
830 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
831 bias
+ map
->surface_count
,
833 uint32_t *bt_map
= bt_state
->map
;
835 if (bt_state
->map
== NULL
)
836 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
838 if (stage
== MESA_SHADER_COMPUTE
&&
839 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
840 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
841 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
843 struct anv_state surface_state
;
845 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
847 const enum isl_format format
=
848 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
849 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
850 format
, bo_offset
, 12, 1);
852 bt_map
[0] = surface_state
.offset
+ state_offset
;
853 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
856 if (map
->surface_count
== 0)
859 if (map
->image_count
> 0) {
861 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
862 if (result
!= VK_SUCCESS
)
865 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
869 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
870 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
872 struct anv_state surface_state
;
874 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
875 /* Color attachment binding */
876 assert(stage
== MESA_SHADER_FRAGMENT
);
877 assert(binding
->binding
== 0);
878 if (binding
->index
< subpass
->color_count
) {
879 const unsigned att
= subpass
->color_attachments
[binding
->index
];
880 surface_state
= cmd_buffer
->state
.attachments
[att
].color_rt_state
;
882 surface_state
= cmd_buffer
->state
.null_surface_state
;
885 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
889 struct anv_descriptor_set
*set
=
890 cmd_buffer
->state
.descriptors
[binding
->set
];
891 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
892 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
894 switch (desc
->type
) {
895 case VK_DESCRIPTOR_TYPE_SAMPLER
:
896 /* Nothing for us to do here */
899 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
900 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
901 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
902 surface_state
= desc
->image_view
->sampler_surface_state
;
903 assert(surface_state
.alloc_size
);
904 add_image_view_relocs(cmd_buffer
, desc
->image_view
, surface_state
);
907 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
908 surface_state
= desc
->image_view
->storage_surface_state
;
909 assert(surface_state
.alloc_size
);
910 add_image_view_relocs(cmd_buffer
, desc
->image_view
, surface_state
);
912 struct brw_image_param
*image_param
=
913 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
915 *image_param
= desc
->image_view
->storage_image_param
;
916 image_param
->surface_idx
= bias
+ s
;
920 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
921 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
922 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
923 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
924 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
925 surface_state
= desc
->buffer_view
->surface_state
;
926 assert(surface_state
.alloc_size
);
927 add_surface_state_reloc(cmd_buffer
, surface_state
,
928 desc
->buffer_view
->bo
,
929 desc
->buffer_view
->offset
);
932 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
933 surface_state
= desc
->buffer_view
->storage_surface_state
;
934 assert(surface_state
.alloc_size
);
935 add_surface_state_reloc(cmd_buffer
, surface_state
,
936 desc
->buffer_view
->bo
,
937 desc
->buffer_view
->offset
);
939 struct brw_image_param
*image_param
=
940 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
942 *image_param
= desc
->buffer_view
->storage_image_param
;
943 image_param
->surface_idx
= bias
+ s
;
947 assert(!"Invalid descriptor type");
951 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
953 assert(image
== map
->image_count
);
956 if (!cmd_buffer
->device
->info
.has_llc
)
957 anv_state_clflush(*bt_state
);
963 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
964 gl_shader_stage stage
,
965 struct anv_state
*state
)
967 struct anv_pipeline
*pipeline
;
969 if (stage
== MESA_SHADER_COMPUTE
)
970 pipeline
= cmd_buffer
->state
.compute_pipeline
;
972 pipeline
= cmd_buffer
->state
.pipeline
;
974 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
975 *state
= (struct anv_state
) { 0, };
979 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
980 if (map
->sampler_count
== 0) {
981 *state
= (struct anv_state
) { 0, };
985 uint32_t size
= map
->sampler_count
* 16;
986 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
988 if (state
->map
== NULL
)
989 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
991 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
992 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
993 struct anv_descriptor_set
*set
=
994 cmd_buffer
->state
.descriptors
[binding
->set
];
995 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
996 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
998 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
999 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1002 struct anv_sampler
*sampler
= desc
->sampler
;
1004 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1005 * happens to be zero.
1007 if (sampler
== NULL
)
1010 memcpy(state
->map
+ (s
* 16),
1011 sampler
->state
, sizeof(sampler
->state
));
1014 if (!cmd_buffer
->device
->info
.has_llc
)
1015 anv_state_clflush(*state
);
1021 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1023 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1024 cmd_buffer
->state
.pipeline
->active_stages
;
1026 VkResult result
= VK_SUCCESS
;
1027 anv_foreach_stage(s
, dirty
) {
1028 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1029 if (result
!= VK_SUCCESS
)
1031 result
= emit_binding_table(cmd_buffer
, s
,
1032 &cmd_buffer
->state
.binding_tables
[s
]);
1033 if (result
!= VK_SUCCESS
)
1037 if (result
!= VK_SUCCESS
) {
1038 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1040 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1041 assert(result
== VK_SUCCESS
);
1043 /* Re-emit state base addresses so we get the new surface state base
1044 * address before we start emitting binding tables etc.
1046 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1048 /* Re-emit all active binding tables */
1049 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
1050 anv_foreach_stage(s
, dirty
) {
1051 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1052 if (result
!= VK_SUCCESS
)
1054 result
= emit_binding_table(cmd_buffer
, s
,
1055 &cmd_buffer
->state
.binding_tables
[s
]);
1056 if (result
!= VK_SUCCESS
)
1061 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1067 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1070 static const uint32_t sampler_state_opcodes
[] = {
1071 [MESA_SHADER_VERTEX
] = 43,
1072 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1073 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1074 [MESA_SHADER_GEOMETRY
] = 46,
1075 [MESA_SHADER_FRAGMENT
] = 47,
1076 [MESA_SHADER_COMPUTE
] = 0,
1079 static const uint32_t binding_table_opcodes
[] = {
1080 [MESA_SHADER_VERTEX
] = 38,
1081 [MESA_SHADER_TESS_CTRL
] = 39,
1082 [MESA_SHADER_TESS_EVAL
] = 40,
1083 [MESA_SHADER_GEOMETRY
] = 41,
1084 [MESA_SHADER_FRAGMENT
] = 42,
1085 [MESA_SHADER_COMPUTE
] = 0,
1088 anv_foreach_stage(s
, stages
) {
1089 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1090 anv_batch_emit(&cmd_buffer
->batch
,
1091 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1092 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1093 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1097 /* Always emit binding table pointers if we're asked to, since on SKL
1098 * this is what flushes push constants. */
1099 anv_batch_emit(&cmd_buffer
->batch
,
1100 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1101 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1102 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1108 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1110 static const uint32_t push_constant_opcodes
[] = {
1111 [MESA_SHADER_VERTEX
] = 21,
1112 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1113 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1114 [MESA_SHADER_GEOMETRY
] = 22,
1115 [MESA_SHADER_FRAGMENT
] = 23,
1116 [MESA_SHADER_COMPUTE
] = 0,
1119 VkShaderStageFlags flushed
= 0;
1121 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
1122 if (stage
== MESA_SHADER_COMPUTE
)
1125 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1127 if (state
.offset
== 0) {
1128 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1129 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1131 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1132 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1133 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1135 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
1136 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1138 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
1139 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1145 flushed
|= mesa_to_vk_shader_stage(stage
);
1148 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1154 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1156 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1159 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1161 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1163 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1165 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1168 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1169 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1171 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1172 GENX(3DSTATE_VERTEX_BUFFERS
));
1174 for_each_bit(vb
, vb_emit
) {
1175 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1176 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1178 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1179 .VertexBufferIndex
= vb
,
1182 .MemoryObjectControlState
= GENX(MOCS
),
1184 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1185 .InstanceDataStepRate
= 1,
1186 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1189 .AddressModifyEnable
= true,
1190 .BufferPitch
= pipeline
->binding_stride
[vb
],
1191 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1194 .BufferSize
= buffer
->size
- offset
1196 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1200 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1205 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1207 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1208 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1210 /* The exact descriptor layout is pulled from the pipeline, so we need
1211 * to re-emit binding tables on every pipeline change.
1213 cmd_buffer
->state
.descriptors_dirty
|=
1214 cmd_buffer
->state
.pipeline
->active_stages
;
1216 /* If the pipeline changed, we may need to re-allocate push constant
1219 cmd_buffer_alloc_push_constants(cmd_buffer
);
1223 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1224 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1225 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1227 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1228 * stall needs to be sent just prior to any 3DSTATE_VS,
1229 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1230 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1231 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1232 * PIPE_CONTROL needs to be sent before any combination of VS
1233 * associated 3DSTATE."
1235 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1236 pc
.DepthStallEnable
= true;
1237 pc
.PostSyncOperation
= WriteImmediateData
;
1239 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1244 /* Render targets live in the same binding table as fragment descriptors */
1245 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1246 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1248 /* We emit the binding tables and sampler tables first, then emit push
1249 * constants and then finally emit binding table and sampler table
1250 * pointers. It has to happen in this order, since emitting the binding
1251 * tables may change the push constants (in case of storage images). After
1252 * emitting push constants, on SKL+ we have to emit the corresponding
1253 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1256 if (cmd_buffer
->state
.descriptors_dirty
)
1257 dirty
= flush_descriptor_sets(cmd_buffer
);
1259 if (cmd_buffer
->state
.push_constants_dirty
) {
1261 /* On Sky Lake and later, the binding table pointers commands are
1262 * what actually flush the changes to push constant state so we need
1263 * to dirty them so they get re-emitted below.
1265 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1267 cmd_buffer_flush_push_constants(cmd_buffer
);
1272 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1274 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1275 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1277 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1278 ANV_CMD_DIRTY_PIPELINE
)) {
1279 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1280 pipeline
->depth_clamp_enable
);
1283 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1284 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1286 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1288 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1292 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1293 struct anv_bo
*bo
, uint32_t offset
)
1295 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1296 GENX(3DSTATE_VERTEX_BUFFERS
));
1298 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1299 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1300 .VertexBufferIndex
= 32, /* Reserved for this */
1301 .AddressModifyEnable
= true,
1304 .MemoryObjectControlState
= GENX(MOCS
),
1305 .BufferStartingAddress
= { bo
, offset
},
1308 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1309 .BufferStartingAddress
= { bo
, offset
},
1310 .EndAddress
= { bo
, offset
+ 8 },
1316 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1317 uint32_t base_vertex
, uint32_t base_instance
)
1319 struct anv_state id_state
=
1320 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1322 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1323 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1325 if (!cmd_buffer
->device
->info
.has_llc
)
1326 anv_state_clflush(id_state
);
1328 emit_base_vertex_instance_bo(cmd_buffer
,
1329 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
1333 VkCommandBuffer commandBuffer
,
1334 uint32_t vertexCount
,
1335 uint32_t instanceCount
,
1336 uint32_t firstVertex
,
1337 uint32_t firstInstance
)
1339 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1340 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1341 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1343 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1345 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1346 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1348 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1349 prim
.VertexAccessType
= SEQUENTIAL
;
1350 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1351 prim
.VertexCountPerInstance
= vertexCount
;
1352 prim
.StartVertexLocation
= firstVertex
;
1353 prim
.InstanceCount
= instanceCount
;
1354 prim
.StartInstanceLocation
= firstInstance
;
1355 prim
.BaseVertexLocation
= 0;
1359 void genX(CmdDrawIndexed
)(
1360 VkCommandBuffer commandBuffer
,
1361 uint32_t indexCount
,
1362 uint32_t instanceCount
,
1363 uint32_t firstIndex
,
1364 int32_t vertexOffset
,
1365 uint32_t firstInstance
)
1367 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1368 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1369 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1371 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1373 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1374 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1376 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1377 prim
.VertexAccessType
= RANDOM
;
1378 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1379 prim
.VertexCountPerInstance
= indexCount
;
1380 prim
.StartVertexLocation
= firstIndex
;
1381 prim
.InstanceCount
= instanceCount
;
1382 prim
.StartInstanceLocation
= firstInstance
;
1383 prim
.BaseVertexLocation
= vertexOffset
;
1387 /* Auto-Draw / Indirect Registers */
1388 #define GEN7_3DPRIM_END_OFFSET 0x2420
1389 #define GEN7_3DPRIM_START_VERTEX 0x2430
1390 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1391 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1392 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1393 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1395 void genX(CmdDrawIndirect
)(
1396 VkCommandBuffer commandBuffer
,
1398 VkDeviceSize offset
,
1402 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1403 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1404 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1405 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1406 struct anv_bo
*bo
= buffer
->bo
;
1407 uint32_t bo_offset
= buffer
->offset
+ offset
;
1409 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1411 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1412 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
1414 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1415 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1416 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1417 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
1418 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
1420 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1421 prim
.IndirectParameterEnable
= true;
1422 prim
.VertexAccessType
= SEQUENTIAL
;
1423 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1427 void genX(CmdDrawIndexedIndirect
)(
1428 VkCommandBuffer commandBuffer
,
1430 VkDeviceSize offset
,
1434 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1435 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1436 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1437 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1438 struct anv_bo
*bo
= buffer
->bo
;
1439 uint32_t bo_offset
= buffer
->offset
+ offset
;
1441 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1443 /* TODO: We need to stomp base vertex to 0 somehow */
1444 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1445 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
1447 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1448 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1449 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1450 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
1451 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
1453 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1454 prim
.IndirectParameterEnable
= true;
1455 prim
.VertexAccessType
= RANDOM
;
1456 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1461 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
1463 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1464 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
1467 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
1468 if (result
!= VK_SUCCESS
)
1470 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1471 if (result
!= VK_SUCCESS
)
1474 struct anv_state push_state
= anv_cmd_buffer_cs_push_constants(cmd_buffer
);
1476 if (push_state
.alloc_size
) {
1477 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
1478 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
1479 curbe
.CURBEDataStartAddress
= push_state
.offset
;
1483 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
1484 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1485 .BindingTablePointer
= surfaces
.offset
,
1486 .SamplerStatePointer
= samplers
.offset
,
1488 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
1490 struct anv_state state
=
1491 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
1492 pipeline
->interface_descriptor_data
,
1493 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
1496 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
1497 anv_batch_emit(&cmd_buffer
->batch
,
1498 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
1499 mid
.InterfaceDescriptorTotalLength
= size
;
1500 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
1507 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1509 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1510 MAYBE_UNUSED VkResult result
;
1512 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
1514 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1516 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
1518 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)
1519 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1521 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
1522 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
1523 /* FIXME: figure out descriptors for gen7 */
1524 result
= flush_compute_descriptor_set(cmd_buffer
);
1525 assert(result
== VK_SUCCESS
);
1526 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
1529 cmd_buffer
->state
.compute_dirty
= 0;
1531 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1537 verify_cmd_parser(const struct anv_device
*device
,
1538 int required_version
,
1539 const char *function
)
1541 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
1542 vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
1543 "cmd parser version %d is required for %s",
1544 required_version
, function
);
1553 void genX(CmdDispatch
)(
1554 VkCommandBuffer commandBuffer
,
1559 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1560 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1561 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1563 if (prog_data
->uses_num_work_groups
) {
1564 struct anv_state state
=
1565 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
1566 uint32_t *sizes
= state
.map
;
1570 if (!cmd_buffer
->device
->info
.has_llc
)
1571 anv_state_clflush(state
);
1572 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
1573 cmd_buffer
->state
.num_workgroups_bo
=
1574 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
1577 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1579 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
1580 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1581 ggw
.ThreadDepthCounterMaximum
= 0;
1582 ggw
.ThreadHeightCounterMaximum
= 0;
1583 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1584 ggw
.ThreadGroupIDXDimension
= x
;
1585 ggw
.ThreadGroupIDYDimension
= y
;
1586 ggw
.ThreadGroupIDZDimension
= z
;
1587 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1588 ggw
.BottomExecutionMask
= 0xffffffff;
1591 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1594 #define GPGPU_DISPATCHDIMX 0x2500
1595 #define GPGPU_DISPATCHDIMY 0x2504
1596 #define GPGPU_DISPATCHDIMZ 0x2508
1598 #define MI_PREDICATE_SRC0 0x2400
1599 #define MI_PREDICATE_SRC1 0x2408
1601 void genX(CmdDispatchIndirect
)(
1602 VkCommandBuffer commandBuffer
,
1604 VkDeviceSize offset
)
1606 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1607 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1608 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1609 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1610 struct anv_bo
*bo
= buffer
->bo
;
1611 uint32_t bo_offset
= buffer
->offset
+ offset
;
1612 struct anv_batch
*batch
= &cmd_buffer
->batch
;
1615 /* Linux 4.4 added command parser version 5 which allows the GPGPU
1616 * indirect dispatch registers to be written.
1618 if (!verify_cmd_parser(cmd_buffer
->device
, 5, "vkCmdDispatchIndirect"))
1622 if (prog_data
->uses_num_work_groups
) {
1623 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
1624 cmd_buffer
->state
.num_workgroups_bo
= bo
;
1627 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1629 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
1630 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
1631 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
1634 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
1635 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
1636 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
1637 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
1639 /* Load compute_dispatch_indirect_x_size into SRC0 */
1640 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
1642 /* predicate = (compute_dispatch_indirect_x_size == 0); */
1643 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1644 mip
.LoadOperation
= LOAD_LOAD
;
1645 mip
.CombineOperation
= COMBINE_SET
;
1646 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1649 /* Load compute_dispatch_indirect_y_size into SRC0 */
1650 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
1652 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
1653 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1654 mip
.LoadOperation
= LOAD_LOAD
;
1655 mip
.CombineOperation
= COMBINE_OR
;
1656 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1659 /* Load compute_dispatch_indirect_z_size into SRC0 */
1660 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
1662 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
1663 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1664 mip
.LoadOperation
= LOAD_LOAD
;
1665 mip
.CombineOperation
= COMBINE_OR
;
1666 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1669 /* predicate = !predicate; */
1670 #define COMPARE_FALSE 1
1671 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1672 mip
.LoadOperation
= LOAD_LOADINV
;
1673 mip
.CombineOperation
= COMBINE_OR
;
1674 mip
.CompareOperation
= COMPARE_FALSE
;
1678 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
1679 ggw
.IndirectParameterEnable
= true;
1680 ggw
.PredicateEnable
= GEN_GEN
<= 7;
1681 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1682 ggw
.ThreadDepthCounterMaximum
= 0;
1683 ggw
.ThreadHeightCounterMaximum
= 0;
1684 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1685 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1686 ggw
.BottomExecutionMask
= 0xffffffff;
1689 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1693 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
1696 #if GEN_GEN >= 8 && GEN_GEN < 10
1697 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
1699 * Software must clear the COLOR_CALC_STATE Valid field in
1700 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
1701 * with Pipeline Select set to GPGPU.
1703 * The internal hardware docs recommend the same workaround for Gen9
1706 if (pipeline
== GPGPU
)
1707 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
1709 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
1710 * PIPELINE_SELECT [DevBWR+]":
1714 * Software must ensure all the write caches are flushed through a
1715 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
1716 * command to invalidate read only caches prior to programming
1717 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
1719 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1720 pc
.RenderTargetCacheFlushEnable
= true;
1721 pc
.DepthCacheFlushEnable
= true;
1722 pc
.DCFlushEnable
= true;
1723 pc
.PostSyncOperation
= NoWrite
;
1724 pc
.CommandStreamerStallEnable
= true;
1727 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1728 pc
.TextureCacheInvalidationEnable
= true;
1729 pc
.ConstantCacheInvalidationEnable
= true;
1730 pc
.StateCacheInvalidationEnable
= true;
1731 pc
.InstructionCacheInvalidateEnable
= true;
1732 pc
.PostSyncOperation
= NoWrite
;
1738 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
1740 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
1741 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
1743 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
1747 ps
.PipelineSelection
= _3D
;
1750 cmd_buffer
->state
.current_pipeline
= _3D
;
1755 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
1757 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
1758 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
1760 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
1764 ps
.PipelineSelection
= GPGPU
;
1767 cmd_buffer
->state
.current_pipeline
= GPGPU
;
1772 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
1774 struct anv_device
*device
= cmd_buffer
->device
;
1775 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1776 const struct anv_image_view
*iview
=
1777 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1778 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
1779 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1780 const bool has_hiz
= image
!= NULL
&& anv_image_has_hiz(image
);
1781 const bool has_stencil
=
1782 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1784 /* FIXME: Implement the PMA stall W/A */
1785 /* FIXME: Width and Height are wrong */
1787 /* Emit 3DSTATE_DEPTH_BUFFER */
1789 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
1790 db
.SurfaceType
= SURFTYPE_2D
;
1791 db
.DepthWriteEnable
= true;
1792 db
.StencilWriteEnable
= has_stencil
;
1794 if (cmd_buffer
->state
.pass
->subpass_count
== 1) {
1795 db
.HierarchicalDepthBufferEnable
= has_hiz
;
1797 anv_finishme("Multiple-subpass HiZ not implemented");
1800 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
1801 &image
->depth_surface
.isl
);
1803 db
.SurfaceBaseAddress
= (struct anv_address
) {
1805 .offset
= image
->offset
+ image
->depth_surface
.offset
,
1807 db
.DepthBufferObjectControlState
= GENX(MOCS
);
1809 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
1810 db
.Height
= image
->extent
.height
- 1;
1811 db
.Width
= image
->extent
.width
- 1;
1812 db
.LOD
= iview
->isl
.base_level
;
1813 db
.Depth
= image
->array_size
- 1; /* FIXME: 3-D */
1814 db
.MinimumArrayElement
= iview
->isl
.base_array_layer
;
1818 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2;
1820 db
.RenderTargetViewExtent
= 1 - 1;
1823 /* Even when no depth buffer is present, the hardware requires that
1824 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
1826 * If a null depth buffer is bound, the driver must instead bind depth as:
1827 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
1828 * 3DSTATE_DEPTH.Width = 1
1829 * 3DSTATE_DEPTH.Height = 1
1830 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
1831 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
1832 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
1833 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
1834 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
1836 * The PRM is wrong, though. The width and height must be programmed to
1837 * actual framebuffer's width and height, even when neither depth buffer
1838 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
1839 * be combined with a stencil buffer so we use D32_FLOAT instead.
1841 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
1842 db
.SurfaceType
= SURFTYPE_2D
;
1843 db
.SurfaceFormat
= D32_FLOAT
;
1844 db
.Width
= fb
->width
- 1;
1845 db
.Height
= fb
->height
- 1;
1846 db
.StencilWriteEnable
= has_stencil
;
1851 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
) {
1852 hdb
.HierarchicalDepthBufferObjectControlState
= GENX(MOCS
);
1853 hdb
.SurfacePitch
= image
->aux_surface
.isl
.row_pitch
- 1;
1854 hdb
.SurfaceBaseAddress
= (struct anv_address
) {
1856 .offset
= image
->offset
+ image
->aux_surface
.offset
,
1859 /* From the SKL PRM Vol2a:
1861 * The interpretation of this field is dependent on Surface Type
1863 * - SURFTYPE_1D: distance in pixels between array slices
1864 * - SURFTYPE_2D/CUBE: distance in rows between array slices
1865 * - SURFTYPE_3D: distance in rows between R - slices
1868 image
->aux_surface
.isl
.dim
== ISL_SURF_DIM_1D
?
1869 isl_surf_get_array_pitch_el(&image
->aux_surface
.isl
) >> 2 :
1870 isl_surf_get_array_pitch_el_rows(&image
->aux_surface
.isl
) >> 2;
1874 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
);
1877 /* Emit 3DSTATE_STENCIL_BUFFER */
1879 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
1880 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1881 sb
.StencilBufferEnable
= true;
1883 sb
.StencilBufferObjectControlState
= GENX(MOCS
);
1885 sb
.SurfacePitch
= image
->stencil_surface
.isl
.row_pitch
- 1;
1888 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2;
1890 sb
.SurfaceBaseAddress
= (struct anv_address
) {
1892 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
1896 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
1899 /* From the IVB PRM Vol2P1, 11.5.5.4 3DSTATE_CLEAR_PARAMS:
1901 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along with
1902 * the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
1903 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)
1905 * Testing also shows that some variant of this restriction may exist HSW+.
1906 * On BDW+, it is not possible to emit 2 of these packets consecutively when
1907 * both have DepthClearValueValid set. An analysis of such state programming
1908 * on SKL showed that the GPU doesn't register the latter packet's clear
1911 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
) {
1913 cp
.DepthClearValueValid
= true;
1915 cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
1916 cp
.DepthClearValue
=
1917 cmd_buffer
->state
.attachments
[ds
].clear_value
.depthStencil
.depth
;
1923 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
1924 struct anv_subpass
*subpass
)
1926 cmd_buffer
->state
.subpass
= subpass
;
1928 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1930 cmd_buffer_emit_depth_stencil(cmd_buffer
);
1931 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_HIZ_RESOLVE
);
1932 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_DEPTH_CLEAR
);
1934 anv_cmd_buffer_clear_subpass(cmd_buffer
);
1937 void genX(CmdBeginRenderPass
)(
1938 VkCommandBuffer commandBuffer
,
1939 const VkRenderPassBeginInfo
* pRenderPassBegin
,
1940 VkSubpassContents contents
)
1942 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1943 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
1944 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
1946 cmd_buffer
->state
.framebuffer
= framebuffer
;
1947 cmd_buffer
->state
.pass
= pass
;
1948 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
1949 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, framebuffer
,
1950 pRenderPassBegin
->pClearValues
);
1952 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1954 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
1957 void genX(CmdNextSubpass
)(
1958 VkCommandBuffer commandBuffer
,
1959 VkSubpassContents contents
)
1961 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1963 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1965 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
1966 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
1969 void genX(CmdEndRenderPass
)(
1970 VkCommandBuffer commandBuffer
)
1972 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1974 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_DEPTH_RESOLVE
);
1975 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
1978 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
1983 emit_ps_depth_count(struct anv_cmd_buffer
*cmd_buffer
,
1984 struct anv_bo
*bo
, uint32_t offset
)
1986 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1987 pc
.DestinationAddressType
= DAT_PPGTT
;
1988 pc
.PostSyncOperation
= WritePSDepthCount
;
1989 pc
.DepthStallEnable
= true;
1990 pc
.Address
= (struct anv_address
) { bo
, offset
};
1992 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
1993 pc
.CommandStreamerStallEnable
= true;
1998 emit_query_availability(struct anv_cmd_buffer
*cmd_buffer
,
1999 struct anv_bo
*bo
, uint32_t offset
)
2001 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2002 pc
.DestinationAddressType
= DAT_PPGTT
;
2003 pc
.PostSyncOperation
= WriteImmediateData
;
2004 pc
.Address
= (struct anv_address
) { bo
, offset
};
2005 pc
.ImmediateData
= 1;
2009 void genX(CmdBeginQuery
)(
2010 VkCommandBuffer commandBuffer
,
2011 VkQueryPool queryPool
,
2013 VkQueryControlFlags flags
)
2015 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2016 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2018 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
2019 * that the pipelining of the depth write breaks. What we see is that
2020 * samples from the render pass clear leaks into the first query
2021 * immediately after the clear. Doing a pipecontrol with a post-sync
2022 * operation and DepthStallEnable seems to work around the issue.
2024 if (cmd_buffer
->state
.need_query_wa
) {
2025 cmd_buffer
->state
.need_query_wa
= false;
2026 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2027 pc
.DepthCacheFlushEnable
= true;
2028 pc
.DepthStallEnable
= true;
2032 switch (pool
->type
) {
2033 case VK_QUERY_TYPE_OCCLUSION
:
2034 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2035 query
* sizeof(struct anv_query_pool_slot
));
2038 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2044 void genX(CmdEndQuery
)(
2045 VkCommandBuffer commandBuffer
,
2046 VkQueryPool queryPool
,
2049 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2050 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2052 switch (pool
->type
) {
2053 case VK_QUERY_TYPE_OCCLUSION
:
2054 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2055 query
* sizeof(struct anv_query_pool_slot
) + 8);
2057 emit_query_availability(cmd_buffer
, &pool
->bo
,
2058 query
* sizeof(struct anv_query_pool_slot
) + 16);
2061 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2067 #define TIMESTAMP 0x2358
2069 void genX(CmdWriteTimestamp
)(
2070 VkCommandBuffer commandBuffer
,
2071 VkPipelineStageFlagBits pipelineStage
,
2072 VkQueryPool queryPool
,
2075 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2076 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2077 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
2079 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
2081 switch (pipelineStage
) {
2082 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
2083 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2084 srm
.RegisterAddress
= TIMESTAMP
;
2085 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
};
2087 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2088 srm
.RegisterAddress
= TIMESTAMP
+ 4;
2089 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
+ 4 };
2094 /* Everything else is bottom-of-pipe */
2095 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2096 pc
.DestinationAddressType
= DAT_PPGTT
;
2097 pc
.PostSyncOperation
= WriteTimestamp
;
2098 pc
.Address
= (struct anv_address
) { &pool
->bo
, offset
};
2100 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2101 pc
.CommandStreamerStallEnable
= true;
2106 emit_query_availability(cmd_buffer
, &pool
->bo
, query
+ 16);
2109 #if GEN_GEN > 7 || GEN_IS_HASWELL
2111 #define alu_opcode(v) __gen_uint((v), 20, 31)
2112 #define alu_operand1(v) __gen_uint((v), 10, 19)
2113 #define alu_operand2(v) __gen_uint((v), 0, 9)
2114 #define alu(opcode, operand1, operand2) \
2115 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
2117 #define OPCODE_NOOP 0x000
2118 #define OPCODE_LOAD 0x080
2119 #define OPCODE_LOADINV 0x480
2120 #define OPCODE_LOAD0 0x081
2121 #define OPCODE_LOAD1 0x481
2122 #define OPCODE_ADD 0x100
2123 #define OPCODE_SUB 0x101
2124 #define OPCODE_AND 0x102
2125 #define OPCODE_OR 0x103
2126 #define OPCODE_XOR 0x104
2127 #define OPCODE_STORE 0x180
2128 #define OPCODE_STOREINV 0x580
2130 #define OPERAND_R0 0x00
2131 #define OPERAND_R1 0x01
2132 #define OPERAND_R2 0x02
2133 #define OPERAND_R3 0x03
2134 #define OPERAND_R4 0x04
2135 #define OPERAND_SRCA 0x20
2136 #define OPERAND_SRCB 0x21
2137 #define OPERAND_ACCU 0x31
2138 #define OPERAND_ZF 0x32
2139 #define OPERAND_CF 0x33
2141 #define CS_GPR(n) (0x2600 + (n) * 8)
2144 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
2145 struct anv_bo
*bo
, uint32_t offset
)
2147 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2148 lrm
.RegisterAddress
= reg
,
2149 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2151 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2152 lrm
.RegisterAddress
= reg
+ 4;
2153 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2158 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
2159 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
2161 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2162 srm
.RegisterAddress
= reg
;
2163 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2166 if (flags
& VK_QUERY_RESULT_64_BIT
) {
2167 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2168 srm
.RegisterAddress
= reg
+ 4;
2169 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2174 void genX(CmdCopyQueryPoolResults
)(
2175 VkCommandBuffer commandBuffer
,
2176 VkQueryPool queryPool
,
2177 uint32_t firstQuery
,
2178 uint32_t queryCount
,
2179 VkBuffer destBuffer
,
2180 VkDeviceSize destOffset
,
2181 VkDeviceSize destStride
,
2182 VkQueryResultFlags flags
)
2184 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2185 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2186 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
2187 uint32_t slot_offset
, dst_offset
;
2189 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
2190 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2191 pc
.CommandStreamerStallEnable
= true;
2192 pc
.StallAtPixelScoreboard
= true;
2196 dst_offset
= buffer
->offset
+ destOffset
;
2197 for (uint32_t i
= 0; i
< queryCount
; i
++) {
2199 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
2200 switch (pool
->type
) {
2201 case VK_QUERY_TYPE_OCCLUSION
:
2202 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2203 CS_GPR(0), &pool
->bo
, slot_offset
);
2204 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2205 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
2207 /* FIXME: We need to clamp the result for 32 bit. */
2209 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
2210 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
2211 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
2212 dw
[3] = alu(OPCODE_SUB
, 0, 0);
2213 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
2216 case VK_QUERY_TYPE_TIMESTAMP
:
2217 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2218 CS_GPR(2), &pool
->bo
, slot_offset
);
2222 unreachable("unhandled query type");
2225 store_query_result(&cmd_buffer
->batch
,
2226 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
2228 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
2229 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
2230 &pool
->bo
, slot_offset
+ 16);
2231 if (flags
& VK_QUERY_RESULT_64_BIT
)
2232 store_query_result(&cmd_buffer
->batch
,
2233 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
2235 store_query_result(&cmd_buffer
->batch
,
2236 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
2239 dst_offset
+= destStride
;
2244 void genX(CmdCopyQueryPoolResults
)(
2245 VkCommandBuffer commandBuffer
,
2246 VkQueryPool queryPool
,
2247 uint32_t firstQuery
,
2248 uint32_t queryCount
,
2249 VkBuffer destBuffer
,
2250 VkDeviceSize destOffset
,
2251 VkDeviceSize destStride
,
2252 VkQueryResultFlags flags
)
2254 anv_finishme("Queries not yet supported on Ivy Bridge");