2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
37 /* We reserve GPR 14 and 15 for conditional rendering */
38 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
39 #define __gen_get_batch_dwords anv_batch_emit_dwords
40 #define __gen_address_offset anv_address_add
41 #include "common/gen_mi_builder.h"
44 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
46 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
47 lri
.RegisterOffset
= reg
;
53 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
55 struct anv_device
*device
= cmd_buffer
->device
;
57 /* If we are emitting a new state base address we probably need to re-emit
60 cmd_buffer
->state
.descriptors_dirty
|= ~0;
62 /* Emit a render target cache flush.
64 * This isn't documented anywhere in the PRM. However, it seems to be
65 * necessary prior to changing the surface state base adress. Without
66 * this, we get GPU hangs when using multi-level command buffers which
67 * clear depth, reset state base address, and then go render stuff.
69 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
70 pc
.DCFlushEnable
= true;
71 pc
.RenderTargetCacheFlushEnable
= true;
72 pc
.CommandStreamerStallEnable
= true;
74 pc
.TileCacheFlushEnable
= true;
78 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
79 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
80 sba
.GeneralStateMOCS
= GENX(MOCS
);
81 sba
.GeneralStateBaseAddressModifyEnable
= true;
83 sba
.StatelessDataPortAccessMOCS
= GENX(MOCS
);
85 sba
.SurfaceStateBaseAddress
=
86 anv_cmd_buffer_surface_base_address(cmd_buffer
);
87 sba
.SurfaceStateMOCS
= GENX(MOCS
);
88 sba
.SurfaceStateBaseAddressModifyEnable
= true;
90 sba
.DynamicStateBaseAddress
=
91 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
92 sba
.DynamicStateMOCS
= GENX(MOCS
);
93 sba
.DynamicStateBaseAddressModifyEnable
= true;
95 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
96 sba
.IndirectObjectMOCS
= GENX(MOCS
);
97 sba
.IndirectObjectBaseAddressModifyEnable
= true;
99 sba
.InstructionBaseAddress
=
100 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
101 sba
.InstructionMOCS
= GENX(MOCS
);
102 sba
.InstructionBaseAddressModifyEnable
= true;
105 /* Broadwell requires that we specify a buffer size for a bunch of
106 * these fields. However, since we will be growing the BO's live, we
107 * just set them all to the maximum.
109 sba
.GeneralStateBufferSize
= 0xfffff;
110 sba
.GeneralStateBufferSizeModifyEnable
= true;
111 sba
.DynamicStateBufferSize
= 0xfffff;
112 sba
.DynamicStateBufferSizeModifyEnable
= true;
113 sba
.IndirectObjectBufferSize
= 0xfffff;
114 sba
.IndirectObjectBufferSizeModifyEnable
= true;
115 sba
.InstructionBufferSize
= 0xfffff;
116 sba
.InstructionBuffersizeModifyEnable
= true;
118 /* On gen7, we have upper bounds instead. According to the docs,
119 * setting an upper bound of zero means that no bounds checking is
120 * performed so, in theory, we should be able to leave them zero.
121 * However, border color is broken and the GPU bounds-checks anyway.
122 * To avoid this and other potential problems, we may as well set it
125 sba
.GeneralStateAccessUpperBound
=
126 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
127 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
128 sba
.DynamicStateAccessUpperBound
=
129 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
130 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
131 sba
.InstructionAccessUpperBound
=
132 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
133 sba
.InstructionAccessUpperBoundModifyEnable
= true;
136 if (cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
) {
137 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
138 .bo
= device
->surface_state_pool
.block_pool
.bo
,
141 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
143 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
144 sba
.BindlessSurfaceStateSize
= 0;
146 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
147 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
150 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
151 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
152 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
153 sba
.BindlessSamplerStateBufferSize
= 0;
157 /* After re-setting the surface state base address, we have to do some
158 * cache flusing so that the sampler engine will pick up the new
159 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
160 * Shared Function > 3D Sampler > State > State Caching (page 96):
162 * Coherency with system memory in the state cache, like the texture
163 * cache is handled partially by software. It is expected that the
164 * command stream or shader will issue Cache Flush operation or
165 * Cache_Flush sampler message to ensure that the L1 cache remains
166 * coherent with system memory.
170 * Whenever the value of the Dynamic_State_Base_Addr,
171 * Surface_State_Base_Addr are altered, the L1 state cache must be
172 * invalidated to ensure the new surface or sampler state is fetched
173 * from system memory.
175 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
176 * which, according the PIPE_CONTROL instruction documentation in the
179 * Setting this bit is independent of any other bit in this packet.
180 * This bit controls the invalidation of the L1 and L2 state caches
181 * at the top of the pipe i.e. at the parsing time.
183 * Unfortunately, experimentation seems to indicate that state cache
184 * invalidation through a PIPE_CONTROL does nothing whatsoever in
185 * regards to surface state and binding tables. In stead, it seems that
186 * invalidating the texture cache is what is actually needed.
188 * XXX: As far as we have been able to determine through
189 * experimentation, shows that flush the texture cache appears to be
190 * sufficient. The theory here is that all of the sampling/rendering
191 * units cache the binding table in the texture cache. However, we have
192 * yet to be able to actually confirm this.
194 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
195 pc
.TextureCacheInvalidationEnable
= true;
196 pc
.ConstantCacheInvalidationEnable
= true;
197 pc
.StateCacheInvalidationEnable
= true;
202 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
203 struct anv_state state
, struct anv_address addr
)
205 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
208 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
209 state
.offset
+ isl_dev
->ss
.addr_offset
,
210 addr
.bo
, addr
.offset
, NULL
);
211 if (result
!= VK_SUCCESS
)
212 anv_batch_set_error(&cmd_buffer
->batch
, result
);
216 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
217 struct anv_surface_state state
)
219 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
221 assert(!anv_address_is_null(state
.address
));
222 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
224 if (!anv_address_is_null(state
.aux_address
)) {
226 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
227 &cmd_buffer
->pool
->alloc
,
228 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
229 state
.aux_address
.bo
,
230 state
.aux_address
.offset
,
232 if (result
!= VK_SUCCESS
)
233 anv_batch_set_error(&cmd_buffer
->batch
, result
);
236 if (!anv_address_is_null(state
.clear_address
)) {
238 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
239 &cmd_buffer
->pool
->alloc
,
241 isl_dev
->ss
.clear_color_state_offset
,
242 state
.clear_address
.bo
,
243 state
.clear_address
.offset
,
245 if (result
!= VK_SUCCESS
)
246 anv_batch_set_error(&cmd_buffer
->batch
, result
);
251 color_attachment_compute_aux_usage(struct anv_device
* device
,
252 struct anv_cmd_state
* cmd_state
,
253 uint32_t att
, VkRect2D render_area
,
254 union isl_color_value
*fast_clear_color
)
256 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
257 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
259 assert(iview
->n_planes
== 1);
261 if (iview
->planes
[0].isl
.base_array_layer
>=
262 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
263 iview
->planes
[0].isl
.base_level
)) {
264 /* There is no aux buffer which corresponds to the level and layer(s)
267 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
268 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
269 att_state
->fast_clear
= false;
273 att_state
->aux_usage
=
274 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
275 VK_IMAGE_ASPECT_COLOR_BIT
,
276 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
278 /* If we don't have aux, then we should have returned early in the layer
279 * check above. If we got here, we must have something.
281 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
283 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
284 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
285 att_state
->input_aux_usage
= att_state
->aux_usage
;
287 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
289 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
290 * setting is only allowed if Surface Format supported for Fast
291 * Clear. In addition, if the surface is bound to the sampling
292 * engine, Surface Format must be supported for Render Target
293 * Compression for surfaces bound to the sampling engine."
295 * In other words, we can only sample from a fast-cleared image if it
296 * also supports color compression.
298 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
) &&
299 isl_format_supports_ccs_d(&device
->info
, iview
->planes
[0].isl
.format
)) {
300 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
302 /* While fast-clear resolves and partial resolves are fairly cheap in the
303 * case where you render to most of the pixels, full resolves are not
304 * because they potentially involve reading and writing the entire
305 * framebuffer. If we can't texture with CCS_E, we should leave it off and
306 * limit ourselves to fast clears.
308 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
309 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
310 anv_perf_warn(device
->instance
, iview
->image
,
311 "Not temporarily enabling CCS_E.");
314 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
318 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
319 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
321 union isl_color_value clear_color
= {};
322 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
324 att_state
->clear_color_is_zero_one
=
325 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
326 att_state
->clear_color_is_zero
=
327 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
329 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
330 /* Start by getting the fast clear type. We use the first subpass
331 * layout here because we don't want to fast-clear if the first subpass
332 * to use the attachment can't handle fast-clears.
334 enum anv_fast_clear_type fast_clear_type
=
335 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
336 VK_IMAGE_ASPECT_COLOR_BIT
,
337 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
338 switch (fast_clear_type
) {
339 case ANV_FAST_CLEAR_NONE
:
340 att_state
->fast_clear
= false;
342 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
343 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
345 case ANV_FAST_CLEAR_ANY
:
346 att_state
->fast_clear
= true;
350 /* Potentially, we could do partial fast-clears but doing so has crazy
351 * alignment restrictions. It's easier to just restrict to full size
352 * fast clears for now.
354 if (render_area
.offset
.x
!= 0 ||
355 render_area
.offset
.y
!= 0 ||
356 render_area
.extent
.width
!= iview
->extent
.width
||
357 render_area
.extent
.height
!= iview
->extent
.height
)
358 att_state
->fast_clear
= false;
360 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
361 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
362 att_state
->fast_clear
= false;
364 /* We only allow fast clears to the first slice of an image (level 0,
365 * layer 0) and only for the entire slice. This guarantees us that, at
366 * any given time, there is only one clear color on any given image at
367 * any given time. At the time of our testing (Jan 17, 2018), there
368 * were no known applications which would benefit from fast-clearing
369 * more than just the first slice.
371 if (att_state
->fast_clear
&&
372 (iview
->planes
[0].isl
.base_level
> 0 ||
373 iview
->planes
[0].isl
.base_array_layer
> 0)) {
374 anv_perf_warn(device
->instance
, iview
->image
,
375 "Rendering with multi-lod or multi-layer framebuffer "
376 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
377 "baseArrayLayer > 0. Not fast clearing.");
378 att_state
->fast_clear
= false;
379 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
380 anv_perf_warn(device
->instance
, iview
->image
,
381 "Rendering to a multi-layer framebuffer with "
382 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
385 if (att_state
->fast_clear
)
386 *fast_clear_color
= clear_color
;
388 att_state
->fast_clear
= false;
393 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
394 struct anv_cmd_state
*cmd_state
,
395 uint32_t att
, VkRect2D render_area
)
397 struct anv_render_pass_attachment
*pass_att
=
398 &cmd_state
->pass
->attachments
[att
];
399 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
400 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
402 /* These will be initialized after the first subpass transition. */
403 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
404 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
407 /* We don't do any HiZ or depth fast-clears on gen7 yet */
408 att_state
->fast_clear
= false;
412 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
413 /* If we're just clearing stencil, we can always HiZ clear */
414 att_state
->fast_clear
= true;
418 /* Default to false for now */
419 att_state
->fast_clear
= false;
421 /* We must have depth in order to have HiZ */
422 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
425 const enum isl_aux_usage first_subpass_aux_usage
=
426 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
427 VK_IMAGE_ASPECT_DEPTH_BIT
,
428 pass_att
->first_subpass_layout
);
429 if (!blorp_can_hiz_clear_depth(&device
->info
,
430 &iview
->image
->planes
[0].surface
.isl
,
431 first_subpass_aux_usage
,
432 iview
->planes
[0].isl
.base_level
,
433 iview
->planes
[0].isl
.base_array_layer
,
434 render_area
.offset
.x
,
435 render_area
.offset
.y
,
436 render_area
.offset
.x
+
437 render_area
.extent
.width
,
438 render_area
.offset
.y
+
439 render_area
.extent
.height
))
442 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
445 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
446 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
447 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
448 * only supports returning 0.0f. Gens prior to gen8 do not support this
454 /* If we got here, then we can fast clear */
455 att_state
->fast_clear
= true;
459 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
461 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
464 /* We only allocate input attachment states for color surfaces. Compression
465 * is not yet enabled for depth textures and stencil doesn't allow
466 * compression so we can just use the texture surface state from the view.
468 return vk_format_is_color(att
->format
);
471 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
472 * the initial layout is undefined, the HiZ buffer and depth buffer will
473 * represent the same data at the end of this operation.
476 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
477 const struct anv_image
*image
,
478 VkImageLayout initial_layout
,
479 VkImageLayout final_layout
)
481 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
482 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
483 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
484 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
485 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
486 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
488 enum isl_aux_op hiz_op
;
489 if (hiz_enabled
&& !enable_hiz
) {
490 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
491 } else if (!hiz_enabled
&& enable_hiz
) {
492 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
494 assert(hiz_enabled
== enable_hiz
);
495 /* If the same buffer will be used, no resolves are necessary. */
496 hiz_op
= ISL_AUX_OP_NONE
;
499 if (hiz_op
!= ISL_AUX_OP_NONE
)
500 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
505 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
507 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
508 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
;
511 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
512 * the initial layout is undefined, the HiZ buffer and depth buffer will
513 * represent the same data at the end of this operation.
516 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
517 const struct anv_image
*image
,
518 uint32_t base_level
, uint32_t level_count
,
519 uint32_t base_layer
, uint32_t layer_count
,
520 VkImageLayout initial_layout
,
521 VkImageLayout final_layout
)
524 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
525 VK_IMAGE_ASPECT_STENCIL_BIT
);
527 /* On gen7, we have to store a texturable version of the stencil buffer in
528 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
529 * forth at strategic points. Stencil writes are only allowed in three
532 * - VK_IMAGE_LAYOUT_GENERAL
533 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
534 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
535 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
537 * For general, we have no nice opportunity to transition so we do the copy
538 * to the shadow unconditionally at the end of the subpass. For transfer
539 * destinations, we can update it as part of the transfer op. For the
540 * other two, we delay the copy until a transition into some other layout.
542 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
543 vk_image_layout_stencil_write_optimal(initial_layout
) &&
544 !vk_image_layout_stencil_write_optimal(final_layout
)) {
545 anv_image_copy_to_shadow(cmd_buffer
, image
,
546 VK_IMAGE_ASPECT_STENCIL_BIT
,
547 base_level
, level_count
,
548 base_layer
, layer_count
);
550 #endif /* GEN_GEN == 7 */
553 #define MI_PREDICATE_SRC0 0x2400
554 #define MI_PREDICATE_SRC1 0x2408
555 #define MI_PREDICATE_RESULT 0x2418
558 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
559 const struct anv_image
*image
,
560 VkImageAspectFlagBits aspect
,
562 uint32_t base_layer
, uint32_t layer_count
,
565 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
567 /* We only have compression tracking for CCS_E */
568 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
571 for (uint32_t a
= 0; a
< layer_count
; a
++) {
572 uint32_t layer
= base_layer
+ a
;
573 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
574 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
577 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
583 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
584 const struct anv_image
*image
,
585 VkImageAspectFlagBits aspect
,
586 enum anv_fast_clear_type fast_clear
)
588 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
589 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
591 sdi
.ImmediateData
= fast_clear
;
594 /* Whenever we have fast-clear, we consider that slice to be compressed.
595 * This makes building predicates much easier.
597 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
598 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
601 /* This is only really practical on haswell and above because it requires
602 * MI math in order to get it correct.
604 #if GEN_GEN >= 8 || GEN_IS_HASWELL
606 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
607 const struct anv_image
*image
,
608 VkImageAspectFlagBits aspect
,
609 uint32_t level
, uint32_t array_layer
,
610 enum isl_aux_op resolve_op
,
611 enum anv_fast_clear_type fast_clear_supported
)
613 struct gen_mi_builder b
;
614 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
616 const struct gen_mi_value fast_clear_type
=
617 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
620 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
621 /* In this case, we're doing a full resolve which means we want the
622 * resolve to happen if any compression (including fast-clears) is
625 * In order to simplify the logic a bit, we make the assumption that,
626 * if the first slice has been fast-cleared, it is also marked as
627 * compressed. See also set_image_fast_clear_state.
629 const struct gen_mi_value compression_state
=
630 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
632 level
, array_layer
));
633 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
635 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
637 if (level
== 0 && array_layer
== 0) {
638 /* If the predicate is true, we want to write 0 to the fast clear type
639 * and, if it's false, leave it alone. We can do this by writing
641 * clear_type = clear_type & ~predicate;
643 struct gen_mi_value new_fast_clear_type
=
644 gen_mi_iand(&b
, fast_clear_type
,
645 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
646 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
648 } else if (level
== 0 && array_layer
== 0) {
649 /* In this case, we are doing a partial resolve to get rid of fast-clear
650 * colors. We don't care about the compression state but we do care
651 * about how much fast clear is allowed by the final layout.
653 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
654 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
656 /* We need to compute (fast_clear_supported < image->fast_clear) */
657 struct gen_mi_value pred
=
658 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
659 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
660 gen_mi_value_ref(&b
, pred
));
662 /* If the predicate is true, we want to write 0 to the fast clear type
663 * and, if it's false, leave it alone. We can do this by writing
665 * clear_type = clear_type & ~predicate;
667 struct gen_mi_value new_fast_clear_type
=
668 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
669 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
671 /* In this case, we're trying to do a partial resolve on a slice that
672 * doesn't have clear color. There's nothing to do.
674 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
678 /* Set src1 to 0 and use a != condition */
679 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
681 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
682 mip
.LoadOperation
= LOAD_LOADINV
;
683 mip
.CombineOperation
= COMBINE_SET
;
684 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
687 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
691 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
692 const struct anv_image
*image
,
693 VkImageAspectFlagBits aspect
,
694 uint32_t level
, uint32_t array_layer
,
695 enum isl_aux_op resolve_op
,
696 enum anv_fast_clear_type fast_clear_supported
)
698 struct gen_mi_builder b
;
699 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
701 struct gen_mi_value fast_clear_type_mem
=
702 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
705 /* This only works for partial resolves and only when the clear color is
706 * all or nothing. On the upside, this emits less command streamer code
707 * and works on Ivybridge and Bay Trail.
709 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
710 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
712 /* We don't support fast clears on anything other than the first slice. */
713 if (level
> 0 || array_layer
> 0)
716 /* On gen8, we don't have a concept of default clear colors because we
717 * can't sample from CCS surfaces. It's enough to just load the fast clear
718 * state into the predicate register.
720 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
721 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
722 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
724 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
725 mip
.LoadOperation
= LOAD_LOADINV
;
726 mip
.CombineOperation
= COMBINE_SET
;
727 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
730 #endif /* GEN_GEN <= 8 */
733 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
734 const struct anv_image
*image
,
735 enum isl_format format
,
736 VkImageAspectFlagBits aspect
,
737 uint32_t level
, uint32_t array_layer
,
738 enum isl_aux_op resolve_op
,
739 enum anv_fast_clear_type fast_clear_supported
)
741 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
744 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
745 aspect
, level
, array_layer
,
746 resolve_op
, fast_clear_supported
);
747 #else /* GEN_GEN <= 8 */
748 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
749 aspect
, level
, array_layer
,
750 resolve_op
, fast_clear_supported
);
753 /* CCS_D only supports full resolves and BLORP will assert on us if we try
754 * to do a partial resolve on a CCS_D surface.
756 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
757 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
758 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
760 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
761 array_layer
, 1, resolve_op
, NULL
, true);
765 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
766 const struct anv_image
*image
,
767 enum isl_format format
,
768 VkImageAspectFlagBits aspect
,
769 uint32_t array_layer
,
770 enum isl_aux_op resolve_op
,
771 enum anv_fast_clear_type fast_clear_supported
)
773 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
774 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
776 #if GEN_GEN >= 8 || GEN_IS_HASWELL
777 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
778 aspect
, 0, array_layer
,
779 resolve_op
, fast_clear_supported
);
781 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
782 array_layer
, 1, resolve_op
, NULL
, true);
784 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
789 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
790 const struct anv_image
*image
,
791 VkImageAspectFlagBits aspect
,
792 enum isl_aux_usage aux_usage
,
795 uint32_t layer_count
)
797 /* The aspect must be exactly one of the image aspects. */
798 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
800 /* The only compression types with more than just fast-clears are MCS,
801 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
802 * track the current fast-clear and compression state. This leaves us
803 * with just MCS and CCS_E.
805 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
806 aux_usage
!= ISL_AUX_USAGE_MCS
)
809 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
810 level
, base_layer
, layer_count
, true);
814 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
815 const struct anv_image
*image
,
816 VkImageAspectFlagBits aspect
)
818 assert(cmd_buffer
&& image
);
819 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
821 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
822 ANV_FAST_CLEAR_NONE
);
824 /* Initialize the struct fields that are accessed for fast-clears so that
825 * the HW restrictions on the field values are satisfied.
827 struct anv_address addr
=
828 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
831 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
832 const unsigned num_dwords
= GEN_GEN
>= 10 ?
833 isl_dev
->ss
.clear_color_state_size
/ 4 :
834 isl_dev
->ss
.clear_value_size
/ 4;
835 for (unsigned i
= 0; i
< num_dwords
; i
++) {
836 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
838 sdi
.Address
.offset
+= i
* 4;
839 sdi
.ImmediateData
= 0;
843 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
845 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
846 /* Pre-SKL, the dword containing the clear values also contains
847 * other fields, so we need to initialize those fields to match the
848 * values that would be in a color attachment.
850 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
851 ISL_CHANNEL_SELECT_GREEN
<< 22 |
852 ISL_CHANNEL_SELECT_BLUE
<< 19 |
853 ISL_CHANNEL_SELECT_ALPHA
<< 16;
854 } else if (GEN_GEN
== 7) {
855 /* On IVB, the dword containing the clear values also contains
856 * other fields that must be zero or can be zero.
858 sdi
.ImmediateData
= 0;
864 /* Copy the fast-clear value dword(s) between a surface state object and an
865 * image's fast clear state buffer.
868 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
869 struct anv_state surface_state
,
870 const struct anv_image
*image
,
871 VkImageAspectFlagBits aspect
,
872 bool copy_from_surface_state
)
874 assert(cmd_buffer
&& image
);
875 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
877 struct anv_address ss_clear_addr
= {
878 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
879 .offset
= surface_state
.offset
+
880 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
882 const struct anv_address entry_addr
=
883 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
884 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
887 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
888 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
889 * in-flight when they are issued even if the memory touched is not
890 * currently active for rendering. The weird bit is that it is not the
891 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
892 * rendering hangs such that the next stalling command after the
893 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
895 * It is unclear exactly why this hang occurs. Both MI commands come with
896 * warnings about the 3D pipeline but that doesn't seem to fully explain
897 * it. My (Jason's) best theory is that it has something to do with the
898 * fact that we're using a GPU state register as our temporary and that
899 * something with reading/writing it is causing problems.
901 * In order to work around this issue, we emit a PIPE_CONTROL with the
902 * command streamer stall bit set.
904 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
905 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
908 struct gen_mi_builder b
;
909 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
911 if (copy_from_surface_state
) {
912 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
914 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
916 /* Updating a surface state object may require that the state cache be
917 * invalidated. From the SKL PRM, Shared Functions -> State -> State
920 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
921 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
922 * modified [...], the L1 state cache must be invalidated to ensure
923 * the new surface or sampler state is fetched from system memory.
925 * In testing, SKL doesn't actually seem to need this, but HSW does.
927 cmd_buffer
->state
.pending_pipe_bits
|=
928 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
933 * @brief Transitions a color buffer from one layout to another.
935 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
938 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
939 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
940 * this represents the maximum layers to transition at each
941 * specified miplevel.
944 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
945 const struct anv_image
*image
,
946 VkImageAspectFlagBits aspect
,
947 const uint32_t base_level
, uint32_t level_count
,
948 uint32_t base_layer
, uint32_t layer_count
,
949 VkImageLayout initial_layout
,
950 VkImageLayout final_layout
)
952 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
953 /* Validate the inputs. */
955 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
956 /* These values aren't supported for simplicity's sake. */
957 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
958 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
959 /* Ensure the subresource range is valid. */
960 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
961 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
962 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
963 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
964 assert(last_level_num
<= image
->levels
);
965 /* The spec disallows these final layouts. */
966 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
967 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
969 /* No work is necessary if the layout stays the same or if this subresource
970 * range lacks auxiliary data.
972 if (initial_layout
== final_layout
)
975 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
977 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
978 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
979 /* This surface is a linear compressed image with a tiled shadow surface
980 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
981 * we need to ensure the shadow copy is up-to-date.
983 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
984 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
985 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
986 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
988 anv_image_copy_to_shadow(cmd_buffer
, image
,
989 VK_IMAGE_ASPECT_COLOR_BIT
,
990 base_level
, level_count
,
991 base_layer
, layer_count
);
994 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
997 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
999 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1000 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1001 /* A subresource in the undefined layout may have been aliased and
1002 * populated with any arrangement of bits. Therefore, we must initialize
1003 * the related aux buffer and clear buffer entry with desirable values.
1004 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1005 * images with VK_IMAGE_TILING_OPTIMAL.
1007 * Initialize the relevant clear buffer entries.
1009 if (base_level
== 0 && base_layer
== 0)
1010 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1012 /* Initialize the aux buffers to enable correct rendering. In order to
1013 * ensure that things such as storage images work correctly, aux buffers
1014 * need to be initialized to valid data.
1016 * Having an aux buffer with invalid data is a problem for two reasons:
1018 * 1) Having an invalid value in the buffer can confuse the hardware.
1019 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1020 * invalid and leads to the hardware doing strange things. It
1021 * doesn't hang as far as we can tell but rendering corruption can
1024 * 2) If this transition is into the GENERAL layout and we then use the
1025 * image as a storage image, then we must have the aux buffer in the
1026 * pass-through state so that, if we then go to texture from the
1027 * image, we get the results of our storage image writes and not the
1028 * fast clear color or other random data.
1030 * For CCS both of the problems above are real demonstrable issues. In
1031 * that case, the only thing we can do is to perform an ambiguate to
1032 * transition the aux surface into the pass-through state.
1034 * For MCS, (2) is never an issue because we don't support multisampled
1035 * storage images. In theory, issue (1) is a problem with MCS but we've
1036 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1037 * theory, be interpreted as something but we don't know that all bit
1038 * patterns are actually valid. For 2x and 8x, you could easily end up
1039 * with the MCS referring to an invalid plane because not all bits of
1040 * the MCS value are actually used. Even though we've never seen issues
1041 * in the wild, it's best to play it safe and initialize the MCS. We
1042 * can use a fast-clear for MCS because we only ever touch from render
1043 * and texture (no image load store).
1045 if (image
->samples
== 1) {
1046 for (uint32_t l
= 0; l
< level_count
; l
++) {
1047 const uint32_t level
= base_level
+ l
;
1049 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1050 if (base_layer
>= aux_layers
)
1051 break; /* We will only get fewer layers as level increases */
1052 uint32_t level_layer_count
=
1053 MIN2(layer_count
, aux_layers
- base_layer
);
1055 anv_image_ccs_op(cmd_buffer
, image
,
1056 image
->planes
[plane
].surface
.isl
.format
,
1057 aspect
, level
, base_layer
, level_layer_count
,
1058 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1060 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1061 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1062 level
, base_layer
, level_layer_count
,
1067 if (image
->samples
== 4 || image
->samples
== 16) {
1068 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1069 "Doing a potentially unnecessary fast-clear to "
1070 "define an MCS buffer.");
1073 assert(base_level
== 0 && level_count
== 1);
1074 anv_image_mcs_op(cmd_buffer
, image
,
1075 image
->planes
[plane
].surface
.isl
.format
,
1076 aspect
, base_layer
, layer_count
,
1077 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1082 const enum isl_aux_usage initial_aux_usage
=
1083 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1084 const enum isl_aux_usage final_aux_usage
=
1085 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1087 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1088 * We can handle transitions between CCS_D/E to and from NONE. What we
1089 * don't yet handle is switching between CCS_E and CCS_D within a given
1090 * image. Doing so in a performant way requires more detailed aux state
1091 * tracking such as what is done in i965. For now, just assume that we
1092 * only have one type of compression.
1094 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1095 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1096 initial_aux_usage
== final_aux_usage
);
1098 /* If initial aux usage is NONE, there is nothing to resolve */
1099 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1102 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1104 /* If the initial layout supports more fast clear than the final layout
1105 * then we need at least a partial resolve.
1107 const enum anv_fast_clear_type initial_fast_clear
=
1108 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1109 const enum anv_fast_clear_type final_fast_clear
=
1110 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1111 if (final_fast_clear
< initial_fast_clear
)
1112 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1114 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1115 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1116 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1118 if (resolve_op
== ISL_AUX_OP_NONE
)
1121 /* Perform a resolve to synchronize data between the main and aux buffer.
1122 * Before we begin, we must satisfy the cache flushing requirement specified
1123 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1125 * Any transition from any value in {Clear, Render, Resolve} to a
1126 * different value in {Clear, Render, Resolve} requires end of pipe
1129 * We perform a flush of the write cache before and after the clear and
1130 * resolve operations to meet this requirement.
1132 * Unlike other drawing, fast clear operations are not properly
1133 * synchronized. The first PIPE_CONTROL here likely ensures that the
1134 * contents of the previous render or clear hit the render target before we
1135 * resolve and the second likely ensures that the resolve is complete before
1136 * we do any more rendering or clearing.
1138 cmd_buffer
->state
.pending_pipe_bits
|=
1139 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1141 for (uint32_t l
= 0; l
< level_count
; l
++) {
1142 uint32_t level
= base_level
+ l
;
1144 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1145 if (base_layer
>= aux_layers
)
1146 break; /* We will only get fewer layers as level increases */
1147 uint32_t level_layer_count
=
1148 MIN2(layer_count
, aux_layers
- base_layer
);
1150 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1151 uint32_t array_layer
= base_layer
+ a
;
1152 if (image
->samples
== 1) {
1153 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1154 image
->planes
[plane
].surface
.isl
.format
,
1155 aspect
, level
, array_layer
, resolve_op
,
1158 /* We only support fast-clear on the first layer so partial
1159 * resolves should not be used on other layers as they will use
1160 * the clear color stored in memory that is only valid for layer0.
1162 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1166 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1167 image
->planes
[plane
].surface
.isl
.format
,
1168 aspect
, array_layer
, resolve_op
,
1174 cmd_buffer
->state
.pending_pipe_bits
|=
1175 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1179 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1182 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1183 struct anv_render_pass
*pass
,
1184 const VkRenderPassBeginInfo
*begin
)
1186 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1187 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1188 struct anv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1190 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1192 if (pass
->attachment_count
> 0) {
1193 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1194 pass
->attachment_count
*
1195 sizeof(state
->attachments
[0]),
1196 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1197 if (state
->attachments
== NULL
) {
1198 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1199 return anv_batch_set_error(&cmd_buffer
->batch
,
1200 VK_ERROR_OUT_OF_HOST_MEMORY
);
1203 state
->attachments
= NULL
;
1206 /* Reserve one for the NULL state. */
1207 unsigned num_states
= 1;
1208 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1209 if (vk_format_is_color(pass
->attachments
[i
].format
))
1212 if (need_input_attachment_state(&pass
->attachments
[i
]))
1216 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1217 state
->render_pass_states
=
1218 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1219 num_states
* ss_stride
, isl_dev
->ss
.align
);
1221 struct anv_state next_state
= state
->render_pass_states
;
1222 next_state
.alloc_size
= isl_dev
->ss
.size
;
1224 state
->null_surface_state
= next_state
;
1225 next_state
.offset
+= ss_stride
;
1226 next_state
.map
+= ss_stride
;
1228 const VkRenderPassAttachmentBeginInfoKHR
*begin_attachment
=
1229 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1231 if (begin
&& !begin_attachment
)
1232 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1234 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1235 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1236 state
->attachments
[i
].color
.state
= next_state
;
1237 next_state
.offset
+= ss_stride
;
1238 next_state
.map
+= ss_stride
;
1241 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1242 state
->attachments
[i
].input
.state
= next_state
;
1243 next_state
.offset
+= ss_stride
;
1244 next_state
.map
+= ss_stride
;
1247 if (begin_attachment
&& begin_attachment
->attachmentCount
!= 0) {
1248 assert(begin_attachment
->attachmentCount
== pass
->attachment_count
);
1249 ANV_FROM_HANDLE(anv_image_view
, iview
, begin_attachment
->pAttachments
[i
]);
1250 cmd_buffer
->state
.attachments
[i
].image_view
= iview
;
1251 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1252 cmd_buffer
->state
.attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1255 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1256 state
->render_pass_states
.alloc_size
);
1259 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1260 isl_extent3d(framebuffer
->width
,
1261 framebuffer
->height
,
1262 framebuffer
->layers
));
1264 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1265 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1266 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1267 VkImageAspectFlags clear_aspects
= 0;
1268 VkImageAspectFlags load_aspects
= 0;
1270 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1271 /* color attachment */
1272 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1273 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1274 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1275 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1278 /* depthstencil attachment */
1279 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1280 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1281 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1282 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1283 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1286 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1287 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1288 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1289 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1290 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1295 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1296 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1297 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1299 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1301 struct anv_image_view
*iview
= cmd_buffer
->state
.attachments
[i
].image_view
;
1302 anv_assert(iview
->vk_format
== att
->format
);
1304 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1305 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1307 union isl_color_value clear_color
= { .u32
= { 0, } };
1308 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1309 anv_assert(iview
->n_planes
== 1);
1310 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1311 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1312 state
, i
, begin
->renderArea
,
1315 anv_image_fill_surface_state(cmd_buffer
->device
,
1317 VK_IMAGE_ASPECT_COLOR_BIT
,
1318 &iview
->planes
[0].isl
,
1319 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1320 state
->attachments
[i
].aux_usage
,
1323 &state
->attachments
[i
].color
,
1326 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1328 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1333 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1334 anv_image_fill_surface_state(cmd_buffer
->device
,
1336 VK_IMAGE_ASPECT_COLOR_BIT
,
1337 &iview
->planes
[0].isl
,
1338 ISL_SURF_USAGE_TEXTURE_BIT
,
1339 state
->attachments
[i
].input_aux_usage
,
1342 &state
->attachments
[i
].input
,
1345 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1354 genX(BeginCommandBuffer
)(
1355 VkCommandBuffer commandBuffer
,
1356 const VkCommandBufferBeginInfo
* pBeginInfo
)
1358 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1360 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1361 * command buffer's state. Otherwise, we must *reset* its state. In both
1362 * cases we reset it.
1364 * From the Vulkan 1.0 spec:
1366 * If a command buffer is in the executable state and the command buffer
1367 * was allocated from a command pool with the
1368 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1369 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1370 * as if vkResetCommandBuffer had been called with
1371 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1372 * the command buffer in the recording state.
1374 anv_cmd_buffer_reset(cmd_buffer
);
1376 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1378 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1379 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1381 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1383 /* We sometimes store vertex data in the dynamic state buffer for blorp
1384 * operations and our dynamic state stream may re-use data from previous
1385 * command buffers. In order to prevent stale cache data, we flush the VF
1386 * cache. We could do this on every blorp call but that's not really
1387 * needed as all of the data will get written by the CPU prior to the GPU
1388 * executing anything. The chances are fairly high that they will use
1389 * blorp at least once per primary command buffer so it shouldn't be
1392 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1393 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1395 /* We send an "Indirect State Pointers Disable" packet at
1396 * EndCommandBuffer, so all push contant packets are ignored during a
1397 * context restore. Documentation says after that command, we need to
1398 * emit push constants again before any rendering operation. So we
1399 * flag them dirty here to make sure they get emitted.
1401 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1403 VkResult result
= VK_SUCCESS
;
1404 if (cmd_buffer
->usage_flags
&
1405 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1406 assert(pBeginInfo
->pInheritanceInfo
);
1407 cmd_buffer
->state
.pass
=
1408 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1409 cmd_buffer
->state
.subpass
=
1410 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1412 /* This is optional in the inheritance info. */
1413 cmd_buffer
->state
.framebuffer
=
1414 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1416 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1417 cmd_buffer
->state
.pass
, NULL
);
1419 /* Record that HiZ is enabled if we can. */
1420 if (cmd_buffer
->state
.framebuffer
) {
1421 const struct anv_image_view
* const iview
=
1422 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1425 VkImageLayout layout
=
1426 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1428 enum isl_aux_usage aux_usage
=
1429 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1430 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1432 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1436 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1439 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1440 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1441 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1442 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1444 /* If secondary buffer supports conditional rendering
1445 * we should emit commands as if conditional rendering is enabled.
1447 cmd_buffer
->state
.conditional_render_enabled
=
1448 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1455 /* From the PRM, Volume 2a:
1457 * "Indirect State Pointers Disable
1459 * At the completion of the post-sync operation associated with this pipe
1460 * control packet, the indirect state pointers in the hardware are
1461 * considered invalid; the indirect pointers are not saved in the context.
1462 * If any new indirect state commands are executed in the command stream
1463 * while the pipe control is pending, the new indirect state commands are
1466 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1467 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1468 * commands are only considered as Indirect State Pointers. Once ISP is
1469 * issued in a context, SW must initialize by programming push constant
1470 * commands for all the shaders (at least to zero length) before attempting
1471 * any rendering operation for the same context."
1473 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1474 * even though they point to a BO that has been already unreferenced at
1475 * the end of the previous batch buffer. This has been fine so far since
1476 * we are protected by these scratch page (every address not covered by
1477 * a BO should be pointing to the scratch page). But on CNL, it is
1478 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1481 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1482 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1483 * context restore, so the mentioned hang doesn't happen. However,
1484 * software must program push constant commands for all stages prior to
1485 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1487 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1488 * constants have been loaded into the EUs prior to disable the push constants
1489 * so that it doesn't hang a previous 3DPRIMITIVE.
1492 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1494 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1495 pc
.StallAtPixelScoreboard
= true;
1496 pc
.CommandStreamerStallEnable
= true;
1498 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1499 pc
.IndirectStatePointersDisable
= true;
1500 pc
.CommandStreamerStallEnable
= true;
1505 genX(EndCommandBuffer
)(
1506 VkCommandBuffer commandBuffer
)
1508 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1510 if (anv_batch_has_error(&cmd_buffer
->batch
))
1511 return cmd_buffer
->batch
.status
;
1513 /* We want every command buffer to start with the PMA fix in a known state,
1514 * so we disable it at the end of the command buffer.
1516 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1518 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1520 emit_isp_disable(cmd_buffer
);
1522 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1528 genX(CmdExecuteCommands
)(
1529 VkCommandBuffer commandBuffer
,
1530 uint32_t commandBufferCount
,
1531 const VkCommandBuffer
* pCmdBuffers
)
1533 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1535 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1537 if (anv_batch_has_error(&primary
->batch
))
1540 /* The secondary command buffers will assume that the PMA fix is disabled
1541 * when they begin executing. Make sure this is true.
1543 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1545 /* The secondary command buffer doesn't know which textures etc. have been
1546 * flushed prior to their execution. Apply those flushes now.
1548 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1550 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1551 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1553 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1554 assert(!anv_batch_has_error(&secondary
->batch
));
1556 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1557 if (secondary
->state
.conditional_render_enabled
) {
1558 if (!primary
->state
.conditional_render_enabled
) {
1559 /* Secondary buffer is constructed as if it will be executed
1560 * with conditional rendering, we should satisfy this dependency
1561 * regardless of conditional rendering being enabled in primary.
1563 struct gen_mi_builder b
;
1564 gen_mi_builder_init(&b
, &primary
->batch
);
1565 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1566 gen_mi_imm(UINT64_MAX
));
1571 if (secondary
->usage_flags
&
1572 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1573 /* If we're continuing a render pass from the primary, we need to
1574 * copy the surface states for the current subpass into the storage
1575 * we allocated for them in BeginCommandBuffer.
1577 struct anv_bo
*ss_bo
=
1578 primary
->device
->surface_state_pool
.block_pool
.bo
;
1579 struct anv_state src_state
= primary
->state
.render_pass_states
;
1580 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1581 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1583 genX(cmd_buffer_so_memcpy
)(primary
,
1584 (struct anv_address
) {
1586 .offset
= dst_state
.offset
,
1588 (struct anv_address
) {
1590 .offset
= src_state
.offset
,
1592 src_state
.alloc_size
);
1595 anv_cmd_buffer_add_secondary(primary
, secondary
);
1598 /* The secondary may have selected a different pipeline (3D or compute) and
1599 * may have changed the current L3$ configuration. Reset our tracking
1600 * variables to invalid values to ensure that we re-emit these in the case
1601 * where we do any draws or compute dispatches from the primary after the
1602 * secondary has returned.
1604 primary
->state
.current_pipeline
= UINT32_MAX
;
1605 primary
->state
.current_l3_config
= NULL
;
1606 primary
->state
.current_hash_scale
= 0;
1608 /* Each of the secondary command buffers will use its own state base
1609 * address. We need to re-emit state base address for the primary after
1610 * all of the secondaries are done.
1612 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1615 genX(cmd_buffer_emit_state_base_address
)(primary
);
1618 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1619 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1620 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1623 * Program the hardware to use the specified L3 configuration.
1626 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1627 const struct gen_l3_config
*cfg
)
1630 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1633 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1634 intel_logd("L3 config transition: ");
1635 gen_dump_l3_config(cfg
, stderr
);
1638 UNUSED
const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1640 /* According to the hardware docs, the L3 partitioning can only be changed
1641 * while the pipeline is completely drained and the caches are flushed,
1642 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1644 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1645 pc
.DCFlushEnable
= true;
1646 pc
.PostSyncOperation
= NoWrite
;
1647 pc
.CommandStreamerStallEnable
= true;
1650 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1651 * invalidation of the relevant caches. Note that because RO invalidation
1652 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1653 * command is processed by the CS) we cannot combine it with the previous
1654 * stalling flush as the hardware documentation suggests, because that
1655 * would cause the CS to stall on previous rendering *after* RO
1656 * invalidation and wouldn't prevent the RO caches from being polluted by
1657 * concurrent rendering before the stall completes. This intentionally
1658 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1659 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1660 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1661 * already guarantee that there is no concurrent GPGPU kernel execution
1662 * (see SKL HSD 2132585).
1664 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1665 pc
.TextureCacheInvalidationEnable
= true;
1666 pc
.ConstantCacheInvalidationEnable
= true;
1667 pc
.InstructionCacheInvalidateEnable
= true;
1668 pc
.StateCacheInvalidationEnable
= true;
1669 pc
.PostSyncOperation
= NoWrite
;
1672 /* Now send a third stalling flush to make sure that invalidation is
1673 * complete when the L3 configuration registers are modified.
1675 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1676 pc
.DCFlushEnable
= true;
1677 pc
.PostSyncOperation
= NoWrite
;
1678 pc
.CommandStreamerStallEnable
= true;
1683 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1686 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1687 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1689 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1690 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1694 anv_pack_struct(&l3cr
, L3_ALLOCATION_REG
,
1696 .SLMEnable
= has_slm
,
1699 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1700 * in L3CNTLREG register. The default setting of the bit is not the
1701 * desirable behavior.
1703 .ErrorDetectionBehaviorControl
= true,
1704 .UseFullWays
= true,
1706 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1707 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1708 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1709 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1711 /* Set up the L3 partitioning. */
1712 emit_lri(&cmd_buffer
->batch
, L3_ALLOCATION_REG_num
, l3cr
);
1716 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1717 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1718 cfg
->n
[GEN_L3P_ALL
];
1719 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1720 cfg
->n
[GEN_L3P_ALL
];
1721 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1722 cfg
->n
[GEN_L3P_ALL
];
1724 assert(!cfg
->n
[GEN_L3P_ALL
]);
1726 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1727 * the matching space on the remaining banks has to be allocated to a
1728 * client (URB for all validated configurations) set to the
1729 * lower-bandwidth 2-bank address hashing mode.
1731 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1732 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1733 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1735 /* Minimum number of ways that can be allocated to the URB. */
1736 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1737 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1739 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1740 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1741 .ConvertDC_UC
= !has_dc
,
1742 .ConvertIS_UC
= !has_is
,
1743 .ConvertC_UC
= !has_c
,
1744 .ConvertT_UC
= !has_t
);
1746 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1747 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1748 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1750 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1751 .SLMEnable
= has_slm
,
1752 .URBLowBandwidth
= urb_low_bw
,
1753 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1755 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1757 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1758 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1760 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1761 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1762 .ISLowBandwidth
= 0,
1763 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1765 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1766 .TLowBandwidth
= 0);
1768 /* Set up the L3 partitioning. */
1769 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1770 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1771 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1774 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1775 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1776 * them disabled to avoid crashing the system hard.
1778 uint32_t scratch1
, chicken3
;
1779 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1780 .L3AtomicDisable
= !has_dc
);
1781 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1782 .L3AtomicDisableMask
= true,
1783 .L3AtomicDisable
= !has_dc
);
1784 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1785 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1791 cmd_buffer
->state
.current_l3_config
= cfg
;
1795 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1797 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1799 /* Flushes are pipelined while invalidations are handled immediately.
1800 * Therefore, if we're flushing anything then we need to schedule a stall
1801 * before any invalidations can happen.
1803 if (bits
& ANV_PIPE_FLUSH_BITS
)
1804 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1806 /* If we're going to do an invalidate and we have a pending CS stall that
1807 * has yet to be resolved, we do the CS stall now.
1809 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1810 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1811 bits
|= ANV_PIPE_CS_STALL_BIT
;
1812 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1815 if (GEN_GEN
>= 12 &&
1816 ((bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
) ||
1817 (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
))) {
1818 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
1821 * Unified Cache (Tile Cache Disabled):
1823 * When the Color and Depth (Z) streams are enabled to be cached in
1824 * the DC space of L2, Software must use "Render Target Cache Flush
1825 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
1826 * Flush" for getting the color and depth (Z) write data to be
1827 * globally observable. In this mode of operation it is not required
1828 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
1830 bits
|= ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
1833 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1834 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1836 pipe
.TileCacheFlushEnable
= bits
& ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
1838 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1839 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1840 pipe
.RenderTargetCacheFlushEnable
=
1841 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1843 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1844 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1845 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1848 * According to the Broadwell documentation, any PIPE_CONTROL with the
1849 * "Command Streamer Stall" bit set must also have another bit set,
1850 * with five different options:
1852 * - Render Target Cache Flush
1853 * - Depth Cache Flush
1854 * - Stall at Pixel Scoreboard
1855 * - Post-Sync Operation
1859 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1860 * mesa and it seems to work fine. The choice is fairly arbitrary.
1862 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1863 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1864 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1865 pipe
.StallAtPixelScoreboard
= true;
1868 /* If a render target flush was emitted, then we can toggle off the bit
1869 * saying that render target writes are ongoing.
1871 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1872 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1874 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1877 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1878 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1880 * "If the VF Cache Invalidation Enable is set to a 1 in a
1881 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1882 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1883 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1886 * This appears to hang Broadwell, so we restrict it to just gen9.
1888 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1889 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1891 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1892 pipe
.StateCacheInvalidationEnable
=
1893 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1894 pipe
.ConstantCacheInvalidationEnable
=
1895 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1896 pipe
.VFCacheInvalidationEnable
=
1897 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1898 pipe
.TextureCacheInvalidationEnable
=
1899 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1900 pipe
.InstructionCacheInvalidateEnable
=
1901 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1903 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1905 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1906 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1907 * “Write Timestamp”.
1909 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1910 pipe
.PostSyncOperation
= WriteImmediateData
;
1912 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1916 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1919 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1922 void genX(CmdPipelineBarrier
)(
1923 VkCommandBuffer commandBuffer
,
1924 VkPipelineStageFlags srcStageMask
,
1925 VkPipelineStageFlags destStageMask
,
1927 uint32_t memoryBarrierCount
,
1928 const VkMemoryBarrier
* pMemoryBarriers
,
1929 uint32_t bufferMemoryBarrierCount
,
1930 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1931 uint32_t imageMemoryBarrierCount
,
1932 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1934 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1936 /* XXX: Right now, we're really dumb and just flush whatever categories
1937 * the app asks for. One of these days we may make this a bit better
1938 * but right now that's all the hardware allows for in most areas.
1940 VkAccessFlags src_flags
= 0;
1941 VkAccessFlags dst_flags
= 0;
1943 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1944 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1945 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1948 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1949 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1950 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1953 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1954 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1955 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1956 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1957 const VkImageSubresourceRange
*range
=
1958 &pImageMemoryBarriers
[i
].subresourceRange
;
1960 uint32_t base_layer
, layer_count
;
1961 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1963 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1965 base_layer
= range
->baseArrayLayer
;
1966 layer_count
= anv_get_layerCount(image
, range
);
1969 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1970 transition_depth_buffer(cmd_buffer
, image
,
1971 pImageMemoryBarriers
[i
].oldLayout
,
1972 pImageMemoryBarriers
[i
].newLayout
);
1975 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1976 transition_stencil_buffer(cmd_buffer
, image
,
1977 range
->baseMipLevel
,
1978 anv_get_levelCount(image
, range
),
1979 base_layer
, layer_count
,
1980 pImageMemoryBarriers
[i
].oldLayout
,
1981 pImageMemoryBarriers
[i
].newLayout
);
1984 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1985 VkImageAspectFlags color_aspects
=
1986 anv_image_expand_aspects(image
, range
->aspectMask
);
1987 uint32_t aspect_bit
;
1988 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1989 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1990 range
->baseMipLevel
,
1991 anv_get_levelCount(image
, range
),
1992 base_layer
, layer_count
,
1993 pImageMemoryBarriers
[i
].oldLayout
,
1994 pImageMemoryBarriers
[i
].newLayout
);
1999 cmd_buffer
->state
.pending_pipe_bits
|=
2000 anv_pipe_flush_bits_for_access_flags(src_flags
) |
2001 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
2005 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
2007 VkShaderStageFlags stages
=
2008 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
2010 /* In order to avoid thrash, we assume that vertex and fragment stages
2011 * always exist. In the rare case where one is missing *and* the other
2012 * uses push concstants, this may be suboptimal. However, avoiding stalls
2013 * seems more important.
2015 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
2017 if (stages
== cmd_buffer
->state
.push_constant_stages
)
2021 const unsigned push_constant_kb
= 32;
2022 #elif GEN_IS_HASWELL
2023 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2025 const unsigned push_constant_kb
= 16;
2028 const unsigned num_stages
=
2029 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2030 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2032 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2033 * units of 2KB. Incidentally, these are the same platforms that have
2034 * 32KB worth of push constant space.
2036 if (push_constant_kb
== 32)
2037 size_per_stage
&= ~1u;
2039 uint32_t kb_used
= 0;
2040 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2041 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2042 anv_batch_emit(&cmd_buffer
->batch
,
2043 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2044 alloc
._3DCommandSubOpcode
= 18 + i
;
2045 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2046 alloc
.ConstantBufferSize
= push_size
;
2048 kb_used
+= push_size
;
2051 anv_batch_emit(&cmd_buffer
->batch
,
2052 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2053 alloc
.ConstantBufferOffset
= kb_used
;
2054 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2057 cmd_buffer
->state
.push_constant_stages
= stages
;
2059 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2061 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2062 * the next 3DPRIMITIVE command after programming the
2063 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2065 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2066 * pipeline setup, we need to dirty push constants.
2068 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2071 static const struct anv_descriptor
*
2072 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2073 const struct anv_pipeline_binding
*binding
)
2075 assert(binding
->set
< MAX_SETS
);
2076 const struct anv_descriptor_set
*set
=
2077 pipe_state
->descriptors
[binding
->set
];
2078 const uint32_t offset
=
2079 set
->layout
->binding
[binding
->binding
].descriptor_index
;
2080 return &set
->descriptors
[offset
+ binding
->index
];
2084 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2085 const struct anv_pipeline_binding
*binding
)
2087 assert(binding
->set
< MAX_SETS
);
2088 const struct anv_descriptor_set
*set
=
2089 pipe_state
->descriptors
[binding
->set
];
2091 uint32_t dynamic_offset_idx
=
2092 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
2093 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
2096 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
2099 static struct anv_address
2100 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2101 struct anv_descriptor_set
*set
)
2104 /* This is a normal descriptor set */
2105 return (struct anv_address
) {
2106 .bo
= &set
->pool
->bo
,
2107 .offset
= set
->desc_mem
.offset
,
2110 /* This is a push descriptor set. We have to flag it as used on the GPU
2111 * so that the next time we push descriptors, we grab a new memory.
2113 struct anv_push_descriptor_set
*push_set
=
2114 (struct anv_push_descriptor_set
*)set
;
2115 push_set
->set_used_on_gpu
= true;
2117 return (struct anv_address
) {
2118 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2119 .offset
= set
->desc_mem
.offset
,
2125 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2126 gl_shader_stage stage
,
2127 struct anv_state
*bt_state
)
2129 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2130 struct anv_cmd_pipeline_state
*pipe_state
;
2131 struct anv_pipeline
*pipeline
;
2132 uint32_t state_offset
;
2135 case MESA_SHADER_COMPUTE
:
2136 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2139 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2142 pipeline
= pipe_state
->pipeline
;
2144 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2145 *bt_state
= (struct anv_state
) { 0, };
2149 struct anv_shader_bin
*bin
= pipeline
->shaders
[stage
];
2150 struct anv_pipeline_bind_map
*map
= &bin
->bind_map
;
2151 if (map
->surface_count
== 0) {
2152 *bt_state
= (struct anv_state
) { 0, };
2156 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2159 uint32_t *bt_map
= bt_state
->map
;
2161 if (bt_state
->map
== NULL
)
2162 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2164 /* We only need to emit relocs if we're not using softpin. If we are using
2165 * softpin then we always keep all user-allocated memory objects resident.
2167 const bool need_client_mem_relocs
=
2168 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
;
2170 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2171 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2173 struct anv_state surface_state
;
2175 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2176 /* Color attachment binding */
2177 assert(stage
== MESA_SHADER_FRAGMENT
);
2178 assert(binding
->binding
== 0);
2179 if (binding
->index
< subpass
->color_count
) {
2180 const unsigned att
=
2181 subpass
->color_attachments
[binding
->index
].attachment
;
2183 /* From the Vulkan 1.0.46 spec:
2185 * "If any color or depth/stencil attachments are
2186 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2189 if (att
== VK_ATTACHMENT_UNUSED
) {
2190 surface_state
= cmd_buffer
->state
.null_surface_state
;
2192 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2195 surface_state
= cmd_buffer
->state
.null_surface_state
;
2198 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2200 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2201 struct anv_state surface_state
=
2202 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2204 struct anv_address constant_data
= {
2205 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2206 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2208 unsigned constant_data_size
=
2209 pipeline
->shaders
[stage
]->constant_data_size
;
2211 const enum isl_format format
=
2212 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2213 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2214 surface_state
, format
,
2215 constant_data
, constant_data_size
, 1);
2217 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2218 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2220 } else if (binding
->set
== ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
) {
2221 /* This is always the first binding for compute shaders */
2222 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2223 if (!get_cs_prog_data(pipeline
)->uses_num_work_groups
)
2226 struct anv_state surface_state
=
2227 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2229 const enum isl_format format
=
2230 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2231 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2233 cmd_buffer
->state
.compute
.num_workgroups
,
2235 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2236 if (need_client_mem_relocs
) {
2237 add_surface_reloc(cmd_buffer
, surface_state
,
2238 cmd_buffer
->state
.compute
.num_workgroups
);
2241 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2242 /* This is a descriptor set buffer so the set index is actually
2243 * given by binding->binding. (Yes, that's confusing.)
2245 struct anv_descriptor_set
*set
=
2246 pipe_state
->descriptors
[binding
->binding
];
2247 assert(set
->desc_mem
.alloc_size
);
2248 assert(set
->desc_surface_state
.alloc_size
);
2249 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2250 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2251 anv_descriptor_set_address(cmd_buffer
, set
));
2255 const struct anv_descriptor
*desc
=
2256 anv_descriptor_for_binding(pipe_state
, binding
);
2258 switch (desc
->type
) {
2259 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2260 /* Nothing for us to do here */
2263 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2264 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2265 struct anv_surface_state sstate
=
2266 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2267 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2268 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2269 surface_state
= sstate
.state
;
2270 assert(surface_state
.alloc_size
);
2271 if (need_client_mem_relocs
)
2272 add_surface_state_relocs(cmd_buffer
, sstate
);
2275 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2276 assert(stage
== MESA_SHADER_FRAGMENT
);
2277 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2278 /* For depth and stencil input attachments, we treat it like any
2279 * old texture that a user may have bound.
2281 struct anv_surface_state sstate
=
2282 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2283 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2284 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2285 surface_state
= sstate
.state
;
2286 assert(surface_state
.alloc_size
);
2287 if (need_client_mem_relocs
)
2288 add_surface_state_relocs(cmd_buffer
, sstate
);
2290 /* For color input attachments, we create the surface state at
2291 * vkBeginRenderPass time so that we can include aux and clear
2292 * color information.
2294 assert(binding
->input_attachment_index
< subpass
->input_count
);
2295 const unsigned subpass_att
= binding
->input_attachment_index
;
2296 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2297 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2301 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2302 struct anv_surface_state sstate
= (binding
->write_only
)
2303 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2304 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2305 surface_state
= sstate
.state
;
2306 assert(surface_state
.alloc_size
);
2307 if (need_client_mem_relocs
)
2308 add_surface_state_relocs(cmd_buffer
, sstate
);
2312 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2313 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2314 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2315 surface_state
= desc
->buffer_view
->surface_state
;
2316 assert(surface_state
.alloc_size
);
2317 if (need_client_mem_relocs
) {
2318 add_surface_reloc(cmd_buffer
, surface_state
,
2319 desc
->buffer_view
->address
);
2323 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2324 /* If the shader never does any UBO pulls (this is a fairly common
2325 * case) then we don't need to fill out those binding table entries.
2326 * The real cost savings here is that we don't have to build the
2327 * surface state for them which is surprisingly expensive when it's
2330 if (!bin
->prog_data
->has_ubo_pull
)
2334 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2335 /* Compute the offset within the buffer */
2336 uint32_t dynamic_offset
=
2337 dynamic_offset_for_binding(pipe_state
, binding
);
2338 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2339 /* Clamp to the buffer size */
2340 offset
= MIN2(offset
, desc
->buffer
->size
);
2341 /* Clamp the range to the buffer size */
2342 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2344 struct anv_address address
=
2345 anv_address_add(desc
->buffer
->address
, offset
);
2348 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2349 enum isl_format format
=
2350 anv_isl_format_for_descriptor_type(desc
->type
);
2352 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2353 format
, address
, range
, 1);
2354 if (need_client_mem_relocs
)
2355 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2359 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2360 surface_state
= (binding
->write_only
)
2361 ? desc
->buffer_view
->writeonly_storage_surface_state
2362 : desc
->buffer_view
->storage_surface_state
;
2363 assert(surface_state
.alloc_size
);
2364 if (need_client_mem_relocs
) {
2365 add_surface_reloc(cmd_buffer
, surface_state
,
2366 desc
->buffer_view
->address
);
2371 assert(!"Invalid descriptor type");
2375 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2379 /* The PIPE_CONTROL command description says:
2381 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2382 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2383 * Target Cache Flush by enabling this bit. When render target flush
2384 * is set due to new association of BTI, PS Scoreboard Stall bit must
2385 * be set in this packet."
2387 * FINISHME: Currently we shuffle around the surface states in the binding
2388 * table based on if they are getting used or not. So, we've to do below
2389 * pipe control flush for every binding table upload. Make changes so
2390 * that we do it only when we modify render target surface states.
2392 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2393 pc
.RenderTargetCacheFlushEnable
= true;
2394 pc
.StallAtPixelScoreboard
= true;
2396 pc
.TileCacheFlushEnable
= true;
2405 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2406 gl_shader_stage stage
,
2407 struct anv_state
*state
)
2409 struct anv_cmd_pipeline_state
*pipe_state
=
2410 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2411 &cmd_buffer
->state
.gfx
.base
;
2412 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2414 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2415 *state
= (struct anv_state
) { 0, };
2419 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2420 if (map
->sampler_count
== 0) {
2421 *state
= (struct anv_state
) { 0, };
2425 uint32_t size
= map
->sampler_count
* 16;
2426 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2428 if (state
->map
== NULL
)
2429 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2431 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2432 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2433 const struct anv_descriptor
*desc
=
2434 anv_descriptor_for_binding(pipe_state
, binding
);
2436 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2437 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2440 struct anv_sampler
*sampler
= desc
->sampler
;
2442 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2443 * happens to be zero.
2445 if (sampler
== NULL
)
2448 memcpy(state
->map
+ (s
* 16),
2449 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2456 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2458 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2460 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2461 pipeline
->active_stages
;
2463 VkResult result
= VK_SUCCESS
;
2464 anv_foreach_stage(s
, dirty
) {
2465 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2466 if (result
!= VK_SUCCESS
)
2468 result
= emit_binding_table(cmd_buffer
, s
,
2469 &cmd_buffer
->state
.binding_tables
[s
]);
2470 if (result
!= VK_SUCCESS
)
2474 if (result
!= VK_SUCCESS
) {
2475 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2477 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2478 if (result
!= VK_SUCCESS
)
2481 /* Re-emit state base addresses so we get the new surface state base
2482 * address before we start emitting binding tables etc.
2484 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2486 /* Re-emit all active binding tables */
2487 dirty
|= pipeline
->active_stages
;
2488 anv_foreach_stage(s
, dirty
) {
2489 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2490 if (result
!= VK_SUCCESS
) {
2491 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2494 result
= emit_binding_table(cmd_buffer
, s
,
2495 &cmd_buffer
->state
.binding_tables
[s
]);
2496 if (result
!= VK_SUCCESS
) {
2497 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2503 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2509 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2512 static const uint32_t sampler_state_opcodes
[] = {
2513 [MESA_SHADER_VERTEX
] = 43,
2514 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2515 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2516 [MESA_SHADER_GEOMETRY
] = 46,
2517 [MESA_SHADER_FRAGMENT
] = 47,
2518 [MESA_SHADER_COMPUTE
] = 0,
2521 static const uint32_t binding_table_opcodes
[] = {
2522 [MESA_SHADER_VERTEX
] = 38,
2523 [MESA_SHADER_TESS_CTRL
] = 39,
2524 [MESA_SHADER_TESS_EVAL
] = 40,
2525 [MESA_SHADER_GEOMETRY
] = 41,
2526 [MESA_SHADER_FRAGMENT
] = 42,
2527 [MESA_SHADER_COMPUTE
] = 0,
2530 anv_foreach_stage(s
, stages
) {
2531 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2532 assert(binding_table_opcodes
[s
] > 0);
2534 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2535 anv_batch_emit(&cmd_buffer
->batch
,
2536 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2537 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2538 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2542 /* Always emit binding table pointers if we're asked to, since on SKL
2543 * this is what flushes push constants. */
2544 anv_batch_emit(&cmd_buffer
->batch
,
2545 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2546 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2547 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2553 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2554 VkShaderStageFlags dirty_stages
)
2556 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2557 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2559 static const uint32_t push_constant_opcodes
[] = {
2560 [MESA_SHADER_VERTEX
] = 21,
2561 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2562 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2563 [MESA_SHADER_GEOMETRY
] = 22,
2564 [MESA_SHADER_FRAGMENT
] = 23,
2565 [MESA_SHADER_COMPUTE
] = 0,
2568 VkShaderStageFlags flushed
= 0;
2570 anv_foreach_stage(stage
, dirty_stages
) {
2571 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2572 assert(push_constant_opcodes
[stage
] > 0);
2574 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2575 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2577 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2578 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2579 const struct brw_stage_prog_data
*prog_data
=
2580 pipeline
->shaders
[stage
]->prog_data
;
2581 const struct anv_pipeline_bind_map
*bind_map
=
2582 &pipeline
->shaders
[stage
]->bind_map
;
2584 /* The Skylake PRM contains the following restriction:
2586 * "The driver must ensure The following case does not occur
2587 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2588 * buffer 3 read length equal to zero committed followed by a
2589 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2592 * To avoid this, we program the buffers in the highest slots.
2593 * This way, slot 0 is only used if slot 3 is also used.
2597 for (int i
= 3; i
>= 0; i
--) {
2598 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2599 if (range
->length
== 0)
2602 const unsigned surface
=
2603 prog_data
->binding_table
.ubo_start
+ range
->block
;
2605 assert(surface
<= bind_map
->surface_count
);
2606 const struct anv_pipeline_binding
*binding
=
2607 &bind_map
->surface_to_descriptor
[surface
];
2609 struct anv_address read_addr
;
2611 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2612 struct anv_address constant_data
= {
2613 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2614 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2616 unsigned constant_data_size
=
2617 pipeline
->shaders
[stage
]->constant_data_size
;
2619 read_len
= MIN2(range
->length
,
2620 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2621 read_addr
= anv_address_add(constant_data
,
2623 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2624 /* This is a descriptor set buffer so the set index is
2625 * actually given by binding->binding. (Yes, that's
2628 struct anv_descriptor_set
*set
=
2629 gfx_state
->base
.descriptors
[binding
->binding
];
2630 struct anv_address desc_buffer_addr
=
2631 anv_descriptor_set_address(cmd_buffer
, set
);
2632 const unsigned desc_buffer_size
= set
->desc_mem
.alloc_size
;
2634 read_len
= MIN2(range
->length
,
2635 DIV_ROUND_UP(desc_buffer_size
, 32) - range
->start
);
2636 read_addr
= anv_address_add(desc_buffer_addr
,
2639 const struct anv_descriptor
*desc
=
2640 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2642 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2643 read_len
= MIN2(range
->length
,
2644 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2645 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2648 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2650 uint32_t dynamic_offset
=
2651 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2652 uint32_t buf_offset
=
2653 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2654 uint32_t buf_range
=
2655 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2657 read_len
= MIN2(range
->length
,
2658 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2659 read_addr
= anv_address_add(desc
->buffer
->address
,
2660 buf_offset
+ range
->start
* 32);
2665 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2666 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2671 struct anv_state state
=
2672 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2674 if (state
.alloc_size
> 0) {
2675 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2676 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2677 .offset
= state
.offset
,
2679 c
.ConstantBody
.ReadLength
[n
] =
2680 DIV_ROUND_UP(state
.alloc_size
, 32);
2683 /* For Ivy Bridge, the push constants packets have a different
2684 * rule that would require us to iterate in the other direction
2685 * and possibly mess around with dynamic state base address.
2686 * Don't bother; just emit regular push constants at n = 0.
2688 struct anv_state state
=
2689 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2691 if (state
.alloc_size
> 0) {
2692 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2693 c
.ConstantBody
.ReadLength
[0] =
2694 DIV_ROUND_UP(state
.alloc_size
, 32);
2700 flushed
|= mesa_to_vk_shader_stage(stage
);
2703 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2708 genX(cmd_buffer_aux_map_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2710 void *aux_map_ctx
= cmd_buffer
->device
->aux_map_ctx
;
2713 uint32_t aux_map_state_num
= gen_aux_map_get_state_num(aux_map_ctx
);
2714 if (cmd_buffer
->state
.last_aux_map_state
!= aux_map_state_num
) {
2715 /* If the aux-map state number increased, then we need to rewrite the
2716 * register. Rewriting the register is used to both set the aux-map
2717 * translation table address, and also to invalidate any previously
2718 * cached translations.
2720 uint64_t base_addr
= gen_aux_map_get_base(aux_map_ctx
);
2721 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2722 lri
.RegisterOffset
= GENX(GFX_AUX_TABLE_BASE_ADDR_num
);
2723 lri
.DataDWord
= base_addr
& 0xffffffff;
2725 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2726 lri
.RegisterOffset
= GENX(GFX_AUX_TABLE_BASE_ADDR_num
) + 4;
2727 lri
.DataDWord
= base_addr
>> 32;
2729 cmd_buffer
->state
.last_aux_map_state
= aux_map_state_num
;
2735 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2737 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2740 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2741 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2742 vb_emit
|= pipeline
->vb_used
;
2744 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2746 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2748 genX(cmd_buffer_emit_hashing_mode
)(cmd_buffer
, UINT_MAX
, UINT_MAX
, 1);
2750 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2753 genX(cmd_buffer_aux_map_state
)(cmd_buffer
);
2757 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2758 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2760 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2761 GENX(3DSTATE_VERTEX_BUFFERS
));
2763 for_each_bit(vb
, vb_emit
) {
2764 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2765 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2767 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2768 .VertexBufferIndex
= vb
,
2770 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2772 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2773 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2776 .AddressModifyEnable
= true,
2777 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2778 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2781 .BufferSize
= buffer
->size
- offset
2783 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2787 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2792 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2795 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2796 /* We don't need any per-buffer dirty tracking because you're not
2797 * allowed to bind different XFB buffers while XFB is enabled.
2799 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2800 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2801 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2803 sob
.SOBufferIndex
= idx
;
2805 sob
._3DCommandOpcode
= 0;
2806 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ idx
;
2809 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2810 sob
.SOBufferEnable
= true;
2811 sob
.MOCS
= cmd_buffer
->device
->default_mocs
,
2812 sob
.StreamOffsetWriteEnable
= false;
2813 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2815 /* Size is in DWords - 1 */
2816 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2821 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2823 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2827 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2828 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2830 /* The exact descriptor layout is pulled from the pipeline, so we need
2831 * to re-emit binding tables on every pipeline change.
2833 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2835 /* If the pipeline changed, we may need to re-allocate push constant
2838 cmd_buffer_alloc_push_constants(cmd_buffer
);
2842 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2843 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2844 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2846 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2847 * stall needs to be sent just prior to any 3DSTATE_VS,
2848 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2849 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2850 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2851 * PIPE_CONTROL needs to be sent before any combination of VS
2852 * associated 3DSTATE."
2854 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2855 pc
.DepthStallEnable
= true;
2856 pc
.PostSyncOperation
= WriteImmediateData
;
2858 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2863 /* Render targets live in the same binding table as fragment descriptors */
2864 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2865 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2867 /* We emit the binding tables and sampler tables first, then emit push
2868 * constants and then finally emit binding table and sampler table
2869 * pointers. It has to happen in this order, since emitting the binding
2870 * tables may change the push constants (in case of storage images). After
2871 * emitting push constants, on SKL+ we have to emit the corresponding
2872 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2875 if (cmd_buffer
->state
.descriptors_dirty
)
2876 dirty
= flush_descriptor_sets(cmd_buffer
);
2878 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2879 /* Because we're pushing UBOs, we have to push whenever either
2880 * descriptors or push constants is dirty.
2882 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2883 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2884 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2888 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2890 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2891 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2893 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2894 ANV_CMD_DIRTY_PIPELINE
)) {
2895 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2896 pipeline
->depth_clamp_enable
);
2899 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2900 ANV_CMD_DIRTY_RENDER_TARGETS
))
2901 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2903 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2905 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2909 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2910 struct anv_address addr
,
2911 uint32_t size
, uint32_t index
)
2913 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2914 GENX(3DSTATE_VERTEX_BUFFERS
));
2916 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2917 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2918 .VertexBufferIndex
= index
,
2919 .AddressModifyEnable
= true,
2921 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2923 .BufferStartingAddress
= addr
,
2926 .BufferStartingAddress
= addr
,
2927 .EndAddress
= anv_address_add(addr
, size
),
2933 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2934 struct anv_address addr
)
2936 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2940 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2941 uint32_t base_vertex
, uint32_t base_instance
)
2943 struct anv_state id_state
=
2944 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2946 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2947 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2949 struct anv_address addr
= {
2950 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2951 .offset
= id_state
.offset
,
2954 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2958 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2960 struct anv_state state
=
2961 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2963 ((uint32_t *)state
.map
)[0] = draw_index
;
2965 struct anv_address addr
= {
2966 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2967 .offset
= state
.offset
,
2970 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2974 VkCommandBuffer commandBuffer
,
2975 uint32_t vertexCount
,
2976 uint32_t instanceCount
,
2977 uint32_t firstVertex
,
2978 uint32_t firstInstance
)
2980 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2981 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2982 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2984 if (anv_batch_has_error(&cmd_buffer
->batch
))
2987 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2989 if (cmd_buffer
->state
.conditional_render_enabled
)
2990 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2992 if (vs_prog_data
->uses_firstvertex
||
2993 vs_prog_data
->uses_baseinstance
)
2994 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2995 if (vs_prog_data
->uses_drawid
)
2996 emit_draw_index(cmd_buffer
, 0);
2998 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2999 * different views. We need to multiply instanceCount by the view count.
3001 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3003 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3004 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3005 prim
.VertexAccessType
= SEQUENTIAL
;
3006 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3007 prim
.VertexCountPerInstance
= vertexCount
;
3008 prim
.StartVertexLocation
= firstVertex
;
3009 prim
.InstanceCount
= instanceCount
;
3010 prim
.StartInstanceLocation
= firstInstance
;
3011 prim
.BaseVertexLocation
= 0;
3015 void genX(CmdDrawIndexed
)(
3016 VkCommandBuffer commandBuffer
,
3017 uint32_t indexCount
,
3018 uint32_t instanceCount
,
3019 uint32_t firstIndex
,
3020 int32_t vertexOffset
,
3021 uint32_t firstInstance
)
3023 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3024 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3025 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3027 if (anv_batch_has_error(&cmd_buffer
->batch
))
3030 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3032 if (cmd_buffer
->state
.conditional_render_enabled
)
3033 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3035 if (vs_prog_data
->uses_firstvertex
||
3036 vs_prog_data
->uses_baseinstance
)
3037 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
3038 if (vs_prog_data
->uses_drawid
)
3039 emit_draw_index(cmd_buffer
, 0);
3041 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3042 * different views. We need to multiply instanceCount by the view count.
3044 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3046 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3047 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3048 prim
.VertexAccessType
= RANDOM
;
3049 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3050 prim
.VertexCountPerInstance
= indexCount
;
3051 prim
.StartVertexLocation
= firstIndex
;
3052 prim
.InstanceCount
= instanceCount
;
3053 prim
.StartInstanceLocation
= firstInstance
;
3054 prim
.BaseVertexLocation
= vertexOffset
;
3058 /* Auto-Draw / Indirect Registers */
3059 #define GEN7_3DPRIM_END_OFFSET 0x2420
3060 #define GEN7_3DPRIM_START_VERTEX 0x2430
3061 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3062 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3063 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3064 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3066 void genX(CmdDrawIndirectByteCountEXT
)(
3067 VkCommandBuffer commandBuffer
,
3068 uint32_t instanceCount
,
3069 uint32_t firstInstance
,
3070 VkBuffer counterBuffer
,
3071 VkDeviceSize counterBufferOffset
,
3072 uint32_t counterOffset
,
3073 uint32_t vertexStride
)
3075 #if GEN_IS_HASWELL || GEN_GEN >= 8
3076 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3077 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3078 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3079 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3081 /* firstVertex is always zero for this draw function */
3082 const uint32_t firstVertex
= 0;
3084 if (anv_batch_has_error(&cmd_buffer
->batch
))
3087 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3089 if (vs_prog_data
->uses_firstvertex
||
3090 vs_prog_data
->uses_baseinstance
)
3091 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3092 if (vs_prog_data
->uses_drawid
)
3093 emit_draw_index(cmd_buffer
, 0);
3095 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3096 * different views. We need to multiply instanceCount by the view count.
3098 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3100 struct gen_mi_builder b
;
3101 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3102 struct gen_mi_value count
=
3103 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3104 counterBufferOffset
));
3106 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3107 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3108 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3110 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3111 gen_mi_imm(firstVertex
));
3112 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3113 gen_mi_imm(instanceCount
));
3114 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3115 gen_mi_imm(firstInstance
));
3116 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3118 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3119 prim
.IndirectParameterEnable
= true;
3120 prim
.VertexAccessType
= SEQUENTIAL
;
3121 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3123 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3127 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3128 struct anv_address addr
,
3131 struct gen_mi_builder b
;
3132 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3134 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3135 gen_mi_mem32(anv_address_add(addr
, 0)));
3137 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3138 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3139 if (view_count
> 1) {
3140 #if GEN_IS_HASWELL || GEN_GEN >= 8
3141 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3143 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3144 "MI_MATH is not supported on Ivy Bridge");
3147 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3149 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3150 gen_mi_mem32(anv_address_add(addr
, 8)));
3153 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3154 gen_mi_mem32(anv_address_add(addr
, 12)));
3155 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3156 gen_mi_mem32(anv_address_add(addr
, 16)));
3158 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3159 gen_mi_mem32(anv_address_add(addr
, 12)));
3160 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3164 void genX(CmdDrawIndirect
)(
3165 VkCommandBuffer commandBuffer
,
3167 VkDeviceSize offset
,
3171 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3172 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3173 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3174 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3176 if (anv_batch_has_error(&cmd_buffer
->batch
))
3179 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3181 if (cmd_buffer
->state
.conditional_render_enabled
)
3182 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3184 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3185 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3187 if (vs_prog_data
->uses_firstvertex
||
3188 vs_prog_data
->uses_baseinstance
)
3189 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3190 if (vs_prog_data
->uses_drawid
)
3191 emit_draw_index(cmd_buffer
, i
);
3193 load_indirect_parameters(cmd_buffer
, draw
, false);
3195 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3196 prim
.IndirectParameterEnable
= true;
3197 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3198 prim
.VertexAccessType
= SEQUENTIAL
;
3199 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3206 void genX(CmdDrawIndexedIndirect
)(
3207 VkCommandBuffer commandBuffer
,
3209 VkDeviceSize offset
,
3213 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3214 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3215 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3216 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3218 if (anv_batch_has_error(&cmd_buffer
->batch
))
3221 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3223 if (cmd_buffer
->state
.conditional_render_enabled
)
3224 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3226 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3227 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3229 /* TODO: We need to stomp base vertex to 0 somehow */
3230 if (vs_prog_data
->uses_firstvertex
||
3231 vs_prog_data
->uses_baseinstance
)
3232 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3233 if (vs_prog_data
->uses_drawid
)
3234 emit_draw_index(cmd_buffer
, i
);
3236 load_indirect_parameters(cmd_buffer
, draw
, true);
3238 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3239 prim
.IndirectParameterEnable
= true;
3240 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3241 prim
.VertexAccessType
= RANDOM
;
3242 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3249 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3252 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3253 struct anv_address count_address
,
3254 const bool conditional_render_enabled
)
3256 struct gen_mi_builder b
;
3257 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3259 if (conditional_render_enabled
) {
3260 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3261 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3262 gen_mi_mem32(count_address
));
3265 /* Upload the current draw count from the draw parameters buffer to
3266 * MI_PREDICATE_SRC0.
3268 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3269 gen_mi_mem32(count_address
));
3271 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3276 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3277 uint32_t draw_index
)
3279 struct gen_mi_builder b
;
3280 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3282 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3283 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3285 if (draw_index
== 0) {
3286 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3287 mip
.LoadOperation
= LOAD_LOADINV
;
3288 mip
.CombineOperation
= COMBINE_SET
;
3289 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3292 /* While draw_index < draw_count the predicate's result will be
3293 * (draw_index == draw_count) ^ TRUE = TRUE
3294 * When draw_index == draw_count the result is
3295 * (TRUE) ^ TRUE = FALSE
3296 * After this all results will be:
3297 * (FALSE) ^ FALSE = FALSE
3299 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3300 mip
.LoadOperation
= LOAD_LOAD
;
3301 mip
.CombineOperation
= COMBINE_XOR
;
3302 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3307 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3309 emit_draw_count_predicate_with_conditional_render(
3310 struct anv_cmd_buffer
*cmd_buffer
,
3311 uint32_t draw_index
)
3313 struct gen_mi_builder b
;
3314 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3316 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3317 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3318 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3321 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3323 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3324 * so we emit MI_PREDICATE to set it.
3327 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3328 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3330 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3331 mip
.LoadOperation
= LOAD_LOADINV
;
3332 mip
.CombineOperation
= COMBINE_SET
;
3333 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3339 void genX(CmdDrawIndirectCountKHR
)(
3340 VkCommandBuffer commandBuffer
,
3342 VkDeviceSize offset
,
3343 VkBuffer _countBuffer
,
3344 VkDeviceSize countBufferOffset
,
3345 uint32_t maxDrawCount
,
3348 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3349 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3350 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3351 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3352 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3353 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3355 if (anv_batch_has_error(&cmd_buffer
->batch
))
3358 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3360 struct anv_address count_address
=
3361 anv_address_add(count_buffer
->address
, countBufferOffset
);
3363 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3364 cmd_state
->conditional_render_enabled
);
3366 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3367 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3369 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3370 if (cmd_state
->conditional_render_enabled
) {
3371 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3373 emit_draw_count_predicate(cmd_buffer
, i
);
3376 emit_draw_count_predicate(cmd_buffer
, i
);
3379 if (vs_prog_data
->uses_firstvertex
||
3380 vs_prog_data
->uses_baseinstance
)
3381 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3382 if (vs_prog_data
->uses_drawid
)
3383 emit_draw_index(cmd_buffer
, i
);
3385 load_indirect_parameters(cmd_buffer
, draw
, false);
3387 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3388 prim
.IndirectParameterEnable
= true;
3389 prim
.PredicateEnable
= true;
3390 prim
.VertexAccessType
= SEQUENTIAL
;
3391 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3398 void genX(CmdDrawIndexedIndirectCountKHR
)(
3399 VkCommandBuffer commandBuffer
,
3401 VkDeviceSize offset
,
3402 VkBuffer _countBuffer
,
3403 VkDeviceSize countBufferOffset
,
3404 uint32_t maxDrawCount
,
3407 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3408 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3409 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3410 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3411 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3412 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3414 if (anv_batch_has_error(&cmd_buffer
->batch
))
3417 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3419 struct anv_address count_address
=
3420 anv_address_add(count_buffer
->address
, countBufferOffset
);
3422 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3423 cmd_state
->conditional_render_enabled
);
3425 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3426 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3428 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3429 if (cmd_state
->conditional_render_enabled
) {
3430 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3432 emit_draw_count_predicate(cmd_buffer
, i
);
3435 emit_draw_count_predicate(cmd_buffer
, i
);
3438 /* TODO: We need to stomp base vertex to 0 somehow */
3439 if (vs_prog_data
->uses_firstvertex
||
3440 vs_prog_data
->uses_baseinstance
)
3441 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3442 if (vs_prog_data
->uses_drawid
)
3443 emit_draw_index(cmd_buffer
, i
);
3445 load_indirect_parameters(cmd_buffer
, draw
, true);
3447 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3448 prim
.IndirectParameterEnable
= true;
3449 prim
.PredicateEnable
= true;
3450 prim
.VertexAccessType
= RANDOM
;
3451 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3458 void genX(CmdBeginTransformFeedbackEXT
)(
3459 VkCommandBuffer commandBuffer
,
3460 uint32_t firstCounterBuffer
,
3461 uint32_t counterBufferCount
,
3462 const VkBuffer
* pCounterBuffers
,
3463 const VkDeviceSize
* pCounterBufferOffsets
)
3465 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3467 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3468 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3469 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3471 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3473 * "Ssoftware must ensure that no HW stream output operations can be in
3474 * process or otherwise pending at the point that the MI_LOAD/STORE
3475 * commands are processed. This will likely require a pipeline flush."
3477 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3478 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3480 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3481 /* If we have a counter buffer, this is a resume so we need to load the
3482 * value into the streamout offset register. Otherwise, this is a begin
3483 * and we need to reset it to zero.
3485 if (pCounterBuffers
&&
3486 idx
>= firstCounterBuffer
&&
3487 idx
- firstCounterBuffer
< counterBufferCount
&&
3488 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3489 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3490 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3491 uint64_t offset
= pCounterBufferOffsets
?
3492 pCounterBufferOffsets
[cb_idx
] : 0;
3494 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3495 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3496 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3500 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3501 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3507 cmd_buffer
->state
.xfb_enabled
= true;
3508 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3511 void genX(CmdEndTransformFeedbackEXT
)(
3512 VkCommandBuffer commandBuffer
,
3513 uint32_t firstCounterBuffer
,
3514 uint32_t counterBufferCount
,
3515 const VkBuffer
* pCounterBuffers
,
3516 const VkDeviceSize
* pCounterBufferOffsets
)
3518 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3520 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3521 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3522 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3524 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3526 * "Ssoftware must ensure that no HW stream output operations can be in
3527 * process or otherwise pending at the point that the MI_LOAD/STORE
3528 * commands are processed. This will likely require a pipeline flush."
3530 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3531 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3533 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3534 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3536 /* If we have a counter buffer, this is a resume so we need to load the
3537 * value into the streamout offset register. Otherwise, this is a begin
3538 * and we need to reset it to zero.
3540 if (pCounterBuffers
&&
3541 cb_idx
< counterBufferCount
&&
3542 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3543 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3544 uint64_t offset
= pCounterBufferOffsets
?
3545 pCounterBufferOffsets
[cb_idx
] : 0;
3547 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3548 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3550 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3555 cmd_buffer
->state
.xfb_enabled
= false;
3556 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3560 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3562 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3563 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3566 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3567 if (result
!= VK_SUCCESS
) {
3568 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3570 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3571 if (result
!= VK_SUCCESS
)
3574 /* Re-emit state base addresses so we get the new surface state base
3575 * address before we start emitting binding tables etc.
3577 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3579 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3580 if (result
!= VK_SUCCESS
) {
3581 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3586 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3587 if (result
!= VK_SUCCESS
) {
3588 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3592 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3593 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3594 .BindingTablePointer
= surfaces
.offset
,
3595 .SamplerStatePointer
= samplers
.offset
,
3597 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3599 struct anv_state state
=
3600 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3601 pipeline
->interface_descriptor_data
,
3602 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3605 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3606 anv_batch_emit(&cmd_buffer
->batch
,
3607 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3608 mid
.InterfaceDescriptorTotalLength
= size
;
3609 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3616 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3618 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3621 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3623 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3625 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3628 genX(cmd_buffer_aux_map_state
)(cmd_buffer
);
3631 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3632 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3634 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3635 * the only bits that are changed are scoreboard related: Scoreboard
3636 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3637 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3640 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3641 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3643 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3646 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3647 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3648 /* FIXME: figure out descriptors for gen7 */
3649 result
= flush_compute_descriptor_set(cmd_buffer
);
3650 if (result
!= VK_SUCCESS
)
3653 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3656 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3657 struct anv_state push_state
=
3658 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3660 if (push_state
.alloc_size
) {
3661 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3662 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3663 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3667 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3670 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3672 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3678 verify_cmd_parser(const struct anv_device
*device
,
3679 int required_version
,
3680 const char *function
)
3682 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3683 return vk_errorf(device
->instance
, device
->instance
,
3684 VK_ERROR_FEATURE_NOT_PRESENT
,
3685 "cmd parser version %d is required for %s",
3686 required_version
, function
);
3695 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3696 uint32_t baseGroupX
,
3697 uint32_t baseGroupY
,
3698 uint32_t baseGroupZ
)
3700 if (anv_batch_has_error(&cmd_buffer
->batch
))
3703 struct anv_push_constants
*push
=
3704 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3705 if (push
->base_work_group_id
[0] != baseGroupX
||
3706 push
->base_work_group_id
[1] != baseGroupY
||
3707 push
->base_work_group_id
[2] != baseGroupZ
) {
3708 push
->base_work_group_id
[0] = baseGroupX
;
3709 push
->base_work_group_id
[1] = baseGroupY
;
3710 push
->base_work_group_id
[2] = baseGroupZ
;
3712 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3716 void genX(CmdDispatch
)(
3717 VkCommandBuffer commandBuffer
,
3722 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3725 void genX(CmdDispatchBase
)(
3726 VkCommandBuffer commandBuffer
,
3727 uint32_t baseGroupX
,
3728 uint32_t baseGroupY
,
3729 uint32_t baseGroupZ
,
3730 uint32_t groupCountX
,
3731 uint32_t groupCountY
,
3732 uint32_t groupCountZ
)
3734 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3735 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3736 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3738 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3739 baseGroupY
, baseGroupZ
);
3741 if (anv_batch_has_error(&cmd_buffer
->batch
))
3744 if (prog_data
->uses_num_work_groups
) {
3745 struct anv_state state
=
3746 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3747 uint32_t *sizes
= state
.map
;
3748 sizes
[0] = groupCountX
;
3749 sizes
[1] = groupCountY
;
3750 sizes
[2] = groupCountZ
;
3751 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3752 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3753 .offset
= state
.offset
,
3757 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3759 if (cmd_buffer
->state
.conditional_render_enabled
)
3760 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3762 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3763 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3764 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3765 ggw
.ThreadDepthCounterMaximum
= 0;
3766 ggw
.ThreadHeightCounterMaximum
= 0;
3767 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3768 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3769 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3770 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3771 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3772 ggw
.BottomExecutionMask
= 0xffffffff;
3775 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3778 #define GPGPU_DISPATCHDIMX 0x2500
3779 #define GPGPU_DISPATCHDIMY 0x2504
3780 #define GPGPU_DISPATCHDIMZ 0x2508
3782 void genX(CmdDispatchIndirect
)(
3783 VkCommandBuffer commandBuffer
,
3785 VkDeviceSize offset
)
3787 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3788 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3789 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3790 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3791 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3792 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3794 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3797 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3798 * indirect dispatch registers to be written.
3800 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3801 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3805 if (prog_data
->uses_num_work_groups
)
3806 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3808 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3810 struct gen_mi_builder b
;
3811 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3813 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
3814 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
3815 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
3817 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
3818 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
3819 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
3822 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3823 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
3824 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3825 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3826 mip
.LoadOperation
= LOAD_LOAD
;
3827 mip
.CombineOperation
= COMBINE_SET
;
3828 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3831 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3832 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
3833 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3834 mip
.LoadOperation
= LOAD_LOAD
;
3835 mip
.CombineOperation
= COMBINE_OR
;
3836 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3839 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3840 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
3841 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3842 mip
.LoadOperation
= LOAD_LOAD
;
3843 mip
.CombineOperation
= COMBINE_OR
;
3844 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3847 /* predicate = !predicate; */
3848 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3849 mip
.LoadOperation
= LOAD_LOADINV
;
3850 mip
.CombineOperation
= COMBINE_OR
;
3851 mip
.CompareOperation
= COMPARE_FALSE
;
3855 if (cmd_buffer
->state
.conditional_render_enabled
) {
3856 /* predicate &= !(conditional_rendering_predicate == 0); */
3857 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
3858 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
3859 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3860 mip
.LoadOperation
= LOAD_LOADINV
;
3861 mip
.CombineOperation
= COMBINE_AND
;
3862 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3867 #else /* GEN_GEN > 7 */
3868 if (cmd_buffer
->state
.conditional_render_enabled
)
3869 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3872 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3873 ggw
.IndirectParameterEnable
= true;
3874 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3875 cmd_buffer
->state
.conditional_render_enabled
;
3876 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3877 ggw
.ThreadDepthCounterMaximum
= 0;
3878 ggw
.ThreadHeightCounterMaximum
= 0;
3879 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3880 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3881 ggw
.BottomExecutionMask
= 0xffffffff;
3884 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3888 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3891 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3893 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3896 #if GEN_GEN >= 8 && GEN_GEN < 10
3897 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3899 * Software must clear the COLOR_CALC_STATE Valid field in
3900 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3901 * with Pipeline Select set to GPGPU.
3903 * The internal hardware docs recommend the same workaround for Gen9
3906 if (pipeline
== GPGPU
)
3907 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3911 if (pipeline
== _3D
) {
3912 /* There is a mid-object preemption workaround which requires you to
3913 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
3914 * even without preemption, we have issues with geometry flickering when
3915 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
3918 const uint32_t subslices
=
3919 MAX2(cmd_buffer
->device
->instance
->physicalDevice
.subslice_total
, 1);
3920 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
3921 vfe
.MaximumNumberofThreads
=
3922 devinfo
->max_cs_threads
* subslices
- 1;
3923 vfe
.NumberofURBEntries
= 2;
3924 vfe
.URBEntryAllocationSize
= 2;
3929 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3930 * PIPELINE_SELECT [DevBWR+]":
3934 * Software must ensure all the write caches are flushed through a
3935 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3936 * command to invalidate read only caches prior to programming
3937 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3939 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3940 pc
.RenderTargetCacheFlushEnable
= true;
3941 pc
.DepthCacheFlushEnable
= true;
3942 pc
.DCFlushEnable
= true;
3943 pc
.PostSyncOperation
= NoWrite
;
3944 pc
.CommandStreamerStallEnable
= true;
3946 pc
.TileCacheFlushEnable
= true;
3950 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3951 pc
.TextureCacheInvalidationEnable
= true;
3952 pc
.ConstantCacheInvalidationEnable
= true;
3953 pc
.StateCacheInvalidationEnable
= true;
3954 pc
.InstructionCacheInvalidateEnable
= true;
3955 pc
.PostSyncOperation
= NoWrite
;
3957 pc
.TileCacheFlushEnable
= true;
3961 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3965 ps
.PipelineSelection
= pipeline
;
3969 if (devinfo
->is_geminilake
) {
3972 * "This chicken bit works around a hardware issue with barrier logic
3973 * encountered when switching between GPGPU and 3D pipelines. To
3974 * workaround the issue, this mode bit should be set after a pipeline
3978 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3980 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3981 : GLK_BARRIER_MODE_3D_HULL
,
3982 .GLKBarrierModeMask
= 1);
3983 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3987 cmd_buffer
->state
.current_pipeline
= pipeline
;
3991 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3993 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3997 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3999 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
4003 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
4008 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
4010 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
4011 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
4012 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
4013 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
4014 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
4015 * Depth Flush Bit set, followed by another pipelined depth stall
4016 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
4017 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
4018 * via a preceding MI_FLUSH)."
4020 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4021 pipe
.DepthStallEnable
= true;
4023 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4024 pipe
.DepthCacheFlushEnable
= true;
4026 pipe
.TileCacheFlushEnable
= true;
4029 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4030 pipe
.DepthStallEnable
= true;
4035 * Update the pixel hashing modes that determine the balancing of PS threads
4036 * across subslices and slices.
4038 * \param width Width bound of the rendering area (already scaled down if \p
4039 * scale is greater than 1).
4040 * \param height Height bound of the rendering area (already scaled down if \p
4041 * scale is greater than 1).
4042 * \param scale The number of framebuffer samples that could potentially be
4043 * affected by an individual channel of the PS thread. This is
4044 * typically one for single-sampled rendering, but for operations
4045 * like CCS resolves and fast clears a single PS invocation may
4046 * update a huge number of pixels, in which case a finer
4047 * balancing is desirable in order to maximally utilize the
4048 * bandwidth available. UINT_MAX can be used as shorthand for
4049 * "finest hashing mode available".
4052 genX(cmd_buffer_emit_hashing_mode
)(struct anv_cmd_buffer
*cmd_buffer
,
4053 unsigned width
, unsigned height
,
4057 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4058 const unsigned slice_hashing
[] = {
4059 /* Because all Gen9 platforms with more than one slice require
4060 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4061 * block is guaranteed to suffer from substantial imbalance, with one
4062 * subslice receiving twice as much work as the other two in the
4065 * The performance impact of that would be particularly severe when
4066 * three-way hashing is also in use for slice balancing (which is the
4067 * case for all Gen9 GT4 platforms), because one of the slices
4068 * receives one every three 16x16 blocks in either direction, which
4069 * is roughly the periodicity of the underlying subslice imbalance
4070 * pattern ("roughly" because in reality the hardware's
4071 * implementation of three-way hashing doesn't do exact modulo 3
4072 * arithmetic, which somewhat decreases the magnitude of this effect
4073 * in practice). This leads to a systematic subslice imbalance
4074 * within that slice regardless of the size of the primitive. The
4075 * 32x32 hashing mode guarantees that the subslice imbalance within a
4076 * single slice hashing block is minimal, largely eliminating this
4080 /* Finest slice hashing mode available. */
4083 const unsigned subslice_hashing
[] = {
4084 /* 16x16 would provide a slight cache locality benefit especially
4085 * visible in the sampler L1 cache efficiency of low-bandwidth
4086 * non-LLC platforms, but it comes at the cost of greater subslice
4087 * imbalance for primitives of dimensions approximately intermediate
4088 * between 16x4 and 16x16.
4091 /* Finest subslice hashing mode available. */
4094 /* Dimensions of the smallest hashing block of a given hashing mode. If
4095 * the rendering area is smaller than this there can't possibly be any
4096 * benefit from switching to this mode, so we optimize out the
4099 const unsigned min_size
[][2] = {
4103 const unsigned idx
= scale
> 1;
4105 if (cmd_buffer
->state
.current_hash_scale
!= scale
&&
4106 (width
> min_size
[idx
][0] || height
> min_size
[idx
][1])) {
4109 anv_pack_struct(>_mode
, GENX(GT_MODE
),
4110 .SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0),
4111 .SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0),
4112 .SubsliceHashing
= subslice_hashing
[idx
],
4113 .SubsliceHashingMask
= -1);
4115 cmd_buffer
->state
.pending_pipe_bits
|=
4116 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
4117 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4119 emit_lri(&cmd_buffer
->batch
, GENX(GT_MODE_num
), gt_mode
);
4121 cmd_buffer
->state
.current_hash_scale
= scale
;
4127 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4129 struct anv_device
*device
= cmd_buffer
->device
;
4130 const struct anv_image_view
*iview
=
4131 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4132 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4134 /* FIXME: Width and Height are wrong */
4136 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4138 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4139 device
->isl_dev
.ds
.size
/ 4);
4143 struct isl_depth_stencil_hiz_emit_info info
= { };
4146 info
.view
= &iview
->planes
[0].isl
;
4148 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4149 uint32_t depth_plane
=
4150 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4151 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4153 info
.depth_surf
= &surface
->isl
;
4155 info
.depth_address
=
4156 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4157 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4158 image
->planes
[depth_plane
].address
.bo
,
4159 image
->planes
[depth_plane
].address
.offset
+
4162 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4165 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4166 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4167 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
4168 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4171 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4172 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4173 image
->planes
[depth_plane
].address
.bo
,
4174 image
->planes
[depth_plane
].address
.offset
+
4175 image
->planes
[depth_plane
].aux_surface
.offset
);
4177 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4181 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4182 uint32_t stencil_plane
=
4183 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4184 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4186 info
.stencil_surf
= &surface
->isl
;
4188 info
.stencil_address
=
4189 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4190 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4191 image
->planes
[stencil_plane
].address
.bo
,
4192 image
->planes
[stencil_plane
].address
.offset
+
4195 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4198 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4200 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
4204 * This ANDs the view mask of the current subpass with the pending clear
4205 * views in the attachment to get the mask of views active in the subpass
4206 * that still need to be cleared.
4208 static inline uint32_t
4209 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4210 const struct anv_attachment_state
*att_state
)
4212 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4216 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4217 const struct anv_attachment_state
*att_state
)
4219 if (!cmd_state
->subpass
->view_mask
)
4222 uint32_t pending_clear_mask
=
4223 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4225 return pending_clear_mask
& 1;
4229 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4232 const uint32_t last_subpass_idx
=
4233 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4234 const struct anv_subpass
*last_subpass
=
4235 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4236 return last_subpass
== cmd_state
->subpass
;
4240 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4241 uint32_t subpass_id
)
4243 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4244 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4245 cmd_state
->subpass
= subpass
;
4247 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4249 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4250 * different views. If the client asks for instancing, we need to use the
4251 * Instance Data Step Rate to ensure that we repeat the client's
4252 * per-instance data once for each view. Since this bit is in
4253 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4257 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4259 /* It is possible to start a render pass with an old pipeline. Because the
4260 * render pass and subpass index are both baked into the pipeline, this is
4261 * highly unlikely. In order to do so, it requires that you have a render
4262 * pass with a single subpass and that you use that render pass twice
4263 * back-to-back and use the same pipeline at the start of the second render
4264 * pass as at the end of the first. In order to avoid unpredictable issues
4265 * with this edge case, we just dirty the pipeline at the start of every
4268 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4270 /* Accumulate any subpass flushes that need to happen before the subpass */
4271 cmd_buffer
->state
.pending_pipe_bits
|=
4272 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4274 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4275 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4277 bool is_multiview
= subpass
->view_mask
!= 0;
4279 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4280 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4281 if (a
== VK_ATTACHMENT_UNUSED
)
4284 assert(a
< cmd_state
->pass
->attachment_count
);
4285 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4287 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4288 const struct anv_image
*image
= iview
->image
;
4290 /* A resolve is necessary before use as an input attachment if the clear
4291 * color or auxiliary buffer usage isn't supported by the sampler.
4293 const bool input_needs_resolve
=
4294 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4295 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4297 VkImageLayout target_layout
;
4298 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4299 !input_needs_resolve
) {
4300 /* Layout transitions before the final only help to enable sampling
4301 * as an input attachment. If the input attachment supports sampling
4302 * using the auxiliary surface, we can skip such transitions by
4303 * making the target layout one that is CCS-aware.
4305 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4307 target_layout
= subpass
->attachments
[i
].layout
;
4310 uint32_t base_layer
, layer_count
;
4311 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4313 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4314 iview
->planes
[0].isl
.base_level
);
4316 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4317 layer_count
= fb
->layers
;
4320 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4321 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4322 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4323 iview
->planes
[0].isl
.base_level
, 1,
4324 base_layer
, layer_count
,
4325 att_state
->current_layout
, target_layout
);
4328 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4329 transition_depth_buffer(cmd_buffer
, image
,
4330 att_state
->current_layout
, target_layout
);
4331 att_state
->aux_usage
=
4332 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4333 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4336 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4337 transition_stencil_buffer(cmd_buffer
, image
,
4338 iview
->planes
[0].isl
.base_level
, 1,
4339 base_layer
, layer_count
,
4340 att_state
->current_layout
, target_layout
);
4342 att_state
->current_layout
= target_layout
;
4344 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4345 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4347 /* Multi-planar images are not supported as attachments */
4348 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4349 assert(image
->n_planes
== 1);
4351 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4352 uint32_t clear_layer_count
= fb
->layers
;
4354 if (att_state
->fast_clear
&&
4355 do_first_layer_clear(cmd_state
, att_state
)) {
4356 /* We only support fast-clears on the first layer */
4357 assert(iview
->planes
[0].isl
.base_level
== 0);
4358 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4360 union isl_color_value clear_color
= {};
4361 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4362 if (iview
->image
->samples
== 1) {
4363 anv_image_ccs_op(cmd_buffer
, image
,
4364 iview
->planes
[0].isl
.format
,
4365 VK_IMAGE_ASPECT_COLOR_BIT
,
4366 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4370 anv_image_mcs_op(cmd_buffer
, image
,
4371 iview
->planes
[0].isl
.format
,
4372 VK_IMAGE_ASPECT_COLOR_BIT
,
4373 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4378 clear_layer_count
--;
4380 att_state
->pending_clear_views
&= ~1;
4382 if (att_state
->clear_color_is_zero
) {
4383 /* This image has the auxiliary buffer enabled. We can mark the
4384 * subresource as not needing a resolve because the clear color
4385 * will match what's in every RENDER_SURFACE_STATE object when
4386 * it's being used for sampling.
4388 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4389 VK_IMAGE_ASPECT_COLOR_BIT
,
4390 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4392 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4393 VK_IMAGE_ASPECT_COLOR_BIT
,
4394 ANV_FAST_CLEAR_ANY
);
4398 /* From the VkFramebufferCreateInfo spec:
4400 * "If the render pass uses multiview, then layers must be one and each
4401 * attachment requires a number of layers that is greater than the
4402 * maximum bit index set in the view mask in the subpasses in which it
4405 * So if multiview is active we ignore the number of layers in the
4406 * framebuffer and instead we honor the view mask from the subpass.
4409 assert(image
->n_planes
== 1);
4410 uint32_t pending_clear_mask
=
4411 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4414 for_each_bit(layer_idx
, pending_clear_mask
) {
4416 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4418 anv_image_clear_color(cmd_buffer
, image
,
4419 VK_IMAGE_ASPECT_COLOR_BIT
,
4420 att_state
->aux_usage
,
4421 iview
->planes
[0].isl
.format
,
4422 iview
->planes
[0].isl
.swizzle
,
4423 iview
->planes
[0].isl
.base_level
,
4426 vk_to_isl_color(att_state
->clear_value
.color
));
4429 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4430 } else if (clear_layer_count
> 0) {
4431 assert(image
->n_planes
== 1);
4432 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4433 att_state
->aux_usage
,
4434 iview
->planes
[0].isl
.format
,
4435 iview
->planes
[0].isl
.swizzle
,
4436 iview
->planes
[0].isl
.base_level
,
4437 base_clear_layer
, clear_layer_count
,
4439 vk_to_isl_color(att_state
->clear_value
.color
));
4441 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4442 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4443 if (att_state
->fast_clear
&& !is_multiview
) {
4444 /* We currently only support HiZ for single-layer images */
4445 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4446 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4447 assert(iview
->planes
[0].isl
.base_level
== 0);
4448 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4449 assert(fb
->layers
== 1);
4452 anv_image_hiz_clear(cmd_buffer
, image
,
4453 att_state
->pending_clear_aspects
,
4454 iview
->planes
[0].isl
.base_level
,
4455 iview
->planes
[0].isl
.base_array_layer
,
4456 fb
->layers
, render_area
,
4457 att_state
->clear_value
.depthStencil
.stencil
);
4458 } else if (is_multiview
) {
4459 uint32_t pending_clear_mask
=
4460 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4463 for_each_bit(layer_idx
, pending_clear_mask
) {
4465 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4467 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4468 att_state
->pending_clear_aspects
,
4469 att_state
->aux_usage
,
4470 iview
->planes
[0].isl
.base_level
,
4473 att_state
->clear_value
.depthStencil
.depth
,
4474 att_state
->clear_value
.depthStencil
.stencil
);
4477 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4479 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4480 att_state
->pending_clear_aspects
,
4481 att_state
->aux_usage
,
4482 iview
->planes
[0].isl
.base_level
,
4483 iview
->planes
[0].isl
.base_array_layer
,
4484 fb
->layers
, render_area
,
4485 att_state
->clear_value
.depthStencil
.depth
,
4486 att_state
->clear_value
.depthStencil
.stencil
);
4489 assert(att_state
->pending_clear_aspects
== 0);
4493 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4494 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4495 iview
->planes
[0].isl
.base_level
== 0 &&
4496 iview
->planes
[0].isl
.base_array_layer
== 0) {
4497 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4498 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4499 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4500 false /* copy to ss */);
4503 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4504 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4505 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4506 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4507 false /* copy to ss */);
4511 if (subpass
->attachments
[i
].usage
==
4512 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4513 /* We assume that if we're starting a subpass, we're going to do some
4514 * rendering so we may end up with compressed data.
4516 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4517 VK_IMAGE_ASPECT_COLOR_BIT
,
4518 att_state
->aux_usage
,
4519 iview
->planes
[0].isl
.base_level
,
4520 iview
->planes
[0].isl
.base_array_layer
,
4522 } else if (subpass
->attachments
[i
].usage
==
4523 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4524 /* We may be writing depth or stencil so we need to mark the surface.
4525 * Unfortunately, there's no way to know at this point whether the
4526 * depth or stencil tests used will actually write to the surface.
4528 * Even though stencil may be plane 1, it always shares a base_level
4531 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4532 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4533 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4534 VK_IMAGE_ASPECT_DEPTH_BIT
,
4535 att_state
->aux_usage
,
4536 ds_view
->base_level
,
4537 ds_view
->base_array_layer
,
4540 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4541 /* Even though stencil may be plane 1, it always shares a
4542 * base_level with depth.
4544 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4545 VK_IMAGE_ASPECT_STENCIL_BIT
,
4547 ds_view
->base_level
,
4548 ds_view
->base_array_layer
,
4553 /* If multiview is enabled, then we are only done clearing when we no
4554 * longer have pending layers to clear, or when we have processed the
4555 * last subpass that uses this attachment.
4557 if (!is_multiview
||
4558 att_state
->pending_clear_views
== 0 ||
4559 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4560 att_state
->pending_clear_aspects
= 0;
4563 att_state
->pending_load_aspects
= 0;
4566 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4569 static enum blorp_filter
4570 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4573 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4574 return BLORP_FILTER_SAMPLE_0
;
4575 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4576 return BLORP_FILTER_AVERAGE
;
4577 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4578 return BLORP_FILTER_MIN_SAMPLE
;
4579 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4580 return BLORP_FILTER_MAX_SAMPLE
;
4582 return BLORP_FILTER_NONE
;
4587 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4589 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4590 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4591 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4592 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4594 if (subpass
->has_color_resolve
) {
4595 /* We are about to do some MSAA resolves. We need to flush so that the
4596 * result of writes to the MSAA color attachments show up in the sampler
4597 * when we blit to the single-sampled resolve target.
4599 cmd_buffer
->state
.pending_pipe_bits
|=
4600 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4601 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4603 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4604 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4605 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4607 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4610 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4611 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4613 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4614 /* From the Vulkan 1.0 spec:
4616 * If the first use of an attachment in a render pass is as a
4617 * resolve attachment, then the loadOp is effectively ignored
4618 * as the resolve is guaranteed to overwrite all pixels in the
4621 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4624 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
4625 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
4627 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4629 enum isl_aux_usage src_aux_usage
=
4630 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4631 enum isl_aux_usage dst_aux_usage
=
4632 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4634 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4635 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4637 anv_image_msaa_resolve(cmd_buffer
,
4638 src_iview
->image
, src_aux_usage
,
4639 src_iview
->planes
[0].isl
.base_level
,
4640 src_iview
->planes
[0].isl
.base_array_layer
,
4641 dst_iview
->image
, dst_aux_usage
,
4642 dst_iview
->planes
[0].isl
.base_level
,
4643 dst_iview
->planes
[0].isl
.base_array_layer
,
4644 VK_IMAGE_ASPECT_COLOR_BIT
,
4645 render_area
.offset
.x
, render_area
.offset
.y
,
4646 render_area
.offset
.x
, render_area
.offset
.y
,
4647 render_area
.extent
.width
,
4648 render_area
.extent
.height
,
4649 fb
->layers
, BLORP_FILTER_NONE
);
4653 if (subpass
->ds_resolve_attachment
) {
4654 /* We are about to do some MSAA resolves. We need to flush so that the
4655 * result of writes to the MSAA depth attachments show up in the sampler
4656 * when we blit to the single-sampled resolve target.
4658 cmd_buffer
->state
.pending_pipe_bits
|=
4659 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4660 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4662 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4663 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4665 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4666 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4668 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4669 /* From the Vulkan 1.0 spec:
4671 * If the first use of an attachment in a render pass is as a
4672 * resolve attachment, then the loadOp is effectively ignored
4673 * as the resolve is guaranteed to overwrite all pixels in the
4676 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4679 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
4680 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
4682 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4684 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4685 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4687 struct anv_attachment_state
*src_state
=
4688 &cmd_state
->attachments
[src_att
];
4689 struct anv_attachment_state
*dst_state
=
4690 &cmd_state
->attachments
[dst_att
];
4692 /* MSAA resolves sample from the source attachment. Transition the
4693 * depth attachment first to get rid of any HiZ that we may not be
4696 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4697 src_state
->current_layout
,
4698 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4699 src_state
->aux_usage
=
4700 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4701 VK_IMAGE_ASPECT_DEPTH_BIT
,
4702 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4703 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4705 /* MSAA resolves write to the resolve attachment as if it were any
4706 * other transfer op. Transition the resolve attachment accordingly.
4708 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4710 /* If our render area is the entire size of the image, we're going to
4711 * blow it all away so we can claim the initial layout is UNDEFINED
4712 * and we'll get a HiZ ambiguate instead of a resolve.
4714 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4715 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4716 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4717 render_area
.extent
.height
== dst_iview
->extent
.height
)
4718 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4720 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4722 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4723 dst_state
->aux_usage
=
4724 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4725 VK_IMAGE_ASPECT_DEPTH_BIT
,
4726 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4727 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4729 enum blorp_filter filter
=
4730 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4732 anv_image_msaa_resolve(cmd_buffer
,
4733 src_iview
->image
, src_state
->aux_usage
,
4734 src_iview
->planes
[0].isl
.base_level
,
4735 src_iview
->planes
[0].isl
.base_array_layer
,
4736 dst_iview
->image
, dst_state
->aux_usage
,
4737 dst_iview
->planes
[0].isl
.base_level
,
4738 dst_iview
->planes
[0].isl
.base_array_layer
,
4739 VK_IMAGE_ASPECT_DEPTH_BIT
,
4740 render_area
.offset
.x
, render_area
.offset
.y
,
4741 render_area
.offset
.x
, render_area
.offset
.y
,
4742 render_area
.extent
.width
,
4743 render_area
.extent
.height
,
4744 fb
->layers
, filter
);
4747 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4748 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4750 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4751 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4753 enum blorp_filter filter
=
4754 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4756 anv_image_msaa_resolve(cmd_buffer
,
4757 src_iview
->image
, src_aux_usage
,
4758 src_iview
->planes
[0].isl
.base_level
,
4759 src_iview
->planes
[0].isl
.base_array_layer
,
4760 dst_iview
->image
, dst_aux_usage
,
4761 dst_iview
->planes
[0].isl
.base_level
,
4762 dst_iview
->planes
[0].isl
.base_array_layer
,
4763 VK_IMAGE_ASPECT_STENCIL_BIT
,
4764 render_area
.offset
.x
, render_area
.offset
.y
,
4765 render_area
.offset
.x
, render_area
.offset
.y
,
4766 render_area
.extent
.width
,
4767 render_area
.extent
.height
,
4768 fb
->layers
, filter
);
4773 /* On gen7, we have to store a texturable version of the stencil buffer in
4774 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
4775 * forth at strategic points. Stencil writes are only allowed in three
4778 * - VK_IMAGE_LAYOUT_GENERAL
4779 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
4780 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
4781 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
4783 * For general, we have no nice opportunity to transition so we do the copy
4784 * to the shadow unconditionally at the end of the subpass. For transfer
4785 * destinations, we can update it as part of the transfer op. For the
4786 * other two, we delay the copy until a transition into some other layout.
4788 if (subpass
->depth_stencil_attachment
) {
4789 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
4790 assert(a
!= VK_ATTACHMENT_UNUSED
);
4792 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4793 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
4794 const struct anv_image
*image
= iview
->image
;
4796 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4797 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
4798 VK_IMAGE_ASPECT_STENCIL_BIT
);
4800 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
4801 att_state
->current_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
4802 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
4803 anv_image_copy_to_shadow(cmd_buffer
, image
,
4804 VK_IMAGE_ASPECT_STENCIL_BIT
,
4805 iview
->planes
[plane
].isl
.base_level
, 1,
4806 iview
->planes
[plane
].isl
.base_array_layer
,
4811 #endif /* GEN_GEN == 7 */
4813 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4814 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4815 if (a
== VK_ATTACHMENT_UNUSED
)
4818 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4821 assert(a
< cmd_state
->pass
->attachment_count
);
4822 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4823 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4824 const struct anv_image
*image
= iview
->image
;
4826 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4827 image
->vk_format
!= iview
->vk_format
) {
4828 enum anv_fast_clear_type fast_clear_type
=
4829 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4830 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4831 att_state
->current_layout
);
4833 /* If any clear color was used, flush it down the aux surfaces. If we
4834 * don't do it now using the view's format we might use the clear
4835 * color incorrectly in the following resolves (for example with an
4836 * SRGB view & a UNORM image).
4838 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4839 anv_perf_warn(cmd_buffer
->device
->instance
, iview
,
4840 "Doing a partial resolve to get rid of clear color at the "
4841 "end of a renderpass due to an image/view format mismatch");
4843 uint32_t base_layer
, layer_count
;
4844 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4846 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4847 iview
->planes
[0].isl
.base_level
);
4849 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4850 layer_count
= fb
->layers
;
4853 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4854 uint32_t array_layer
= base_layer
+ a
;
4855 if (image
->samples
== 1) {
4856 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4857 iview
->planes
[0].isl
.format
,
4858 VK_IMAGE_ASPECT_COLOR_BIT
,
4859 iview
->planes
[0].isl
.base_level
,
4861 ISL_AUX_OP_PARTIAL_RESOLVE
,
4862 ANV_FAST_CLEAR_NONE
);
4864 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4865 iview
->planes
[0].isl
.format
,
4866 VK_IMAGE_ASPECT_COLOR_BIT
,
4868 ISL_AUX_OP_PARTIAL_RESOLVE
,
4869 ANV_FAST_CLEAR_NONE
);
4875 /* Transition the image into the final layout for this render pass */
4876 VkImageLayout target_layout
=
4877 cmd_state
->pass
->attachments
[a
].final_layout
;
4879 uint32_t base_layer
, layer_count
;
4880 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4882 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4883 iview
->planes
[0].isl
.base_level
);
4885 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4886 layer_count
= fb
->layers
;
4889 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4890 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4891 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4892 iview
->planes
[0].isl
.base_level
, 1,
4893 base_layer
, layer_count
,
4894 att_state
->current_layout
, target_layout
);
4897 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4898 transition_depth_buffer(cmd_buffer
, image
,
4899 att_state
->current_layout
, target_layout
);
4902 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4903 transition_stencil_buffer(cmd_buffer
, image
,
4904 iview
->planes
[0].isl
.base_level
, 1,
4905 base_layer
, layer_count
,
4906 att_state
->current_layout
, target_layout
);
4910 /* Accumulate any subpass flushes that need to happen after the subpass.
4911 * Yes, they do get accumulated twice in the NextSubpass case but since
4912 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4913 * ORing the bits in twice so it's harmless.
4915 cmd_buffer
->state
.pending_pipe_bits
|=
4916 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4919 void genX(CmdBeginRenderPass
)(
4920 VkCommandBuffer commandBuffer
,
4921 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4922 VkSubpassContents contents
)
4924 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4925 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4926 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4928 cmd_buffer
->state
.framebuffer
= framebuffer
;
4929 cmd_buffer
->state
.pass
= pass
;
4930 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4932 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4934 /* If we failed to setup the attachments we should not try to go further */
4935 if (result
!= VK_SUCCESS
) {
4936 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4940 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4942 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4945 void genX(CmdBeginRenderPass2KHR
)(
4946 VkCommandBuffer commandBuffer
,
4947 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4948 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4950 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4951 pSubpassBeginInfo
->contents
);
4954 void genX(CmdNextSubpass
)(
4955 VkCommandBuffer commandBuffer
,
4956 VkSubpassContents contents
)
4958 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4960 if (anv_batch_has_error(&cmd_buffer
->batch
))
4963 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4965 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4966 cmd_buffer_end_subpass(cmd_buffer
);
4967 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4970 void genX(CmdNextSubpass2KHR
)(
4971 VkCommandBuffer commandBuffer
,
4972 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4973 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4975 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4978 void genX(CmdEndRenderPass
)(
4979 VkCommandBuffer commandBuffer
)
4981 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4983 if (anv_batch_has_error(&cmd_buffer
->batch
))
4986 cmd_buffer_end_subpass(cmd_buffer
);
4988 cmd_buffer
->state
.hiz_enabled
= false;
4991 anv_dump_add_attachments(cmd_buffer
);
4994 /* Remove references to render pass specific state. This enables us to
4995 * detect whether or not we're in a renderpass.
4997 cmd_buffer
->state
.framebuffer
= NULL
;
4998 cmd_buffer
->state
.pass
= NULL
;
4999 cmd_buffer
->state
.subpass
= NULL
;
5002 void genX(CmdEndRenderPass2KHR
)(
5003 VkCommandBuffer commandBuffer
,
5004 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5006 genX(CmdEndRenderPass
)(commandBuffer
);
5010 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
5012 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5013 struct gen_mi_builder b
;
5014 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5016 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
5017 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
5018 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
5020 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
5021 mip
.LoadOperation
= LOAD_LOADINV
;
5022 mip
.CombineOperation
= COMBINE_SET
;
5023 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
5028 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5029 void genX(CmdBeginConditionalRenderingEXT
)(
5030 VkCommandBuffer commandBuffer
,
5031 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5033 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5034 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5035 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5036 struct anv_address value_address
=
5037 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
5039 const bool isInverted
= pConditionalRenderingBegin
->flags
&
5040 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
5042 cmd_state
->conditional_render_enabled
= true;
5044 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5046 struct gen_mi_builder b
;
5047 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5049 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5051 * If the value of the predicate in buffer memory changes
5052 * while conditional rendering is active, the rendering commands
5053 * may be discarded in an implementation-dependent way.
5054 * Some implementations may latch the value of the predicate
5055 * upon beginning conditional rendering while others
5056 * may read it before every rendering command.
5058 * So it's perfectly fine to read a value from the buffer once.
5060 struct gen_mi_value value
= gen_mi_mem32(value_address
);
5062 /* Precompute predicate result, it is necessary to support secondary
5063 * command buffers since it is unknown if conditional rendering is
5064 * inverted when populating them.
5066 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
5067 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
5068 gen_mi_ult(&b
, gen_mi_imm(0), value
));
5071 void genX(CmdEndConditionalRenderingEXT
)(
5072 VkCommandBuffer commandBuffer
)
5074 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5075 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5077 cmd_state
->conditional_render_enabled
= false;
5081 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5082 * command streamer for later execution.
5084 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5085 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5086 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5087 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5088 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5089 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5090 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5091 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5092 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5093 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5094 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5095 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5096 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5097 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5098 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5100 void genX(CmdSetEvent
)(
5101 VkCommandBuffer commandBuffer
,
5103 VkPipelineStageFlags stageMask
)
5105 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5106 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5108 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5109 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5110 pc
.StallAtPixelScoreboard
= true;
5111 pc
.CommandStreamerStallEnable
= true;
5114 pc
.DestinationAddressType
= DAT_PPGTT
,
5115 pc
.PostSyncOperation
= WriteImmediateData
,
5116 pc
.Address
= (struct anv_address
) {
5117 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5120 pc
.ImmediateData
= VK_EVENT_SET
;
5124 void genX(CmdResetEvent
)(
5125 VkCommandBuffer commandBuffer
,
5127 VkPipelineStageFlags stageMask
)
5129 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5130 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5132 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5133 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5134 pc
.StallAtPixelScoreboard
= true;
5135 pc
.CommandStreamerStallEnable
= true;
5138 pc
.DestinationAddressType
= DAT_PPGTT
;
5139 pc
.PostSyncOperation
= WriteImmediateData
;
5140 pc
.Address
= (struct anv_address
) {
5141 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5144 pc
.ImmediateData
= VK_EVENT_RESET
;
5148 void genX(CmdWaitEvents
)(
5149 VkCommandBuffer commandBuffer
,
5150 uint32_t eventCount
,
5151 const VkEvent
* pEvents
,
5152 VkPipelineStageFlags srcStageMask
,
5153 VkPipelineStageFlags destStageMask
,
5154 uint32_t memoryBarrierCount
,
5155 const VkMemoryBarrier
* pMemoryBarriers
,
5156 uint32_t bufferMemoryBarrierCount
,
5157 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5158 uint32_t imageMemoryBarrierCount
,
5159 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5162 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5164 for (uint32_t i
= 0; i
< eventCount
; i
++) {
5165 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
5167 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
5168 sem
.WaitMode
= PollingMode
,
5169 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
5170 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
5171 sem
.SemaphoreAddress
= (struct anv_address
) {
5172 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5178 anv_finishme("Implement events on gen7");
5181 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
5182 false, /* byRegion */
5183 memoryBarrierCount
, pMemoryBarriers
,
5184 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5185 imageMemoryBarrierCount
, pImageMemoryBarriers
);
5188 VkResult
genX(CmdSetPerformanceOverrideINTEL
)(
5189 VkCommandBuffer commandBuffer
,
5190 const VkPerformanceOverrideInfoINTEL
* pOverrideInfo
)
5192 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5194 switch (pOverrideInfo
->type
) {
5195 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL
: {
5199 anv_pack_struct(&dw
, GENX(CS_DEBUG_MODE2
),
5200 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5201 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5202 ._3DRenderingInstructionDisableMask
= true,
5203 .MediaInstructionDisableMask
= true);
5204 emit_lri(&cmd_buffer
->batch
, GENX(CS_DEBUG_MODE2_num
), dw
);
5206 anv_pack_struct(&dw
, GENX(INSTPM
),
5207 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5208 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5209 ._3DRenderingInstructionDisableMask
= true,
5210 .MediaInstructionDisableMask
= true);
5211 emit_lri(&cmd_buffer
->batch
, GENX(INSTPM_num
), dw
);
5216 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL
:
5217 if (pOverrideInfo
->enable
) {
5218 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
5219 cmd_buffer
->state
.pending_pipe_bits
|=
5220 ANV_PIPE_FLUSH_BITS
|
5221 ANV_PIPE_INVALIDATE_BITS
;
5222 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5227 unreachable("Invalid override");
5233 VkResult
genX(CmdSetPerformanceStreamMarkerINTEL
)(
5234 VkCommandBuffer commandBuffer
,
5235 const VkPerformanceStreamMarkerInfoINTEL
* pMarkerInfo
)
5237 /* TODO: Waiting on the register to write, might depend on generation. */