anv: Use 3DSTATE_CONSTANT_ALL when possible.
[mesa.git] / src / intel / vulkan / genX_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26
27 #include "anv_private.h"
28 #include "vk_format_info.h"
29 #include "vk_util.h"
30 #include "util/fast_idiv_by_const.h"
31
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
36
37 /* We reserve GPR 14 and 15 for conditional rendering */
38 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
39 #define __gen_get_batch_dwords anv_batch_emit_dwords
40 #define __gen_address_offset anv_address_add
41 #include "common/gen_mi_builder.h"
42
43 static void
44 emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
45 {
46 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
47 lri.RegisterOffset = reg;
48 lri.DataDWord = imm;
49 }
50 }
51
52 void
53 genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
54 {
55 struct anv_device *device = cmd_buffer->device;
56 uint32_t mocs = device->isl_dev.mocs.internal;
57
58 /* If we are emitting a new state base address we probably need to re-emit
59 * binding tables.
60 */
61 cmd_buffer->state.descriptors_dirty |= ~0;
62
63 /* Emit a render target cache flush.
64 *
65 * This isn't documented anywhere in the PRM. However, it seems to be
66 * necessary prior to changing the surface state base adress. Without
67 * this, we get GPU hangs when using multi-level command buffers which
68 * clear depth, reset state base address, and then go render stuff.
69 */
70 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
71 pc.DCFlushEnable = true;
72 pc.RenderTargetCacheFlushEnable = true;
73 pc.CommandStreamerStallEnable = true;
74 #if GEN_GEN >= 12
75 pc.TileCacheFlushEnable = true;
76 #endif
77 }
78
79 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
80 sba.GeneralStateBaseAddress = (struct anv_address) { NULL, 0 };
81 sba.GeneralStateMOCS = mocs;
82 sba.GeneralStateBaseAddressModifyEnable = true;
83
84 sba.StatelessDataPortAccessMOCS = mocs;
85
86 sba.SurfaceStateBaseAddress =
87 anv_cmd_buffer_surface_base_address(cmd_buffer);
88 sba.SurfaceStateMOCS = mocs;
89 sba.SurfaceStateBaseAddressModifyEnable = true;
90
91 sba.DynamicStateBaseAddress =
92 (struct anv_address) { device->dynamic_state_pool.block_pool.bo, 0 };
93 sba.DynamicStateMOCS = mocs;
94 sba.DynamicStateBaseAddressModifyEnable = true;
95
96 sba.IndirectObjectBaseAddress = (struct anv_address) { NULL, 0 };
97 sba.IndirectObjectMOCS = mocs;
98 sba.IndirectObjectBaseAddressModifyEnable = true;
99
100 sba.InstructionBaseAddress =
101 (struct anv_address) { device->instruction_state_pool.block_pool.bo, 0 };
102 sba.InstructionMOCS = mocs;
103 sba.InstructionBaseAddressModifyEnable = true;
104
105 # if (GEN_GEN >= 8)
106 /* Broadwell requires that we specify a buffer size for a bunch of
107 * these fields. However, since we will be growing the BO's live, we
108 * just set them all to the maximum.
109 */
110 sba.GeneralStateBufferSize = 0xfffff;
111 sba.GeneralStateBufferSizeModifyEnable = true;
112 sba.DynamicStateBufferSize = 0xfffff;
113 sba.DynamicStateBufferSizeModifyEnable = true;
114 sba.IndirectObjectBufferSize = 0xfffff;
115 sba.IndirectObjectBufferSizeModifyEnable = true;
116 sba.InstructionBufferSize = 0xfffff;
117 sba.InstructionBuffersizeModifyEnable = true;
118 # else
119 /* On gen7, we have upper bounds instead. According to the docs,
120 * setting an upper bound of zero means that no bounds checking is
121 * performed so, in theory, we should be able to leave them zero.
122 * However, border color is broken and the GPU bounds-checks anyway.
123 * To avoid this and other potential problems, we may as well set it
124 * for everything.
125 */
126 sba.GeneralStateAccessUpperBound =
127 (struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
128 sba.GeneralStateAccessUpperBoundModifyEnable = true;
129 sba.DynamicStateAccessUpperBound =
130 (struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
131 sba.DynamicStateAccessUpperBoundModifyEnable = true;
132 sba.InstructionAccessUpperBound =
133 (struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
134 sba.InstructionAccessUpperBoundModifyEnable = true;
135 # endif
136 # if (GEN_GEN >= 9)
137 if (cmd_buffer->device->instance->physicalDevice.use_softpin) {
138 sba.BindlessSurfaceStateBaseAddress = (struct anv_address) {
139 .bo = device->surface_state_pool.block_pool.bo,
140 .offset = 0,
141 };
142 sba.BindlessSurfaceStateSize = (1 << 20) - 1;
143 } else {
144 sba.BindlessSurfaceStateBaseAddress = ANV_NULL_ADDRESS;
145 sba.BindlessSurfaceStateSize = 0;
146 }
147 sba.BindlessSurfaceStateMOCS = mocs;
148 sba.BindlessSurfaceStateBaseAddressModifyEnable = true;
149 # endif
150 # if (GEN_GEN >= 10)
151 sba.BindlessSamplerStateBaseAddress = (struct anv_address) { NULL, 0 };
152 sba.BindlessSamplerStateMOCS = mocs;
153 sba.BindlessSamplerStateBaseAddressModifyEnable = true;
154 sba.BindlessSamplerStateBufferSize = 0;
155 # endif
156 }
157
158 /* After re-setting the surface state base address, we have to do some
159 * cache flusing so that the sampler engine will pick up the new
160 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
161 * Shared Function > 3D Sampler > State > State Caching (page 96):
162 *
163 * Coherency with system memory in the state cache, like the texture
164 * cache is handled partially by software. It is expected that the
165 * command stream or shader will issue Cache Flush operation or
166 * Cache_Flush sampler message to ensure that the L1 cache remains
167 * coherent with system memory.
168 *
169 * [...]
170 *
171 * Whenever the value of the Dynamic_State_Base_Addr,
172 * Surface_State_Base_Addr are altered, the L1 state cache must be
173 * invalidated to ensure the new surface or sampler state is fetched
174 * from system memory.
175 *
176 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
177 * which, according the PIPE_CONTROL instruction documentation in the
178 * Broadwell PRM:
179 *
180 * Setting this bit is independent of any other bit in this packet.
181 * This bit controls the invalidation of the L1 and L2 state caches
182 * at the top of the pipe i.e. at the parsing time.
183 *
184 * Unfortunately, experimentation seems to indicate that state cache
185 * invalidation through a PIPE_CONTROL does nothing whatsoever in
186 * regards to surface state and binding tables. In stead, it seems that
187 * invalidating the texture cache is what is actually needed.
188 *
189 * XXX: As far as we have been able to determine through
190 * experimentation, shows that flush the texture cache appears to be
191 * sufficient. The theory here is that all of the sampling/rendering
192 * units cache the binding table in the texture cache. However, we have
193 * yet to be able to actually confirm this.
194 */
195 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
196 pc.TextureCacheInvalidationEnable = true;
197 pc.ConstantCacheInvalidationEnable = true;
198 pc.StateCacheInvalidationEnable = true;
199 }
200 }
201
202 static void
203 add_surface_reloc(struct anv_cmd_buffer *cmd_buffer,
204 struct anv_state state, struct anv_address addr)
205 {
206 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
207
208 VkResult result =
209 anv_reloc_list_add(&cmd_buffer->surface_relocs, &cmd_buffer->pool->alloc,
210 state.offset + isl_dev->ss.addr_offset,
211 addr.bo, addr.offset, NULL);
212 if (result != VK_SUCCESS)
213 anv_batch_set_error(&cmd_buffer->batch, result);
214 }
215
216 static void
217 add_surface_state_relocs(struct anv_cmd_buffer *cmd_buffer,
218 struct anv_surface_state state)
219 {
220 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
221
222 assert(!anv_address_is_null(state.address));
223 add_surface_reloc(cmd_buffer, state.state, state.address);
224
225 if (!anv_address_is_null(state.aux_address)) {
226 VkResult result =
227 anv_reloc_list_add(&cmd_buffer->surface_relocs,
228 &cmd_buffer->pool->alloc,
229 state.state.offset + isl_dev->ss.aux_addr_offset,
230 state.aux_address.bo,
231 state.aux_address.offset,
232 NULL);
233 if (result != VK_SUCCESS)
234 anv_batch_set_error(&cmd_buffer->batch, result);
235 }
236
237 if (!anv_address_is_null(state.clear_address)) {
238 VkResult result =
239 anv_reloc_list_add(&cmd_buffer->surface_relocs,
240 &cmd_buffer->pool->alloc,
241 state.state.offset +
242 isl_dev->ss.clear_color_state_offset,
243 state.clear_address.bo,
244 state.clear_address.offset,
245 NULL);
246 if (result != VK_SUCCESS)
247 anv_batch_set_error(&cmd_buffer->batch, result);
248 }
249 }
250
251 static void
252 color_attachment_compute_aux_usage(struct anv_device * device,
253 struct anv_cmd_state * cmd_state,
254 uint32_t att, VkRect2D render_area,
255 union isl_color_value *fast_clear_color)
256 {
257 struct anv_attachment_state *att_state = &cmd_state->attachments[att];
258 struct anv_image_view *iview = cmd_state->attachments[att].image_view;
259
260 assert(iview->n_planes == 1);
261
262 if (iview->planes[0].isl.base_array_layer >=
263 anv_image_aux_layers(iview->image, VK_IMAGE_ASPECT_COLOR_BIT,
264 iview->planes[0].isl.base_level)) {
265 /* There is no aux buffer which corresponds to the level and layer(s)
266 * being accessed.
267 */
268 att_state->aux_usage = ISL_AUX_USAGE_NONE;
269 att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
270 att_state->fast_clear = false;
271 return;
272 }
273
274 att_state->aux_usage =
275 anv_layout_to_aux_usage(&device->info, iview->image,
276 VK_IMAGE_ASPECT_COLOR_BIT,
277 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL);
278
279 /* If we don't have aux, then we should have returned early in the layer
280 * check above. If we got here, we must have something.
281 */
282 assert(att_state->aux_usage != ISL_AUX_USAGE_NONE);
283
284 if (att_state->aux_usage == ISL_AUX_USAGE_CCS_E ||
285 att_state->aux_usage == ISL_AUX_USAGE_MCS) {
286 att_state->input_aux_usage = att_state->aux_usage;
287 } else {
288 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
289 *
290 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
291 * setting is only allowed if Surface Format supported for Fast
292 * Clear. In addition, if the surface is bound to the sampling
293 * engine, Surface Format must be supported for Render Target
294 * Compression for surfaces bound to the sampling engine."
295 *
296 * In other words, we can only sample from a fast-cleared image if it
297 * also supports color compression.
298 */
299 if (isl_format_supports_ccs_e(&device->info, iview->planes[0].isl.format) &&
300 isl_format_supports_ccs_d(&device->info, iview->planes[0].isl.format)) {
301 att_state->input_aux_usage = ISL_AUX_USAGE_CCS_D;
302
303 /* While fast-clear resolves and partial resolves are fairly cheap in the
304 * case where you render to most of the pixels, full resolves are not
305 * because they potentially involve reading and writing the entire
306 * framebuffer. If we can't texture with CCS_E, we should leave it off and
307 * limit ourselves to fast clears.
308 */
309 if (cmd_state->pass->attachments[att].first_subpass_layout ==
310 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL) {
311 anv_perf_warn(device->instance, iview->image,
312 "Not temporarily enabling CCS_E.");
313 }
314 } else {
315 att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
316 }
317 }
318
319 assert(iview->image->planes[0].aux_surface.isl.usage &
320 (ISL_SURF_USAGE_CCS_BIT | ISL_SURF_USAGE_MCS_BIT));
321
322 union isl_color_value clear_color = {};
323 anv_clear_color_from_att_state(&clear_color, att_state, iview);
324
325 att_state->clear_color_is_zero_one =
326 isl_color_value_is_zero_one(clear_color, iview->planes[0].isl.format);
327 att_state->clear_color_is_zero =
328 isl_color_value_is_zero(clear_color, iview->planes[0].isl.format);
329
330 if (att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
331 /* Start by getting the fast clear type. We use the first subpass
332 * layout here because we don't want to fast-clear if the first subpass
333 * to use the attachment can't handle fast-clears.
334 */
335 enum anv_fast_clear_type fast_clear_type =
336 anv_layout_to_fast_clear_type(&device->info, iview->image,
337 VK_IMAGE_ASPECT_COLOR_BIT,
338 cmd_state->pass->attachments[att].first_subpass_layout);
339 switch (fast_clear_type) {
340 case ANV_FAST_CLEAR_NONE:
341 att_state->fast_clear = false;
342 break;
343 case ANV_FAST_CLEAR_DEFAULT_VALUE:
344 att_state->fast_clear = att_state->clear_color_is_zero;
345 break;
346 case ANV_FAST_CLEAR_ANY:
347 att_state->fast_clear = true;
348 break;
349 }
350
351 /* Potentially, we could do partial fast-clears but doing so has crazy
352 * alignment restrictions. It's easier to just restrict to full size
353 * fast clears for now.
354 */
355 if (render_area.offset.x != 0 ||
356 render_area.offset.y != 0 ||
357 render_area.extent.width != iview->extent.width ||
358 render_area.extent.height != iview->extent.height)
359 att_state->fast_clear = false;
360
361 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
362 if (GEN_GEN <= 8 && !att_state->clear_color_is_zero_one)
363 att_state->fast_clear = false;
364
365 /* We only allow fast clears to the first slice of an image (level 0,
366 * layer 0) and only for the entire slice. This guarantees us that, at
367 * any given time, there is only one clear color on any given image at
368 * any given time. At the time of our testing (Jan 17, 2018), there
369 * were no known applications which would benefit from fast-clearing
370 * more than just the first slice.
371 */
372 if (att_state->fast_clear &&
373 (iview->planes[0].isl.base_level > 0 ||
374 iview->planes[0].isl.base_array_layer > 0)) {
375 anv_perf_warn(device->instance, iview->image,
376 "Rendering with multi-lod or multi-layer framebuffer "
377 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
378 "baseArrayLayer > 0. Not fast clearing.");
379 att_state->fast_clear = false;
380 } else if (att_state->fast_clear && cmd_state->framebuffer->layers > 1) {
381 anv_perf_warn(device->instance, iview->image,
382 "Rendering to a multi-layer framebuffer with "
383 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
384 }
385
386 if (att_state->fast_clear)
387 *fast_clear_color = clear_color;
388 } else {
389 att_state->fast_clear = false;
390 }
391 }
392
393 static void
394 depth_stencil_attachment_compute_aux_usage(struct anv_device *device,
395 struct anv_cmd_state *cmd_state,
396 uint32_t att, VkRect2D render_area)
397 {
398 struct anv_render_pass_attachment *pass_att =
399 &cmd_state->pass->attachments[att];
400 struct anv_attachment_state *att_state = &cmd_state->attachments[att];
401 struct anv_image_view *iview = cmd_state->attachments[att].image_view;
402
403 /* These will be initialized after the first subpass transition. */
404 att_state->aux_usage = ISL_AUX_USAGE_NONE;
405 att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
406
407 if (GEN_GEN == 7) {
408 /* We don't do any HiZ or depth fast-clears on gen7 yet */
409 att_state->fast_clear = false;
410 return;
411 }
412
413 if (!(att_state->pending_clear_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
414 /* If we're just clearing stencil, we can always HiZ clear */
415 att_state->fast_clear = true;
416 return;
417 }
418
419 /* Default to false for now */
420 att_state->fast_clear = false;
421
422 /* We must have depth in order to have HiZ */
423 if (!(iview->image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
424 return;
425
426 const enum isl_aux_usage first_subpass_aux_usage =
427 anv_layout_to_aux_usage(&device->info, iview->image,
428 VK_IMAGE_ASPECT_DEPTH_BIT,
429 pass_att->first_subpass_layout);
430 if (!blorp_can_hiz_clear_depth(&device->info,
431 &iview->image->planes[0].surface.isl,
432 first_subpass_aux_usage,
433 iview->planes[0].isl.base_level,
434 iview->planes[0].isl.base_array_layer,
435 render_area.offset.x,
436 render_area.offset.y,
437 render_area.offset.x +
438 render_area.extent.width,
439 render_area.offset.y +
440 render_area.extent.height))
441 return;
442
443 if (att_state->clear_value.depthStencil.depth != ANV_HZ_FC_VAL)
444 return;
445
446 if (GEN_GEN == 8 && anv_can_sample_with_hiz(&device->info, iview->image)) {
447 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
448 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
449 * only supports returning 0.0f. Gens prior to gen8 do not support this
450 * feature at all.
451 */
452 return;
453 }
454
455 /* If we got here, then we can fast clear */
456 att_state->fast_clear = true;
457 }
458
459 static bool
460 need_input_attachment_state(const struct anv_render_pass_attachment *att)
461 {
462 if (!(att->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT))
463 return false;
464
465 /* We only allocate input attachment states for color surfaces. Compression
466 * is not yet enabled for depth textures and stencil doesn't allow
467 * compression so we can just use the texture surface state from the view.
468 */
469 return vk_format_is_color(att->format);
470 }
471
472 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
473 * the initial layout is undefined, the HiZ buffer and depth buffer will
474 * represent the same data at the end of this operation.
475 */
476 static void
477 transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
478 const struct anv_image *image,
479 VkImageLayout initial_layout,
480 VkImageLayout final_layout)
481 {
482 const bool hiz_enabled = ISL_AUX_USAGE_HIZ ==
483 anv_layout_to_aux_usage(&cmd_buffer->device->info, image,
484 VK_IMAGE_ASPECT_DEPTH_BIT, initial_layout);
485 const bool enable_hiz = ISL_AUX_USAGE_HIZ ==
486 anv_layout_to_aux_usage(&cmd_buffer->device->info, image,
487 VK_IMAGE_ASPECT_DEPTH_BIT, final_layout);
488
489 enum isl_aux_op hiz_op;
490 if (hiz_enabled && !enable_hiz) {
491 hiz_op = ISL_AUX_OP_FULL_RESOLVE;
492 } else if (!hiz_enabled && enable_hiz) {
493 hiz_op = ISL_AUX_OP_AMBIGUATE;
494 } else {
495 assert(hiz_enabled == enable_hiz);
496 /* If the same buffer will be used, no resolves are necessary. */
497 hiz_op = ISL_AUX_OP_NONE;
498 }
499
500 if (hiz_op != ISL_AUX_OP_NONE)
501 anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
502 0, 0, 1, hiz_op);
503 }
504
505 static inline bool
506 vk_image_layout_stencil_write_optimal(VkImageLayout layout)
507 {
508 return layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
509 layout == VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL ||
510 layout == VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR;
511 }
512
513 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
514 * the initial layout is undefined, the HiZ buffer and depth buffer will
515 * represent the same data at the end of this operation.
516 */
517 static void
518 transition_stencil_buffer(struct anv_cmd_buffer *cmd_buffer,
519 const struct anv_image *image,
520 uint32_t base_level, uint32_t level_count,
521 uint32_t base_layer, uint32_t layer_count,
522 VkImageLayout initial_layout,
523 VkImageLayout final_layout)
524 {
525 #if GEN_GEN == 7
526 uint32_t plane = anv_image_aspect_to_plane(image->aspects,
527 VK_IMAGE_ASPECT_STENCIL_BIT);
528
529 /* On gen7, we have to store a texturable version of the stencil buffer in
530 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
531 * forth at strategic points. Stencil writes are only allowed in following
532 * layouts:
533 *
534 * - VK_IMAGE_LAYOUT_GENERAL
535 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
536 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
537 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
538 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
539 *
540 * For general, we have no nice opportunity to transition so we do the copy
541 * to the shadow unconditionally at the end of the subpass. For transfer
542 * destinations, we can update it as part of the transfer op. For the other
543 * layouts, we delay the copy until a transition into some other layout.
544 */
545 if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
546 vk_image_layout_stencil_write_optimal(initial_layout) &&
547 !vk_image_layout_stencil_write_optimal(final_layout)) {
548 anv_image_copy_to_shadow(cmd_buffer, image,
549 VK_IMAGE_ASPECT_STENCIL_BIT,
550 base_level, level_count,
551 base_layer, layer_count);
552 }
553 #endif /* GEN_GEN == 7 */
554 }
555
556 #define MI_PREDICATE_SRC0 0x2400
557 #define MI_PREDICATE_SRC1 0x2408
558 #define MI_PREDICATE_RESULT 0x2418
559
560 static void
561 set_image_compressed_bit(struct anv_cmd_buffer *cmd_buffer,
562 const struct anv_image *image,
563 VkImageAspectFlagBits aspect,
564 uint32_t level,
565 uint32_t base_layer, uint32_t layer_count,
566 bool compressed)
567 {
568 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
569
570 /* We only have compression tracking for CCS_E */
571 if (image->planes[plane].aux_usage != ISL_AUX_USAGE_CCS_E)
572 return;
573
574 for (uint32_t a = 0; a < layer_count; a++) {
575 uint32_t layer = base_layer + a;
576 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
577 sdi.Address = anv_image_get_compression_state_addr(cmd_buffer->device,
578 image, aspect,
579 level, layer);
580 sdi.ImmediateData = compressed ? UINT32_MAX : 0;
581 }
582 }
583 }
584
585 static void
586 set_image_fast_clear_state(struct anv_cmd_buffer *cmd_buffer,
587 const struct anv_image *image,
588 VkImageAspectFlagBits aspect,
589 enum anv_fast_clear_type fast_clear)
590 {
591 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
592 sdi.Address = anv_image_get_fast_clear_type_addr(cmd_buffer->device,
593 image, aspect);
594 sdi.ImmediateData = fast_clear;
595 }
596
597 /* Whenever we have fast-clear, we consider that slice to be compressed.
598 * This makes building predicates much easier.
599 */
600 if (fast_clear != ANV_FAST_CLEAR_NONE)
601 set_image_compressed_bit(cmd_buffer, image, aspect, 0, 0, 1, true);
602 }
603
604 /* This is only really practical on haswell and above because it requires
605 * MI math in order to get it correct.
606 */
607 #if GEN_GEN >= 8 || GEN_IS_HASWELL
608 static void
609 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
610 const struct anv_image *image,
611 VkImageAspectFlagBits aspect,
612 uint32_t level, uint32_t array_layer,
613 enum isl_aux_op resolve_op,
614 enum anv_fast_clear_type fast_clear_supported)
615 {
616 struct gen_mi_builder b;
617 gen_mi_builder_init(&b, &cmd_buffer->batch);
618
619 const struct gen_mi_value fast_clear_type =
620 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer->device,
621 image, aspect));
622
623 if (resolve_op == ISL_AUX_OP_FULL_RESOLVE) {
624 /* In this case, we're doing a full resolve which means we want the
625 * resolve to happen if any compression (including fast-clears) is
626 * present.
627 *
628 * In order to simplify the logic a bit, we make the assumption that,
629 * if the first slice has been fast-cleared, it is also marked as
630 * compressed. See also set_image_fast_clear_state.
631 */
632 const struct gen_mi_value compression_state =
633 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer->device,
634 image, aspect,
635 level, array_layer));
636 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
637 compression_state);
638 gen_mi_store(&b, compression_state, gen_mi_imm(0));
639
640 if (level == 0 && array_layer == 0) {
641 /* If the predicate is true, we want to write 0 to the fast clear type
642 * and, if it's false, leave it alone. We can do this by writing
643 *
644 * clear_type = clear_type & ~predicate;
645 */
646 struct gen_mi_value new_fast_clear_type =
647 gen_mi_iand(&b, fast_clear_type,
648 gen_mi_inot(&b, gen_mi_reg64(MI_PREDICATE_SRC0)));
649 gen_mi_store(&b, fast_clear_type, new_fast_clear_type);
650 }
651 } else if (level == 0 && array_layer == 0) {
652 /* In this case, we are doing a partial resolve to get rid of fast-clear
653 * colors. We don't care about the compression state but we do care
654 * about how much fast clear is allowed by the final layout.
655 */
656 assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
657 assert(fast_clear_supported < ANV_FAST_CLEAR_ANY);
658
659 /* We need to compute (fast_clear_supported < image->fast_clear) */
660 struct gen_mi_value pred =
661 gen_mi_ult(&b, gen_mi_imm(fast_clear_supported), fast_clear_type);
662 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
663 gen_mi_value_ref(&b, pred));
664
665 /* If the predicate is true, we want to write 0 to the fast clear type
666 * and, if it's false, leave it alone. We can do this by writing
667 *
668 * clear_type = clear_type & ~predicate;
669 */
670 struct gen_mi_value new_fast_clear_type =
671 gen_mi_iand(&b, fast_clear_type, gen_mi_inot(&b, pred));
672 gen_mi_store(&b, fast_clear_type, new_fast_clear_type);
673 } else {
674 /* In this case, we're trying to do a partial resolve on a slice that
675 * doesn't have clear color. There's nothing to do.
676 */
677 assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
678 return;
679 }
680
681 /* Set src1 to 0 and use a != condition */
682 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
683
684 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
685 mip.LoadOperation = LOAD_LOADINV;
686 mip.CombineOperation = COMBINE_SET;
687 mip.CompareOperation = COMPARE_SRCS_EQUAL;
688 }
689 }
690 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
691
692 #if GEN_GEN <= 8
693 static void
694 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
695 const struct anv_image *image,
696 VkImageAspectFlagBits aspect,
697 uint32_t level, uint32_t array_layer,
698 enum isl_aux_op resolve_op,
699 enum anv_fast_clear_type fast_clear_supported)
700 {
701 struct gen_mi_builder b;
702 gen_mi_builder_init(&b, &cmd_buffer->batch);
703
704 struct gen_mi_value fast_clear_type_mem =
705 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer->device,
706 image, aspect));
707
708 /* This only works for partial resolves and only when the clear color is
709 * all or nothing. On the upside, this emits less command streamer code
710 * and works on Ivybridge and Bay Trail.
711 */
712 assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
713 assert(fast_clear_supported != ANV_FAST_CLEAR_ANY);
714
715 /* We don't support fast clears on anything other than the first slice. */
716 if (level > 0 || array_layer > 0)
717 return;
718
719 /* On gen8, we don't have a concept of default clear colors because we
720 * can't sample from CCS surfaces. It's enough to just load the fast clear
721 * state into the predicate register.
722 */
723 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), fast_clear_type_mem);
724 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
725 gen_mi_store(&b, fast_clear_type_mem, gen_mi_imm(0));
726
727 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
728 mip.LoadOperation = LOAD_LOADINV;
729 mip.CombineOperation = COMBINE_SET;
730 mip.CompareOperation = COMPARE_SRCS_EQUAL;
731 }
732 }
733 #endif /* GEN_GEN <= 8 */
734
735 static void
736 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer *cmd_buffer,
737 const struct anv_image *image,
738 enum isl_format format,
739 VkImageAspectFlagBits aspect,
740 uint32_t level, uint32_t array_layer,
741 enum isl_aux_op resolve_op,
742 enum anv_fast_clear_type fast_clear_supported)
743 {
744 const uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
745
746 #if GEN_GEN >= 9
747 anv_cmd_compute_resolve_predicate(cmd_buffer, image,
748 aspect, level, array_layer,
749 resolve_op, fast_clear_supported);
750 #else /* GEN_GEN <= 8 */
751 anv_cmd_simple_resolve_predicate(cmd_buffer, image,
752 aspect, level, array_layer,
753 resolve_op, fast_clear_supported);
754 #endif
755
756 /* CCS_D only supports full resolves and BLORP will assert on us if we try
757 * to do a partial resolve on a CCS_D surface.
758 */
759 if (resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE &&
760 image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE)
761 resolve_op = ISL_AUX_OP_FULL_RESOLVE;
762
763 anv_image_ccs_op(cmd_buffer, image, format, aspect, level,
764 array_layer, 1, resolve_op, NULL, true);
765 }
766
767 static void
768 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer *cmd_buffer,
769 const struct anv_image *image,
770 enum isl_format format,
771 VkImageAspectFlagBits aspect,
772 uint32_t array_layer,
773 enum isl_aux_op resolve_op,
774 enum anv_fast_clear_type fast_clear_supported)
775 {
776 assert(aspect == VK_IMAGE_ASPECT_COLOR_BIT);
777 assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
778
779 #if GEN_GEN >= 8 || GEN_IS_HASWELL
780 anv_cmd_compute_resolve_predicate(cmd_buffer, image,
781 aspect, 0, array_layer,
782 resolve_op, fast_clear_supported);
783
784 anv_image_mcs_op(cmd_buffer, image, format, aspect,
785 array_layer, 1, resolve_op, NULL, true);
786 #else
787 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
788 #endif
789 }
790
791 void
792 genX(cmd_buffer_mark_image_written)(struct anv_cmd_buffer *cmd_buffer,
793 const struct anv_image *image,
794 VkImageAspectFlagBits aspect,
795 enum isl_aux_usage aux_usage,
796 uint32_t level,
797 uint32_t base_layer,
798 uint32_t layer_count)
799 {
800 /* The aspect must be exactly one of the image aspects. */
801 assert(util_bitcount(aspect) == 1 && (aspect & image->aspects));
802
803 /* The only compression types with more than just fast-clears are MCS,
804 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
805 * track the current fast-clear and compression state. This leaves us
806 * with just MCS and CCS_E.
807 */
808 if (aux_usage != ISL_AUX_USAGE_CCS_E &&
809 aux_usage != ISL_AUX_USAGE_MCS)
810 return;
811
812 set_image_compressed_bit(cmd_buffer, image, aspect,
813 level, base_layer, layer_count, true);
814 }
815
816 static void
817 init_fast_clear_color(struct anv_cmd_buffer *cmd_buffer,
818 const struct anv_image *image,
819 VkImageAspectFlagBits aspect)
820 {
821 assert(cmd_buffer && image);
822 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
823
824 set_image_fast_clear_state(cmd_buffer, image, aspect,
825 ANV_FAST_CLEAR_NONE);
826
827 /* Initialize the struct fields that are accessed for fast-clears so that
828 * the HW restrictions on the field values are satisfied.
829 */
830 struct anv_address addr =
831 anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
832
833 if (GEN_GEN >= 9) {
834 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
835 const unsigned num_dwords = GEN_GEN >= 10 ?
836 isl_dev->ss.clear_color_state_size / 4 :
837 isl_dev->ss.clear_value_size / 4;
838 for (unsigned i = 0; i < num_dwords; i++) {
839 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
840 sdi.Address = addr;
841 sdi.Address.offset += i * 4;
842 sdi.ImmediateData = 0;
843 }
844 }
845 } else {
846 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
847 sdi.Address = addr;
848 if (GEN_GEN >= 8 || GEN_IS_HASWELL) {
849 /* Pre-SKL, the dword containing the clear values also contains
850 * other fields, so we need to initialize those fields to match the
851 * values that would be in a color attachment.
852 */
853 sdi.ImmediateData = ISL_CHANNEL_SELECT_RED << 25 |
854 ISL_CHANNEL_SELECT_GREEN << 22 |
855 ISL_CHANNEL_SELECT_BLUE << 19 |
856 ISL_CHANNEL_SELECT_ALPHA << 16;
857 } else if (GEN_GEN == 7) {
858 /* On IVB, the dword containing the clear values also contains
859 * other fields that must be zero or can be zero.
860 */
861 sdi.ImmediateData = 0;
862 }
863 }
864 }
865 }
866
867 /* Copy the fast-clear value dword(s) between a surface state object and an
868 * image's fast clear state buffer.
869 */
870 static void
871 genX(copy_fast_clear_dwords)(struct anv_cmd_buffer *cmd_buffer,
872 struct anv_state surface_state,
873 const struct anv_image *image,
874 VkImageAspectFlagBits aspect,
875 bool copy_from_surface_state)
876 {
877 assert(cmd_buffer && image);
878 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
879
880 struct anv_address ss_clear_addr = {
881 .bo = cmd_buffer->device->surface_state_pool.block_pool.bo,
882 .offset = surface_state.offset +
883 cmd_buffer->device->isl_dev.ss.clear_value_offset,
884 };
885 const struct anv_address entry_addr =
886 anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
887 unsigned copy_size = cmd_buffer->device->isl_dev.ss.clear_value_size;
888
889 #if GEN_GEN == 7
890 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
891 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
892 * in-flight when they are issued even if the memory touched is not
893 * currently active for rendering. The weird bit is that it is not the
894 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
895 * rendering hangs such that the next stalling command after the
896 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
897 *
898 * It is unclear exactly why this hang occurs. Both MI commands come with
899 * warnings about the 3D pipeline but that doesn't seem to fully explain
900 * it. My (Jason's) best theory is that it has something to do with the
901 * fact that we're using a GPU state register as our temporary and that
902 * something with reading/writing it is causing problems.
903 *
904 * In order to work around this issue, we emit a PIPE_CONTROL with the
905 * command streamer stall bit set.
906 */
907 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
908 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
909 #endif
910
911 struct gen_mi_builder b;
912 gen_mi_builder_init(&b, &cmd_buffer->batch);
913
914 if (copy_from_surface_state) {
915 gen_mi_memcpy(&b, entry_addr, ss_clear_addr, copy_size);
916 } else {
917 gen_mi_memcpy(&b, ss_clear_addr, entry_addr, copy_size);
918
919 /* Updating a surface state object may require that the state cache be
920 * invalidated. From the SKL PRM, Shared Functions -> State -> State
921 * Caching:
922 *
923 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
924 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
925 * modified [...], the L1 state cache must be invalidated to ensure
926 * the new surface or sampler state is fetched from system memory.
927 *
928 * In testing, SKL doesn't actually seem to need this, but HSW does.
929 */
930 cmd_buffer->state.pending_pipe_bits |=
931 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
932 }
933 }
934
935 /**
936 * @brief Transitions a color buffer from one layout to another.
937 *
938 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
939 * more information.
940 *
941 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
942 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
943 * this represents the maximum layers to transition at each
944 * specified miplevel.
945 */
946 static void
947 transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
948 const struct anv_image *image,
949 VkImageAspectFlagBits aspect,
950 const uint32_t base_level, uint32_t level_count,
951 uint32_t base_layer, uint32_t layer_count,
952 VkImageLayout initial_layout,
953 VkImageLayout final_layout)
954 {
955 const struct gen_device_info *devinfo = &cmd_buffer->device->info;
956 /* Validate the inputs. */
957 assert(cmd_buffer);
958 assert(image && image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
959 /* These values aren't supported for simplicity's sake. */
960 assert(level_count != VK_REMAINING_MIP_LEVELS &&
961 layer_count != VK_REMAINING_ARRAY_LAYERS);
962 /* Ensure the subresource range is valid. */
963 UNUSED uint64_t last_level_num = base_level + level_count;
964 const uint32_t max_depth = anv_minify(image->extent.depth, base_level);
965 UNUSED const uint32_t image_layers = MAX2(image->array_size, max_depth);
966 assert((uint64_t)base_layer + layer_count <= image_layers);
967 assert(last_level_num <= image->levels);
968 /* The spec disallows these final layouts. */
969 assert(final_layout != VK_IMAGE_LAYOUT_UNDEFINED &&
970 final_layout != VK_IMAGE_LAYOUT_PREINITIALIZED);
971
972 /* No work is necessary if the layout stays the same or if this subresource
973 * range lacks auxiliary data.
974 */
975 if (initial_layout == final_layout)
976 return;
977
978 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
979
980 if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
981 final_layout == VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL) {
982 /* This surface is a linear compressed image with a tiled shadow surface
983 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
984 * we need to ensure the shadow copy is up-to-date.
985 */
986 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
987 assert(image->planes[plane].surface.isl.tiling == ISL_TILING_LINEAR);
988 assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR);
989 assert(isl_format_is_compressed(image->planes[plane].surface.isl.format));
990 assert(plane == 0);
991 anv_image_copy_to_shadow(cmd_buffer, image,
992 VK_IMAGE_ASPECT_COLOR_BIT,
993 base_level, level_count,
994 base_layer, layer_count);
995 }
996
997 if (base_layer >= anv_image_aux_layers(image, aspect, base_level))
998 return;
999
1000 assert(image->tiling == VK_IMAGE_TILING_OPTIMAL);
1001
1002 if (initial_layout == VK_IMAGE_LAYOUT_UNDEFINED ||
1003 initial_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
1004 /* A subresource in the undefined layout may have been aliased and
1005 * populated with any arrangement of bits. Therefore, we must initialize
1006 * the related aux buffer and clear buffer entry with desirable values.
1007 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1008 * images with VK_IMAGE_TILING_OPTIMAL.
1009 *
1010 * Initialize the relevant clear buffer entries.
1011 */
1012 if (base_level == 0 && base_layer == 0)
1013 init_fast_clear_color(cmd_buffer, image, aspect);
1014
1015 /* Initialize the aux buffers to enable correct rendering. In order to
1016 * ensure that things such as storage images work correctly, aux buffers
1017 * need to be initialized to valid data.
1018 *
1019 * Having an aux buffer with invalid data is a problem for two reasons:
1020 *
1021 * 1) Having an invalid value in the buffer can confuse the hardware.
1022 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1023 * invalid and leads to the hardware doing strange things. It
1024 * doesn't hang as far as we can tell but rendering corruption can
1025 * occur.
1026 *
1027 * 2) If this transition is into the GENERAL layout and we then use the
1028 * image as a storage image, then we must have the aux buffer in the
1029 * pass-through state so that, if we then go to texture from the
1030 * image, we get the results of our storage image writes and not the
1031 * fast clear color or other random data.
1032 *
1033 * For CCS both of the problems above are real demonstrable issues. In
1034 * that case, the only thing we can do is to perform an ambiguate to
1035 * transition the aux surface into the pass-through state.
1036 *
1037 * For MCS, (2) is never an issue because we don't support multisampled
1038 * storage images. In theory, issue (1) is a problem with MCS but we've
1039 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1040 * theory, be interpreted as something but we don't know that all bit
1041 * patterns are actually valid. For 2x and 8x, you could easily end up
1042 * with the MCS referring to an invalid plane because not all bits of
1043 * the MCS value are actually used. Even though we've never seen issues
1044 * in the wild, it's best to play it safe and initialize the MCS. We
1045 * can use a fast-clear for MCS because we only ever touch from render
1046 * and texture (no image load store).
1047 */
1048 if (image->samples == 1) {
1049 for (uint32_t l = 0; l < level_count; l++) {
1050 const uint32_t level = base_level + l;
1051
1052 uint32_t aux_layers = anv_image_aux_layers(image, aspect, level);
1053 if (base_layer >= aux_layers)
1054 break; /* We will only get fewer layers as level increases */
1055 uint32_t level_layer_count =
1056 MIN2(layer_count, aux_layers - base_layer);
1057
1058 anv_image_ccs_op(cmd_buffer, image,
1059 image->planes[plane].surface.isl.format,
1060 aspect, level, base_layer, level_layer_count,
1061 ISL_AUX_OP_AMBIGUATE, NULL, false);
1062
1063 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) {
1064 set_image_compressed_bit(cmd_buffer, image, aspect,
1065 level, base_layer, level_layer_count,
1066 false);
1067 }
1068 }
1069 } else {
1070 if (image->samples == 4 || image->samples == 16) {
1071 anv_perf_warn(cmd_buffer->device->instance, image,
1072 "Doing a potentially unnecessary fast-clear to "
1073 "define an MCS buffer.");
1074 }
1075
1076 assert(base_level == 0 && level_count == 1);
1077 anv_image_mcs_op(cmd_buffer, image,
1078 image->planes[plane].surface.isl.format,
1079 aspect, base_layer, layer_count,
1080 ISL_AUX_OP_FAST_CLEAR, NULL, false);
1081 }
1082 return;
1083 }
1084
1085 const enum isl_aux_usage initial_aux_usage =
1086 anv_layout_to_aux_usage(devinfo, image, aspect, initial_layout);
1087 const enum isl_aux_usage final_aux_usage =
1088 anv_layout_to_aux_usage(devinfo, image, aspect, final_layout);
1089
1090 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1091 * We can handle transitions between CCS_D/E to and from NONE. What we
1092 * don't yet handle is switching between CCS_E and CCS_D within a given
1093 * image. Doing so in a performant way requires more detailed aux state
1094 * tracking such as what is done in i965. For now, just assume that we
1095 * only have one type of compression.
1096 */
1097 assert(initial_aux_usage == ISL_AUX_USAGE_NONE ||
1098 final_aux_usage == ISL_AUX_USAGE_NONE ||
1099 initial_aux_usage == final_aux_usage);
1100
1101 /* If initial aux usage is NONE, there is nothing to resolve */
1102 if (initial_aux_usage == ISL_AUX_USAGE_NONE)
1103 return;
1104
1105 enum isl_aux_op resolve_op = ISL_AUX_OP_NONE;
1106
1107 /* If the initial layout supports more fast clear than the final layout
1108 * then we need at least a partial resolve.
1109 */
1110 const enum anv_fast_clear_type initial_fast_clear =
1111 anv_layout_to_fast_clear_type(devinfo, image, aspect, initial_layout);
1112 const enum anv_fast_clear_type final_fast_clear =
1113 anv_layout_to_fast_clear_type(devinfo, image, aspect, final_layout);
1114 if (final_fast_clear < initial_fast_clear)
1115 resolve_op = ISL_AUX_OP_PARTIAL_RESOLVE;
1116
1117 if (initial_aux_usage == ISL_AUX_USAGE_CCS_E &&
1118 final_aux_usage != ISL_AUX_USAGE_CCS_E)
1119 resolve_op = ISL_AUX_OP_FULL_RESOLVE;
1120
1121 if (resolve_op == ISL_AUX_OP_NONE)
1122 return;
1123
1124 /* Perform a resolve to synchronize data between the main and aux buffer.
1125 * Before we begin, we must satisfy the cache flushing requirement specified
1126 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1127 *
1128 * Any transition from any value in {Clear, Render, Resolve} to a
1129 * different value in {Clear, Render, Resolve} requires end of pipe
1130 * synchronization.
1131 *
1132 * We perform a flush of the write cache before and after the clear and
1133 * resolve operations to meet this requirement.
1134 *
1135 * Unlike other drawing, fast clear operations are not properly
1136 * synchronized. The first PIPE_CONTROL here likely ensures that the
1137 * contents of the previous render or clear hit the render target before we
1138 * resolve and the second likely ensures that the resolve is complete before
1139 * we do any more rendering or clearing.
1140 */
1141 cmd_buffer->state.pending_pipe_bits |=
1142 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1143
1144 for (uint32_t l = 0; l < level_count; l++) {
1145 uint32_t level = base_level + l;
1146
1147 uint32_t aux_layers = anv_image_aux_layers(image, aspect, level);
1148 if (base_layer >= aux_layers)
1149 break; /* We will only get fewer layers as level increases */
1150 uint32_t level_layer_count =
1151 MIN2(layer_count, aux_layers - base_layer);
1152
1153 for (uint32_t a = 0; a < level_layer_count; a++) {
1154 uint32_t array_layer = base_layer + a;
1155 if (image->samples == 1) {
1156 anv_cmd_predicated_ccs_resolve(cmd_buffer, image,
1157 image->planes[plane].surface.isl.format,
1158 aspect, level, array_layer, resolve_op,
1159 final_fast_clear);
1160 } else {
1161 /* We only support fast-clear on the first layer so partial
1162 * resolves should not be used on other layers as they will use
1163 * the clear color stored in memory that is only valid for layer0.
1164 */
1165 if (resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE &&
1166 array_layer != 0)
1167 continue;
1168
1169 anv_cmd_predicated_mcs_resolve(cmd_buffer, image,
1170 image->planes[plane].surface.isl.format,
1171 aspect, array_layer, resolve_op,
1172 final_fast_clear);
1173 }
1174 }
1175 }
1176
1177 cmd_buffer->state.pending_pipe_bits |=
1178 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1179 }
1180
1181 /**
1182 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1183 */
1184 static VkResult
1185 genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer *cmd_buffer,
1186 struct anv_render_pass *pass,
1187 const VkRenderPassBeginInfo *begin)
1188 {
1189 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
1190 struct anv_cmd_state *state = &cmd_buffer->state;
1191 struct anv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1192
1193 vk_free(&cmd_buffer->pool->alloc, state->attachments);
1194
1195 if (pass->attachment_count > 0) {
1196 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1197 pass->attachment_count *
1198 sizeof(state->attachments[0]),
1199 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1200 if (state->attachments == NULL) {
1201 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1202 return anv_batch_set_error(&cmd_buffer->batch,
1203 VK_ERROR_OUT_OF_HOST_MEMORY);
1204 }
1205 } else {
1206 state->attachments = NULL;
1207 }
1208
1209 /* Reserve one for the NULL state. */
1210 unsigned num_states = 1;
1211 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1212 if (vk_format_is_color(pass->attachments[i].format))
1213 num_states++;
1214
1215 if (need_input_attachment_state(&pass->attachments[i]))
1216 num_states++;
1217 }
1218
1219 const uint32_t ss_stride = align_u32(isl_dev->ss.size, isl_dev->ss.align);
1220 state->render_pass_states =
1221 anv_state_stream_alloc(&cmd_buffer->surface_state_stream,
1222 num_states * ss_stride, isl_dev->ss.align);
1223
1224 struct anv_state next_state = state->render_pass_states;
1225 next_state.alloc_size = isl_dev->ss.size;
1226
1227 state->null_surface_state = next_state;
1228 next_state.offset += ss_stride;
1229 next_state.map += ss_stride;
1230
1231 const VkRenderPassAttachmentBeginInfoKHR *begin_attachment =
1232 vk_find_struct_const(begin, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR);
1233
1234 if (begin && !begin_attachment)
1235 assert(pass->attachment_count == framebuffer->attachment_count);
1236
1237 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1238 if (vk_format_is_color(pass->attachments[i].format)) {
1239 state->attachments[i].color.state = next_state;
1240 next_state.offset += ss_stride;
1241 next_state.map += ss_stride;
1242 }
1243
1244 if (need_input_attachment_state(&pass->attachments[i])) {
1245 state->attachments[i].input.state = next_state;
1246 next_state.offset += ss_stride;
1247 next_state.map += ss_stride;
1248 }
1249
1250 if (begin_attachment && begin_attachment->attachmentCount != 0) {
1251 assert(begin_attachment->attachmentCount == pass->attachment_count);
1252 ANV_FROM_HANDLE(anv_image_view, iview, begin_attachment->pAttachments[i]);
1253 cmd_buffer->state.attachments[i].image_view = iview;
1254 } else if (framebuffer && i < framebuffer->attachment_count) {
1255 cmd_buffer->state.attachments[i].image_view = framebuffer->attachments[i];
1256 }
1257 }
1258 assert(next_state.offset == state->render_pass_states.offset +
1259 state->render_pass_states.alloc_size);
1260
1261 if (begin) {
1262 isl_null_fill_state(isl_dev, state->null_surface_state.map,
1263 isl_extent3d(framebuffer->width,
1264 framebuffer->height,
1265 framebuffer->layers));
1266
1267 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1268 struct anv_render_pass_attachment *att = &pass->attachments[i];
1269 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1270 VkImageAspectFlags clear_aspects = 0;
1271 VkImageAspectFlags load_aspects = 0;
1272
1273 if (att_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
1274 /* color attachment */
1275 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1276 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1277 } else if (att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
1278 load_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1279 }
1280 } else {
1281 /* depthstencil attachment */
1282 if (att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
1283 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1284 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1285 } else if (att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
1286 load_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1287 }
1288 }
1289 if (att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1290 if (att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1291 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1292 } else if (att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
1293 load_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1294 }
1295 }
1296 }
1297
1298 state->attachments[i].current_layout = att->initial_layout;
1299 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
1300 state->attachments[i].pending_clear_aspects = clear_aspects;
1301 state->attachments[i].pending_load_aspects = load_aspects;
1302 if (clear_aspects)
1303 state->attachments[i].clear_value = begin->pClearValues[i];
1304
1305 struct anv_image_view *iview = cmd_buffer->state.attachments[i].image_view;
1306 anv_assert(iview->vk_format == att->format);
1307
1308 const uint32_t num_layers = iview->planes[0].isl.array_len;
1309 state->attachments[i].pending_clear_views = (1 << num_layers) - 1;
1310
1311 union isl_color_value clear_color = { .u32 = { 0, } };
1312 if (att_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
1313 anv_assert(iview->n_planes == 1);
1314 assert(att_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1315 color_attachment_compute_aux_usage(cmd_buffer->device,
1316 state, i, begin->renderArea,
1317 &clear_color);
1318
1319 anv_image_fill_surface_state(cmd_buffer->device,
1320 iview->image,
1321 VK_IMAGE_ASPECT_COLOR_BIT,
1322 &iview->planes[0].isl,
1323 ISL_SURF_USAGE_RENDER_TARGET_BIT,
1324 state->attachments[i].aux_usage,
1325 &clear_color,
1326 0,
1327 &state->attachments[i].color,
1328 NULL);
1329
1330 add_surface_state_relocs(cmd_buffer, state->attachments[i].color);
1331 } else {
1332 depth_stencil_attachment_compute_aux_usage(cmd_buffer->device,
1333 state, i,
1334 begin->renderArea);
1335 }
1336
1337 if (need_input_attachment_state(&pass->attachments[i])) {
1338 anv_image_fill_surface_state(cmd_buffer->device,
1339 iview->image,
1340 VK_IMAGE_ASPECT_COLOR_BIT,
1341 &iview->planes[0].isl,
1342 ISL_SURF_USAGE_TEXTURE_BIT,
1343 state->attachments[i].input_aux_usage,
1344 &clear_color,
1345 0,
1346 &state->attachments[i].input,
1347 NULL);
1348
1349 add_surface_state_relocs(cmd_buffer, state->attachments[i].input);
1350 }
1351 }
1352 }
1353
1354 return VK_SUCCESS;
1355 }
1356
1357 VkResult
1358 genX(BeginCommandBuffer)(
1359 VkCommandBuffer commandBuffer,
1360 const VkCommandBufferBeginInfo* pBeginInfo)
1361 {
1362 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1363
1364 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1365 * command buffer's state. Otherwise, we must *reset* its state. In both
1366 * cases we reset it.
1367 *
1368 * From the Vulkan 1.0 spec:
1369 *
1370 * If a command buffer is in the executable state and the command buffer
1371 * was allocated from a command pool with the
1372 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1373 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1374 * as if vkResetCommandBuffer had been called with
1375 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1376 * the command buffer in the recording state.
1377 */
1378 anv_cmd_buffer_reset(cmd_buffer);
1379
1380 cmd_buffer->usage_flags = pBeginInfo->flags;
1381
1382 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY ||
1383 !(cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT));
1384
1385 genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
1386
1387 /* We sometimes store vertex data in the dynamic state buffer for blorp
1388 * operations and our dynamic state stream may re-use data from previous
1389 * command buffers. In order to prevent stale cache data, we flush the VF
1390 * cache. We could do this on every blorp call but that's not really
1391 * needed as all of the data will get written by the CPU prior to the GPU
1392 * executing anything. The chances are fairly high that they will use
1393 * blorp at least once per primary command buffer so it shouldn't be
1394 * wasted.
1395 */
1396 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY)
1397 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1398
1399 /* We send an "Indirect State Pointers Disable" packet at
1400 * EndCommandBuffer, so all push contant packets are ignored during a
1401 * context restore. Documentation says after that command, we need to
1402 * emit push constants again before any rendering operation. So we
1403 * flag them dirty here to make sure they get emitted.
1404 */
1405 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_ALL_GRAPHICS;
1406
1407 VkResult result = VK_SUCCESS;
1408 if (cmd_buffer->usage_flags &
1409 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1410 assert(pBeginInfo->pInheritanceInfo);
1411 cmd_buffer->state.pass =
1412 anv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1413 cmd_buffer->state.subpass =
1414 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1415
1416 /* This is optional in the inheritance info. */
1417 cmd_buffer->state.framebuffer =
1418 anv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1419
1420 result = genX(cmd_buffer_setup_attachments)(cmd_buffer,
1421 cmd_buffer->state.pass, NULL);
1422
1423 /* Record that HiZ is enabled if we can. */
1424 if (cmd_buffer->state.framebuffer) {
1425 const struct anv_image_view * const iview =
1426 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
1427
1428 if (iview) {
1429 VkImageLayout layout =
1430 cmd_buffer->state.subpass->depth_stencil_attachment->layout;
1431
1432 enum isl_aux_usage aux_usage =
1433 anv_layout_to_aux_usage(&cmd_buffer->device->info, iview->image,
1434 VK_IMAGE_ASPECT_DEPTH_BIT, layout);
1435
1436 cmd_buffer->state.hiz_enabled = aux_usage == ISL_AUX_USAGE_HIZ;
1437 }
1438 }
1439
1440 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
1441 }
1442
1443 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1444 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) {
1445 const VkCommandBufferInheritanceConditionalRenderingInfoEXT *conditional_rendering_info =
1446 vk_find_struct_const(pBeginInfo->pInheritanceInfo->pNext, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT);
1447
1448 /* If secondary buffer supports conditional rendering
1449 * we should emit commands as if conditional rendering is enabled.
1450 */
1451 cmd_buffer->state.conditional_render_enabled =
1452 conditional_rendering_info && conditional_rendering_info->conditionalRenderingEnable;
1453 }
1454 #endif
1455
1456 return result;
1457 }
1458
1459 /* From the PRM, Volume 2a:
1460 *
1461 * "Indirect State Pointers Disable
1462 *
1463 * At the completion of the post-sync operation associated with this pipe
1464 * control packet, the indirect state pointers in the hardware are
1465 * considered invalid; the indirect pointers are not saved in the context.
1466 * If any new indirect state commands are executed in the command stream
1467 * while the pipe control is pending, the new indirect state commands are
1468 * preserved.
1469 *
1470 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1471 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1472 * commands are only considered as Indirect State Pointers. Once ISP is
1473 * issued in a context, SW must initialize by programming push constant
1474 * commands for all the shaders (at least to zero length) before attempting
1475 * any rendering operation for the same context."
1476 *
1477 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1478 * even though they point to a BO that has been already unreferenced at
1479 * the end of the previous batch buffer. This has been fine so far since
1480 * we are protected by these scratch page (every address not covered by
1481 * a BO should be pointing to the scratch page). But on CNL, it is
1482 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1483 * instruction.
1484 *
1485 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1486 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1487 * context restore, so the mentioned hang doesn't happen. However,
1488 * software must program push constant commands for all stages prior to
1489 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1490 *
1491 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1492 * constants have been loaded into the EUs prior to disable the push constants
1493 * so that it doesn't hang a previous 3DPRIMITIVE.
1494 */
1495 static void
1496 emit_isp_disable(struct anv_cmd_buffer *cmd_buffer)
1497 {
1498 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1499 pc.StallAtPixelScoreboard = true;
1500 pc.CommandStreamerStallEnable = true;
1501 }
1502 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1503 pc.IndirectStatePointersDisable = true;
1504 pc.CommandStreamerStallEnable = true;
1505 }
1506 }
1507
1508 VkResult
1509 genX(EndCommandBuffer)(
1510 VkCommandBuffer commandBuffer)
1511 {
1512 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1513
1514 if (anv_batch_has_error(&cmd_buffer->batch))
1515 return cmd_buffer->batch.status;
1516
1517 /* We want every command buffer to start with the PMA fix in a known state,
1518 * so we disable it at the end of the command buffer.
1519 */
1520 genX(cmd_buffer_enable_pma_fix)(cmd_buffer, false);
1521
1522 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
1523
1524 emit_isp_disable(cmd_buffer);
1525
1526 anv_cmd_buffer_end_batch_buffer(cmd_buffer);
1527
1528 return VK_SUCCESS;
1529 }
1530
1531 void
1532 genX(CmdExecuteCommands)(
1533 VkCommandBuffer commandBuffer,
1534 uint32_t commandBufferCount,
1535 const VkCommandBuffer* pCmdBuffers)
1536 {
1537 ANV_FROM_HANDLE(anv_cmd_buffer, primary, commandBuffer);
1538
1539 assert(primary->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1540
1541 if (anv_batch_has_error(&primary->batch))
1542 return;
1543
1544 /* The secondary command buffers will assume that the PMA fix is disabled
1545 * when they begin executing. Make sure this is true.
1546 */
1547 genX(cmd_buffer_enable_pma_fix)(primary, false);
1548
1549 /* The secondary command buffer doesn't know which textures etc. have been
1550 * flushed prior to their execution. Apply those flushes now.
1551 */
1552 genX(cmd_buffer_apply_pipe_flushes)(primary);
1553
1554 for (uint32_t i = 0; i < commandBufferCount; i++) {
1555 ANV_FROM_HANDLE(anv_cmd_buffer, secondary, pCmdBuffers[i]);
1556
1557 assert(secondary->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY);
1558 assert(!anv_batch_has_error(&secondary->batch));
1559
1560 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1561 if (secondary->state.conditional_render_enabled) {
1562 if (!primary->state.conditional_render_enabled) {
1563 /* Secondary buffer is constructed as if it will be executed
1564 * with conditional rendering, we should satisfy this dependency
1565 * regardless of conditional rendering being enabled in primary.
1566 */
1567 struct gen_mi_builder b;
1568 gen_mi_builder_init(&b, &primary->batch);
1569 gen_mi_store(&b, gen_mi_reg64(ANV_PREDICATE_RESULT_REG),
1570 gen_mi_imm(UINT64_MAX));
1571 }
1572 }
1573 #endif
1574
1575 if (secondary->usage_flags &
1576 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1577 /* If we're continuing a render pass from the primary, we need to
1578 * copy the surface states for the current subpass into the storage
1579 * we allocated for them in BeginCommandBuffer.
1580 */
1581 struct anv_bo *ss_bo =
1582 primary->device->surface_state_pool.block_pool.bo;
1583 struct anv_state src_state = primary->state.render_pass_states;
1584 struct anv_state dst_state = secondary->state.render_pass_states;
1585 assert(src_state.alloc_size == dst_state.alloc_size);
1586
1587 genX(cmd_buffer_so_memcpy)(primary,
1588 (struct anv_address) {
1589 .bo = ss_bo,
1590 .offset = dst_state.offset,
1591 },
1592 (struct anv_address) {
1593 .bo = ss_bo,
1594 .offset = src_state.offset,
1595 },
1596 src_state.alloc_size);
1597 }
1598
1599 anv_cmd_buffer_add_secondary(primary, secondary);
1600 }
1601
1602 /* The secondary may have selected a different pipeline (3D or compute) and
1603 * may have changed the current L3$ configuration. Reset our tracking
1604 * variables to invalid values to ensure that we re-emit these in the case
1605 * where we do any draws or compute dispatches from the primary after the
1606 * secondary has returned.
1607 */
1608 primary->state.current_pipeline = UINT32_MAX;
1609 primary->state.current_l3_config = NULL;
1610 primary->state.current_hash_scale = 0;
1611
1612 /* Each of the secondary command buffers will use its own state base
1613 * address. We need to re-emit state base address for the primary after
1614 * all of the secondaries are done.
1615 *
1616 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1617 * address calls?
1618 */
1619 genX(cmd_buffer_emit_state_base_address)(primary);
1620 }
1621
1622 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1623 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1624 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1625
1626 /**
1627 * Program the hardware to use the specified L3 configuration.
1628 */
1629 void
1630 genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
1631 const struct gen_l3_config *cfg)
1632 {
1633 assert(cfg);
1634 if (cfg == cmd_buffer->state.current_l3_config)
1635 return;
1636
1637 if (unlikely(INTEL_DEBUG & DEBUG_L3)) {
1638 intel_logd("L3 config transition: ");
1639 gen_dump_l3_config(cfg, stderr);
1640 }
1641
1642 UNUSED const bool has_slm = cfg->n[GEN_L3P_SLM];
1643
1644 /* According to the hardware docs, the L3 partitioning can only be changed
1645 * while the pipeline is completely drained and the caches are flushed,
1646 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1647 */
1648 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1649 pc.DCFlushEnable = true;
1650 pc.PostSyncOperation = NoWrite;
1651 pc.CommandStreamerStallEnable = true;
1652 }
1653
1654 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1655 * invalidation of the relevant caches. Note that because RO invalidation
1656 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1657 * command is processed by the CS) we cannot combine it with the previous
1658 * stalling flush as the hardware documentation suggests, because that
1659 * would cause the CS to stall on previous rendering *after* RO
1660 * invalidation and wouldn't prevent the RO caches from being polluted by
1661 * concurrent rendering before the stall completes. This intentionally
1662 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1663 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1664 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1665 * already guarantee that there is no concurrent GPGPU kernel execution
1666 * (see SKL HSD 2132585).
1667 */
1668 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1669 pc.TextureCacheInvalidationEnable = true;
1670 pc.ConstantCacheInvalidationEnable = true;
1671 pc.InstructionCacheInvalidateEnable = true;
1672 pc.StateCacheInvalidationEnable = true;
1673 pc.PostSyncOperation = NoWrite;
1674 }
1675
1676 /* Now send a third stalling flush to make sure that invalidation is
1677 * complete when the L3 configuration registers are modified.
1678 */
1679 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1680 pc.DCFlushEnable = true;
1681 pc.PostSyncOperation = NoWrite;
1682 pc.CommandStreamerStallEnable = true;
1683 }
1684
1685 #if GEN_GEN >= 8
1686
1687 assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
1688
1689 #if GEN_GEN >= 12
1690 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1691 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1692 #else
1693 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1694 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1695 #endif
1696
1697 uint32_t l3cr;
1698 anv_pack_struct(&l3cr, L3_ALLOCATION_REG,
1699 #if GEN_GEN < 12
1700 .SLMEnable = has_slm,
1701 #endif
1702 #if GEN_GEN == 11
1703 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1704 * in L3CNTLREG register. The default setting of the bit is not the
1705 * desirable behavior.
1706 */
1707 .ErrorDetectionBehaviorControl = true,
1708 .UseFullWays = true,
1709 #endif
1710 .URBAllocation = cfg->n[GEN_L3P_URB],
1711 .ROAllocation = cfg->n[GEN_L3P_RO],
1712 .DCAllocation = cfg->n[GEN_L3P_DC],
1713 .AllAllocation = cfg->n[GEN_L3P_ALL]);
1714
1715 /* Set up the L3 partitioning. */
1716 emit_lri(&cmd_buffer->batch, L3_ALLOCATION_REG_num, l3cr);
1717
1718 #else
1719
1720 const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL];
1721 const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] ||
1722 cfg->n[GEN_L3P_ALL];
1723 const bool has_c = cfg->n[GEN_L3P_C] || cfg->n[GEN_L3P_RO] ||
1724 cfg->n[GEN_L3P_ALL];
1725 const bool has_t = cfg->n[GEN_L3P_T] || cfg->n[GEN_L3P_RO] ||
1726 cfg->n[GEN_L3P_ALL];
1727
1728 assert(!cfg->n[GEN_L3P_ALL]);
1729
1730 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1731 * the matching space on the remaining banks has to be allocated to a
1732 * client (URB for all validated configurations) set to the
1733 * lower-bandwidth 2-bank address hashing mode.
1734 */
1735 const struct gen_device_info *devinfo = &cmd_buffer->device->info;
1736 const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
1737 assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
1738
1739 /* Minimum number of ways that can be allocated to the URB. */
1740 const unsigned n0_urb = devinfo->is_baytrail ? 32 : 0;
1741 assert(cfg->n[GEN_L3P_URB] >= n0_urb);
1742
1743 uint32_t l3sqcr1, l3cr2, l3cr3;
1744 anv_pack_struct(&l3sqcr1, GENX(L3SQCREG1),
1745 .ConvertDC_UC = !has_dc,
1746 .ConvertIS_UC = !has_is,
1747 .ConvertC_UC = !has_c,
1748 .ConvertT_UC = !has_t);
1749 l3sqcr1 |=
1750 GEN_IS_HASWELL ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
1751 devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
1752 IVB_L3SQCREG1_SQGHPCI_DEFAULT;
1753
1754 anv_pack_struct(&l3cr2, GENX(L3CNTLREG2),
1755 .SLMEnable = has_slm,
1756 .URBLowBandwidth = urb_low_bw,
1757 .URBAllocation = cfg->n[GEN_L3P_URB] - n0_urb,
1758 #if !GEN_IS_HASWELL
1759 .ALLAllocation = cfg->n[GEN_L3P_ALL],
1760 #endif
1761 .ROAllocation = cfg->n[GEN_L3P_RO],
1762 .DCAllocation = cfg->n[GEN_L3P_DC]);
1763
1764 anv_pack_struct(&l3cr3, GENX(L3CNTLREG3),
1765 .ISAllocation = cfg->n[GEN_L3P_IS],
1766 .ISLowBandwidth = 0,
1767 .CAllocation = cfg->n[GEN_L3P_C],
1768 .CLowBandwidth = 0,
1769 .TAllocation = cfg->n[GEN_L3P_T],
1770 .TLowBandwidth = 0);
1771
1772 /* Set up the L3 partitioning. */
1773 emit_lri(&cmd_buffer->batch, GENX(L3SQCREG1_num), l3sqcr1);
1774 emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG2_num), l3cr2);
1775 emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG3_num), l3cr3);
1776
1777 #if GEN_IS_HASWELL
1778 if (cmd_buffer->device->instance->physicalDevice.cmd_parser_version >= 4) {
1779 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1780 * them disabled to avoid crashing the system hard.
1781 */
1782 uint32_t scratch1, chicken3;
1783 anv_pack_struct(&scratch1, GENX(SCRATCH1),
1784 .L3AtomicDisable = !has_dc);
1785 anv_pack_struct(&chicken3, GENX(CHICKEN3),
1786 .L3AtomicDisableMask = true,
1787 .L3AtomicDisable = !has_dc);
1788 emit_lri(&cmd_buffer->batch, GENX(SCRATCH1_num), scratch1);
1789 emit_lri(&cmd_buffer->batch, GENX(CHICKEN3_num), chicken3);
1790 }
1791 #endif
1792
1793 #endif
1794
1795 cmd_buffer->state.current_l3_config = cfg;
1796 }
1797
1798 void
1799 genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
1800 {
1801 enum anv_pipe_bits bits = cmd_buffer->state.pending_pipe_bits;
1802
1803 if (cmd_buffer->device->instance->physicalDevice.always_flush_cache)
1804 bits |= ANV_PIPE_FLUSH_BITS | ANV_PIPE_INVALIDATE_BITS;
1805
1806 /* Flushes are pipelined while invalidations are handled immediately.
1807 * Therefore, if we're flushing anything then we need to schedule a stall
1808 * before any invalidations can happen.
1809 */
1810 if (bits & ANV_PIPE_FLUSH_BITS)
1811 bits |= ANV_PIPE_NEEDS_CS_STALL_BIT;
1812
1813 /* If we're going to do an invalidate and we have a pending CS stall that
1814 * has yet to be resolved, we do the CS stall now.
1815 */
1816 if ((bits & ANV_PIPE_INVALIDATE_BITS) &&
1817 (bits & ANV_PIPE_NEEDS_CS_STALL_BIT)) {
1818 bits |= ANV_PIPE_CS_STALL_BIT;
1819 bits &= ~ANV_PIPE_NEEDS_CS_STALL_BIT;
1820 }
1821
1822 if (GEN_GEN >= 12 &&
1823 ((bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT) ||
1824 (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT))) {
1825 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
1826 * Enable):
1827 *
1828 * Unified Cache (Tile Cache Disabled):
1829 *
1830 * When the Color and Depth (Z) streams are enabled to be cached in
1831 * the DC space of L2, Software must use "Render Target Cache Flush
1832 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
1833 * Flush" for getting the color and depth (Z) write data to be
1834 * globally observable. In this mode of operation it is not required
1835 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
1836 */
1837 bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
1838 }
1839
1840 if (bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_CS_STALL_BIT)) {
1841 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
1842 #if GEN_GEN >= 12
1843 pipe.TileCacheFlushEnable = bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT;
1844 #endif
1845 pipe.DepthCacheFlushEnable = bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1846 pipe.DCFlushEnable = bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1847 pipe.RenderTargetCacheFlushEnable =
1848 bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1849
1850 pipe.DepthStallEnable = bits & ANV_PIPE_DEPTH_STALL_BIT;
1851 pipe.CommandStreamerStallEnable = bits & ANV_PIPE_CS_STALL_BIT;
1852 pipe.StallAtPixelScoreboard = bits & ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
1853
1854 /*
1855 * According to the Broadwell documentation, any PIPE_CONTROL with the
1856 * "Command Streamer Stall" bit set must also have another bit set,
1857 * with five different options:
1858 *
1859 * - Render Target Cache Flush
1860 * - Depth Cache Flush
1861 * - Stall at Pixel Scoreboard
1862 * - Post-Sync Operation
1863 * - Depth Stall
1864 * - DC Flush Enable
1865 *
1866 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1867 * mesa and it seems to work fine. The choice is fairly arbitrary.
1868 */
1869 if ((bits & ANV_PIPE_CS_STALL_BIT) &&
1870 !(bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_DEPTH_STALL_BIT |
1871 ANV_PIPE_STALL_AT_SCOREBOARD_BIT)))
1872 pipe.StallAtPixelScoreboard = true;
1873 }
1874
1875 /* If a render target flush was emitted, then we can toggle off the bit
1876 * saying that render target writes are ongoing.
1877 */
1878 if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1879 bits &= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES);
1880
1881 bits &= ~(ANV_PIPE_FLUSH_BITS | ANV_PIPE_CS_STALL_BIT);
1882 }
1883
1884 if (bits & ANV_PIPE_INVALIDATE_BITS) {
1885 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1886 *
1887 * "If the VF Cache Invalidation Enable is set to a 1 in a
1888 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1889 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1890 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1891 * a 1."
1892 *
1893 * This appears to hang Broadwell, so we restrict it to just gen9.
1894 */
1895 if (GEN_GEN == 9 && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT))
1896 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe);
1897
1898 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
1899 pipe.StateCacheInvalidationEnable =
1900 bits & ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
1901 pipe.ConstantCacheInvalidationEnable =
1902 bits & ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1903 pipe.VFCacheInvalidationEnable =
1904 bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1905 pipe.TextureCacheInvalidationEnable =
1906 bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1907 pipe.InstructionCacheInvalidateEnable =
1908 bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT;
1909
1910 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1911 *
1912 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1913 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1914 * “Write Timestamp”.
1915 */
1916 if (GEN_GEN == 9 && pipe.VFCacheInvalidationEnable) {
1917 pipe.PostSyncOperation = WriteImmediateData;
1918 pipe.Address =
1919 (struct anv_address) { cmd_buffer->device->workaround_bo, 0 };
1920 }
1921 }
1922
1923 bits &= ~ANV_PIPE_INVALIDATE_BITS;
1924 }
1925
1926 cmd_buffer->state.pending_pipe_bits = bits;
1927 }
1928
1929 void genX(CmdPipelineBarrier)(
1930 VkCommandBuffer commandBuffer,
1931 VkPipelineStageFlags srcStageMask,
1932 VkPipelineStageFlags destStageMask,
1933 VkBool32 byRegion,
1934 uint32_t memoryBarrierCount,
1935 const VkMemoryBarrier* pMemoryBarriers,
1936 uint32_t bufferMemoryBarrierCount,
1937 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
1938 uint32_t imageMemoryBarrierCount,
1939 const VkImageMemoryBarrier* pImageMemoryBarriers)
1940 {
1941 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1942
1943 /* XXX: Right now, we're really dumb and just flush whatever categories
1944 * the app asks for. One of these days we may make this a bit better
1945 * but right now that's all the hardware allows for in most areas.
1946 */
1947 VkAccessFlags src_flags = 0;
1948 VkAccessFlags dst_flags = 0;
1949
1950 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
1951 src_flags |= pMemoryBarriers[i].srcAccessMask;
1952 dst_flags |= pMemoryBarriers[i].dstAccessMask;
1953 }
1954
1955 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
1956 src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
1957 dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
1958 }
1959
1960 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
1961 src_flags |= pImageMemoryBarriers[i].srcAccessMask;
1962 dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
1963 ANV_FROM_HANDLE(anv_image, image, pImageMemoryBarriers[i].image);
1964 const VkImageSubresourceRange *range =
1965 &pImageMemoryBarriers[i].subresourceRange;
1966
1967 uint32_t base_layer, layer_count;
1968 if (image->type == VK_IMAGE_TYPE_3D) {
1969 base_layer = 0;
1970 layer_count = anv_minify(image->extent.depth, range->baseMipLevel);
1971 } else {
1972 base_layer = range->baseArrayLayer;
1973 layer_count = anv_get_layerCount(image, range);
1974 }
1975
1976 if (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT) {
1977 transition_depth_buffer(cmd_buffer, image,
1978 pImageMemoryBarriers[i].oldLayout,
1979 pImageMemoryBarriers[i].newLayout);
1980 }
1981
1982 if (range->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT) {
1983 transition_stencil_buffer(cmd_buffer, image,
1984 range->baseMipLevel,
1985 anv_get_levelCount(image, range),
1986 base_layer, layer_count,
1987 pImageMemoryBarriers[i].oldLayout,
1988 pImageMemoryBarriers[i].newLayout);
1989 }
1990
1991 if (range->aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
1992 VkImageAspectFlags color_aspects =
1993 anv_image_expand_aspects(image, range->aspectMask);
1994 uint32_t aspect_bit;
1995 anv_foreach_image_aspect_bit(aspect_bit, image, color_aspects) {
1996 transition_color_buffer(cmd_buffer, image, 1UL << aspect_bit,
1997 range->baseMipLevel,
1998 anv_get_levelCount(image, range),
1999 base_layer, layer_count,
2000 pImageMemoryBarriers[i].oldLayout,
2001 pImageMemoryBarriers[i].newLayout);
2002 }
2003 }
2004 }
2005
2006 cmd_buffer->state.pending_pipe_bits |=
2007 anv_pipe_flush_bits_for_access_flags(src_flags) |
2008 anv_pipe_invalidate_bits_for_access_flags(dst_flags);
2009 }
2010
2011 static void
2012 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer *cmd_buffer)
2013 {
2014 VkShaderStageFlags stages =
2015 cmd_buffer->state.gfx.base.pipeline->active_stages;
2016
2017 /* In order to avoid thrash, we assume that vertex and fragment stages
2018 * always exist. In the rare case where one is missing *and* the other
2019 * uses push concstants, this may be suboptimal. However, avoiding stalls
2020 * seems more important.
2021 */
2022 stages |= VK_SHADER_STAGE_FRAGMENT_BIT | VK_SHADER_STAGE_VERTEX_BIT;
2023
2024 if (stages == cmd_buffer->state.push_constant_stages)
2025 return;
2026
2027 #if GEN_GEN >= 8
2028 const unsigned push_constant_kb = 32;
2029 #elif GEN_IS_HASWELL
2030 const unsigned push_constant_kb = cmd_buffer->device->info.gt == 3 ? 32 : 16;
2031 #else
2032 const unsigned push_constant_kb = 16;
2033 #endif
2034
2035 const unsigned num_stages =
2036 util_bitcount(stages & VK_SHADER_STAGE_ALL_GRAPHICS);
2037 unsigned size_per_stage = push_constant_kb / num_stages;
2038
2039 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2040 * units of 2KB. Incidentally, these are the same platforms that have
2041 * 32KB worth of push constant space.
2042 */
2043 if (push_constant_kb == 32)
2044 size_per_stage &= ~1u;
2045
2046 uint32_t kb_used = 0;
2047 for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) {
2048 unsigned push_size = (stages & (1 << i)) ? size_per_stage : 0;
2049 anv_batch_emit(&cmd_buffer->batch,
2050 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) {
2051 alloc._3DCommandSubOpcode = 18 + i;
2052 alloc.ConstantBufferOffset = (push_size > 0) ? kb_used : 0;
2053 alloc.ConstantBufferSize = push_size;
2054 }
2055 kb_used += push_size;
2056 }
2057
2058 anv_batch_emit(&cmd_buffer->batch,
2059 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS), alloc) {
2060 alloc.ConstantBufferOffset = kb_used;
2061 alloc.ConstantBufferSize = push_constant_kb - kb_used;
2062 }
2063
2064 cmd_buffer->state.push_constant_stages = stages;
2065
2066 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2067 *
2068 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2069 * the next 3DPRIMITIVE command after programming the
2070 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2071 *
2072 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2073 * pipeline setup, we need to dirty push constants.
2074 */
2075 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_ALL_GRAPHICS;
2076 }
2077
2078 static struct anv_address
2079 anv_descriptor_set_address(struct anv_cmd_buffer *cmd_buffer,
2080 struct anv_descriptor_set *set)
2081 {
2082 if (set->pool) {
2083 /* This is a normal descriptor set */
2084 return (struct anv_address) {
2085 .bo = set->pool->bo,
2086 .offset = set->desc_mem.offset,
2087 };
2088 } else {
2089 /* This is a push descriptor set. We have to flag it as used on the GPU
2090 * so that the next time we push descriptors, we grab a new memory.
2091 */
2092 struct anv_push_descriptor_set *push_set =
2093 (struct anv_push_descriptor_set *)set;
2094 push_set->set_used_on_gpu = true;
2095
2096 return (struct anv_address) {
2097 .bo = cmd_buffer->dynamic_state_stream.state_pool->block_pool.bo,
2098 .offset = set->desc_mem.offset,
2099 };
2100 }
2101 }
2102
2103 static VkResult
2104 emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
2105 gl_shader_stage stage,
2106 struct anv_state *bt_state)
2107 {
2108 struct anv_subpass *subpass = cmd_buffer->state.subpass;
2109 struct anv_cmd_pipeline_state *pipe_state;
2110 struct anv_pipeline *pipeline;
2111 uint32_t state_offset;
2112
2113 switch (stage) {
2114 case MESA_SHADER_COMPUTE:
2115 pipe_state = &cmd_buffer->state.compute.base;
2116 break;
2117 default:
2118 pipe_state = &cmd_buffer->state.gfx.base;
2119 break;
2120 }
2121 pipeline = pipe_state->pipeline;
2122
2123 if (!anv_pipeline_has_stage(pipeline, stage)) {
2124 *bt_state = (struct anv_state) { 0, };
2125 return VK_SUCCESS;
2126 }
2127
2128 struct anv_pipeline_bind_map *map = &pipeline->shaders[stage]->bind_map;
2129 if (map->surface_count == 0) {
2130 *bt_state = (struct anv_state) { 0, };
2131 return VK_SUCCESS;
2132 }
2133
2134 *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer,
2135 map->surface_count,
2136 &state_offset);
2137 uint32_t *bt_map = bt_state->map;
2138
2139 if (bt_state->map == NULL)
2140 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2141
2142 /* We only need to emit relocs if we're not using softpin. If we are using
2143 * softpin then we always keep all user-allocated memory objects resident.
2144 */
2145 const bool need_client_mem_relocs =
2146 !cmd_buffer->device->instance->physicalDevice.use_softpin;
2147
2148 for (uint32_t s = 0; s < map->surface_count; s++) {
2149 struct anv_pipeline_binding *binding = &map->surface_to_descriptor[s];
2150
2151 struct anv_state surface_state;
2152
2153 switch (binding->set) {
2154 case ANV_DESCRIPTOR_SET_NULL:
2155 bt_map[s] = 0;
2156 break;
2157
2158 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS:
2159 /* Color attachment binding */
2160 assert(stage == MESA_SHADER_FRAGMENT);
2161 if (binding->index < subpass->color_count) {
2162 const unsigned att =
2163 subpass->color_attachments[binding->index].attachment;
2164
2165 /* From the Vulkan 1.0.46 spec:
2166 *
2167 * "If any color or depth/stencil attachments are
2168 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2169 * attachments."
2170 */
2171 if (att == VK_ATTACHMENT_UNUSED) {
2172 surface_state = cmd_buffer->state.null_surface_state;
2173 } else {
2174 surface_state = cmd_buffer->state.attachments[att].color.state;
2175 }
2176 } else {
2177 surface_state = cmd_buffer->state.null_surface_state;
2178 }
2179
2180 bt_map[s] = surface_state.offset + state_offset;
2181 break;
2182
2183 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS: {
2184 struct anv_state surface_state =
2185 anv_cmd_buffer_alloc_surface_state(cmd_buffer);
2186
2187 struct anv_address constant_data = {
2188 .bo = pipeline->device->dynamic_state_pool.block_pool.bo,
2189 .offset = pipeline->shaders[stage]->constant_data.offset,
2190 };
2191 unsigned constant_data_size =
2192 pipeline->shaders[stage]->constant_data_size;
2193
2194 const enum isl_format format =
2195 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER);
2196 anv_fill_buffer_surface_state(cmd_buffer->device,
2197 surface_state, format,
2198 constant_data, constant_data_size, 1);
2199
2200 bt_map[s] = surface_state.offset + state_offset;
2201 add_surface_reloc(cmd_buffer, surface_state, constant_data);
2202 break;
2203 }
2204
2205 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS: {
2206 /* This is always the first binding for compute shaders */
2207 assert(stage == MESA_SHADER_COMPUTE && s == 0);
2208
2209 struct anv_state surface_state =
2210 anv_cmd_buffer_alloc_surface_state(cmd_buffer);
2211
2212 const enum isl_format format =
2213 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER);
2214 anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
2215 format,
2216 cmd_buffer->state.compute.num_workgroups,
2217 12, 1);
2218 bt_map[s] = surface_state.offset + state_offset;
2219 if (need_client_mem_relocs) {
2220 add_surface_reloc(cmd_buffer, surface_state,
2221 cmd_buffer->state.compute.num_workgroups);
2222 }
2223 break;
2224 }
2225
2226 case ANV_DESCRIPTOR_SET_DESCRIPTORS: {
2227 /* This is a descriptor set buffer so the set index is actually
2228 * given by binding->binding. (Yes, that's confusing.)
2229 */
2230 struct anv_descriptor_set *set =
2231 pipe_state->descriptors[binding->index];
2232 assert(set->desc_mem.alloc_size);
2233 assert(set->desc_surface_state.alloc_size);
2234 bt_map[s] = set->desc_surface_state.offset + state_offset;
2235 add_surface_reloc(cmd_buffer, set->desc_surface_state,
2236 anv_descriptor_set_address(cmd_buffer, set));
2237 break;
2238 }
2239
2240 default: {
2241 assert(binding->set < MAX_SETS);
2242 const struct anv_descriptor *desc =
2243 &pipe_state->descriptors[binding->set]->descriptors[binding->index];
2244
2245 switch (desc->type) {
2246 case VK_DESCRIPTOR_TYPE_SAMPLER:
2247 /* Nothing for us to do here */
2248 continue;
2249
2250 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2251 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE: {
2252 struct anv_surface_state sstate =
2253 (desc->layout == VK_IMAGE_LAYOUT_GENERAL) ?
2254 desc->image_view->planes[binding->plane].general_sampler_surface_state :
2255 desc->image_view->planes[binding->plane].optimal_sampler_surface_state;
2256 surface_state = sstate.state;
2257 assert(surface_state.alloc_size);
2258 if (need_client_mem_relocs)
2259 add_surface_state_relocs(cmd_buffer, sstate);
2260 break;
2261 }
2262 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
2263 assert(stage == MESA_SHADER_FRAGMENT);
2264 if ((desc->image_view->aspect_mask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0) {
2265 /* For depth and stencil input attachments, we treat it like any
2266 * old texture that a user may have bound.
2267 */
2268 assert(desc->image_view->n_planes == 1);
2269 struct anv_surface_state sstate =
2270 (desc->layout == VK_IMAGE_LAYOUT_GENERAL) ?
2271 desc->image_view->planes[0].general_sampler_surface_state :
2272 desc->image_view->planes[0].optimal_sampler_surface_state;
2273 surface_state = sstate.state;
2274 assert(surface_state.alloc_size);
2275 if (need_client_mem_relocs)
2276 add_surface_state_relocs(cmd_buffer, sstate);
2277 } else {
2278 /* For color input attachments, we create the surface state at
2279 * vkBeginRenderPass time so that we can include aux and clear
2280 * color information.
2281 */
2282 assert(binding->input_attachment_index < subpass->input_count);
2283 const unsigned subpass_att = binding->input_attachment_index;
2284 const unsigned att = subpass->input_attachments[subpass_att].attachment;
2285 surface_state = cmd_buffer->state.attachments[att].input.state;
2286 }
2287 break;
2288
2289 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: {
2290 struct anv_surface_state sstate = (binding->write_only)
2291 ? desc->image_view->planes[binding->plane].writeonly_storage_surface_state
2292 : desc->image_view->planes[binding->plane].storage_surface_state;
2293 surface_state = sstate.state;
2294 assert(surface_state.alloc_size);
2295 if (need_client_mem_relocs)
2296 add_surface_state_relocs(cmd_buffer, sstate);
2297 break;
2298 }
2299
2300 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2301 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2302 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2303 surface_state = desc->buffer_view->surface_state;
2304 assert(surface_state.alloc_size);
2305 if (need_client_mem_relocs) {
2306 add_surface_reloc(cmd_buffer, surface_state,
2307 desc->buffer_view->address);
2308 }
2309 break;
2310
2311 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2312 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: {
2313 /* Compute the offset within the buffer */
2314 struct anv_push_constants *push =
2315 &cmd_buffer->state.push_constants[stage];
2316
2317 uint32_t dynamic_offset =
2318 push->dynamic_offsets[binding->dynamic_offset_index];
2319 uint64_t offset = desc->offset + dynamic_offset;
2320 /* Clamp to the buffer size */
2321 offset = MIN2(offset, desc->buffer->size);
2322 /* Clamp the range to the buffer size */
2323 uint32_t range = MIN2(desc->range, desc->buffer->size - offset);
2324
2325 struct anv_address address =
2326 anv_address_add(desc->buffer->address, offset);
2327
2328 surface_state =
2329 anv_state_stream_alloc(&cmd_buffer->surface_state_stream, 64, 64);
2330 enum isl_format format =
2331 anv_isl_format_for_descriptor_type(desc->type);
2332
2333 anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
2334 format, address, range, 1);
2335 if (need_client_mem_relocs)
2336 add_surface_reloc(cmd_buffer, surface_state, address);
2337 break;
2338 }
2339
2340 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2341 surface_state = (binding->write_only)
2342 ? desc->buffer_view->writeonly_storage_surface_state
2343 : desc->buffer_view->storage_surface_state;
2344 assert(surface_state.alloc_size);
2345 if (need_client_mem_relocs) {
2346 add_surface_reloc(cmd_buffer, surface_state,
2347 desc->buffer_view->address);
2348 }
2349 break;
2350
2351 default:
2352 assert(!"Invalid descriptor type");
2353 continue;
2354 }
2355 bt_map[s] = surface_state.offset + state_offset;
2356 break;
2357 }
2358 }
2359 }
2360
2361 return VK_SUCCESS;
2362 }
2363
2364 static VkResult
2365 emit_samplers(struct anv_cmd_buffer *cmd_buffer,
2366 gl_shader_stage stage,
2367 struct anv_state *state)
2368 {
2369 struct anv_cmd_pipeline_state *pipe_state =
2370 stage == MESA_SHADER_COMPUTE ? &cmd_buffer->state.compute.base :
2371 &cmd_buffer->state.gfx.base;
2372 struct anv_pipeline *pipeline = pipe_state->pipeline;
2373
2374 if (!anv_pipeline_has_stage(pipeline, stage)) {
2375 *state = (struct anv_state) { 0, };
2376 return VK_SUCCESS;
2377 }
2378
2379 struct anv_pipeline_bind_map *map = &pipeline->shaders[stage]->bind_map;
2380 if (map->sampler_count == 0) {
2381 *state = (struct anv_state) { 0, };
2382 return VK_SUCCESS;
2383 }
2384
2385 uint32_t size = map->sampler_count * 16;
2386 *state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 32);
2387
2388 if (state->map == NULL)
2389 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2390
2391 for (uint32_t s = 0; s < map->sampler_count; s++) {
2392 struct anv_pipeline_binding *binding = &map->sampler_to_descriptor[s];
2393 const struct anv_descriptor *desc =
2394 &pipe_state->descriptors[binding->set]->descriptors[binding->index];
2395
2396 if (desc->type != VK_DESCRIPTOR_TYPE_SAMPLER &&
2397 desc->type != VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
2398 continue;
2399
2400 struct anv_sampler *sampler = desc->sampler;
2401
2402 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2403 * happens to be zero.
2404 */
2405 if (sampler == NULL)
2406 continue;
2407
2408 memcpy(state->map + (s * 16),
2409 sampler->state[binding->plane], sizeof(sampler->state[0]));
2410 }
2411
2412 return VK_SUCCESS;
2413 }
2414
2415 static uint32_t
2416 flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer)
2417 {
2418 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
2419
2420 VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
2421 pipeline->active_stages;
2422
2423 VkResult result = VK_SUCCESS;
2424 anv_foreach_stage(s, dirty) {
2425 result = emit_samplers(cmd_buffer, s, &cmd_buffer->state.samplers[s]);
2426 if (result != VK_SUCCESS)
2427 break;
2428 result = emit_binding_table(cmd_buffer, s,
2429 &cmd_buffer->state.binding_tables[s]);
2430 if (result != VK_SUCCESS)
2431 break;
2432 }
2433
2434 if (result != VK_SUCCESS) {
2435 assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
2436
2437 result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
2438 if (result != VK_SUCCESS)
2439 return 0;
2440
2441 /* Re-emit state base addresses so we get the new surface state base
2442 * address before we start emitting binding tables etc.
2443 */
2444 genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
2445
2446 /* Re-emit all active binding tables */
2447 dirty |= pipeline->active_stages;
2448 anv_foreach_stage(s, dirty) {
2449 result = emit_samplers(cmd_buffer, s, &cmd_buffer->state.samplers[s]);
2450 if (result != VK_SUCCESS) {
2451 anv_batch_set_error(&cmd_buffer->batch, result);
2452 return 0;
2453 }
2454 result = emit_binding_table(cmd_buffer, s,
2455 &cmd_buffer->state.binding_tables[s]);
2456 if (result != VK_SUCCESS) {
2457 anv_batch_set_error(&cmd_buffer->batch, result);
2458 return 0;
2459 }
2460 }
2461 }
2462
2463 cmd_buffer->state.descriptors_dirty &= ~dirty;
2464
2465 return dirty;
2466 }
2467
2468 static void
2469 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
2470 uint32_t stages)
2471 {
2472 static const uint32_t sampler_state_opcodes[] = {
2473 [MESA_SHADER_VERTEX] = 43,
2474 [MESA_SHADER_TESS_CTRL] = 44, /* HS */
2475 [MESA_SHADER_TESS_EVAL] = 45, /* DS */
2476 [MESA_SHADER_GEOMETRY] = 46,
2477 [MESA_SHADER_FRAGMENT] = 47,
2478 [MESA_SHADER_COMPUTE] = 0,
2479 };
2480
2481 static const uint32_t binding_table_opcodes[] = {
2482 [MESA_SHADER_VERTEX] = 38,
2483 [MESA_SHADER_TESS_CTRL] = 39,
2484 [MESA_SHADER_TESS_EVAL] = 40,
2485 [MESA_SHADER_GEOMETRY] = 41,
2486 [MESA_SHADER_FRAGMENT] = 42,
2487 [MESA_SHADER_COMPUTE] = 0,
2488 };
2489
2490 anv_foreach_stage(s, stages) {
2491 assert(s < ARRAY_SIZE(binding_table_opcodes));
2492 assert(binding_table_opcodes[s] > 0);
2493
2494 if (cmd_buffer->state.samplers[s].alloc_size > 0) {
2495 anv_batch_emit(&cmd_buffer->batch,
2496 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ssp) {
2497 ssp._3DCommandSubOpcode = sampler_state_opcodes[s];
2498 ssp.PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset;
2499 }
2500 }
2501
2502 /* Always emit binding table pointers if we're asked to, since on SKL
2503 * this is what flushes push constants. */
2504 anv_batch_emit(&cmd_buffer->batch,
2505 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), btp) {
2506 btp._3DCommandSubOpcode = binding_table_opcodes[s];
2507 btp.PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset;
2508 }
2509 }
2510 }
2511
2512 static struct anv_address
2513 get_push_range_address(struct anv_cmd_buffer *cmd_buffer,
2514 gl_shader_stage stage,
2515 const struct anv_push_range *range)
2516 {
2517 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2518 const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
2519 switch (range->set) {
2520 case ANV_DESCRIPTOR_SET_DESCRIPTORS: {
2521 /* This is a descriptor set buffer so the set index is
2522 * actually given by binding->binding. (Yes, that's
2523 * confusing.)
2524 */
2525 struct anv_descriptor_set *set =
2526 gfx_state->base.descriptors[range->index];
2527 return anv_descriptor_set_address(cmd_buffer, set);
2528 break;
2529 }
2530
2531 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS: {
2532 struct anv_state state =
2533 anv_cmd_buffer_push_constants(cmd_buffer, stage);
2534 return (struct anv_address) {
2535 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
2536 .offset = state.offset,
2537 };
2538 break;
2539 }
2540
2541 default: {
2542 assert(range->set < MAX_SETS);
2543 struct anv_descriptor_set *set =
2544 gfx_state->base.descriptors[range->set];
2545 const struct anv_descriptor *desc =
2546 &set->descriptors[range->index];
2547
2548 if (desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
2549 return desc->buffer_view->address;
2550 } else {
2551 assert(desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC);
2552 struct anv_push_constants *push =
2553 &cmd_buffer->state.push_constants[stage];
2554 uint32_t dynamic_offset =
2555 push->dynamic_offsets[range->dynamic_offset_index];
2556 return anv_address_add(desc->buffer->address,
2557 desc->offset + dynamic_offset);
2558 }
2559 }
2560 }
2561 #else
2562 /* For Ivy Bridge, push constants are relative to dynamic state
2563 * base address and we only ever push actual push constants.
2564 */
2565 assert(range->length > 0);
2566 assert(range->set == ANV_DESCRIPTOR_SET_PUSH_CONSTANTS);
2567 struct anv_state state =
2568 anv_cmd_buffer_push_constants(cmd_buffer, stage);
2569 return (struct anv_address) {
2570 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
2571 .offset = state.offset,
2572 };
2573 #endif
2574 }
2575
2576 static void
2577 cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer,
2578 gl_shader_stage stage, unsigned buffer_count)
2579 {
2580 const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
2581 const struct anv_pipeline *pipeline = gfx_state->base.pipeline;
2582
2583 static const uint32_t push_constant_opcodes[] = {
2584 [MESA_SHADER_VERTEX] = 21,
2585 [MESA_SHADER_TESS_CTRL] = 25, /* HS */
2586 [MESA_SHADER_TESS_EVAL] = 26, /* DS */
2587 [MESA_SHADER_GEOMETRY] = 22,
2588 [MESA_SHADER_FRAGMENT] = 23,
2589 [MESA_SHADER_COMPUTE] = 0,
2590 };
2591
2592 assert(stage < ARRAY_SIZE(push_constant_opcodes));
2593 assert(push_constant_opcodes[stage] > 0);
2594
2595 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS), c) {
2596 c._3DCommandSubOpcode = push_constant_opcodes[stage];
2597
2598 if (anv_pipeline_has_stage(pipeline, stage)) {
2599 const struct anv_pipeline_bind_map *bind_map =
2600 &pipeline->shaders[stage]->bind_map;
2601
2602 /* The Skylake PRM contains the following restriction:
2603 *
2604 * "The driver must ensure The following case does not occur
2605 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2606 * buffer 3 read length equal to zero committed followed by a
2607 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2608 * zero committed."
2609 *
2610 * To avoid this, we program the buffers in the highest slots.
2611 * This way, slot 0 is only used if slot 3 is also used.
2612 */
2613 assert(buffer_count <= 4);
2614 const unsigned shift = 4 - buffer_count;
2615 for (unsigned i = 0; i < buffer_count; i++) {
2616 const struct anv_push_range *range = &bind_map->push_ranges[i];
2617
2618 /* At this point we only have non-empty ranges */
2619 assert(range->length > 0);
2620
2621 /* For Ivy Bridge, make sure we only set the first range (actual
2622 * push constants)
2623 */
2624 assert((GEN_GEN >= 8 || GEN_IS_HASWELL) || i == 0);
2625
2626 const struct anv_address addr =
2627 get_push_range_address(cmd_buffer, stage, range);
2628 c.ConstantBody.ReadLength[i + shift] = range->length;
2629 c.ConstantBody.Buffer[i + shift] =
2630 anv_address_add(addr, range->start * 32);
2631 }
2632 }
2633 }
2634 }
2635
2636 #if GEN_GEN >= 12
2637 static void
2638 cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer *cmd_buffer,
2639 uint32_t shader_mask, uint32_t count)
2640 {
2641 if (count == 0) {
2642 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_ALL), c) {
2643 c.ShaderUpdateEnable = shader_mask;
2644 }
2645 return;
2646 }
2647
2648 const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
2649 const struct anv_pipeline *pipeline = gfx_state->base.pipeline;
2650
2651 static const uint32_t push_constant_opcodes[] = {
2652 [MESA_SHADER_VERTEX] = 21,
2653 [MESA_SHADER_TESS_CTRL] = 25, /* HS */
2654 [MESA_SHADER_TESS_EVAL] = 26, /* DS */
2655 [MESA_SHADER_GEOMETRY] = 22,
2656 [MESA_SHADER_FRAGMENT] = 23,
2657 [MESA_SHADER_COMPUTE] = 0,
2658 };
2659
2660 gl_shader_stage stage = vk_to_mesa_shader_stage(shader_mask);
2661 assert(stage < ARRAY_SIZE(push_constant_opcodes));
2662 assert(push_constant_opcodes[stage] > 0);
2663
2664 const struct anv_pipeline_bind_map *bind_map =
2665 &pipeline->shaders[stage]->bind_map;
2666
2667 uint32_t *dw;
2668 const uint32_t buffers = (1 << count) - 1;
2669 const uint32_t num_dwords = 2 + 2 * count;
2670
2671 dw = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
2672 GENX(3DSTATE_CONSTANT_ALL),
2673 .ShaderUpdateEnable = shader_mask,
2674 .PointerBufferMask = buffers);
2675
2676 for (int i = 0; i < count; i++) {
2677 const struct anv_push_range *range = &bind_map->push_ranges[i];
2678 const struct anv_address addr =
2679 get_push_range_address(cmd_buffer, stage, range);
2680
2681 GENX(3DSTATE_CONSTANT_ALL_DATA_pack)(
2682 &cmd_buffer->batch, dw + 2 + i * 2,
2683 &(struct GENX(3DSTATE_CONSTANT_ALL_DATA)) {
2684 .PointerToConstantBuffer = anv_address_add(addr, range->start * 32),
2685 .ConstantBufferReadLength = range->length,
2686 });
2687 }
2688 }
2689 #endif
2690
2691 static void
2692 cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer,
2693 VkShaderStageFlags dirty_stages)
2694 {
2695 VkShaderStageFlags flushed = 0;
2696 const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
2697 const struct anv_pipeline *pipeline = gfx_state->base.pipeline;
2698
2699 #if GEN_GEN >= 12
2700 uint32_t nobuffer_stages = 0;
2701 #endif
2702
2703 anv_foreach_stage(stage, dirty_stages) {
2704 unsigned buffer_count = 0;
2705 flushed |= mesa_to_vk_shader_stage(stage);
2706 uint32_t max_push_range = 0;
2707
2708 if (anv_pipeline_has_stage(pipeline, stage)) {
2709 const struct anv_pipeline_bind_map *bind_map =
2710 &pipeline->shaders[stage]->bind_map;
2711
2712 for (unsigned i = 0; i < 4; i++) {
2713 const struct anv_push_range *range = &bind_map->push_ranges[i];
2714 if (range->length > 0) {
2715 buffer_count++;
2716 if (GEN_GEN >= 12 && range->length > max_push_range)
2717 max_push_range = range->length;
2718 }
2719 }
2720 }
2721
2722 #if GEN_GEN >= 12
2723 /* If this stage doesn't have any push constants, emit it later in a
2724 * single CONSTANT_ALL packet.
2725 */
2726 if (buffer_count == 0) {
2727 nobuffer_stages |= 1 << stage;
2728 continue;
2729 }
2730
2731 /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
2732 * contains only 5 bits, so we can only use it for buffers smaller than
2733 * 32.
2734 */
2735 if (max_push_range < 32) {
2736 cmd_buffer_emit_push_constant_all(cmd_buffer, 1 << stage,
2737 buffer_count);
2738 continue;
2739 }
2740 #endif
2741
2742 cmd_buffer_emit_push_constant(cmd_buffer, stage, buffer_count);
2743 }
2744
2745 #if GEN_GEN >= 12
2746 if (nobuffer_stages)
2747 cmd_buffer_emit_push_constant_all(cmd_buffer, nobuffer_stages, 0);
2748 #endif
2749
2750 cmd_buffer->state.push_constants_dirty &= ~flushed;
2751 }
2752
2753 #if GEN_GEN >= 12
2754 void
2755 genX(cmd_buffer_aux_map_state)(struct anv_cmd_buffer *cmd_buffer)
2756 {
2757 void *aux_map_ctx = cmd_buffer->device->aux_map_ctx;
2758 if (!aux_map_ctx)
2759 return;
2760 uint32_t aux_map_state_num = gen_aux_map_get_state_num(aux_map_ctx);
2761 if (cmd_buffer->state.last_aux_map_state != aux_map_state_num) {
2762 /* If the aux-map state number increased, then we need to rewrite the
2763 * register. Rewriting the register is used to both set the aux-map
2764 * translation table address, and also to invalidate any previously
2765 * cached translations.
2766 */
2767 uint64_t base_addr = gen_aux_map_get_base(aux_map_ctx);
2768 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
2769 lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num);
2770 lri.DataDWord = base_addr & 0xffffffff;
2771 }
2772 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
2773 lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4;
2774 lri.DataDWord = base_addr >> 32;
2775 }
2776 cmd_buffer->state.last_aux_map_state = aux_map_state_num;
2777 }
2778 }
2779 #endif
2780
2781 void
2782 genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
2783 {
2784 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
2785 uint32_t *p;
2786
2787 uint32_t vb_emit = cmd_buffer->state.gfx.vb_dirty & pipeline->vb_used;
2788 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE)
2789 vb_emit |= pipeline->vb_used;
2790
2791 assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
2792
2793 genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->urb.l3_config);
2794
2795 genX(cmd_buffer_emit_hashing_mode)(cmd_buffer, UINT_MAX, UINT_MAX, 1);
2796
2797 genX(flush_pipeline_select_3d)(cmd_buffer);
2798
2799 #if GEN_GEN >= 12
2800 genX(cmd_buffer_aux_map_state)(cmd_buffer);
2801 #endif
2802
2803 if (vb_emit) {
2804 const uint32_t num_buffers = __builtin_popcount(vb_emit);
2805 const uint32_t num_dwords = 1 + num_buffers * 4;
2806
2807 p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
2808 GENX(3DSTATE_VERTEX_BUFFERS));
2809 uint32_t vb, i = 0;
2810 for_each_bit(vb, vb_emit) {
2811 struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
2812 uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
2813
2814 struct GENX(VERTEX_BUFFER_STATE) state = {
2815 .VertexBufferIndex = vb,
2816
2817 .MOCS = anv_mocs_for_bo(cmd_buffer->device, buffer->address.bo),
2818 #if GEN_GEN <= 7
2819 .BufferAccessType = pipeline->vb[vb].instanced ? INSTANCEDATA : VERTEXDATA,
2820 .InstanceDataStepRate = pipeline->vb[vb].instance_divisor,
2821 #endif
2822
2823 .AddressModifyEnable = true,
2824 .BufferPitch = pipeline->vb[vb].stride,
2825 .BufferStartingAddress = anv_address_add(buffer->address, offset),
2826
2827 #if GEN_GEN >= 8
2828 .BufferSize = buffer->size - offset
2829 #else
2830 .EndAddress = anv_address_add(buffer->address, buffer->size - 1),
2831 #endif
2832 };
2833
2834 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, &p[1 + i * 4], &state);
2835 i++;
2836 }
2837 }
2838
2839 cmd_buffer->state.gfx.vb_dirty &= ~vb_emit;
2840
2841 #if GEN_GEN >= 8
2842 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_XFB_ENABLE) {
2843 /* We don't need any per-buffer dirty tracking because you're not
2844 * allowed to bind different XFB buffers while XFB is enabled.
2845 */
2846 for (unsigned idx = 0; idx < MAX_XFB_BUFFERS; idx++) {
2847 struct anv_xfb_binding *xfb = &cmd_buffer->state.xfb_bindings[idx];
2848 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) {
2849 #if GEN_GEN < 12
2850 sob.SOBufferIndex = idx;
2851 #else
2852 sob._3DCommandOpcode = 0;
2853 sob._3DCommandSubOpcode = SO_BUFFER_INDEX_0_CMD + idx;
2854 #endif
2855
2856 if (cmd_buffer->state.xfb_enabled && xfb->buffer && xfb->size != 0) {
2857 sob.SOBufferEnable = true;
2858 sob.MOCS = cmd_buffer->device->isl_dev.mocs.internal,
2859 sob.StreamOffsetWriteEnable = false;
2860 sob.SurfaceBaseAddress = anv_address_add(xfb->buffer->address,
2861 xfb->offset);
2862 /* Size is in DWords - 1 */
2863 sob.SurfaceSize = xfb->size / 4 - 1;
2864 }
2865 }
2866 }
2867
2868 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2869 if (GEN_GEN >= 10)
2870 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
2871 }
2872 #endif
2873
2874 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) {
2875 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
2876
2877 /* If the pipeline changed, we may need to re-allocate push constant
2878 * space in the URB.
2879 */
2880 cmd_buffer_alloc_push_constants(cmd_buffer);
2881 }
2882
2883 #if GEN_GEN <= 7
2884 if (cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_VERTEX_BIT ||
2885 cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_VERTEX_BIT) {
2886 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2887 *
2888 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2889 * stall needs to be sent just prior to any 3DSTATE_VS,
2890 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2891 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2892 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2893 * PIPE_CONTROL needs to be sent before any combination of VS
2894 * associated 3DSTATE."
2895 */
2896 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
2897 pc.DepthStallEnable = true;
2898 pc.PostSyncOperation = WriteImmediateData;
2899 pc.Address =
2900 (struct anv_address) { cmd_buffer->device->workaround_bo, 0 };
2901 }
2902 }
2903 #endif
2904
2905 /* Render targets live in the same binding table as fragment descriptors */
2906 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_RENDER_TARGETS)
2907 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
2908
2909 /* We emit the binding tables and sampler tables first, then emit push
2910 * constants and then finally emit binding table and sampler table
2911 * pointers. It has to happen in this order, since emitting the binding
2912 * tables may change the push constants (in case of storage images). After
2913 * emitting push constants, on SKL+ we have to emit the corresponding
2914 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2915 */
2916 uint32_t dirty = 0;
2917 if (cmd_buffer->state.descriptors_dirty)
2918 dirty = flush_descriptor_sets(cmd_buffer);
2919
2920 if (dirty || cmd_buffer->state.push_constants_dirty) {
2921 /* Because we're pushing UBOs, we have to push whenever either
2922 * descriptors or push constants is dirty.
2923 */
2924 dirty |= cmd_buffer->state.push_constants_dirty;
2925 dirty &= ANV_STAGE_MASK & VK_SHADER_STAGE_ALL_GRAPHICS;
2926 cmd_buffer_flush_push_constants(cmd_buffer, dirty);
2927 }
2928
2929 if (dirty)
2930 cmd_buffer_emit_descriptor_pointers(cmd_buffer, dirty);
2931
2932 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
2933 gen8_cmd_buffer_emit_viewport(cmd_buffer);
2934
2935 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2936 ANV_CMD_DIRTY_PIPELINE)) {
2937 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer,
2938 pipeline->depth_clamp_enable);
2939 }
2940
2941 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_SCISSOR |
2942 ANV_CMD_DIRTY_RENDER_TARGETS))
2943 gen7_cmd_buffer_emit_scissor(cmd_buffer);
2944
2945 genX(cmd_buffer_flush_dynamic_state)(cmd_buffer);
2946
2947 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
2948 }
2949
2950 static void
2951 emit_vertex_bo(struct anv_cmd_buffer *cmd_buffer,
2952 struct anv_address addr,
2953 uint32_t size, uint32_t index)
2954 {
2955 uint32_t *p = anv_batch_emitn(&cmd_buffer->batch, 5,
2956 GENX(3DSTATE_VERTEX_BUFFERS));
2957
2958 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, p + 1,
2959 &(struct GENX(VERTEX_BUFFER_STATE)) {
2960 .VertexBufferIndex = index,
2961 .AddressModifyEnable = true,
2962 .BufferPitch = 0,
2963 .MOCS = addr.bo ? anv_mocs_for_bo(cmd_buffer->device, addr.bo) : 0,
2964 .NullVertexBuffer = size == 0,
2965 #if (GEN_GEN >= 8)
2966 .BufferStartingAddress = addr,
2967 .BufferSize = size
2968 #else
2969 .BufferStartingAddress = addr,
2970 .EndAddress = anv_address_add(addr, size),
2971 #endif
2972 });
2973 }
2974
2975 static void
2976 emit_base_vertex_instance_bo(struct anv_cmd_buffer *cmd_buffer,
2977 struct anv_address addr)
2978 {
2979 emit_vertex_bo(cmd_buffer, addr, addr.bo ? 8 : 0, ANV_SVGS_VB_INDEX);
2980 }
2981
2982 static void
2983 emit_base_vertex_instance(struct anv_cmd_buffer *cmd_buffer,
2984 uint32_t base_vertex, uint32_t base_instance)
2985 {
2986 if (base_vertex == 0 && base_instance == 0) {
2987 emit_base_vertex_instance_bo(cmd_buffer, ANV_NULL_ADDRESS);
2988 } else {
2989 struct anv_state id_state =
2990 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 8, 4);
2991
2992 ((uint32_t *)id_state.map)[0] = base_vertex;
2993 ((uint32_t *)id_state.map)[1] = base_instance;
2994
2995 struct anv_address addr = {
2996 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
2997 .offset = id_state.offset,
2998 };
2999
3000 emit_base_vertex_instance_bo(cmd_buffer, addr);
3001 }
3002 }
3003
3004 static void
3005 emit_draw_index(struct anv_cmd_buffer *cmd_buffer, uint32_t draw_index)
3006 {
3007 struct anv_state state =
3008 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 4, 4);
3009
3010 ((uint32_t *)state.map)[0] = draw_index;
3011
3012 struct anv_address addr = {
3013 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
3014 .offset = state.offset,
3015 };
3016
3017 emit_vertex_bo(cmd_buffer, addr, 4, ANV_DRAWID_VB_INDEX);
3018 }
3019
3020 void genX(CmdDraw)(
3021 VkCommandBuffer commandBuffer,
3022 uint32_t vertexCount,
3023 uint32_t instanceCount,
3024 uint32_t firstVertex,
3025 uint32_t firstInstance)
3026 {
3027 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3028 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
3029 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
3030
3031 if (anv_batch_has_error(&cmd_buffer->batch))
3032 return;
3033
3034 genX(cmd_buffer_flush_state)(cmd_buffer);
3035
3036 if (cmd_buffer->state.conditional_render_enabled)
3037 genX(cmd_emit_conditional_render_predicate)(cmd_buffer);
3038
3039 if (vs_prog_data->uses_firstvertex ||
3040 vs_prog_data->uses_baseinstance)
3041 emit_base_vertex_instance(cmd_buffer, firstVertex, firstInstance);
3042 if (vs_prog_data->uses_drawid)
3043 emit_draw_index(cmd_buffer, 0);
3044
3045 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3046 * different views. We need to multiply instanceCount by the view count.
3047 */
3048 instanceCount *= anv_subpass_view_count(cmd_buffer->state.subpass);
3049
3050 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
3051 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
3052 prim.VertexAccessType = SEQUENTIAL;
3053 prim.PrimitiveTopologyType = pipeline->topology;
3054 prim.VertexCountPerInstance = vertexCount;
3055 prim.StartVertexLocation = firstVertex;
3056 prim.InstanceCount = instanceCount;
3057 prim.StartInstanceLocation = firstInstance;
3058 prim.BaseVertexLocation = 0;
3059 }
3060 }
3061
3062 void genX(CmdDrawIndexed)(
3063 VkCommandBuffer commandBuffer,
3064 uint32_t indexCount,
3065 uint32_t instanceCount,
3066 uint32_t firstIndex,
3067 int32_t vertexOffset,
3068 uint32_t firstInstance)
3069 {
3070 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3071 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
3072 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
3073
3074 if (anv_batch_has_error(&cmd_buffer->batch))
3075 return;
3076
3077 genX(cmd_buffer_flush_state)(cmd_buffer);
3078
3079 if (cmd_buffer->state.conditional_render_enabled)
3080 genX(cmd_emit_conditional_render_predicate)(cmd_buffer);
3081
3082 if (vs_prog_data->uses_firstvertex ||
3083 vs_prog_data->uses_baseinstance)
3084 emit_base_vertex_instance(cmd_buffer, vertexOffset, firstInstance);
3085 if (vs_prog_data->uses_drawid)
3086 emit_draw_index(cmd_buffer, 0);
3087
3088 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3089 * different views. We need to multiply instanceCount by the view count.
3090 */
3091 instanceCount *= anv_subpass_view_count(cmd_buffer->state.subpass);
3092
3093 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
3094 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
3095 prim.VertexAccessType = RANDOM;
3096 prim.PrimitiveTopologyType = pipeline->topology;
3097 prim.VertexCountPerInstance = indexCount;
3098 prim.StartVertexLocation = firstIndex;
3099 prim.InstanceCount = instanceCount;
3100 prim.StartInstanceLocation = firstInstance;
3101 prim.BaseVertexLocation = vertexOffset;
3102 }
3103 }
3104
3105 /* Auto-Draw / Indirect Registers */
3106 #define GEN7_3DPRIM_END_OFFSET 0x2420
3107 #define GEN7_3DPRIM_START_VERTEX 0x2430
3108 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3109 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3110 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3111 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3112
3113 void genX(CmdDrawIndirectByteCountEXT)(
3114 VkCommandBuffer commandBuffer,
3115 uint32_t instanceCount,
3116 uint32_t firstInstance,
3117 VkBuffer counterBuffer,
3118 VkDeviceSize counterBufferOffset,
3119 uint32_t counterOffset,
3120 uint32_t vertexStride)
3121 {
3122 #if GEN_IS_HASWELL || GEN_GEN >= 8
3123 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3124 ANV_FROM_HANDLE(anv_buffer, counter_buffer, counterBuffer);
3125 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
3126 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
3127
3128 /* firstVertex is always zero for this draw function */
3129 const uint32_t firstVertex = 0;
3130
3131 if (anv_batch_has_error(&cmd_buffer->batch))
3132 return;
3133
3134 genX(cmd_buffer_flush_state)(cmd_buffer);
3135
3136 if (vs_prog_data->uses_firstvertex ||
3137 vs_prog_data->uses_baseinstance)
3138 emit_base_vertex_instance(cmd_buffer, firstVertex, firstInstance);
3139 if (vs_prog_data->uses_drawid)
3140 emit_draw_index(cmd_buffer, 0);
3141
3142 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3143 * different views. We need to multiply instanceCount by the view count.
3144 */
3145 instanceCount *= anv_subpass_view_count(cmd_buffer->state.subpass);
3146
3147 struct gen_mi_builder b;
3148 gen_mi_builder_init(&b, &cmd_buffer->batch);
3149 struct gen_mi_value count =
3150 gen_mi_mem32(anv_address_add(counter_buffer->address,
3151 counterBufferOffset));
3152 if (counterOffset)
3153 count = gen_mi_isub(&b, count, gen_mi_imm(counterOffset));
3154 count = gen_mi_udiv32_imm(&b, count, vertexStride);
3155 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT), count);
3156
3157 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX),
3158 gen_mi_imm(firstVertex));
3159 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT),
3160 gen_mi_imm(instanceCount));
3161 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE),
3162 gen_mi_imm(firstInstance));
3163 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX), gen_mi_imm(0));
3164
3165 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
3166 prim.IndirectParameterEnable = true;
3167 prim.VertexAccessType = SEQUENTIAL;
3168 prim.PrimitiveTopologyType = pipeline->topology;
3169 }
3170 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3171 }
3172
3173 static void
3174 load_indirect_parameters(struct anv_cmd_buffer *cmd_buffer,
3175 struct anv_address addr,
3176 bool indexed)
3177 {
3178 struct gen_mi_builder b;
3179 gen_mi_builder_init(&b, &cmd_buffer->batch);
3180
3181 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT),
3182 gen_mi_mem32(anv_address_add(addr, 0)));
3183
3184 struct gen_mi_value instance_count = gen_mi_mem32(anv_address_add(addr, 4));
3185 unsigned view_count = anv_subpass_view_count(cmd_buffer->state.subpass);
3186 if (view_count > 1) {
3187 #if GEN_IS_HASWELL || GEN_GEN >= 8
3188 instance_count = gen_mi_imul_imm(&b, instance_count, view_count);
3189 #else
3190 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3191 "MI_MATH is not supported on Ivy Bridge");
3192 #endif
3193 }
3194 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT), instance_count);
3195
3196 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX),
3197 gen_mi_mem32(anv_address_add(addr, 8)));
3198
3199 if (indexed) {
3200 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX),
3201 gen_mi_mem32(anv_address_add(addr, 12)));
3202 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE),
3203 gen_mi_mem32(anv_address_add(addr, 16)));
3204 } else {
3205 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE),
3206 gen_mi_mem32(anv_address_add(addr, 12)));
3207 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX), gen_mi_imm(0));
3208 }
3209 }
3210
3211 void genX(CmdDrawIndirect)(
3212 VkCommandBuffer commandBuffer,
3213 VkBuffer _buffer,
3214 VkDeviceSize offset,
3215 uint32_t drawCount,
3216 uint32_t stride)
3217 {
3218 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3219 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
3220 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
3221 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
3222
3223 if (anv_batch_has_error(&cmd_buffer->batch))
3224 return;
3225
3226 genX(cmd_buffer_flush_state)(cmd_buffer);
3227
3228 if (cmd_buffer->state.conditional_render_enabled)
3229 genX(cmd_emit_conditional_render_predicate)(cmd_buffer);
3230
3231 for (uint32_t i = 0; i < drawCount; i++) {
3232 struct anv_address draw = anv_address_add(buffer->address, offset);
3233
3234 if (vs_prog_data->uses_firstvertex ||
3235 vs_prog_data->uses_baseinstance)
3236 emit_base_vertex_instance_bo(cmd_buffer, anv_address_add(draw, 8));
3237 if (vs_prog_data->uses_drawid)
3238 emit_draw_index(cmd_buffer, i);
3239
3240 load_indirect_parameters(cmd_buffer, draw, false);
3241
3242 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
3243 prim.IndirectParameterEnable = true;
3244 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
3245 prim.VertexAccessType = SEQUENTIAL;
3246 prim.PrimitiveTopologyType = pipeline->topology;
3247 }
3248
3249 offset += stride;
3250 }
3251 }
3252
3253 void genX(CmdDrawIndexedIndirect)(
3254 VkCommandBuffer commandBuffer,
3255 VkBuffer _buffer,
3256 VkDeviceSize offset,
3257 uint32_t drawCount,
3258 uint32_t stride)
3259 {
3260 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3261 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
3262 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
3263 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
3264
3265 if (anv_batch_has_error(&cmd_buffer->batch))
3266 return;
3267
3268 genX(cmd_buffer_flush_state)(cmd_buffer);
3269
3270 if (cmd_buffer->state.conditional_render_enabled)
3271 genX(cmd_emit_conditional_render_predicate)(cmd_buffer);
3272
3273 for (uint32_t i = 0; i < drawCount; i++) {
3274 struct anv_address draw = anv_address_add(buffer->address, offset);
3275
3276 /* TODO: We need to stomp base vertex to 0 somehow */
3277 if (vs_prog_data->uses_firstvertex ||
3278 vs_prog_data->uses_baseinstance)
3279 emit_base_vertex_instance_bo(cmd_buffer, anv_address_add(draw, 12));
3280 if (vs_prog_data->uses_drawid)
3281 emit_draw_index(cmd_buffer, i);
3282
3283 load_indirect_parameters(cmd_buffer, draw, true);
3284
3285 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
3286 prim.IndirectParameterEnable = true;
3287 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
3288 prim.VertexAccessType = RANDOM;
3289 prim.PrimitiveTopologyType = pipeline->topology;
3290 }
3291
3292 offset += stride;
3293 }
3294 }
3295
3296 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3297
3298 static void
3299 prepare_for_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer,
3300 struct anv_address count_address,
3301 const bool conditional_render_enabled)
3302 {
3303 struct gen_mi_builder b;
3304 gen_mi_builder_init(&b, &cmd_buffer->batch);
3305
3306 if (conditional_render_enabled) {
3307 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3308 gen_mi_store(&b, gen_mi_reg64(TMP_DRAW_COUNT_REG),
3309 gen_mi_mem32(count_address));
3310 #endif
3311 } else {
3312 /* Upload the current draw count from the draw parameters buffer to
3313 * MI_PREDICATE_SRC0.
3314 */
3315 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
3316 gen_mi_mem32(count_address));
3317
3318 gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC1 + 4), gen_mi_imm(0));
3319 }
3320 }
3321
3322 static void
3323 emit_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer,
3324 uint32_t draw_index)
3325 {
3326 struct gen_mi_builder b;
3327 gen_mi_builder_init(&b, &cmd_buffer->batch);
3328
3329 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3330 gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC1), gen_mi_imm(draw_index));
3331
3332 if (draw_index == 0) {
3333 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
3334 mip.LoadOperation = LOAD_LOADINV;
3335 mip.CombineOperation = COMBINE_SET;
3336 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3337 }
3338 } else {
3339 /* While draw_index < draw_count the predicate's result will be
3340 * (draw_index == draw_count) ^ TRUE = TRUE
3341 * When draw_index == draw_count the result is
3342 * (TRUE) ^ TRUE = FALSE
3343 * After this all results will be:
3344 * (FALSE) ^ FALSE = FALSE
3345 */
3346 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
3347 mip.LoadOperation = LOAD_LOAD;
3348 mip.CombineOperation = COMBINE_XOR;
3349 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3350 }
3351 }
3352 }
3353
3354 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3355 static void
3356 emit_draw_count_predicate_with_conditional_render(
3357 struct anv_cmd_buffer *cmd_buffer,
3358 uint32_t draw_index)
3359 {
3360 struct gen_mi_builder b;
3361 gen_mi_builder_init(&b, &cmd_buffer->batch);
3362
3363 struct gen_mi_value pred = gen_mi_ult(&b, gen_mi_imm(draw_index),
3364 gen_mi_reg64(TMP_DRAW_COUNT_REG));
3365 pred = gen_mi_iand(&b, pred, gen_mi_reg64(ANV_PREDICATE_RESULT_REG));
3366
3367 #if GEN_GEN >= 8
3368 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_RESULT), pred);
3369 #else
3370 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3371 * so we emit MI_PREDICATE to set it.
3372 */
3373
3374 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), pred);
3375 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
3376
3377 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
3378 mip.LoadOperation = LOAD_LOADINV;
3379 mip.CombineOperation = COMBINE_SET;
3380 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3381 }
3382 #endif
3383 }
3384 #endif
3385
3386 void genX(CmdDrawIndirectCountKHR)(
3387 VkCommandBuffer commandBuffer,
3388 VkBuffer _buffer,
3389 VkDeviceSize offset,
3390 VkBuffer _countBuffer,
3391 VkDeviceSize countBufferOffset,
3392 uint32_t maxDrawCount,
3393 uint32_t stride)
3394 {
3395 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3396 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
3397 ANV_FROM_HANDLE(anv_buffer, count_buffer, _countBuffer);
3398 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
3399 struct anv_pipeline *pipeline = cmd_state->gfx.base.pipeline;
3400 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
3401
3402 if (anv_batch_has_error(&cmd_buffer->batch))
3403 return;
3404
3405 genX(cmd_buffer_flush_state)(cmd_buffer);
3406
3407 struct anv_address count_address =
3408 anv_address_add(count_buffer->address, countBufferOffset);
3409
3410 prepare_for_draw_count_predicate(cmd_buffer, count_address,
3411 cmd_state->conditional_render_enabled);
3412
3413 for (uint32_t i = 0; i < maxDrawCount; i++) {
3414 struct anv_address draw = anv_address_add(buffer->address, offset);
3415
3416 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3417 if (cmd_state->conditional_render_enabled) {
3418 emit_draw_count_predicate_with_conditional_render(cmd_buffer, i);
3419 } else {
3420 emit_draw_count_predicate(cmd_buffer, i);
3421 }
3422 #else
3423 emit_draw_count_predicate(cmd_buffer, i);
3424 #endif
3425
3426 if (vs_prog_data->uses_firstvertex ||
3427 vs_prog_data->uses_baseinstance)
3428 emit_base_vertex_instance_bo(cmd_buffer, anv_address_add(draw, 8));
3429 if (vs_prog_data->uses_drawid)
3430 emit_draw_index(cmd_buffer, i);
3431
3432 load_indirect_parameters(cmd_buffer, draw, false);
3433
3434 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
3435 prim.IndirectParameterEnable = true;
3436 prim.PredicateEnable = true;
3437 prim.VertexAccessType = SEQUENTIAL;
3438 prim.PrimitiveTopologyType = pipeline->topology;
3439 }
3440
3441 offset += stride;
3442 }
3443 }
3444
3445 void genX(CmdDrawIndexedIndirectCountKHR)(
3446 VkCommandBuffer commandBuffer,
3447 VkBuffer _buffer,
3448 VkDeviceSize offset,
3449 VkBuffer _countBuffer,
3450 VkDeviceSize countBufferOffset,
3451 uint32_t maxDrawCount,
3452 uint32_t stride)
3453 {
3454 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3455 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
3456 ANV_FROM_HANDLE(anv_buffer, count_buffer, _countBuffer);
3457 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
3458 struct anv_pipeline *pipeline = cmd_state->gfx.base.pipeline;
3459 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
3460
3461 if (anv_batch_has_error(&cmd_buffer->batch))
3462 return;
3463
3464 genX(cmd_buffer_flush_state)(cmd_buffer);
3465
3466 struct anv_address count_address =
3467 anv_address_add(count_buffer->address, countBufferOffset);
3468
3469 prepare_for_draw_count_predicate(cmd_buffer, count_address,
3470 cmd_state->conditional_render_enabled);
3471
3472 for (uint32_t i = 0; i < maxDrawCount; i++) {
3473 struct anv_address draw = anv_address_add(buffer->address, offset);
3474
3475 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3476 if (cmd_state->conditional_render_enabled) {
3477 emit_draw_count_predicate_with_conditional_render(cmd_buffer, i);
3478 } else {
3479 emit_draw_count_predicate(cmd_buffer, i);
3480 }
3481 #else
3482 emit_draw_count_predicate(cmd_buffer, i);
3483 #endif
3484
3485 /* TODO: We need to stomp base vertex to 0 somehow */
3486 if (vs_prog_data->uses_firstvertex ||
3487 vs_prog_data->uses_baseinstance)
3488 emit_base_vertex_instance_bo(cmd_buffer, anv_address_add(draw, 12));
3489 if (vs_prog_data->uses_drawid)
3490 emit_draw_index(cmd_buffer, i);
3491
3492 load_indirect_parameters(cmd_buffer, draw, true);
3493
3494 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
3495 prim.IndirectParameterEnable = true;
3496 prim.PredicateEnable = true;
3497 prim.VertexAccessType = RANDOM;
3498 prim.PrimitiveTopologyType = pipeline->topology;
3499 }
3500
3501 offset += stride;
3502 }
3503 }
3504
3505 void genX(CmdBeginTransformFeedbackEXT)(
3506 VkCommandBuffer commandBuffer,
3507 uint32_t firstCounterBuffer,
3508 uint32_t counterBufferCount,
3509 const VkBuffer* pCounterBuffers,
3510 const VkDeviceSize* pCounterBufferOffsets)
3511 {
3512 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3513
3514 assert(firstCounterBuffer < MAX_XFB_BUFFERS);
3515 assert(counterBufferCount <= MAX_XFB_BUFFERS);
3516 assert(firstCounterBuffer + counterBufferCount <= MAX_XFB_BUFFERS);
3517
3518 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3519 *
3520 * "Ssoftware must ensure that no HW stream output operations can be in
3521 * process or otherwise pending at the point that the MI_LOAD/STORE
3522 * commands are processed. This will likely require a pipeline flush."
3523 */
3524 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
3525 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
3526
3527 for (uint32_t idx = 0; idx < MAX_XFB_BUFFERS; idx++) {
3528 /* If we have a counter buffer, this is a resume so we need to load the
3529 * value into the streamout offset register. Otherwise, this is a begin
3530 * and we need to reset it to zero.
3531 */
3532 if (pCounterBuffers &&
3533 idx >= firstCounterBuffer &&
3534 idx - firstCounterBuffer < counterBufferCount &&
3535 pCounterBuffers[idx - firstCounterBuffer] != VK_NULL_HANDLE) {
3536 uint32_t cb_idx = idx - firstCounterBuffer;
3537 ANV_FROM_HANDLE(anv_buffer, counter_buffer, pCounterBuffers[cb_idx]);
3538 uint64_t offset = pCounterBufferOffsets ?
3539 pCounterBufferOffsets[cb_idx] : 0;
3540
3541 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
3542 lrm.RegisterAddress = GENX(SO_WRITE_OFFSET0_num) + idx * 4;
3543 lrm.MemoryAddress = anv_address_add(counter_buffer->address,
3544 offset);
3545 }
3546 } else {
3547 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
3548 lri.RegisterOffset = GENX(SO_WRITE_OFFSET0_num) + idx * 4;
3549 lri.DataDWord = 0;
3550 }
3551 }
3552 }
3553
3554 cmd_buffer->state.xfb_enabled = true;
3555 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_XFB_ENABLE;
3556 }
3557
3558 void genX(CmdEndTransformFeedbackEXT)(
3559 VkCommandBuffer commandBuffer,
3560 uint32_t firstCounterBuffer,
3561 uint32_t counterBufferCount,
3562 const VkBuffer* pCounterBuffers,
3563 const VkDeviceSize* pCounterBufferOffsets)
3564 {
3565 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3566
3567 assert(firstCounterBuffer < MAX_XFB_BUFFERS);
3568 assert(counterBufferCount <= MAX_XFB_BUFFERS);
3569 assert(firstCounterBuffer + counterBufferCount <= MAX_XFB_BUFFERS);
3570
3571 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3572 *
3573 * "Ssoftware must ensure that no HW stream output operations can be in
3574 * process or otherwise pending at the point that the MI_LOAD/STORE
3575 * commands are processed. This will likely require a pipeline flush."
3576 */
3577 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
3578 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
3579
3580 for (uint32_t cb_idx = 0; cb_idx < counterBufferCount; cb_idx++) {
3581 unsigned idx = firstCounterBuffer + cb_idx;
3582
3583 /* If we have a counter buffer, this is a resume so we need to load the
3584 * value into the streamout offset register. Otherwise, this is a begin
3585 * and we need to reset it to zero.
3586 */
3587 if (pCounterBuffers &&
3588 cb_idx < counterBufferCount &&
3589 pCounterBuffers[cb_idx] != VK_NULL_HANDLE) {
3590 ANV_FROM_HANDLE(anv_buffer, counter_buffer, pCounterBuffers[cb_idx]);
3591 uint64_t offset = pCounterBufferOffsets ?
3592 pCounterBufferOffsets[cb_idx] : 0;
3593
3594 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) {
3595 srm.MemoryAddress = anv_address_add(counter_buffer->address,
3596 offset);
3597 srm.RegisterAddress = GENX(SO_WRITE_OFFSET0_num) + idx * 4;
3598 }
3599 }
3600 }
3601
3602 cmd_buffer->state.xfb_enabled = false;
3603 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_XFB_ENABLE;
3604 }
3605
3606 static VkResult
3607 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
3608 {
3609 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
3610 struct anv_state surfaces = { 0, }, samplers = { 0, };
3611 VkResult result;
3612
3613 result = emit_binding_table(cmd_buffer, MESA_SHADER_COMPUTE, &surfaces);
3614 if (result != VK_SUCCESS) {
3615 assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
3616
3617 result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
3618 if (result != VK_SUCCESS)
3619 return result;
3620
3621 /* Re-emit state base addresses so we get the new surface state base
3622 * address before we start emitting binding tables etc.
3623 */
3624 genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
3625
3626 result = emit_binding_table(cmd_buffer, MESA_SHADER_COMPUTE, &surfaces);
3627 if (result != VK_SUCCESS) {
3628 anv_batch_set_error(&cmd_buffer->batch, result);
3629 return result;
3630 }
3631 }
3632
3633 result = emit_samplers(cmd_buffer, MESA_SHADER_COMPUTE, &samplers);
3634 if (result != VK_SUCCESS) {
3635 anv_batch_set_error(&cmd_buffer->batch, result);
3636 return result;
3637 }
3638
3639 uint32_t iface_desc_data_dw[GENX(INTERFACE_DESCRIPTOR_DATA_length)];
3640 struct GENX(INTERFACE_DESCRIPTOR_DATA) desc = {
3641 .BindingTablePointer = surfaces.offset,
3642 .SamplerStatePointer = samplers.offset,
3643 };
3644 GENX(INTERFACE_DESCRIPTOR_DATA_pack)(NULL, iface_desc_data_dw, &desc);
3645
3646 struct anv_state state =
3647 anv_cmd_buffer_merge_dynamic(cmd_buffer, iface_desc_data_dw,
3648 pipeline->interface_descriptor_data,
3649 GENX(INTERFACE_DESCRIPTOR_DATA_length),
3650 64);
3651
3652 uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
3653 anv_batch_emit(&cmd_buffer->batch,
3654 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
3655 mid.InterfaceDescriptorTotalLength = size;
3656 mid.InterfaceDescriptorDataStartAddress = state.offset;
3657 }
3658
3659 return VK_SUCCESS;
3660 }
3661
3662 void
3663 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
3664 {
3665 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
3666 VkResult result;
3667
3668 assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
3669
3670 genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->urb.l3_config);
3671
3672 genX(flush_pipeline_select_gpgpu)(cmd_buffer);
3673
3674 #if GEN_GEN >= 12
3675 genX(cmd_buffer_aux_map_state)(cmd_buffer);
3676 #endif
3677
3678 if (cmd_buffer->state.compute.pipeline_dirty) {
3679 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3680 *
3681 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3682 * the only bits that are changed are scoreboard related: Scoreboard
3683 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3684 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3685 * sufficient."
3686 */
3687 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
3688 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
3689
3690 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
3691
3692 /* The workgroup size of the pipeline affects our push constant layout
3693 * so flag push constants as dirty if we change the pipeline.
3694 */
3695 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
3696 }
3697
3698 if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
3699 cmd_buffer->state.compute.pipeline_dirty) {
3700 /* FIXME: figure out descriptors for gen7 */
3701 result = flush_compute_descriptor_set(cmd_buffer);
3702 if (result != VK_SUCCESS)
3703 return;
3704
3705 cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
3706 }
3707
3708 if (cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_COMPUTE_BIT) {
3709 struct anv_state push_state =
3710 anv_cmd_buffer_cs_push_constants(cmd_buffer);
3711
3712 if (push_state.alloc_size) {
3713 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
3714 curbe.CURBETotalDataLength = push_state.alloc_size;
3715 curbe.CURBEDataStartAddress = push_state.offset;
3716 }
3717 }
3718
3719 cmd_buffer->state.push_constants_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
3720 }
3721
3722 cmd_buffer->state.compute.pipeline_dirty = false;
3723
3724 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
3725 }
3726
3727 #if GEN_GEN == 7
3728
3729 static VkResult
3730 verify_cmd_parser(const struct anv_device *device,
3731 int required_version,
3732 const char *function)
3733 {
3734 if (device->instance->physicalDevice.cmd_parser_version < required_version) {
3735 return vk_errorf(device->instance, device->instance,
3736 VK_ERROR_FEATURE_NOT_PRESENT,
3737 "cmd parser version %d is required for %s",
3738 required_version, function);
3739 } else {
3740 return VK_SUCCESS;
3741 }
3742 }
3743
3744 #endif
3745
3746 static void
3747 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer *cmd_buffer,
3748 uint32_t baseGroupX,
3749 uint32_t baseGroupY,
3750 uint32_t baseGroupZ)
3751 {
3752 if (anv_batch_has_error(&cmd_buffer->batch))
3753 return;
3754
3755 struct anv_push_constants *push =
3756 &cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
3757 if (push->cs.base_work_group_id[0] != baseGroupX ||
3758 push->cs.base_work_group_id[1] != baseGroupY ||
3759 push->cs.base_work_group_id[2] != baseGroupZ) {
3760 push->cs.base_work_group_id[0] = baseGroupX;
3761 push->cs.base_work_group_id[1] = baseGroupY;
3762 push->cs.base_work_group_id[2] = baseGroupZ;
3763
3764 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
3765 }
3766 }
3767
3768 void genX(CmdDispatch)(
3769 VkCommandBuffer commandBuffer,
3770 uint32_t x,
3771 uint32_t y,
3772 uint32_t z)
3773 {
3774 genX(CmdDispatchBase)(commandBuffer, 0, 0, 0, x, y, z);
3775 }
3776
3777 void genX(CmdDispatchBase)(
3778 VkCommandBuffer commandBuffer,
3779 uint32_t baseGroupX,
3780 uint32_t baseGroupY,
3781 uint32_t baseGroupZ,
3782 uint32_t groupCountX,
3783 uint32_t groupCountY,
3784 uint32_t groupCountZ)
3785 {
3786 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3787 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
3788 const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
3789
3790 anv_cmd_buffer_push_base_group_id(cmd_buffer, baseGroupX,
3791 baseGroupY, baseGroupZ);
3792
3793 if (anv_batch_has_error(&cmd_buffer->batch))
3794 return;
3795
3796 if (prog_data->uses_num_work_groups) {
3797 struct anv_state state =
3798 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 12, 4);
3799 uint32_t *sizes = state.map;
3800 sizes[0] = groupCountX;
3801 sizes[1] = groupCountY;
3802 sizes[2] = groupCountZ;
3803 cmd_buffer->state.compute.num_workgroups = (struct anv_address) {
3804 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
3805 .offset = state.offset,
3806 };
3807 }
3808
3809 genX(cmd_buffer_flush_compute_state)(cmd_buffer);
3810
3811 if (cmd_buffer->state.conditional_render_enabled)
3812 genX(cmd_emit_conditional_render_predicate)(cmd_buffer);
3813
3814 anv_batch_emit(&cmd_buffer->batch, GENX(GPGPU_WALKER), ggw) {
3815 ggw.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
3816 ggw.SIMDSize = prog_data->simd_size / 16;
3817 ggw.ThreadDepthCounterMaximum = 0;
3818 ggw.ThreadHeightCounterMaximum = 0;
3819 ggw.ThreadWidthCounterMaximum = prog_data->threads - 1;
3820 ggw.ThreadGroupIDXDimension = groupCountX;
3821 ggw.ThreadGroupIDYDimension = groupCountY;
3822 ggw.ThreadGroupIDZDimension = groupCountZ;
3823 ggw.RightExecutionMask = pipeline->cs_right_mask;
3824 ggw.BottomExecutionMask = 0xffffffff;
3825 }
3826
3827 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_STATE_FLUSH), msf);
3828 }
3829
3830 #define GPGPU_DISPATCHDIMX 0x2500
3831 #define GPGPU_DISPATCHDIMY 0x2504
3832 #define GPGPU_DISPATCHDIMZ 0x2508
3833
3834 void genX(CmdDispatchIndirect)(
3835 VkCommandBuffer commandBuffer,
3836 VkBuffer _buffer,
3837 VkDeviceSize offset)
3838 {
3839 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3840 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
3841 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
3842 const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
3843 struct anv_address addr = anv_address_add(buffer->address, offset);
3844 struct anv_batch *batch = &cmd_buffer->batch;
3845
3846 anv_cmd_buffer_push_base_group_id(cmd_buffer, 0, 0, 0);
3847
3848 #if GEN_GEN == 7
3849 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3850 * indirect dispatch registers to be written.
3851 */
3852 if (verify_cmd_parser(cmd_buffer->device, 5,
3853 "vkCmdDispatchIndirect") != VK_SUCCESS)
3854 return;
3855 #endif
3856
3857 if (prog_data->uses_num_work_groups)
3858 cmd_buffer->state.compute.num_workgroups = addr;
3859
3860 genX(cmd_buffer_flush_compute_state)(cmd_buffer);
3861
3862 struct gen_mi_builder b;
3863 gen_mi_builder_init(&b, &cmd_buffer->batch);
3864
3865 struct gen_mi_value size_x = gen_mi_mem32(anv_address_add(addr, 0));
3866 struct gen_mi_value size_y = gen_mi_mem32(anv_address_add(addr, 4));
3867 struct gen_mi_value size_z = gen_mi_mem32(anv_address_add(addr, 8));
3868
3869 gen_mi_store(&b, gen_mi_reg32(GPGPU_DISPATCHDIMX), size_x);
3870 gen_mi_store(&b, gen_mi_reg32(GPGPU_DISPATCHDIMY), size_y);
3871 gen_mi_store(&b, gen_mi_reg32(GPGPU_DISPATCHDIMZ), size_z);
3872
3873 #if GEN_GEN <= 7
3874 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3875 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), size_x);
3876 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
3877 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
3878 mip.LoadOperation = LOAD_LOAD;
3879 mip.CombineOperation = COMBINE_SET;
3880 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3881 }
3882
3883 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3884 gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC0), size_y);
3885 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
3886 mip.LoadOperation = LOAD_LOAD;
3887 mip.CombineOperation = COMBINE_OR;
3888 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3889 }
3890
3891 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3892 gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC0), size_z);
3893 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
3894 mip.LoadOperation = LOAD_LOAD;
3895 mip.CombineOperation = COMBINE_OR;
3896 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3897 }
3898
3899 /* predicate = !predicate; */
3900 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
3901 mip.LoadOperation = LOAD_LOADINV;
3902 mip.CombineOperation = COMBINE_OR;
3903 mip.CompareOperation = COMPARE_FALSE;
3904 }
3905
3906 #if GEN_IS_HASWELL
3907 if (cmd_buffer->state.conditional_render_enabled) {
3908 /* predicate &= !(conditional_rendering_predicate == 0); */
3909 gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC0),
3910 gen_mi_reg32(ANV_PREDICATE_RESULT_REG));
3911 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
3912 mip.LoadOperation = LOAD_LOADINV;
3913 mip.CombineOperation = COMBINE_AND;
3914 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3915 }
3916 }
3917 #endif
3918
3919 #else /* GEN_GEN > 7 */
3920 if (cmd_buffer->state.conditional_render_enabled)
3921 genX(cmd_emit_conditional_render_predicate)(cmd_buffer);
3922 #endif
3923
3924 anv_batch_emit(batch, GENX(GPGPU_WALKER), ggw) {
3925 ggw.IndirectParameterEnable = true;
3926 ggw.PredicateEnable = GEN_GEN <= 7 ||
3927 cmd_buffer->state.conditional_render_enabled;
3928 ggw.SIMDSize = prog_data->simd_size / 16;
3929 ggw.ThreadDepthCounterMaximum = 0;
3930 ggw.ThreadHeightCounterMaximum = 0;
3931 ggw.ThreadWidthCounterMaximum = prog_data->threads - 1;
3932 ggw.RightExecutionMask = pipeline->cs_right_mask;
3933 ggw.BottomExecutionMask = 0xffffffff;
3934 }
3935
3936 anv_batch_emit(batch, GENX(MEDIA_STATE_FLUSH), msf);
3937 }
3938
3939 static void
3940 genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
3941 uint32_t pipeline)
3942 {
3943 UNUSED const struct gen_device_info *devinfo = &cmd_buffer->device->info;
3944
3945 if (cmd_buffer->state.current_pipeline == pipeline)
3946 return;
3947
3948 #if GEN_GEN >= 8 && GEN_GEN < 10
3949 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3950 *
3951 * Software must clear the COLOR_CALC_STATE Valid field in
3952 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3953 * with Pipeline Select set to GPGPU.
3954 *
3955 * The internal hardware docs recommend the same workaround for Gen9
3956 * hardware too.
3957 */
3958 if (pipeline == GPGPU)
3959 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
3960 #endif
3961
3962 #if GEN_GEN == 9
3963 if (pipeline == _3D) {
3964 /* There is a mid-object preemption workaround which requires you to
3965 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
3966 * even without preemption, we have issues with geometry flickering when
3967 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
3968 * really know why.
3969 */
3970 const uint32_t subslices =
3971 MAX2(cmd_buffer->device->instance->physicalDevice.subslice_total, 1);
3972 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_VFE_STATE), vfe) {
3973 vfe.MaximumNumberofThreads =
3974 devinfo->max_cs_threads * subslices - 1;
3975 vfe.NumberofURBEntries = 2;
3976 vfe.URBEntryAllocationSize = 2;
3977 }
3978 }
3979 #endif
3980
3981 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3982 * PIPELINE_SELECT [DevBWR+]":
3983 *
3984 * Project: DEVSNB+
3985 *
3986 * Software must ensure all the write caches are flushed through a
3987 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3988 * command to invalidate read only caches prior to programming
3989 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3990 */
3991 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
3992 pc.RenderTargetCacheFlushEnable = true;
3993 pc.DepthCacheFlushEnable = true;
3994 pc.DCFlushEnable = true;
3995 pc.PostSyncOperation = NoWrite;
3996 pc.CommandStreamerStallEnable = true;
3997 #if GEN_GEN >= 12
3998 pc.TileCacheFlushEnable = true;
3999 #endif
4000 }
4001
4002 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
4003 pc.TextureCacheInvalidationEnable = true;
4004 pc.ConstantCacheInvalidationEnable = true;
4005 pc.StateCacheInvalidationEnable = true;
4006 pc.InstructionCacheInvalidateEnable = true;
4007 pc.PostSyncOperation = NoWrite;
4008 #if GEN_GEN >= 12
4009 pc.TileCacheFlushEnable = true;
4010 #endif
4011 }
4012
4013 anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {
4014 #if GEN_GEN >= 9
4015 ps.MaskBits = 3;
4016 #endif
4017 ps.PipelineSelection = pipeline;
4018 }
4019
4020 #if GEN_GEN == 9
4021 if (devinfo->is_geminilake) {
4022 /* Project: DevGLK
4023 *
4024 * "This chicken bit works around a hardware issue with barrier logic
4025 * encountered when switching between GPGPU and 3D pipelines. To
4026 * workaround the issue, this mode bit should be set after a pipeline
4027 * is selected."
4028 */
4029 uint32_t scec;
4030 anv_pack_struct(&scec, GENX(SLICE_COMMON_ECO_CHICKEN1),
4031 .GLKBarrierMode =
4032 pipeline == GPGPU ? GLK_BARRIER_MODE_GPGPU
4033 : GLK_BARRIER_MODE_3D_HULL,
4034 .GLKBarrierModeMask = 1);
4035 emit_lri(&cmd_buffer->batch, GENX(SLICE_COMMON_ECO_CHICKEN1_num), scec);
4036 }
4037 #endif
4038
4039 cmd_buffer->state.current_pipeline = pipeline;
4040 }
4041
4042 void
4043 genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer)
4044 {
4045 genX(flush_pipeline_select)(cmd_buffer, _3D);
4046 }
4047
4048 void
4049 genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer)
4050 {
4051 genX(flush_pipeline_select)(cmd_buffer, GPGPU);
4052 }
4053
4054 void
4055 genX(cmd_buffer_emit_gen7_depth_flush)(struct anv_cmd_buffer *cmd_buffer)
4056 {
4057 if (GEN_GEN >= 8)
4058 return;
4059
4060 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
4061 *
4062 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
4063 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
4064 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
4065 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
4066 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
4067 * Depth Flush Bit set, followed by another pipelined depth stall
4068 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
4069 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
4070 * via a preceding MI_FLUSH)."
4071 */
4072 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
4073 pipe.DepthStallEnable = true;
4074 }
4075 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
4076 pipe.DepthCacheFlushEnable = true;
4077 #if GEN_GEN >= 12
4078 pipe.TileCacheFlushEnable = true;
4079 #endif
4080 }
4081 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
4082 pipe.DepthStallEnable = true;
4083 }
4084 }
4085
4086 /**
4087 * Update the pixel hashing modes that determine the balancing of PS threads
4088 * across subslices and slices.
4089 *
4090 * \param width Width bound of the rendering area (already scaled down if \p
4091 * scale is greater than 1).
4092 * \param height Height bound of the rendering area (already scaled down if \p
4093 * scale is greater than 1).
4094 * \param scale The number of framebuffer samples that could potentially be
4095 * affected by an individual channel of the PS thread. This is
4096 * typically one for single-sampled rendering, but for operations
4097 * like CCS resolves and fast clears a single PS invocation may
4098 * update a huge number of pixels, in which case a finer
4099 * balancing is desirable in order to maximally utilize the
4100 * bandwidth available. UINT_MAX can be used as shorthand for
4101 * "finest hashing mode available".
4102 */
4103 void
4104 genX(cmd_buffer_emit_hashing_mode)(struct anv_cmd_buffer *cmd_buffer,
4105 unsigned width, unsigned height,
4106 unsigned scale)
4107 {
4108 #if GEN_GEN == 9
4109 const struct gen_device_info *devinfo = &cmd_buffer->device->info;
4110 const unsigned slice_hashing[] = {
4111 /* Because all Gen9 platforms with more than one slice require
4112 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4113 * block is guaranteed to suffer from substantial imbalance, with one
4114 * subslice receiving twice as much work as the other two in the
4115 * slice.
4116 *
4117 * The performance impact of that would be particularly severe when
4118 * three-way hashing is also in use for slice balancing (which is the
4119 * case for all Gen9 GT4 platforms), because one of the slices
4120 * receives one every three 16x16 blocks in either direction, which
4121 * is roughly the periodicity of the underlying subslice imbalance
4122 * pattern ("roughly" because in reality the hardware's
4123 * implementation of three-way hashing doesn't do exact modulo 3
4124 * arithmetic, which somewhat decreases the magnitude of this effect
4125 * in practice). This leads to a systematic subslice imbalance
4126 * within that slice regardless of the size of the primitive. The
4127 * 32x32 hashing mode guarantees that the subslice imbalance within a
4128 * single slice hashing block is minimal, largely eliminating this
4129 * effect.
4130 */
4131 _32x32,
4132 /* Finest slice hashing mode available. */
4133 NORMAL
4134 };
4135 const unsigned subslice_hashing[] = {
4136 /* 16x16 would provide a slight cache locality benefit especially
4137 * visible in the sampler L1 cache efficiency of low-bandwidth
4138 * non-LLC platforms, but it comes at the cost of greater subslice
4139 * imbalance for primitives of dimensions approximately intermediate
4140 * between 16x4 and 16x16.
4141 */
4142 _16x4,
4143 /* Finest subslice hashing mode available. */
4144 _8x4
4145 };
4146 /* Dimensions of the smallest hashing block of a given hashing mode. If
4147 * the rendering area is smaller than this there can't possibly be any
4148 * benefit from switching to this mode, so we optimize out the
4149 * transition.
4150 */
4151 const unsigned min_size[][2] = {
4152 { 16, 4 },
4153 { 8, 4 }
4154 };
4155 const unsigned idx = scale > 1;
4156
4157 if (cmd_buffer->state.current_hash_scale != scale &&
4158 (width > min_size[idx][0] || height > min_size[idx][1])) {
4159 uint32_t gt_mode;
4160
4161 anv_pack_struct(&gt_mode, GENX(GT_MODE),
4162 .SliceHashing = (devinfo->num_slices > 1 ? slice_hashing[idx] : 0),
4163 .SliceHashingMask = (devinfo->num_slices > 1 ? -1 : 0),
4164 .SubsliceHashing = subslice_hashing[idx],
4165 .SubsliceHashingMask = -1);
4166
4167 cmd_buffer->state.pending_pipe_bits |=
4168 ANV_PIPE_CS_STALL_BIT | ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
4169 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
4170
4171 emit_lri(&cmd_buffer->batch, GENX(GT_MODE_num), gt_mode);
4172
4173 cmd_buffer->state.current_hash_scale = scale;
4174 }
4175 #endif
4176 }
4177
4178 static void
4179 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
4180 {
4181 struct anv_device *device = cmd_buffer->device;
4182 const struct anv_image_view *iview =
4183 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
4184 const struct anv_image *image = iview ? iview->image : NULL;
4185
4186 /* FIXME: Width and Height are wrong */
4187
4188 genX(cmd_buffer_emit_gen7_depth_flush)(cmd_buffer);
4189
4190 uint32_t *dw = anv_batch_emit_dwords(&cmd_buffer->batch,
4191 device->isl_dev.ds.size / 4);
4192 if (dw == NULL)
4193 return;
4194
4195 struct isl_depth_stencil_hiz_emit_info info = { };
4196
4197 if (iview)
4198 info.view = &iview->planes[0].isl;
4199
4200 if (image && (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
4201 uint32_t depth_plane =
4202 anv_image_aspect_to_plane(image->aspects, VK_IMAGE_ASPECT_DEPTH_BIT);
4203 const struct anv_surface *surface = &image->planes[depth_plane].surface;
4204
4205 info.depth_surf = &surface->isl;
4206
4207 info.depth_address =
4208 anv_batch_emit_reloc(&cmd_buffer->batch,
4209 dw + device->isl_dev.ds.depth_offset / 4,
4210 image->planes[depth_plane].address.bo,
4211 image->planes[depth_plane].address.offset +
4212 surface->offset);
4213 info.mocs =
4214 anv_mocs_for_bo(device, image->planes[depth_plane].address.bo);
4215
4216 const uint32_t ds =
4217 cmd_buffer->state.subpass->depth_stencil_attachment->attachment;
4218 info.hiz_usage = cmd_buffer->state.attachments[ds].aux_usage;
4219 if (info.hiz_usage == ISL_AUX_USAGE_HIZ) {
4220 info.hiz_surf = &image->planes[depth_plane].aux_surface.isl;
4221
4222 info.hiz_address =
4223 anv_batch_emit_reloc(&cmd_buffer->batch,
4224 dw + device->isl_dev.ds.hiz_offset / 4,
4225 image->planes[depth_plane].address.bo,
4226 image->planes[depth_plane].address.offset +
4227 image->planes[depth_plane].aux_surface.offset);
4228
4229 info.depth_clear_value = ANV_HZ_FC_VAL;
4230 }
4231 }
4232
4233 if (image && (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT)) {
4234 uint32_t stencil_plane =
4235 anv_image_aspect_to_plane(image->aspects, VK_IMAGE_ASPECT_STENCIL_BIT);
4236 const struct anv_surface *surface = &image->planes[stencil_plane].surface;
4237
4238 info.stencil_surf = &surface->isl;
4239
4240 info.stencil_address =
4241 anv_batch_emit_reloc(&cmd_buffer->batch,
4242 dw + device->isl_dev.ds.stencil_offset / 4,
4243 image->planes[stencil_plane].address.bo,
4244 image->planes[stencil_plane].address.offset +
4245 surface->offset);
4246 info.mocs =
4247 anv_mocs_for_bo(device, image->planes[stencil_plane].address.bo);
4248 }
4249
4250 isl_emit_depth_stencil_hiz_s(&device->isl_dev, dw, &info);
4251
4252 if (GEN_GEN >= 12) {
4253 /* GEN:BUG:1408224581
4254 *
4255 * Workaround: Gen12LP Astep only An additional pipe control with
4256 * post-sync = store dword operation would be required.( w/a is to
4257 * have an additional pipe control after the stencil state whenever
4258 * the surface state bits of this state is changing).
4259 */
4260 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
4261 pc.PostSyncOperation = WriteImmediateData;
4262 pc.Address =
4263 (struct anv_address) { cmd_buffer->device->workaround_bo, 0 };
4264 }
4265 }
4266 cmd_buffer->state.hiz_enabled = info.hiz_usage == ISL_AUX_USAGE_HIZ;
4267 }
4268
4269 /**
4270 * This ANDs the view mask of the current subpass with the pending clear
4271 * views in the attachment to get the mask of views active in the subpass
4272 * that still need to be cleared.
4273 */
4274 static inline uint32_t
4275 get_multiview_subpass_clear_mask(const struct anv_cmd_state *cmd_state,
4276 const struct anv_attachment_state *att_state)
4277 {
4278 return cmd_state->subpass->view_mask & att_state->pending_clear_views;
4279 }
4280
4281 static inline bool
4282 do_first_layer_clear(const struct anv_cmd_state *cmd_state,
4283 const struct anv_attachment_state *att_state)
4284 {
4285 if (!cmd_state->subpass->view_mask)
4286 return true;
4287
4288 uint32_t pending_clear_mask =
4289 get_multiview_subpass_clear_mask(cmd_state, att_state);
4290
4291 return pending_clear_mask & 1;
4292 }
4293
4294 static inline bool
4295 current_subpass_is_last_for_attachment(const struct anv_cmd_state *cmd_state,
4296 uint32_t att_idx)
4297 {
4298 const uint32_t last_subpass_idx =
4299 cmd_state->pass->attachments[att_idx].last_subpass_idx;
4300 const struct anv_subpass *last_subpass =
4301 &cmd_state->pass->subpasses[last_subpass_idx];
4302 return last_subpass == cmd_state->subpass;
4303 }
4304
4305 static void
4306 cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
4307 uint32_t subpass_id)
4308 {
4309 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
4310 struct anv_subpass *subpass = &cmd_state->pass->subpasses[subpass_id];
4311 cmd_state->subpass = subpass;
4312
4313 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
4314
4315 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4316 * different views. If the client asks for instancing, we need to use the
4317 * Instance Data Step Rate to ensure that we repeat the client's
4318 * per-instance data once for each view. Since this bit is in
4319 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4320 * of each subpass.
4321 */
4322 if (GEN_GEN == 7)
4323 cmd_buffer->state.gfx.vb_dirty |= ~0;
4324
4325 /* It is possible to start a render pass with an old pipeline. Because the
4326 * render pass and subpass index are both baked into the pipeline, this is
4327 * highly unlikely. In order to do so, it requires that you have a render
4328 * pass with a single subpass and that you use that render pass twice
4329 * back-to-back and use the same pipeline at the start of the second render
4330 * pass as at the end of the first. In order to avoid unpredictable issues
4331 * with this edge case, we just dirty the pipeline at the start of every
4332 * subpass.
4333 */
4334 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
4335
4336 /* Accumulate any subpass flushes that need to happen before the subpass */
4337 cmd_buffer->state.pending_pipe_bits |=
4338 cmd_buffer->state.pass->subpass_flushes[subpass_id];
4339
4340 VkRect2D render_area = cmd_buffer->state.render_area;
4341 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
4342
4343 bool is_multiview = subpass->view_mask != 0;
4344
4345 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4346 const uint32_t a = subpass->attachments[i].attachment;
4347 if (a == VK_ATTACHMENT_UNUSED)
4348 continue;
4349
4350 assert(a < cmd_state->pass->attachment_count);
4351 struct anv_attachment_state *att_state = &cmd_state->attachments[a];
4352
4353 struct anv_image_view *iview = cmd_state->attachments[a].image_view;
4354 const struct anv_image *image = iview->image;
4355
4356 /* A resolve is necessary before use as an input attachment if the clear
4357 * color or auxiliary buffer usage isn't supported by the sampler.
4358 */
4359 const bool input_needs_resolve =
4360 (att_state->fast_clear && !att_state->clear_color_is_zero_one) ||
4361 att_state->input_aux_usage != att_state->aux_usage;
4362
4363 VkImageLayout target_layout, target_stencil_layout;
4364 if (iview->aspect_mask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV &&
4365 !input_needs_resolve) {
4366 /* Layout transitions before the final only help to enable sampling
4367 * as an input attachment. If the input attachment supports sampling
4368 * using the auxiliary surface, we can skip such transitions by
4369 * making the target layout one that is CCS-aware.
4370 */
4371 target_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
4372 } else {
4373 target_layout = subpass->attachments[i].layout;
4374 target_stencil_layout = subpass->attachments[i].stencil_layout;
4375 }
4376
4377 uint32_t base_layer, layer_count;
4378 if (image->type == VK_IMAGE_TYPE_3D) {
4379 base_layer = 0;
4380 layer_count = anv_minify(iview->image->extent.depth,
4381 iview->planes[0].isl.base_level);
4382 } else {
4383 base_layer = iview->planes[0].isl.base_array_layer;
4384 layer_count = fb->layers;
4385 }
4386
4387 if (image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
4388 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
4389 transition_color_buffer(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
4390 iview->planes[0].isl.base_level, 1,
4391 base_layer, layer_count,
4392 att_state->current_layout, target_layout);
4393 }
4394
4395 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
4396 transition_depth_buffer(cmd_buffer, image,
4397 att_state->current_layout, target_layout);
4398 att_state->aux_usage =
4399 anv_layout_to_aux_usage(&cmd_buffer->device->info, image,
4400 VK_IMAGE_ASPECT_DEPTH_BIT, target_layout);
4401 }
4402
4403 if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
4404 transition_stencil_buffer(cmd_buffer, image,
4405 iview->planes[0].isl.base_level, 1,
4406 base_layer, layer_count,
4407 att_state->current_stencil_layout,
4408 target_stencil_layout);
4409 }
4410 att_state->current_layout = target_layout;
4411 att_state->current_stencil_layout = target_stencil_layout;
4412
4413 if (att_state->pending_clear_aspects & VK_IMAGE_ASPECT_COLOR_BIT) {
4414 assert(att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
4415
4416 /* Multi-planar images are not supported as attachments */
4417 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
4418 assert(image->n_planes == 1);
4419
4420 uint32_t base_clear_layer = iview->planes[0].isl.base_array_layer;
4421 uint32_t clear_layer_count = fb->layers;
4422
4423 if (att_state->fast_clear &&
4424 do_first_layer_clear(cmd_state, att_state)) {
4425 /* We only support fast-clears on the first layer */
4426 assert(iview->planes[0].isl.base_level == 0);
4427 assert(iview->planes[0].isl.base_array_layer == 0);
4428
4429 union isl_color_value clear_color = {};
4430 anv_clear_color_from_att_state(&clear_color, att_state, iview);
4431 if (iview->image->samples == 1) {
4432 anv_image_ccs_op(cmd_buffer, image,
4433 iview->planes[0].isl.format,
4434 VK_IMAGE_ASPECT_COLOR_BIT,
4435 0, 0, 1, ISL_AUX_OP_FAST_CLEAR,
4436 &clear_color,
4437 false);
4438 } else {
4439 anv_image_mcs_op(cmd_buffer, image,
4440 iview->planes[0].isl.format,
4441 VK_IMAGE_ASPECT_COLOR_BIT,
4442 0, 1, ISL_AUX_OP_FAST_CLEAR,
4443 &clear_color,
4444 false);
4445 }
4446 base_clear_layer++;
4447 clear_layer_count--;
4448 if (is_multiview)
4449 att_state->pending_clear_views &= ~1;
4450
4451 if (att_state->clear_color_is_zero) {
4452 /* This image has the auxiliary buffer enabled. We can mark the
4453 * subresource as not needing a resolve because the clear color
4454 * will match what's in every RENDER_SURFACE_STATE object when
4455 * it's being used for sampling.
4456 */
4457 set_image_fast_clear_state(cmd_buffer, iview->image,
4458 VK_IMAGE_ASPECT_COLOR_BIT,
4459 ANV_FAST_CLEAR_DEFAULT_VALUE);
4460 } else {
4461 set_image_fast_clear_state(cmd_buffer, iview->image,
4462 VK_IMAGE_ASPECT_COLOR_BIT,
4463 ANV_FAST_CLEAR_ANY);
4464 }
4465 }
4466
4467 /* From the VkFramebufferCreateInfo spec:
4468 *
4469 * "If the render pass uses multiview, then layers must be one and each
4470 * attachment requires a number of layers that is greater than the
4471 * maximum bit index set in the view mask in the subpasses in which it
4472 * is used."
4473 *
4474 * So if multiview is active we ignore the number of layers in the
4475 * framebuffer and instead we honor the view mask from the subpass.
4476 */
4477 if (is_multiview) {
4478 assert(image->n_planes == 1);
4479 uint32_t pending_clear_mask =
4480 get_multiview_subpass_clear_mask(cmd_state, att_state);
4481
4482 uint32_t layer_idx;
4483 for_each_bit(layer_idx, pending_clear_mask) {
4484 uint32_t layer =
4485 iview->planes[0].isl.base_array_layer + layer_idx;
4486
4487 anv_image_clear_color(cmd_buffer, image,
4488 VK_IMAGE_ASPECT_COLOR_BIT,
4489 att_state->aux_usage,
4490 iview->planes[0].isl.format,
4491 iview->planes[0].isl.swizzle,
4492 iview->planes[0].isl.base_level,
4493 layer, 1,
4494 render_area,
4495 vk_to_isl_color(att_state->clear_value.color));
4496 }
4497
4498 att_state->pending_clear_views &= ~pending_clear_mask;
4499 } else if (clear_layer_count > 0) {
4500 assert(image->n_planes == 1);
4501 anv_image_clear_color(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
4502 att_state->aux_usage,
4503 iview->planes[0].isl.format,
4504 iview->planes[0].isl.swizzle,
4505 iview->planes[0].isl.base_level,
4506 base_clear_layer, clear_layer_count,
4507 render_area,
4508 vk_to_isl_color(att_state->clear_value.color));
4509 }
4510 } else if (att_state->pending_clear_aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
4511 VK_IMAGE_ASPECT_STENCIL_BIT)) {
4512 if (att_state->fast_clear && !is_multiview) {
4513 /* We currently only support HiZ for single-layer images */
4514 if (att_state->pending_clear_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
4515 assert(iview->image->planes[0].aux_usage == ISL_AUX_USAGE_HIZ);
4516 assert(iview->planes[0].isl.base_level == 0);
4517 assert(iview->planes[0].isl.base_array_layer == 0);
4518 assert(fb->layers == 1);
4519 }
4520
4521 anv_image_hiz_clear(cmd_buffer, image,
4522 att_state->pending_clear_aspects,
4523 iview->planes[0].isl.base_level,
4524 iview->planes[0].isl.base_array_layer,
4525 fb->layers, render_area,
4526 att_state->clear_value.depthStencil.stencil);
4527 } else if (is_multiview) {
4528 uint32_t pending_clear_mask =
4529 get_multiview_subpass_clear_mask(cmd_state, att_state);
4530
4531 uint32_t layer_idx;
4532 for_each_bit(layer_idx, pending_clear_mask) {
4533 uint32_t layer =
4534 iview->planes[0].isl.base_array_layer + layer_idx;
4535
4536 anv_image_clear_depth_stencil(cmd_buffer, image,
4537 att_state->pending_clear_aspects,
4538 att_state->aux_usage,
4539 iview->planes[0].isl.base_level,
4540 layer, 1,
4541 render_area,
4542 att_state->clear_value.depthStencil.depth,
4543 att_state->clear_value.depthStencil.stencil);
4544 }
4545
4546 att_state->pending_clear_views &= ~pending_clear_mask;
4547 } else {
4548 anv_image_clear_depth_stencil(cmd_buffer, image,
4549 att_state->pending_clear_aspects,
4550 att_state->aux_usage,
4551 iview->planes[0].isl.base_level,
4552 iview->planes[0].isl.base_array_layer,
4553 fb->layers, render_area,
4554 att_state->clear_value.depthStencil.depth,
4555 att_state->clear_value.depthStencil.stencil);
4556 }
4557 } else {
4558 assert(att_state->pending_clear_aspects == 0);
4559 }
4560
4561 if (GEN_GEN < 10 &&
4562 (att_state->pending_load_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) &&
4563 image->planes[0].aux_surface.isl.size_B > 0 &&
4564 iview->planes[0].isl.base_level == 0 &&
4565 iview->planes[0].isl.base_array_layer == 0) {
4566 if (att_state->aux_usage != ISL_AUX_USAGE_NONE) {
4567 genX(copy_fast_clear_dwords)(cmd_buffer, att_state->color.state,
4568 image, VK_IMAGE_ASPECT_COLOR_BIT,
4569 false /* copy to ss */);
4570 }
4571
4572 if (need_input_attachment_state(&cmd_state->pass->attachments[a]) &&
4573 att_state->input_aux_usage != ISL_AUX_USAGE_NONE) {
4574 genX(copy_fast_clear_dwords)(cmd_buffer, att_state->input.state,
4575 image, VK_IMAGE_ASPECT_COLOR_BIT,
4576 false /* copy to ss */);
4577 }
4578 }
4579
4580 if (subpass->attachments[i].usage ==
4581 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) {
4582 /* We assume that if we're starting a subpass, we're going to do some
4583 * rendering so we may end up with compressed data.
4584 */
4585 genX(cmd_buffer_mark_image_written)(cmd_buffer, iview->image,
4586 VK_IMAGE_ASPECT_COLOR_BIT,
4587 att_state->aux_usage,
4588 iview->planes[0].isl.base_level,
4589 iview->planes[0].isl.base_array_layer,
4590 fb->layers);
4591 } else if (subpass->attachments[i].usage ==
4592 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT) {
4593 /* We may be writing depth or stencil so we need to mark the surface.
4594 * Unfortunately, there's no way to know at this point whether the
4595 * depth or stencil tests used will actually write to the surface.
4596 *
4597 * Even though stencil may be plane 1, it always shares a base_level
4598 * with depth.
4599 */
4600 const struct isl_view *ds_view = &iview->planes[0].isl;
4601 if (iview->aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) {
4602 genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
4603 VK_IMAGE_ASPECT_DEPTH_BIT,
4604 att_state->aux_usage,
4605 ds_view->base_level,
4606 ds_view->base_array_layer,
4607 fb->layers);
4608 }
4609 if (iview->aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) {
4610 /* Even though stencil may be plane 1, it always shares a
4611 * base_level with depth.
4612 */
4613 genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
4614 VK_IMAGE_ASPECT_STENCIL_BIT,
4615 ISL_AUX_USAGE_NONE,
4616 ds_view->base_level,
4617 ds_view->base_array_layer,
4618 fb->layers);
4619 }
4620 }
4621
4622 /* If multiview is enabled, then we are only done clearing when we no
4623 * longer have pending layers to clear, or when we have processed the
4624 * last subpass that uses this attachment.
4625 */
4626 if (!is_multiview ||
4627 att_state->pending_clear_views == 0 ||
4628 current_subpass_is_last_for_attachment(cmd_state, a)) {
4629 att_state->pending_clear_aspects = 0;
4630 }
4631
4632 att_state->pending_load_aspects = 0;
4633 }
4634
4635 cmd_buffer_emit_depth_stencil(cmd_buffer);
4636
4637 #if GEN_GEN >= 11
4638 /* The PIPE_CONTROL command description says:
4639 *
4640 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
4641 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
4642 * Target Cache Flush by enabling this bit. When render target flush
4643 * is set due to new association of BTI, PS Scoreboard Stall bit must
4644 * be set in this packet."
4645 */
4646 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
4647 pc.RenderTargetCacheFlushEnable = true;
4648 pc.StallAtPixelScoreboard = true;
4649 #if GEN_GEN >= 12
4650 pc.TileCacheFlushEnable = true;
4651 #endif
4652 }
4653 #endif
4654 }
4655
4656 static enum blorp_filter
4657 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode)
4658 {
4659 switch (vk_mode) {
4660 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
4661 return BLORP_FILTER_SAMPLE_0;
4662 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
4663 return BLORP_FILTER_AVERAGE;
4664 case VK_RESOLVE_MODE_MIN_BIT_KHR:
4665 return BLORP_FILTER_MIN_SAMPLE;
4666 case VK_RESOLVE_MODE_MAX_BIT_KHR:
4667 return BLORP_FILTER_MAX_SAMPLE;
4668 default:
4669 return BLORP_FILTER_NONE;
4670 }
4671 }
4672
4673 static void
4674 cmd_buffer_end_subpass(struct anv_cmd_buffer *cmd_buffer)
4675 {
4676 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
4677 struct anv_subpass *subpass = cmd_state->subpass;
4678 uint32_t subpass_id = anv_get_subpass_id(&cmd_buffer->state);
4679 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
4680
4681 if (subpass->has_color_resolve) {
4682 /* We are about to do some MSAA resolves. We need to flush so that the
4683 * result of writes to the MSAA color attachments show up in the sampler
4684 * when we blit to the single-sampled resolve target.
4685 */
4686 cmd_buffer->state.pending_pipe_bits |=
4687 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
4688 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
4689
4690 for (uint32_t i = 0; i < subpass->color_count; ++i) {
4691 uint32_t src_att = subpass->color_attachments[i].attachment;
4692 uint32_t dst_att = subpass->resolve_attachments[i].attachment;
4693
4694 if (dst_att == VK_ATTACHMENT_UNUSED)
4695 continue;
4696
4697 assert(src_att < cmd_buffer->state.pass->attachment_count);
4698 assert(dst_att < cmd_buffer->state.pass->attachment_count);
4699
4700 if (cmd_buffer->state.attachments[dst_att].pending_clear_aspects) {
4701 /* From the Vulkan 1.0 spec:
4702 *
4703 * If the first use of an attachment in a render pass is as a
4704 * resolve attachment, then the loadOp is effectively ignored
4705 * as the resolve is guaranteed to overwrite all pixels in the
4706 * render area.
4707 */
4708 cmd_buffer->state.attachments[dst_att].pending_clear_aspects = 0;
4709 }
4710
4711 struct anv_image_view *src_iview = cmd_state->attachments[src_att].image_view;
4712 struct anv_image_view *dst_iview = cmd_state->attachments[dst_att].image_view;
4713
4714 const VkRect2D render_area = cmd_buffer->state.render_area;
4715
4716 enum isl_aux_usage src_aux_usage =
4717 cmd_buffer->state.attachments[src_att].aux_usage;
4718 enum isl_aux_usage dst_aux_usage =
4719 cmd_buffer->state.attachments[dst_att].aux_usage;
4720
4721 assert(src_iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT &&
4722 dst_iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT);
4723
4724 anv_image_msaa_resolve(cmd_buffer,
4725 src_iview->image, src_aux_usage,
4726 src_iview->planes[0].isl.base_level,
4727 src_iview->planes[0].isl.base_array_layer,
4728 dst_iview->image, dst_aux_usage,
4729 dst_iview->planes[0].isl.base_level,
4730 dst_iview->planes[0].isl.base_array_layer,
4731 VK_IMAGE_ASPECT_COLOR_BIT,
4732 render_area.offset.x, render_area.offset.y,
4733 render_area.offset.x, render_area.offset.y,
4734 render_area.extent.width,
4735 render_area.extent.height,
4736 fb->layers, BLORP_FILTER_NONE);
4737 }
4738 }
4739
4740 if (subpass->ds_resolve_attachment) {
4741 /* We are about to do some MSAA resolves. We need to flush so that the
4742 * result of writes to the MSAA depth attachments show up in the sampler
4743 * when we blit to the single-sampled resolve target.
4744 */
4745 cmd_buffer->state.pending_pipe_bits |=
4746 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
4747 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
4748
4749 uint32_t src_att = subpass->depth_stencil_attachment->attachment;
4750 uint32_t dst_att = subpass->ds_resolve_attachment->attachment;
4751
4752 assert(src_att < cmd_buffer->state.pass->attachment_count);
4753 assert(dst_att < cmd_buffer->state.pass->attachment_count);
4754
4755 if (cmd_buffer->state.attachments[dst_att].pending_clear_aspects) {
4756 /* From the Vulkan 1.0 spec:
4757 *
4758 * If the first use of an attachment in a render pass is as a
4759 * resolve attachment, then the loadOp is effectively ignored
4760 * as the resolve is guaranteed to overwrite all pixels in the
4761 * render area.
4762 */
4763 cmd_buffer->state.attachments[dst_att].pending_clear_aspects = 0;
4764 }
4765
4766 struct anv_image_view *src_iview = cmd_state->attachments[src_att].image_view;
4767 struct anv_image_view *dst_iview = cmd_state->attachments[dst_att].image_view;
4768
4769 const VkRect2D render_area = cmd_buffer->state.render_area;
4770
4771 struct anv_attachment_state *src_state =
4772 &cmd_state->attachments[src_att];
4773 struct anv_attachment_state *dst_state =
4774 &cmd_state->attachments[dst_att];
4775
4776 if ((src_iview->image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
4777 subpass->depth_resolve_mode != VK_RESOLVE_MODE_NONE_KHR) {
4778
4779 /* MSAA resolves sample from the source attachment. Transition the
4780 * depth attachment first to get rid of any HiZ that we may not be
4781 * able to handle.
4782 */
4783 transition_depth_buffer(cmd_buffer, src_iview->image,
4784 src_state->current_layout,
4785 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL);
4786 src_state->aux_usage =
4787 anv_layout_to_aux_usage(&cmd_buffer->device->info, src_iview->image,
4788 VK_IMAGE_ASPECT_DEPTH_BIT,
4789 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL);
4790 src_state->current_layout = VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL;
4791
4792 /* MSAA resolves write to the resolve attachment as if it were any
4793 * other transfer op. Transition the resolve attachment accordingly.
4794 */
4795 VkImageLayout dst_initial_layout = dst_state->current_layout;
4796
4797 /* If our render area is the entire size of the image, we're going to
4798 * blow it all away so we can claim the initial layout is UNDEFINED
4799 * and we'll get a HiZ ambiguate instead of a resolve.
4800 */
4801 if (dst_iview->image->type != VK_IMAGE_TYPE_3D &&
4802 render_area.offset.x == 0 && render_area.offset.y == 0 &&
4803 render_area.extent.width == dst_iview->extent.width &&
4804 render_area.extent.height == dst_iview->extent.height)
4805 dst_initial_layout = VK_IMAGE_LAYOUT_UNDEFINED;
4806
4807 transition_depth_buffer(cmd_buffer, dst_iview->image,
4808 dst_initial_layout,
4809 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
4810 dst_state->aux_usage =
4811 anv_layout_to_aux_usage(&cmd_buffer->device->info, dst_iview->image,
4812 VK_IMAGE_ASPECT_DEPTH_BIT,
4813 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
4814 dst_state->current_layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL;
4815
4816 enum blorp_filter filter =
4817 vk_to_blorp_resolve_mode(subpass->depth_resolve_mode);
4818
4819 anv_image_msaa_resolve(cmd_buffer,
4820 src_iview->image, src_state->aux_usage,
4821 src_iview->planes[0].isl.base_level,
4822 src_iview->planes[0].isl.base_array_layer,
4823 dst_iview->image, dst_state->aux_usage,
4824 dst_iview->planes[0].isl.base_level,
4825 dst_iview->planes[0].isl.base_array_layer,
4826 VK_IMAGE_ASPECT_DEPTH_BIT,
4827 render_area.offset.x, render_area.offset.y,
4828 render_area.offset.x, render_area.offset.y,
4829 render_area.extent.width,
4830 render_area.extent.height,
4831 fb->layers, filter);
4832 }
4833
4834 if ((src_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
4835 subpass->stencil_resolve_mode != VK_RESOLVE_MODE_NONE_KHR) {
4836
4837 src_state->current_stencil_layout = VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL;
4838 dst_state->current_stencil_layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL;
4839
4840 enum isl_aux_usage src_aux_usage = ISL_AUX_USAGE_NONE;
4841 enum isl_aux_usage dst_aux_usage = ISL_AUX_USAGE_NONE;
4842
4843 enum blorp_filter filter =
4844 vk_to_blorp_resolve_mode(subpass->stencil_resolve_mode);
4845
4846 anv_image_msaa_resolve(cmd_buffer,
4847 src_iview->image, src_aux_usage,
4848 src_iview->planes[0].isl.base_level,
4849 src_iview->planes[0].isl.base_array_layer,
4850 dst_iview->image, dst_aux_usage,
4851 dst_iview->planes[0].isl.base_level,
4852 dst_iview->planes[0].isl.base_array_layer,
4853 VK_IMAGE_ASPECT_STENCIL_BIT,
4854 render_area.offset.x, render_area.offset.y,
4855 render_area.offset.x, render_area.offset.y,
4856 render_area.extent.width,
4857 render_area.extent.height,
4858 fb->layers, filter);
4859 }
4860 }
4861
4862 #if GEN_GEN == 7
4863 /* On gen7, we have to store a texturable version of the stencil buffer in
4864 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
4865 * forth at strategic points. Stencil writes are only allowed in following
4866 * layouts:
4867 *
4868 * - VK_IMAGE_LAYOUT_GENERAL
4869 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
4870 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
4871 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
4872 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
4873 *
4874 * For general, we have no nice opportunity to transition so we do the copy
4875 * to the shadow unconditionally at the end of the subpass. For transfer
4876 * destinations, we can update it as part of the transfer op. For the other
4877 * layouts, we delay the copy until a transition into some other layout.
4878 */
4879 if (subpass->depth_stencil_attachment) {
4880 uint32_t a = subpass->depth_stencil_attachment->attachment;
4881 assert(a != VK_ATTACHMENT_UNUSED);
4882
4883 struct anv_attachment_state *att_state = &cmd_state->attachments[a];
4884 struct anv_image_view *iview = cmd_state->attachments[a].image_view;;
4885 const struct anv_image *image = iview->image;
4886
4887 if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
4888 uint32_t plane = anv_image_aspect_to_plane(image->aspects,
4889 VK_IMAGE_ASPECT_STENCIL_BIT);
4890
4891 if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
4892 att_state->current_stencil_layout == VK_IMAGE_LAYOUT_GENERAL) {
4893 assert(image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
4894 anv_image_copy_to_shadow(cmd_buffer, image,
4895 VK_IMAGE_ASPECT_STENCIL_BIT,
4896 iview->planes[plane].isl.base_level, 1,
4897 iview->planes[plane].isl.base_array_layer,
4898 fb->layers);
4899 }
4900 }
4901 }
4902 #endif /* GEN_GEN == 7 */
4903
4904 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4905 const uint32_t a = subpass->attachments[i].attachment;
4906 if (a == VK_ATTACHMENT_UNUSED)
4907 continue;
4908
4909 if (cmd_state->pass->attachments[a].last_subpass_idx != subpass_id)
4910 continue;
4911
4912 assert(a < cmd_state->pass->attachment_count);
4913 struct anv_attachment_state *att_state = &cmd_state->attachments[a];
4914 struct anv_image_view *iview = cmd_state->attachments[a].image_view;
4915 const struct anv_image *image = iview->image;
4916
4917 if ((image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) &&
4918 image->vk_format != iview->vk_format) {
4919 enum anv_fast_clear_type fast_clear_type =
4920 anv_layout_to_fast_clear_type(&cmd_buffer->device->info,
4921 image, VK_IMAGE_ASPECT_COLOR_BIT,
4922 att_state->current_layout);
4923
4924 /* If any clear color was used, flush it down the aux surfaces. If we
4925 * don't do it now using the view's format we might use the clear
4926 * color incorrectly in the following resolves (for example with an
4927 * SRGB view & a UNORM image).
4928 */
4929 if (fast_clear_type != ANV_FAST_CLEAR_NONE) {
4930 anv_perf_warn(cmd_buffer->device->instance, iview,
4931 "Doing a partial resolve to get rid of clear color at the "
4932 "end of a renderpass due to an image/view format mismatch");
4933
4934 uint32_t base_layer, layer_count;
4935 if (image->type == VK_IMAGE_TYPE_3D) {
4936 base_layer = 0;
4937 layer_count = anv_minify(iview->image->extent.depth,
4938 iview->planes[0].isl.base_level);
4939 } else {
4940 base_layer = iview->planes[0].isl.base_array_layer;
4941 layer_count = fb->layers;
4942 }
4943
4944 for (uint32_t a = 0; a < layer_count; a++) {
4945 uint32_t array_layer = base_layer + a;
4946 if (image->samples == 1) {
4947 anv_cmd_predicated_ccs_resolve(cmd_buffer, image,
4948 iview->planes[0].isl.format,
4949 VK_IMAGE_ASPECT_COLOR_BIT,
4950 iview->planes[0].isl.base_level,
4951 array_layer,
4952 ISL_AUX_OP_PARTIAL_RESOLVE,
4953 ANV_FAST_CLEAR_NONE);
4954 } else {
4955 anv_cmd_predicated_mcs_resolve(cmd_buffer, image,
4956 iview->planes[0].isl.format,
4957 VK_IMAGE_ASPECT_COLOR_BIT,
4958 base_layer,
4959 ISL_AUX_OP_PARTIAL_RESOLVE,
4960 ANV_FAST_CLEAR_NONE);
4961 }
4962 }
4963 }
4964 }
4965
4966 /* Transition the image into the final layout for this render pass */
4967 VkImageLayout target_layout =
4968 cmd_state->pass->attachments[a].final_layout;
4969 VkImageLayout target_stencil_layout =
4970 cmd_state->pass->attachments[a].stencil_final_layout;
4971
4972 uint32_t base_layer, layer_count;
4973 if (image->type == VK_IMAGE_TYPE_3D) {
4974 base_layer = 0;
4975 layer_count = anv_minify(iview->image->extent.depth,
4976 iview->planes[0].isl.base_level);
4977 } else {
4978 base_layer = iview->planes[0].isl.base_array_layer;
4979 layer_count = fb->layers;
4980 }
4981
4982 if (image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
4983 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
4984 transition_color_buffer(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
4985 iview->planes[0].isl.base_level, 1,
4986 base_layer, layer_count,
4987 att_state->current_layout, target_layout);
4988 }
4989
4990 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
4991 transition_depth_buffer(cmd_buffer, image,
4992 att_state->current_layout, target_layout);
4993 }
4994
4995 if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
4996 transition_stencil_buffer(cmd_buffer, image,
4997 iview->planes[0].isl.base_level, 1,
4998 base_layer, layer_count,
4999 att_state->current_stencil_layout,
5000 target_stencil_layout);
5001 }
5002 }
5003
5004 /* Accumulate any subpass flushes that need to happen after the subpass.
5005 * Yes, they do get accumulated twice in the NextSubpass case but since
5006 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
5007 * ORing the bits in twice so it's harmless.
5008 */
5009 cmd_buffer->state.pending_pipe_bits |=
5010 cmd_buffer->state.pass->subpass_flushes[subpass_id + 1];
5011 }
5012
5013 void genX(CmdBeginRenderPass)(
5014 VkCommandBuffer commandBuffer,
5015 const VkRenderPassBeginInfo* pRenderPassBegin,
5016 VkSubpassContents contents)
5017 {
5018 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
5019 ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
5020 ANV_FROM_HANDLE(anv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
5021
5022 cmd_buffer->state.framebuffer = framebuffer;
5023 cmd_buffer->state.pass = pass;
5024 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
5025 VkResult result =
5026 genX(cmd_buffer_setup_attachments)(cmd_buffer, pass, pRenderPassBegin);
5027
5028 /* If we failed to setup the attachments we should not try to go further */
5029 if (result != VK_SUCCESS) {
5030 assert(anv_batch_has_error(&cmd_buffer->batch));
5031 return;
5032 }
5033
5034 genX(flush_pipeline_select_3d)(cmd_buffer);
5035
5036 cmd_buffer_begin_subpass(cmd_buffer, 0);
5037 }
5038
5039 void genX(CmdBeginRenderPass2KHR)(
5040 VkCommandBuffer commandBuffer,
5041 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
5042 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
5043 {
5044 genX(CmdBeginRenderPass)(commandBuffer, pRenderPassBeginInfo,
5045 pSubpassBeginInfo->contents);
5046 }
5047
5048 void genX(CmdNextSubpass)(
5049 VkCommandBuffer commandBuffer,
5050 VkSubpassContents contents)
5051 {
5052 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
5053
5054 if (anv_batch_has_error(&cmd_buffer->batch))
5055 return;
5056
5057 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
5058
5059 uint32_t prev_subpass = anv_get_subpass_id(&cmd_buffer->state);
5060 cmd_buffer_end_subpass(cmd_buffer);
5061 cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
5062 }
5063
5064 void genX(CmdNextSubpass2KHR)(
5065 VkCommandBuffer commandBuffer,
5066 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
5067 const VkSubpassEndInfoKHR* pSubpassEndInfo)
5068 {
5069 genX(CmdNextSubpass)(commandBuffer, pSubpassBeginInfo->contents);
5070 }
5071
5072 void genX(CmdEndRenderPass)(
5073 VkCommandBuffer commandBuffer)
5074 {
5075 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
5076
5077 if (anv_batch_has_error(&cmd_buffer->batch))
5078 return;
5079
5080 cmd_buffer_end_subpass(cmd_buffer);
5081
5082 cmd_buffer->state.hiz_enabled = false;
5083
5084 #ifndef NDEBUG
5085 anv_dump_add_attachments(cmd_buffer);
5086 #endif
5087
5088 /* Remove references to render pass specific state. This enables us to
5089 * detect whether or not we're in a renderpass.
5090 */
5091 cmd_buffer->state.framebuffer = NULL;
5092 cmd_buffer->state.pass = NULL;
5093 cmd_buffer->state.subpass = NULL;
5094 }
5095
5096 void genX(CmdEndRenderPass2KHR)(
5097 VkCommandBuffer commandBuffer,
5098 const VkSubpassEndInfoKHR* pSubpassEndInfo)
5099 {
5100 genX(CmdEndRenderPass)(commandBuffer);
5101 }
5102
5103 void
5104 genX(cmd_emit_conditional_render_predicate)(struct anv_cmd_buffer *cmd_buffer)
5105 {
5106 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5107 struct gen_mi_builder b;
5108 gen_mi_builder_init(&b, &cmd_buffer->batch);
5109
5110 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
5111 gen_mi_reg32(ANV_PREDICATE_RESULT_REG));
5112 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
5113
5114 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
5115 mip.LoadOperation = LOAD_LOADINV;
5116 mip.CombineOperation = COMBINE_SET;
5117 mip.CompareOperation = COMPARE_SRCS_EQUAL;
5118 }
5119 #endif
5120 }
5121
5122 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5123 void genX(CmdBeginConditionalRenderingEXT)(
5124 VkCommandBuffer commandBuffer,
5125 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5126 {
5127 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
5128 ANV_FROM_HANDLE(anv_buffer, buffer, pConditionalRenderingBegin->buffer);
5129 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
5130 struct anv_address value_address =
5131 anv_address_add(buffer->address, pConditionalRenderingBegin->offset);
5132
5133 const bool isInverted = pConditionalRenderingBegin->flags &
5134 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT;
5135
5136 cmd_state->conditional_render_enabled = true;
5137
5138 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
5139
5140 struct gen_mi_builder b;
5141 gen_mi_builder_init(&b, &cmd_buffer->batch);
5142
5143 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5144 *
5145 * If the value of the predicate in buffer memory changes
5146 * while conditional rendering is active, the rendering commands
5147 * may be discarded in an implementation-dependent way.
5148 * Some implementations may latch the value of the predicate
5149 * upon beginning conditional rendering while others
5150 * may read it before every rendering command.
5151 *
5152 * So it's perfectly fine to read a value from the buffer once.
5153 */
5154 struct gen_mi_value value = gen_mi_mem32(value_address);
5155
5156 /* Precompute predicate result, it is necessary to support secondary
5157 * command buffers since it is unknown if conditional rendering is
5158 * inverted when populating them.
5159 */
5160 gen_mi_store(&b, gen_mi_reg64(ANV_PREDICATE_RESULT_REG),
5161 isInverted ? gen_mi_uge(&b, gen_mi_imm(0), value) :
5162 gen_mi_ult(&b, gen_mi_imm(0), value));
5163 }
5164
5165 void genX(CmdEndConditionalRenderingEXT)(
5166 VkCommandBuffer commandBuffer)
5167 {
5168 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
5169 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
5170
5171 cmd_state->conditional_render_enabled = false;
5172 }
5173 #endif
5174
5175 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5176 * command streamer for later execution.
5177 */
5178 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5179 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5180 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5181 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5182 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5183 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5184 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5185 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5186 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5187 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5188 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5189 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5190 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5191 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5192 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5193
5194 void genX(CmdSetEvent)(
5195 VkCommandBuffer commandBuffer,
5196 VkEvent _event,
5197 VkPipelineStageFlags stageMask)
5198 {
5199 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
5200 ANV_FROM_HANDLE(anv_event, event, _event);
5201
5202 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
5203 if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
5204 pc.StallAtPixelScoreboard = true;
5205 pc.CommandStreamerStallEnable = true;
5206 }
5207
5208 pc.DestinationAddressType = DAT_PPGTT,
5209 pc.PostSyncOperation = WriteImmediateData,
5210 pc.Address = (struct anv_address) {
5211 cmd_buffer->device->dynamic_state_pool.block_pool.bo,
5212 event->state.offset
5213 };
5214 pc.ImmediateData = VK_EVENT_SET;
5215 }
5216 }
5217
5218 void genX(CmdResetEvent)(
5219 VkCommandBuffer commandBuffer,
5220 VkEvent _event,
5221 VkPipelineStageFlags stageMask)
5222 {
5223 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
5224 ANV_FROM_HANDLE(anv_event, event, _event);
5225
5226 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
5227 if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
5228 pc.StallAtPixelScoreboard = true;
5229 pc.CommandStreamerStallEnable = true;
5230 }
5231
5232 pc.DestinationAddressType = DAT_PPGTT;
5233 pc.PostSyncOperation = WriteImmediateData;
5234 pc.Address = (struct anv_address) {
5235 cmd_buffer->device->dynamic_state_pool.block_pool.bo,
5236 event->state.offset
5237 };
5238 pc.ImmediateData = VK_EVENT_RESET;
5239 }
5240 }
5241
5242 void genX(CmdWaitEvents)(
5243 VkCommandBuffer commandBuffer,
5244 uint32_t eventCount,
5245 const VkEvent* pEvents,
5246 VkPipelineStageFlags srcStageMask,
5247 VkPipelineStageFlags destStageMask,
5248 uint32_t memoryBarrierCount,
5249 const VkMemoryBarrier* pMemoryBarriers,
5250 uint32_t bufferMemoryBarrierCount,
5251 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5252 uint32_t imageMemoryBarrierCount,
5253 const VkImageMemoryBarrier* pImageMemoryBarriers)
5254 {
5255 #if GEN_GEN >= 8
5256 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
5257
5258 for (uint32_t i = 0; i < eventCount; i++) {
5259 ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
5260
5261 anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT), sem) {
5262 sem.WaitMode = PollingMode,
5263 sem.CompareOperation = COMPARE_SAD_EQUAL_SDD,
5264 sem.SemaphoreDataDword = VK_EVENT_SET,
5265 sem.SemaphoreAddress = (struct anv_address) {
5266 cmd_buffer->device->dynamic_state_pool.block_pool.bo,
5267 event->state.offset
5268 };
5269 }
5270 }
5271 #else
5272 anv_finishme("Implement events on gen7");
5273 #endif
5274
5275 genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
5276 false, /* byRegion */
5277 memoryBarrierCount, pMemoryBarriers,
5278 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5279 imageMemoryBarrierCount, pImageMemoryBarriers);
5280 }
5281
5282 VkResult genX(CmdSetPerformanceOverrideINTEL)(
5283 VkCommandBuffer commandBuffer,
5284 const VkPerformanceOverrideInfoINTEL* pOverrideInfo)
5285 {
5286 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
5287
5288 switch (pOverrideInfo->type) {
5289 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL: {
5290 uint32_t dw;
5291
5292 #if GEN_GEN >= 9
5293 anv_pack_struct(&dw, GENX(CS_DEBUG_MODE2),
5294 ._3DRenderingInstructionDisable = pOverrideInfo->enable,
5295 .MediaInstructionDisable = pOverrideInfo->enable,
5296 ._3DRenderingInstructionDisableMask = true,
5297 .MediaInstructionDisableMask = true);
5298 emit_lri(&cmd_buffer->batch, GENX(CS_DEBUG_MODE2_num), dw);
5299 #else
5300 anv_pack_struct(&dw, GENX(INSTPM),
5301 ._3DRenderingInstructionDisable = pOverrideInfo->enable,
5302 .MediaInstructionDisable = pOverrideInfo->enable,
5303 ._3DRenderingInstructionDisableMask = true,
5304 .MediaInstructionDisableMask = true);
5305 emit_lri(&cmd_buffer->batch, GENX(INSTPM_num), dw);
5306 #endif
5307 break;
5308 }
5309
5310 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL:
5311 if (pOverrideInfo->enable) {
5312 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
5313 cmd_buffer->state.pending_pipe_bits |=
5314 ANV_PIPE_FLUSH_BITS |
5315 ANV_PIPE_INVALIDATE_BITS;
5316 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
5317 }
5318 break;
5319
5320 default:
5321 unreachable("Invalid override");
5322 }
5323
5324 return VK_SUCCESS;
5325 }
5326
5327 VkResult genX(CmdSetPerformanceStreamMarkerINTEL)(
5328 VkCommandBuffer commandBuffer,
5329 const VkPerformanceStreamMarkerInfoINTEL* pMarkerInfo)
5330 {
5331 /* TODO: Waiting on the register to write, might depend on generation. */
5332
5333 return VK_SUCCESS;
5334 }