2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
, uint32_t reg
, struct anv_address addr
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= addr
;
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
53 #if GEN_IS_HASWELL || GEN_GEN >= 8
55 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
57 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
58 lrr
.SourceRegisterAddress
= src
;
59 lrr
.DestinationRegisterAddress
= dst
;
65 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
67 struct anv_device
*device
= cmd_buffer
->device
;
69 /* If we are emitting a new state base address we probably need to re-emit
72 cmd_buffer
->state
.descriptors_dirty
|= ~0;
74 /* Emit a render target cache flush.
76 * This isn't documented anywhere in the PRM. However, it seems to be
77 * necessary prior to changing the surface state base adress. Without
78 * this, we get GPU hangs when using multi-level command buffers which
79 * clear depth, reset state base address, and then go render stuff.
81 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
82 pc
.DCFlushEnable
= true;
83 pc
.RenderTargetCacheFlushEnable
= true;
84 pc
.CommandStreamerStallEnable
= true;
87 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
88 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
89 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
90 sba
.GeneralStateBaseAddressModifyEnable
= true;
92 sba
.SurfaceStateBaseAddress
=
93 anv_cmd_buffer_surface_base_address(cmd_buffer
);
94 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
95 sba
.SurfaceStateBaseAddressModifyEnable
= true;
97 sba
.DynamicStateBaseAddress
=
98 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
99 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
100 sba
.DynamicStateBaseAddressModifyEnable
= true;
102 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
103 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
104 sba
.IndirectObjectBaseAddressModifyEnable
= true;
106 sba
.InstructionBaseAddress
=
107 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
108 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
109 sba
.InstructionBaseAddressModifyEnable
= true;
112 /* Broadwell requires that we specify a buffer size for a bunch of
113 * these fields. However, since we will be growing the BO's live, we
114 * just set them all to the maximum.
116 sba
.GeneralStateBufferSize
= 0xfffff;
117 sba
.GeneralStateBufferSizeModifyEnable
= true;
118 sba
.DynamicStateBufferSize
= 0xfffff;
119 sba
.DynamicStateBufferSizeModifyEnable
= true;
120 sba
.IndirectObjectBufferSize
= 0xfffff;
121 sba
.IndirectObjectBufferSizeModifyEnable
= true;
122 sba
.InstructionBufferSize
= 0xfffff;
123 sba
.InstructionBuffersizeModifyEnable
= true;
127 /* After re-setting the surface state base address, we have to do some
128 * cache flusing so that the sampler engine will pick up the new
129 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
130 * Shared Function > 3D Sampler > State > State Caching (page 96):
132 * Coherency with system memory in the state cache, like the texture
133 * cache is handled partially by software. It is expected that the
134 * command stream or shader will issue Cache Flush operation or
135 * Cache_Flush sampler message to ensure that the L1 cache remains
136 * coherent with system memory.
140 * Whenever the value of the Dynamic_State_Base_Addr,
141 * Surface_State_Base_Addr are altered, the L1 state cache must be
142 * invalidated to ensure the new surface or sampler state is fetched
143 * from system memory.
145 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
146 * which, according the PIPE_CONTROL instruction documentation in the
149 * Setting this bit is independent of any other bit in this packet.
150 * This bit controls the invalidation of the L1 and L2 state caches
151 * at the top of the pipe i.e. at the parsing time.
153 * Unfortunately, experimentation seems to indicate that state cache
154 * invalidation through a PIPE_CONTROL does nothing whatsoever in
155 * regards to surface state and binding tables. In stead, it seems that
156 * invalidating the texture cache is what is actually needed.
158 * XXX: As far as we have been able to determine through
159 * experimentation, shows that flush the texture cache appears to be
160 * sufficient. The theory here is that all of the sampling/rendering
161 * units cache the binding table in the texture cache. However, we have
162 * yet to be able to actually confirm this.
164 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
165 pc
.TextureCacheInvalidationEnable
= true;
166 pc
.ConstantCacheInvalidationEnable
= true;
167 pc
.StateCacheInvalidationEnable
= true;
172 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
173 struct anv_state state
, struct anv_address addr
)
175 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
178 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
179 state
.offset
+ isl_dev
->ss
.addr_offset
,
180 addr
.bo
, addr
.offset
);
181 if (result
!= VK_SUCCESS
)
182 anv_batch_set_error(&cmd_buffer
->batch
, result
);
186 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
187 struct anv_surface_state state
)
189 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
191 assert(!anv_address_is_null(state
.address
));
192 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
194 if (!anv_address_is_null(state
.aux_address
)) {
196 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
197 &cmd_buffer
->pool
->alloc
,
198 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
199 state
.aux_address
.bo
, state
.aux_address
.offset
);
200 if (result
!= VK_SUCCESS
)
201 anv_batch_set_error(&cmd_buffer
->batch
, result
);
204 if (!anv_address_is_null(state
.clear_address
)) {
206 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
207 &cmd_buffer
->pool
->alloc
,
209 isl_dev
->ss
.clear_color_state_offset
,
210 state
.clear_address
.bo
, state
.clear_address
.offset
);
211 if (result
!= VK_SUCCESS
)
212 anv_batch_set_error(&cmd_buffer
->batch
, result
);
217 color_attachment_compute_aux_usage(struct anv_device
* device
,
218 struct anv_cmd_state
* cmd_state
,
219 uint32_t att
, VkRect2D render_area
,
220 union isl_color_value
*fast_clear_color
)
222 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
223 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
225 assert(iview
->n_planes
== 1);
227 if (iview
->planes
[0].isl
.base_array_layer
>=
228 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
229 iview
->planes
[0].isl
.base_level
)) {
230 /* There is no aux buffer which corresponds to the level and layer(s)
233 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
234 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
235 att_state
->fast_clear
= false;
239 att_state
->aux_usage
=
240 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
241 VK_IMAGE_ASPECT_COLOR_BIT
,
242 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
244 /* If we don't have aux, then we should have returned early in the layer
245 * check above. If we got here, we must have something.
247 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
249 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
250 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
251 att_state
->input_aux_usage
= att_state
->aux_usage
;
253 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
255 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
256 * setting is only allowed if Surface Format supported for Fast
257 * Clear. In addition, if the surface is bound to the sampling
258 * engine, Surface Format must be supported for Render Target
259 * Compression for surfaces bound to the sampling engine."
261 * In other words, we can only sample from a fast-cleared image if it
262 * also supports color compression.
264 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
265 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
267 /* While fast-clear resolves and partial resolves are fairly cheap in the
268 * case where you render to most of the pixels, full resolves are not
269 * because they potentially involve reading and writing the entire
270 * framebuffer. If we can't texture with CCS_E, we should leave it off and
271 * limit ourselves to fast clears.
273 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
274 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
275 anv_perf_warn(device
->instance
, iview
->image
,
276 "Not temporarily enabling CCS_E.");
279 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
283 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
284 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
286 union isl_color_value clear_color
= {};
287 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
289 att_state
->clear_color_is_zero_one
=
290 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
291 att_state
->clear_color_is_zero
=
292 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
294 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
295 /* Start by getting the fast clear type. We use the first subpass
296 * layout here because we don't want to fast-clear if the first subpass
297 * to use the attachment can't handle fast-clears.
299 enum anv_fast_clear_type fast_clear_type
=
300 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
301 VK_IMAGE_ASPECT_COLOR_BIT
,
302 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
303 switch (fast_clear_type
) {
304 case ANV_FAST_CLEAR_NONE
:
305 att_state
->fast_clear
= false;
307 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
308 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
310 case ANV_FAST_CLEAR_ANY
:
311 att_state
->fast_clear
= true;
315 /* Potentially, we could do partial fast-clears but doing so has crazy
316 * alignment restrictions. It's easier to just restrict to full size
317 * fast clears for now.
319 if (render_area
.offset
.x
!= 0 ||
320 render_area
.offset
.y
!= 0 ||
321 render_area
.extent
.width
!= iview
->extent
.width
||
322 render_area
.extent
.height
!= iview
->extent
.height
)
323 att_state
->fast_clear
= false;
325 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
326 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
327 att_state
->fast_clear
= false;
329 /* We only allow fast clears to the first slice of an image (level 0,
330 * layer 0) and only for the entire slice. This guarantees us that, at
331 * any given time, there is only one clear color on any given image at
332 * any given time. At the time of our testing (Jan 17, 2018), there
333 * were no known applications which would benefit from fast-clearing
334 * more than just the first slice.
336 if (att_state
->fast_clear
&&
337 (iview
->planes
[0].isl
.base_level
> 0 ||
338 iview
->planes
[0].isl
.base_array_layer
> 0)) {
339 anv_perf_warn(device
->instance
, iview
->image
,
340 "Rendering with multi-lod or multi-layer framebuffer "
341 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
342 "baseArrayLayer > 0. Not fast clearing.");
343 att_state
->fast_clear
= false;
344 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
345 anv_perf_warn(device
->instance
, iview
->image
,
346 "Rendering to a multi-layer framebuffer with "
347 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
350 if (att_state
->fast_clear
)
351 *fast_clear_color
= clear_color
;
353 att_state
->fast_clear
= false;
358 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
359 struct anv_cmd_state
*cmd_state
,
360 uint32_t att
, VkRect2D render_area
)
362 struct anv_render_pass_attachment
*pass_att
=
363 &cmd_state
->pass
->attachments
[att
];
364 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
365 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
367 /* These will be initialized after the first subpass transition. */
368 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
369 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
372 /* We don't do any HiZ or depth fast-clears on gen7 yet */
373 att_state
->fast_clear
= false;
377 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
378 /* If we're just clearing stencil, we can always HiZ clear */
379 att_state
->fast_clear
= true;
383 /* Default to false for now */
384 att_state
->fast_clear
= false;
386 /* We must have depth in order to have HiZ */
387 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
390 const enum isl_aux_usage first_subpass_aux_usage
=
391 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
392 VK_IMAGE_ASPECT_DEPTH_BIT
,
393 pass_att
->first_subpass_layout
);
394 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
397 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
398 iview
->planes
[0].isl
.format
,
399 iview
->image
->samples
,
400 render_area
.offset
.x
,
401 render_area
.offset
.y
,
402 render_area
.offset
.x
+
403 render_area
.extent
.width
,
404 render_area
.offset
.y
+
405 render_area
.extent
.height
))
408 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
411 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
412 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
413 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
414 * only supports returning 0.0f. Gens prior to gen8 do not support this
420 /* If we got here, then we can fast clear */
421 att_state
->fast_clear
= true;
425 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
427 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
430 /* We only allocate input attachment states for color surfaces. Compression
431 * is not yet enabled for depth textures and stencil doesn't allow
432 * compression so we can just use the texture surface state from the view.
434 return vk_format_is_color(att
->format
);
437 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
438 * the initial layout is undefined, the HiZ buffer and depth buffer will
439 * represent the same data at the end of this operation.
442 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
443 const struct anv_image
*image
,
444 VkImageLayout initial_layout
,
445 VkImageLayout final_layout
)
447 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
448 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
449 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
450 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
451 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
452 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
454 enum isl_aux_op hiz_op
;
455 if (hiz_enabled
&& !enable_hiz
) {
456 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
457 } else if (!hiz_enabled
&& enable_hiz
) {
458 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
460 assert(hiz_enabled
== enable_hiz
);
461 /* If the same buffer will be used, no resolves are necessary. */
462 hiz_op
= ISL_AUX_OP_NONE
;
465 if (hiz_op
!= ISL_AUX_OP_NONE
)
466 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
470 #define MI_PREDICATE_SRC0 0x2400
471 #define MI_PREDICATE_SRC1 0x2408
474 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
475 const struct anv_image
*image
,
476 VkImageAspectFlagBits aspect
,
478 uint32_t base_layer
, uint32_t layer_count
,
481 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
483 /* We only have compression tracking for CCS_E */
484 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
487 for (uint32_t a
= 0; a
< layer_count
; a
++) {
488 uint32_t layer
= base_layer
+ a
;
489 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
490 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
493 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
499 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
500 const struct anv_image
*image
,
501 VkImageAspectFlagBits aspect
,
502 enum anv_fast_clear_type fast_clear
)
504 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
505 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
507 sdi
.ImmediateData
= fast_clear
;
510 /* Whenever we have fast-clear, we consider that slice to be compressed.
511 * This makes building predicates much easier.
513 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
514 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
517 #if GEN_IS_HASWELL || GEN_GEN >= 8
518 static inline uint32_t
519 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
521 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
523 .Operand1
= operand1
,
524 .Operand2
= operand2
,
528 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
534 #define CS_GPR(n) (0x2600 + (n) * 8)
536 /* This is only really practical on haswell and above because it requires
537 * MI math in order to get it correct.
539 #if GEN_GEN >= 8 || GEN_IS_HASWELL
541 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
542 const struct anv_image
*image
,
543 VkImageAspectFlagBits aspect
,
544 uint32_t level
, uint32_t array_layer
,
545 enum isl_aux_op resolve_op
,
546 enum anv_fast_clear_type fast_clear_supported
)
548 struct anv_address fast_clear_type_addr
=
549 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
551 /* Name some registers */
552 const int image_fc_reg
= MI_ALU_REG0
;
553 const int fc_imm_reg
= MI_ALU_REG1
;
554 const int pred_reg
= MI_ALU_REG2
;
558 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
559 /* In this case, we're doing a full resolve which means we want the
560 * resolve to happen if any compression (including fast-clears) is
563 * In order to simplify the logic a bit, we make the assumption that,
564 * if the first slice has been fast-cleared, it is also marked as
565 * compressed. See also set_image_fast_clear_state.
567 struct anv_address compression_state_addr
=
568 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
569 aspect
, level
, array_layer
);
570 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
571 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
572 lrm
.MemoryAddress
= compression_state_addr
;
574 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
575 sdi
.Address
= compression_state_addr
;
576 sdi
.ImmediateData
= 0;
579 if (level
== 0 && array_layer
== 0) {
580 /* If the predicate is true, we want to write 0 to the fast clear type
581 * and, if it's false, leave it alone. We can do this by writing
583 * clear_type = clear_type & ~predicate;
585 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
586 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
587 lrm
.MemoryAddress
= fast_clear_type_addr
;
589 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
590 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
591 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
594 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
595 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
596 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
597 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
598 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
600 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
601 srm
.MemoryAddress
= fast_clear_type_addr
;
602 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
605 } else if (level
== 0 && array_layer
== 0) {
606 /* In this case, we are doing a partial resolve to get rid of fast-clear
607 * colors. We don't care about the compression state but we do care
608 * about how much fast clear is allowed by the final layout.
610 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
611 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
613 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
614 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
615 lrm
.MemoryAddress
= fast_clear_type_addr
;
617 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
619 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
620 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
622 /* We need to compute (fast_clear_supported < image->fast_clear).
623 * We do this by subtracting and storing the carry bit.
625 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
626 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
627 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
628 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
629 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
631 /* Store the predicate */
632 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
634 /* If the predicate is true, we want to write 0 to the fast clear type
635 * and, if it's false, leave it alone. We can do this by writing
637 * clear_type = clear_type & ~predicate;
639 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
640 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
641 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
642 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
643 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
645 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
646 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
647 srm
.MemoryAddress
= fast_clear_type_addr
;
650 /* In this case, we're trying to do a partial resolve on a slice that
651 * doesn't have clear color. There's nothing to do.
653 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
657 /* We use the first half of src0 for the actual predicate. Set the second
658 * half of src0 and all of src1 to 0 as the predicate operation will be
659 * doing an implicit src0 != src1.
661 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
662 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
663 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
665 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
666 mip
.LoadOperation
= LOAD_LOADINV
;
667 mip
.CombineOperation
= COMBINE_SET
;
668 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
671 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
675 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
676 const struct anv_image
*image
,
677 VkImageAspectFlagBits aspect
,
678 uint32_t level
, uint32_t array_layer
,
679 enum isl_aux_op resolve_op
,
680 enum anv_fast_clear_type fast_clear_supported
)
682 struct anv_address fast_clear_type_addr
=
683 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
685 /* This only works for partial resolves and only when the clear color is
686 * all or nothing. On the upside, this emits less command streamer code
687 * and works on Ivybridge and Bay Trail.
689 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
690 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
692 /* We don't support fast clears on anything other than the first slice. */
693 if (level
> 0 || array_layer
> 0)
696 /* On gen8, we don't have a concept of default clear colors because we
697 * can't sample from CCS surfaces. It's enough to just load the fast clear
698 * state into the predicate register.
700 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
701 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
702 lrm
.MemoryAddress
= fast_clear_type_addr
;
704 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
705 sdi
.Address
= fast_clear_type_addr
;
706 sdi
.ImmediateData
= 0;
709 /* We use the first half of src0 for the actual predicate. Set the second
710 * half of src0 and all of src1 to 0 as the predicate operation will be
711 * doing an implicit src0 != src1.
713 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
714 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
715 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
717 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
718 mip
.LoadOperation
= LOAD_LOADINV
;
719 mip
.CombineOperation
= COMBINE_SET
;
720 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
723 #endif /* GEN_GEN <= 8 */
726 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
727 const struct anv_image
*image
,
728 VkImageAspectFlagBits aspect
,
729 uint32_t level
, uint32_t array_layer
,
730 enum isl_aux_op resolve_op
,
731 enum anv_fast_clear_type fast_clear_supported
)
733 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
736 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
737 aspect
, level
, array_layer
,
738 resolve_op
, fast_clear_supported
);
739 #else /* GEN_GEN <= 8 */
740 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
741 aspect
, level
, array_layer
,
742 resolve_op
, fast_clear_supported
);
745 /* CCS_D only supports full resolves and BLORP will assert on us if we try
746 * to do a partial resolve on a CCS_D surface.
748 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
749 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
750 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
752 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
753 array_layer
, 1, resolve_op
, NULL
, true);
757 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
758 const struct anv_image
*image
,
759 VkImageAspectFlagBits aspect
,
760 uint32_t array_layer
,
761 enum isl_aux_op resolve_op
,
762 enum anv_fast_clear_type fast_clear_supported
)
764 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
765 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
767 #if GEN_GEN >= 8 || GEN_IS_HASWELL
768 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
769 aspect
, 0, array_layer
,
770 resolve_op
, fast_clear_supported
);
772 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
773 array_layer
, 1, resolve_op
, NULL
, true);
775 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
780 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
781 const struct anv_image
*image
,
782 VkImageAspectFlagBits aspect
,
783 enum isl_aux_usage aux_usage
,
786 uint32_t layer_count
)
788 /* The aspect must be exactly one of the image aspects. */
789 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
791 /* The only compression types with more than just fast-clears are MCS,
792 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
793 * track the current fast-clear and compression state. This leaves us
794 * with just MCS and CCS_E.
796 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
797 aux_usage
!= ISL_AUX_USAGE_MCS
)
800 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
801 level
, base_layer
, layer_count
, true);
805 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
806 const struct anv_image
*image
,
807 VkImageAspectFlagBits aspect
)
809 assert(cmd_buffer
&& image
);
810 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
812 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
813 ANV_FAST_CLEAR_NONE
);
815 /* The fast clear value dword(s) will be copied into a surface state object.
816 * Ensure that the restrictions of the fields in the dword(s) are followed.
818 * CCS buffers on SKL+ can have any value set for the clear colors.
820 if (image
->samples
== 1 && GEN_GEN
>= 9)
823 /* Other combinations of auxiliary buffers and platforms require specific
824 * values in the clear value dword(s).
826 struct anv_address addr
=
827 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
830 for (unsigned i
= 0; i
< 4; i
++) {
831 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
833 sdi
.Address
.offset
+= i
* 4;
834 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
835 assert(image
->samples
> 1);
836 sdi
.ImmediateData
= 0;
840 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
842 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
843 /* Pre-SKL, the dword containing the clear values also contains
844 * other fields, so we need to initialize those fields to match the
845 * values that would be in a color attachment.
847 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
848 ISL_CHANNEL_SELECT_GREEN
<< 22 |
849 ISL_CHANNEL_SELECT_BLUE
<< 19 |
850 ISL_CHANNEL_SELECT_ALPHA
<< 16;
851 } else if (GEN_GEN
== 7) {
852 /* On IVB, the dword containing the clear values also contains
853 * other fields that must be zero or can be zero.
855 sdi
.ImmediateData
= 0;
861 /* Copy the fast-clear value dword(s) between a surface state object and an
862 * image's fast clear state buffer.
865 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
866 struct anv_state surface_state
,
867 const struct anv_image
*image
,
868 VkImageAspectFlagBits aspect
,
869 bool copy_from_surface_state
)
871 assert(cmd_buffer
&& image
);
872 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
874 struct anv_address ss_clear_addr
= {
875 .bo
= &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
876 .offset
= surface_state
.offset
+
877 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
879 const struct anv_address entry_addr
=
880 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
881 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
883 if (copy_from_surface_state
) {
884 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
,
885 ss_clear_addr
, copy_size
);
887 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_clear_addr
,
888 entry_addr
, copy_size
);
890 /* Updating a surface state object may require that the state cache be
891 * invalidated. From the SKL PRM, Shared Functions -> State -> State
894 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
895 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
896 * modified [...], the L1 state cache must be invalidated to ensure
897 * the new surface or sampler state is fetched from system memory.
899 * In testing, SKL doesn't actually seem to need this, but HSW does.
901 cmd_buffer
->state
.pending_pipe_bits
|=
902 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
907 * @brief Transitions a color buffer from one layout to another.
909 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
912 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
913 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
914 * this represents the maximum layers to transition at each
915 * specified miplevel.
918 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
919 const struct anv_image
*image
,
920 VkImageAspectFlagBits aspect
,
921 const uint32_t base_level
, uint32_t level_count
,
922 uint32_t base_layer
, uint32_t layer_count
,
923 VkImageLayout initial_layout
,
924 VkImageLayout final_layout
)
926 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
927 /* Validate the inputs. */
929 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
930 /* These values aren't supported for simplicity's sake. */
931 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
932 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
933 /* Ensure the subresource range is valid. */
934 uint64_t last_level_num
= base_level
+ level_count
;
935 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
936 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
937 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
938 assert(last_level_num
<= image
->levels
);
939 /* The spec disallows these final layouts. */
940 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
941 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
943 /* No work is necessary if the layout stays the same or if this subresource
944 * range lacks auxiliary data.
946 if (initial_layout
== final_layout
)
949 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
951 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
952 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
953 /* This surface is a linear compressed image with a tiled shadow surface
954 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
955 * we need to ensure the shadow copy is up-to-date.
957 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
958 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
959 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
960 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
962 anv_image_copy_to_shadow(cmd_buffer
, image
,
963 base_level
, level_count
,
964 base_layer
, layer_count
);
967 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
970 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
972 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
973 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
974 /* A subresource in the undefined layout may have been aliased and
975 * populated with any arrangement of bits. Therefore, we must initialize
976 * the related aux buffer and clear buffer entry with desirable values.
977 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
978 * images with VK_IMAGE_TILING_OPTIMAL.
980 * Initialize the relevant clear buffer entries.
982 if (base_level
== 0 && base_layer
== 0)
983 init_fast_clear_color(cmd_buffer
, image
, aspect
);
985 /* Initialize the aux buffers to enable correct rendering. In order to
986 * ensure that things such as storage images work correctly, aux buffers
987 * need to be initialized to valid data.
989 * Having an aux buffer with invalid data is a problem for two reasons:
991 * 1) Having an invalid value in the buffer can confuse the hardware.
992 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
993 * invalid and leads to the hardware doing strange things. It
994 * doesn't hang as far as we can tell but rendering corruption can
997 * 2) If this transition is into the GENERAL layout and we then use the
998 * image as a storage image, then we must have the aux buffer in the
999 * pass-through state so that, if we then go to texture from the
1000 * image, we get the results of our storage image writes and not the
1001 * fast clear color or other random data.
1003 * For CCS both of the problems above are real demonstrable issues. In
1004 * that case, the only thing we can do is to perform an ambiguate to
1005 * transition the aux surface into the pass-through state.
1007 * For MCS, (2) is never an issue because we don't support multisampled
1008 * storage images. In theory, issue (1) is a problem with MCS but we've
1009 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1010 * theory, be interpreted as something but we don't know that all bit
1011 * patterns are actually valid. For 2x and 8x, you could easily end up
1012 * with the MCS referring to an invalid plane because not all bits of
1013 * the MCS value are actually used. Even though we've never seen issues
1014 * in the wild, it's best to play it safe and initialize the MCS. We
1015 * can use a fast-clear for MCS because we only ever touch from render
1016 * and texture (no image load store).
1018 if (image
->samples
== 1) {
1019 for (uint32_t l
= 0; l
< level_count
; l
++) {
1020 const uint32_t level
= base_level
+ l
;
1022 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1023 if (base_layer
>= aux_layers
)
1024 break; /* We will only get fewer layers as level increases */
1025 uint32_t level_layer_count
=
1026 MIN2(layer_count
, aux_layers
- base_layer
);
1028 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
1029 base_layer
, level_layer_count
,
1030 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1032 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1033 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1034 level
, base_layer
, level_layer_count
,
1039 if (image
->samples
== 4 || image
->samples
== 16) {
1040 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1041 "Doing a potentially unnecessary fast-clear to "
1042 "define an MCS buffer.");
1045 assert(base_level
== 0 && level_count
== 1);
1046 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
1047 base_layer
, layer_count
,
1048 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1053 const enum isl_aux_usage initial_aux_usage
=
1054 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1055 const enum isl_aux_usage final_aux_usage
=
1056 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1058 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1059 * We can handle transitions between CCS_D/E to and from NONE. What we
1060 * don't yet handle is switching between CCS_E and CCS_D within a given
1061 * image. Doing so in a performant way requires more detailed aux state
1062 * tracking such as what is done in i965. For now, just assume that we
1063 * only have one type of compression.
1065 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1066 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1067 initial_aux_usage
== final_aux_usage
);
1069 /* If initial aux usage is NONE, there is nothing to resolve */
1070 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1073 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1075 /* If the initial layout supports more fast clear than the final layout
1076 * then we need at least a partial resolve.
1078 const enum anv_fast_clear_type initial_fast_clear
=
1079 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1080 const enum anv_fast_clear_type final_fast_clear
=
1081 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1082 if (final_fast_clear
< initial_fast_clear
)
1083 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1085 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1086 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1087 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1089 if (resolve_op
== ISL_AUX_OP_NONE
)
1092 /* Perform a resolve to synchronize data between the main and aux buffer.
1093 * Before we begin, we must satisfy the cache flushing requirement specified
1094 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1096 * Any transition from any value in {Clear, Render, Resolve} to a
1097 * different value in {Clear, Render, Resolve} requires end of pipe
1100 * We perform a flush of the write cache before and after the clear and
1101 * resolve operations to meet this requirement.
1103 * Unlike other drawing, fast clear operations are not properly
1104 * synchronized. The first PIPE_CONTROL here likely ensures that the
1105 * contents of the previous render or clear hit the render target before we
1106 * resolve and the second likely ensures that the resolve is complete before
1107 * we do any more rendering or clearing.
1109 cmd_buffer
->state
.pending_pipe_bits
|=
1110 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1112 for (uint32_t l
= 0; l
< level_count
; l
++) {
1113 uint32_t level
= base_level
+ l
;
1115 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1116 if (base_layer
>= aux_layers
)
1117 break; /* We will only get fewer layers as level increases */
1118 uint32_t level_layer_count
=
1119 MIN2(layer_count
, aux_layers
- base_layer
);
1121 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1122 uint32_t array_layer
= base_layer
+ a
;
1123 if (image
->samples
== 1) {
1124 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
, aspect
,
1125 level
, array_layer
, resolve_op
,
1128 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
, aspect
,
1129 array_layer
, resolve_op
,
1135 cmd_buffer
->state
.pending_pipe_bits
|=
1136 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1140 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1143 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1144 struct anv_render_pass
*pass
,
1145 const VkRenderPassBeginInfo
*begin
)
1147 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1148 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1150 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1152 if (pass
->attachment_count
> 0) {
1153 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1154 pass
->attachment_count
*
1155 sizeof(state
->attachments
[0]),
1156 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1157 if (state
->attachments
== NULL
) {
1158 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1159 return anv_batch_set_error(&cmd_buffer
->batch
,
1160 VK_ERROR_OUT_OF_HOST_MEMORY
);
1163 state
->attachments
= NULL
;
1166 /* Reserve one for the NULL state. */
1167 unsigned num_states
= 1;
1168 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1169 if (vk_format_is_color(pass
->attachments
[i
].format
))
1172 if (need_input_attachment_state(&pass
->attachments
[i
]))
1176 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1177 state
->render_pass_states
=
1178 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1179 num_states
* ss_stride
, isl_dev
->ss
.align
);
1181 struct anv_state next_state
= state
->render_pass_states
;
1182 next_state
.alloc_size
= isl_dev
->ss
.size
;
1184 state
->null_surface_state
= next_state
;
1185 next_state
.offset
+= ss_stride
;
1186 next_state
.map
+= ss_stride
;
1188 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1189 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1190 state
->attachments
[i
].color
.state
= next_state
;
1191 next_state
.offset
+= ss_stride
;
1192 next_state
.map
+= ss_stride
;
1195 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1196 state
->attachments
[i
].input
.state
= next_state
;
1197 next_state
.offset
+= ss_stride
;
1198 next_state
.map
+= ss_stride
;
1201 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1202 state
->render_pass_states
.alloc_size
);
1205 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1206 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1208 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1209 isl_extent3d(framebuffer
->width
,
1210 framebuffer
->height
,
1211 framebuffer
->layers
));
1213 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1214 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1215 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1216 VkImageAspectFlags clear_aspects
= 0;
1217 VkImageAspectFlags load_aspects
= 0;
1219 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1220 /* color attachment */
1221 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1222 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1223 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1224 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1227 /* depthstencil attachment */
1228 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1229 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1230 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1231 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1232 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1235 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1236 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1237 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1238 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1239 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1244 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1245 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1246 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1248 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1250 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1251 anv_assert(iview
->vk_format
== att
->format
);
1253 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1254 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1256 union isl_color_value clear_color
= { .u32
= { 0, } };
1257 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1258 anv_assert(iview
->n_planes
== 1);
1259 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1260 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1261 state
, i
, begin
->renderArea
,
1264 anv_image_fill_surface_state(cmd_buffer
->device
,
1266 VK_IMAGE_ASPECT_COLOR_BIT
,
1267 &iview
->planes
[0].isl
,
1268 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1269 state
->attachments
[i
].aux_usage
,
1272 &state
->attachments
[i
].color
,
1275 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1277 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1282 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1283 anv_image_fill_surface_state(cmd_buffer
->device
,
1285 VK_IMAGE_ASPECT_COLOR_BIT
,
1286 &iview
->planes
[0].isl
,
1287 ISL_SURF_USAGE_TEXTURE_BIT
,
1288 state
->attachments
[i
].input_aux_usage
,
1291 &state
->attachments
[i
].input
,
1294 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1303 genX(BeginCommandBuffer
)(
1304 VkCommandBuffer commandBuffer
,
1305 const VkCommandBufferBeginInfo
* pBeginInfo
)
1307 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1309 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1310 * command buffer's state. Otherwise, we must *reset* its state. In both
1311 * cases we reset it.
1313 * From the Vulkan 1.0 spec:
1315 * If a command buffer is in the executable state and the command buffer
1316 * was allocated from a command pool with the
1317 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1318 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1319 * as if vkResetCommandBuffer had been called with
1320 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1321 * the command buffer in the recording state.
1323 anv_cmd_buffer_reset(cmd_buffer
);
1325 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1327 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1328 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1330 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1332 /* We sometimes store vertex data in the dynamic state buffer for blorp
1333 * operations and our dynamic state stream may re-use data from previous
1334 * command buffers. In order to prevent stale cache data, we flush the VF
1335 * cache. We could do this on every blorp call but that's not really
1336 * needed as all of the data will get written by the CPU prior to the GPU
1337 * executing anything. The chances are fairly high that they will use
1338 * blorp at least once per primary command buffer so it shouldn't be
1341 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1342 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1344 /* We send an "Indirect State Pointers Disable" packet at
1345 * EndCommandBuffer, so all push contant packets are ignored during a
1346 * context restore. Documentation says after that command, we need to
1347 * emit push constants again before any rendering operation. So we
1348 * flag them dirty here to make sure they get emitted.
1350 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1352 VkResult result
= VK_SUCCESS
;
1353 if (cmd_buffer
->usage_flags
&
1354 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1355 assert(pBeginInfo
->pInheritanceInfo
);
1356 cmd_buffer
->state
.pass
=
1357 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1358 cmd_buffer
->state
.subpass
=
1359 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1361 /* This is optional in the inheritance info. */
1362 cmd_buffer
->state
.framebuffer
=
1363 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1365 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1366 cmd_buffer
->state
.pass
, NULL
);
1368 /* Record that HiZ is enabled if we can. */
1369 if (cmd_buffer
->state
.framebuffer
) {
1370 const struct anv_image_view
* const iview
=
1371 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1374 VkImageLayout layout
=
1375 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1377 enum isl_aux_usage aux_usage
=
1378 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1379 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1381 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1385 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1391 /* From the PRM, Volume 2a:
1393 * "Indirect State Pointers Disable
1395 * At the completion of the post-sync operation associated with this pipe
1396 * control packet, the indirect state pointers in the hardware are
1397 * considered invalid; the indirect pointers are not saved in the context.
1398 * If any new indirect state commands are executed in the command stream
1399 * while the pipe control is pending, the new indirect state commands are
1402 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1403 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1404 * commands are only considered as Indirect State Pointers. Once ISP is
1405 * issued in a context, SW must initialize by programming push constant
1406 * commands for all the shaders (at least to zero length) before attempting
1407 * any rendering operation for the same context."
1409 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1410 * even though they point to a BO that has been already unreferenced at
1411 * the end of the previous batch buffer. This has been fine so far since
1412 * we are protected by these scratch page (every address not covered by
1413 * a BO should be pointing to the scratch page). But on CNL, it is
1414 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1417 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1418 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1419 * context restore, so the mentioned hang doesn't happen. However,
1420 * software must program push constant commands for all stages prior to
1421 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1423 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1424 * constants have been loaded into the EUs prior to disable the push constants
1425 * so that it doesn't hang a previous 3DPRIMITIVE.
1428 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1430 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1431 pc
.StallAtPixelScoreboard
= true;
1432 pc
.CommandStreamerStallEnable
= true;
1434 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1435 pc
.IndirectStatePointersDisable
= true;
1436 pc
.CommandStreamerStallEnable
= true;
1441 genX(EndCommandBuffer
)(
1442 VkCommandBuffer commandBuffer
)
1444 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1446 if (anv_batch_has_error(&cmd_buffer
->batch
))
1447 return cmd_buffer
->batch
.status
;
1449 /* We want every command buffer to start with the PMA fix in a known state,
1450 * so we disable it at the end of the command buffer.
1452 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1454 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1456 emit_isp_disable(cmd_buffer
);
1458 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1464 genX(CmdExecuteCommands
)(
1465 VkCommandBuffer commandBuffer
,
1466 uint32_t commandBufferCount
,
1467 const VkCommandBuffer
* pCmdBuffers
)
1469 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1471 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1473 if (anv_batch_has_error(&primary
->batch
))
1476 /* The secondary command buffers will assume that the PMA fix is disabled
1477 * when they begin executing. Make sure this is true.
1479 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1481 /* The secondary command buffer doesn't know which textures etc. have been
1482 * flushed prior to their execution. Apply those flushes now.
1484 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1486 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1487 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1489 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1490 assert(!anv_batch_has_error(&secondary
->batch
));
1492 if (secondary
->usage_flags
&
1493 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1494 /* If we're continuing a render pass from the primary, we need to
1495 * copy the surface states for the current subpass into the storage
1496 * we allocated for them in BeginCommandBuffer.
1498 struct anv_bo
*ss_bo
=
1499 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1500 struct anv_state src_state
= primary
->state
.render_pass_states
;
1501 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1502 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1504 genX(cmd_buffer_so_memcpy
)(primary
,
1505 (struct anv_address
) {
1507 .offset
= dst_state
.offset
,
1509 (struct anv_address
) {
1511 .offset
= src_state
.offset
,
1513 src_state
.alloc_size
);
1516 anv_cmd_buffer_add_secondary(primary
, secondary
);
1519 /* The secondary may have selected a different pipeline (3D or compute) and
1520 * may have changed the current L3$ configuration. Reset our tracking
1521 * variables to invalid values to ensure that we re-emit these in the case
1522 * where we do any draws or compute dispatches from the primary after the
1523 * secondary has returned.
1525 primary
->state
.current_pipeline
= UINT32_MAX
;
1526 primary
->state
.current_l3_config
= NULL
;
1528 /* Each of the secondary command buffers will use its own state base
1529 * address. We need to re-emit state base address for the primary after
1530 * all of the secondaries are done.
1532 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1535 genX(cmd_buffer_emit_state_base_address
)(primary
);
1538 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1539 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1540 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1543 * Program the hardware to use the specified L3 configuration.
1546 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1547 const struct gen_l3_config
*cfg
)
1550 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1553 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1554 intel_logd("L3 config transition: ");
1555 gen_dump_l3_config(cfg
, stderr
);
1558 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1560 /* According to the hardware docs, the L3 partitioning can only be changed
1561 * while the pipeline is completely drained and the caches are flushed,
1562 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1564 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1565 pc
.DCFlushEnable
= true;
1566 pc
.PostSyncOperation
= NoWrite
;
1567 pc
.CommandStreamerStallEnable
= true;
1570 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1571 * invalidation of the relevant caches. Note that because RO invalidation
1572 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1573 * command is processed by the CS) we cannot combine it with the previous
1574 * stalling flush as the hardware documentation suggests, because that
1575 * would cause the CS to stall on previous rendering *after* RO
1576 * invalidation and wouldn't prevent the RO caches from being polluted by
1577 * concurrent rendering before the stall completes. This intentionally
1578 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1579 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1580 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1581 * already guarantee that there is no concurrent GPGPU kernel execution
1582 * (see SKL HSD 2132585).
1584 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1585 pc
.TextureCacheInvalidationEnable
= true;
1586 pc
.ConstantCacheInvalidationEnable
= true;
1587 pc
.InstructionCacheInvalidateEnable
= true;
1588 pc
.StateCacheInvalidationEnable
= true;
1589 pc
.PostSyncOperation
= NoWrite
;
1592 /* Now send a third stalling flush to make sure that invalidation is
1593 * complete when the L3 configuration registers are modified.
1595 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1596 pc
.DCFlushEnable
= true;
1597 pc
.PostSyncOperation
= NoWrite
;
1598 pc
.CommandStreamerStallEnable
= true;
1603 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1606 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1607 .SLMEnable
= has_slm
,
1608 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1609 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1610 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1611 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1613 /* Set up the L3 partitioning. */
1614 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1618 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1619 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1620 cfg
->n
[GEN_L3P_ALL
];
1621 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1622 cfg
->n
[GEN_L3P_ALL
];
1623 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1624 cfg
->n
[GEN_L3P_ALL
];
1626 assert(!cfg
->n
[GEN_L3P_ALL
]);
1628 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1629 * the matching space on the remaining banks has to be allocated to a
1630 * client (URB for all validated configurations) set to the
1631 * lower-bandwidth 2-bank address hashing mode.
1633 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1634 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1635 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1637 /* Minimum number of ways that can be allocated to the URB. */
1638 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1639 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1641 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1642 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1643 .ConvertDC_UC
= !has_dc
,
1644 .ConvertIS_UC
= !has_is
,
1645 .ConvertC_UC
= !has_c
,
1646 .ConvertT_UC
= !has_t
);
1648 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1649 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1650 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1652 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1653 .SLMEnable
= has_slm
,
1654 .URBLowBandwidth
= urb_low_bw
,
1655 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1657 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1659 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1660 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1662 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1663 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1664 .ISLowBandwidth
= 0,
1665 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1667 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1668 .TLowBandwidth
= 0);
1670 /* Set up the L3 partitioning. */
1671 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1672 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1673 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1676 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1677 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1678 * them disabled to avoid crashing the system hard.
1680 uint32_t scratch1
, chicken3
;
1681 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1682 .L3AtomicDisable
= !has_dc
);
1683 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1684 .L3AtomicDisableMask
= true,
1685 .L3AtomicDisable
= !has_dc
);
1686 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1687 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1693 cmd_buffer
->state
.current_l3_config
= cfg
;
1697 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1699 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1701 /* Flushes are pipelined while invalidations are handled immediately.
1702 * Therefore, if we're flushing anything then we need to schedule a stall
1703 * before any invalidations can happen.
1705 if (bits
& ANV_PIPE_FLUSH_BITS
)
1706 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1708 /* If we're going to do an invalidate and we have a pending CS stall that
1709 * has yet to be resolved, we do the CS stall now.
1711 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1712 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1713 bits
|= ANV_PIPE_CS_STALL_BIT
;
1714 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1717 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1718 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1719 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1720 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1721 pipe
.RenderTargetCacheFlushEnable
=
1722 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1724 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1725 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1726 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1729 * According to the Broadwell documentation, any PIPE_CONTROL with the
1730 * "Command Streamer Stall" bit set must also have another bit set,
1731 * with five different options:
1733 * - Render Target Cache Flush
1734 * - Depth Cache Flush
1735 * - Stall at Pixel Scoreboard
1736 * - Post-Sync Operation
1740 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1741 * mesa and it seems to work fine. The choice is fairly arbitrary.
1743 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1744 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1745 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1746 pipe
.StallAtPixelScoreboard
= true;
1749 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1752 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1753 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1755 * "If the VF Cache Invalidation Enable is set to a 1 in a
1756 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1757 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1758 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1761 * This appears to hang Broadwell, so we restrict it to just gen9.
1763 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1764 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1766 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1767 pipe
.StateCacheInvalidationEnable
=
1768 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1769 pipe
.ConstantCacheInvalidationEnable
=
1770 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1771 pipe
.VFCacheInvalidationEnable
=
1772 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1773 pipe
.TextureCacheInvalidationEnable
=
1774 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1775 pipe
.InstructionCacheInvalidateEnable
=
1776 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1778 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1780 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1781 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1782 * “Write Timestamp”.
1784 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1785 pipe
.PostSyncOperation
= WriteImmediateData
;
1787 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1791 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1794 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1797 void genX(CmdPipelineBarrier
)(
1798 VkCommandBuffer commandBuffer
,
1799 VkPipelineStageFlags srcStageMask
,
1800 VkPipelineStageFlags destStageMask
,
1802 uint32_t memoryBarrierCount
,
1803 const VkMemoryBarrier
* pMemoryBarriers
,
1804 uint32_t bufferMemoryBarrierCount
,
1805 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1806 uint32_t imageMemoryBarrierCount
,
1807 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1809 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1811 /* XXX: Right now, we're really dumb and just flush whatever categories
1812 * the app asks for. One of these days we may make this a bit better
1813 * but right now that's all the hardware allows for in most areas.
1815 VkAccessFlags src_flags
= 0;
1816 VkAccessFlags dst_flags
= 0;
1818 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1819 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1820 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1823 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1824 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1825 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1828 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1829 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1830 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1831 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1832 const VkImageSubresourceRange
*range
=
1833 &pImageMemoryBarriers
[i
].subresourceRange
;
1835 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1836 transition_depth_buffer(cmd_buffer
, image
,
1837 pImageMemoryBarriers
[i
].oldLayout
,
1838 pImageMemoryBarriers
[i
].newLayout
);
1839 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1840 VkImageAspectFlags color_aspects
=
1841 anv_image_expand_aspects(image
, range
->aspectMask
);
1842 uint32_t aspect_bit
;
1844 uint32_t base_layer
, layer_count
;
1845 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1847 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1849 base_layer
= range
->baseArrayLayer
;
1850 layer_count
= anv_get_layerCount(image
, range
);
1853 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1854 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1855 range
->baseMipLevel
,
1856 anv_get_levelCount(image
, range
),
1857 base_layer
, layer_count
,
1858 pImageMemoryBarriers
[i
].oldLayout
,
1859 pImageMemoryBarriers
[i
].newLayout
);
1864 cmd_buffer
->state
.pending_pipe_bits
|=
1865 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1866 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1870 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1872 VkShaderStageFlags stages
=
1873 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1875 /* In order to avoid thrash, we assume that vertex and fragment stages
1876 * always exist. In the rare case where one is missing *and* the other
1877 * uses push concstants, this may be suboptimal. However, avoiding stalls
1878 * seems more important.
1880 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1882 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1886 const unsigned push_constant_kb
= 32;
1887 #elif GEN_IS_HASWELL
1888 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1890 const unsigned push_constant_kb
= 16;
1893 const unsigned num_stages
=
1894 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1895 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1897 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1898 * units of 2KB. Incidentally, these are the same platforms that have
1899 * 32KB worth of push constant space.
1901 if (push_constant_kb
== 32)
1902 size_per_stage
&= ~1u;
1904 uint32_t kb_used
= 0;
1905 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1906 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1907 anv_batch_emit(&cmd_buffer
->batch
,
1908 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1909 alloc
._3DCommandSubOpcode
= 18 + i
;
1910 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1911 alloc
.ConstantBufferSize
= push_size
;
1913 kb_used
+= push_size
;
1916 anv_batch_emit(&cmd_buffer
->batch
,
1917 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1918 alloc
.ConstantBufferOffset
= kb_used
;
1919 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1922 cmd_buffer
->state
.push_constant_stages
= stages
;
1924 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1926 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1927 * the next 3DPRIMITIVE command after programming the
1928 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1930 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1931 * pipeline setup, we need to dirty push constants.
1933 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1936 static const struct anv_descriptor
*
1937 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1938 const struct anv_pipeline_binding
*binding
)
1940 assert(binding
->set
< MAX_SETS
);
1941 const struct anv_descriptor_set
*set
=
1942 pipe_state
->descriptors
[binding
->set
];
1943 const uint32_t offset
=
1944 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1945 return &set
->descriptors
[offset
+ binding
->index
];
1949 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1950 const struct anv_pipeline_binding
*binding
)
1952 assert(binding
->set
< MAX_SETS
);
1953 const struct anv_descriptor_set
*set
=
1954 pipe_state
->descriptors
[binding
->set
];
1956 uint32_t dynamic_offset_idx
=
1957 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1958 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1961 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1965 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1966 gl_shader_stage stage
,
1967 struct anv_state
*bt_state
)
1969 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1970 struct anv_cmd_pipeline_state
*pipe_state
;
1971 struct anv_pipeline
*pipeline
;
1972 uint32_t bias
, state_offset
;
1975 case MESA_SHADER_COMPUTE
:
1976 pipe_state
= &cmd_buffer
->state
.compute
.base
;
1980 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
1984 pipeline
= pipe_state
->pipeline
;
1986 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1987 *bt_state
= (struct anv_state
) { 0, };
1991 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1992 if (bias
+ map
->surface_count
== 0) {
1993 *bt_state
= (struct anv_state
) { 0, };
1997 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1998 bias
+ map
->surface_count
,
2000 uint32_t *bt_map
= bt_state
->map
;
2002 if (bt_state
->map
== NULL
)
2003 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2005 if (stage
== MESA_SHADER_COMPUTE
&&
2006 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
2007 struct anv_state surface_state
;
2009 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2011 const enum isl_format format
=
2012 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2013 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2015 cmd_buffer
->state
.compute
.num_workgroups
,
2018 bt_map
[0] = surface_state
.offset
+ state_offset
;
2019 add_surface_reloc(cmd_buffer
, surface_state
,
2020 cmd_buffer
->state
.compute
.num_workgroups
);
2023 if (map
->surface_count
== 0)
2026 if (map
->image_count
> 0) {
2028 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
2029 if (result
!= VK_SUCCESS
)
2032 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
2036 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2037 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2039 struct anv_state surface_state
;
2041 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2042 /* Color attachment binding */
2043 assert(stage
== MESA_SHADER_FRAGMENT
);
2044 assert(binding
->binding
== 0);
2045 if (binding
->index
< subpass
->color_count
) {
2046 const unsigned att
=
2047 subpass
->color_attachments
[binding
->index
].attachment
;
2049 /* From the Vulkan 1.0.46 spec:
2051 * "If any color or depth/stencil attachments are
2052 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2055 if (att
== VK_ATTACHMENT_UNUSED
) {
2056 surface_state
= cmd_buffer
->state
.null_surface_state
;
2058 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2061 surface_state
= cmd_buffer
->state
.null_surface_state
;
2064 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2066 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2067 struct anv_state surface_state
=
2068 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2070 struct anv_address constant_data
= {
2071 .bo
= &pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2072 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2074 unsigned constant_data_size
=
2075 pipeline
->shaders
[stage
]->constant_data_size
;
2077 const enum isl_format format
=
2078 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2079 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2080 surface_state
, format
,
2081 constant_data
, constant_data_size
, 1);
2083 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2084 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2088 const struct anv_descriptor
*desc
=
2089 anv_descriptor_for_binding(pipe_state
, binding
);
2091 switch (desc
->type
) {
2092 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2093 /* Nothing for us to do here */
2096 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2097 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2098 struct anv_surface_state sstate
=
2099 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2100 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2101 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2102 surface_state
= sstate
.state
;
2103 assert(surface_state
.alloc_size
);
2104 add_surface_state_relocs(cmd_buffer
, sstate
);
2107 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2108 assert(stage
== MESA_SHADER_FRAGMENT
);
2109 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2110 /* For depth and stencil input attachments, we treat it like any
2111 * old texture that a user may have bound.
2113 struct anv_surface_state sstate
=
2114 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2115 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2116 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2117 surface_state
= sstate
.state
;
2118 assert(surface_state
.alloc_size
);
2119 add_surface_state_relocs(cmd_buffer
, sstate
);
2121 /* For color input attachments, we create the surface state at
2122 * vkBeginRenderPass time so that we can include aux and clear
2123 * color information.
2125 assert(binding
->input_attachment_index
< subpass
->input_count
);
2126 const unsigned subpass_att
= binding
->input_attachment_index
;
2127 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2128 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2132 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2133 struct anv_surface_state sstate
= (binding
->write_only
)
2134 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2135 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2136 surface_state
= sstate
.state
;
2137 assert(surface_state
.alloc_size
);
2138 add_surface_state_relocs(cmd_buffer
, sstate
);
2140 struct brw_image_param
*image_param
=
2141 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2143 *image_param
= desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2147 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2148 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2149 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2150 surface_state
= desc
->buffer_view
->surface_state
;
2151 assert(surface_state
.alloc_size
);
2152 add_surface_reloc(cmd_buffer
, surface_state
,
2153 desc
->buffer_view
->address
);
2156 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2157 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2158 /* Compute the offset within the buffer */
2159 uint32_t dynamic_offset
=
2160 dynamic_offset_for_binding(pipe_state
, binding
);
2161 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2162 /* Clamp to the buffer size */
2163 offset
= MIN2(offset
, desc
->buffer
->size
);
2164 /* Clamp the range to the buffer size */
2165 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2167 struct anv_address address
=
2168 anv_address_add(desc
->buffer
->address
, offset
);
2171 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2172 enum isl_format format
=
2173 anv_isl_format_for_descriptor_type(desc
->type
);
2175 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2176 format
, address
, range
, 1);
2177 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2181 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2182 surface_state
= (binding
->write_only
)
2183 ? desc
->buffer_view
->writeonly_storage_surface_state
2184 : desc
->buffer_view
->storage_surface_state
;
2185 assert(surface_state
.alloc_size
);
2186 add_surface_reloc(cmd_buffer
, surface_state
,
2187 desc
->buffer_view
->address
);
2189 struct brw_image_param
*image_param
=
2190 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2192 *image_param
= desc
->buffer_view
->storage_image_param
;
2196 assert(!"Invalid descriptor type");
2200 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2202 assert(image
== map
->image_count
);
2205 anv_state_flush(cmd_buffer
->device
, *bt_state
);
2208 /* The PIPE_CONTROL command description says:
2210 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2211 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2212 * Target Cache Flush by enabling this bit. When render target flush
2213 * is set due to new association of BTI, PS Scoreboard Stall bit must
2214 * be set in this packet."
2216 * FINISHME: Currently we shuffle around the surface states in the binding
2217 * table based on if they are getting used or not. So, we've to do below
2218 * pipe control flush for every binding table upload. Make changes so
2219 * that we do it only when we modify render target surface states.
2221 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2222 pc
.RenderTargetCacheFlushEnable
= true;
2223 pc
.StallAtPixelScoreboard
= true;
2231 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2232 gl_shader_stage stage
,
2233 struct anv_state
*state
)
2235 struct anv_cmd_pipeline_state
*pipe_state
=
2236 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2237 &cmd_buffer
->state
.gfx
.base
;
2238 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2240 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2241 *state
= (struct anv_state
) { 0, };
2245 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2246 if (map
->sampler_count
== 0) {
2247 *state
= (struct anv_state
) { 0, };
2251 uint32_t size
= map
->sampler_count
* 16;
2252 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2254 if (state
->map
== NULL
)
2255 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2257 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2258 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2259 const struct anv_descriptor
*desc
=
2260 anv_descriptor_for_binding(pipe_state
, binding
);
2262 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2263 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2266 struct anv_sampler
*sampler
= desc
->sampler
;
2268 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2269 * happens to be zero.
2271 if (sampler
== NULL
)
2274 memcpy(state
->map
+ (s
* 16),
2275 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2278 anv_state_flush(cmd_buffer
->device
, *state
);
2284 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2286 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2288 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2289 pipeline
->active_stages
;
2291 VkResult result
= VK_SUCCESS
;
2292 anv_foreach_stage(s
, dirty
) {
2293 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2294 if (result
!= VK_SUCCESS
)
2296 result
= emit_binding_table(cmd_buffer
, s
,
2297 &cmd_buffer
->state
.binding_tables
[s
]);
2298 if (result
!= VK_SUCCESS
)
2302 if (result
!= VK_SUCCESS
) {
2303 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2305 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2306 if (result
!= VK_SUCCESS
)
2309 /* Re-emit state base addresses so we get the new surface state base
2310 * address before we start emitting binding tables etc.
2312 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2314 /* Re-emit all active binding tables */
2315 dirty
|= pipeline
->active_stages
;
2316 anv_foreach_stage(s
, dirty
) {
2317 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2318 if (result
!= VK_SUCCESS
) {
2319 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2322 result
= emit_binding_table(cmd_buffer
, s
,
2323 &cmd_buffer
->state
.binding_tables
[s
]);
2324 if (result
!= VK_SUCCESS
) {
2325 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2331 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2337 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2340 static const uint32_t sampler_state_opcodes
[] = {
2341 [MESA_SHADER_VERTEX
] = 43,
2342 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2343 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2344 [MESA_SHADER_GEOMETRY
] = 46,
2345 [MESA_SHADER_FRAGMENT
] = 47,
2346 [MESA_SHADER_COMPUTE
] = 0,
2349 static const uint32_t binding_table_opcodes
[] = {
2350 [MESA_SHADER_VERTEX
] = 38,
2351 [MESA_SHADER_TESS_CTRL
] = 39,
2352 [MESA_SHADER_TESS_EVAL
] = 40,
2353 [MESA_SHADER_GEOMETRY
] = 41,
2354 [MESA_SHADER_FRAGMENT
] = 42,
2355 [MESA_SHADER_COMPUTE
] = 0,
2358 anv_foreach_stage(s
, stages
) {
2359 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2360 assert(binding_table_opcodes
[s
] > 0);
2362 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2363 anv_batch_emit(&cmd_buffer
->batch
,
2364 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2365 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2366 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2370 /* Always emit binding table pointers if we're asked to, since on SKL
2371 * this is what flushes push constants. */
2372 anv_batch_emit(&cmd_buffer
->batch
,
2373 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2374 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2375 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2381 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2382 VkShaderStageFlags dirty_stages
)
2384 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2385 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2387 static const uint32_t push_constant_opcodes
[] = {
2388 [MESA_SHADER_VERTEX
] = 21,
2389 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2390 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2391 [MESA_SHADER_GEOMETRY
] = 22,
2392 [MESA_SHADER_FRAGMENT
] = 23,
2393 [MESA_SHADER_COMPUTE
] = 0,
2396 VkShaderStageFlags flushed
= 0;
2398 anv_foreach_stage(stage
, dirty_stages
) {
2399 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2400 assert(push_constant_opcodes
[stage
] > 0);
2402 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2403 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2405 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2406 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2407 const struct brw_stage_prog_data
*prog_data
=
2408 pipeline
->shaders
[stage
]->prog_data
;
2409 const struct anv_pipeline_bind_map
*bind_map
=
2410 &pipeline
->shaders
[stage
]->bind_map
;
2412 /* The Skylake PRM contains the following restriction:
2414 * "The driver must ensure The following case does not occur
2415 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2416 * buffer 3 read length equal to zero committed followed by a
2417 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2420 * To avoid this, we program the buffers in the highest slots.
2421 * This way, slot 0 is only used if slot 3 is also used.
2425 for (int i
= 3; i
>= 0; i
--) {
2426 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2427 if (range
->length
== 0)
2430 const unsigned surface
=
2431 prog_data
->binding_table
.ubo_start
+ range
->block
;
2433 assert(surface
<= bind_map
->surface_count
);
2434 const struct anv_pipeline_binding
*binding
=
2435 &bind_map
->surface_to_descriptor
[surface
];
2437 struct anv_address read_addr
;
2439 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2440 struct anv_address constant_data
= {
2441 .bo
= &pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2442 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2444 unsigned constant_data_size
=
2445 pipeline
->shaders
[stage
]->constant_data_size
;
2447 read_len
= MIN2(range
->length
,
2448 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2449 read_addr
= anv_address_add(constant_data
,
2452 const struct anv_descriptor
*desc
=
2453 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2455 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2456 read_len
= MIN2(range
->length
,
2457 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2458 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2461 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2463 uint32_t dynamic_offset
=
2464 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2465 uint32_t buf_offset
=
2466 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2467 uint32_t buf_range
=
2468 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2470 read_len
= MIN2(range
->length
,
2471 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2472 read_addr
= anv_address_add(desc
->buffer
->address
,
2473 buf_offset
+ range
->start
* 32);
2478 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2479 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2484 struct anv_state state
=
2485 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2487 if (state
.alloc_size
> 0) {
2488 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2489 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2490 .offset
= state
.offset
,
2492 c
.ConstantBody
.ReadLength
[n
] =
2493 DIV_ROUND_UP(state
.alloc_size
, 32);
2496 /* For Ivy Bridge, the push constants packets have a different
2497 * rule that would require us to iterate in the other direction
2498 * and possibly mess around with dynamic state base address.
2499 * Don't bother; just emit regular push constants at n = 0.
2501 struct anv_state state
=
2502 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2504 if (state
.alloc_size
> 0) {
2505 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2506 c
.ConstantBody
.ReadLength
[0] =
2507 DIV_ROUND_UP(state
.alloc_size
, 32);
2513 flushed
|= mesa_to_vk_shader_stage(stage
);
2516 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2520 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2522 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2525 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2526 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2527 vb_emit
|= pipeline
->vb_used
;
2529 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2531 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2533 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2536 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2537 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2539 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2540 GENX(3DSTATE_VERTEX_BUFFERS
));
2542 for_each_bit(vb
, vb_emit
) {
2543 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2544 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2546 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2547 .VertexBufferIndex
= vb
,
2550 .MemoryObjectControlState
= GENX(MOCS
),
2552 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2553 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2554 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2557 .AddressModifyEnable
= true,
2558 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2559 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2562 .BufferSize
= buffer
->size
- offset
2564 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2568 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2573 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2575 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2576 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2578 /* The exact descriptor layout is pulled from the pipeline, so we need
2579 * to re-emit binding tables on every pipeline change.
2581 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2583 /* If the pipeline changed, we may need to re-allocate push constant
2586 cmd_buffer_alloc_push_constants(cmd_buffer
);
2590 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2591 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2592 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2594 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2595 * stall needs to be sent just prior to any 3DSTATE_VS,
2596 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2597 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2598 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2599 * PIPE_CONTROL needs to be sent before any combination of VS
2600 * associated 3DSTATE."
2602 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2603 pc
.DepthStallEnable
= true;
2604 pc
.PostSyncOperation
= WriteImmediateData
;
2606 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2611 /* Render targets live in the same binding table as fragment descriptors */
2612 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2613 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2615 /* We emit the binding tables and sampler tables first, then emit push
2616 * constants and then finally emit binding table and sampler table
2617 * pointers. It has to happen in this order, since emitting the binding
2618 * tables may change the push constants (in case of storage images). After
2619 * emitting push constants, on SKL+ we have to emit the corresponding
2620 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2623 if (cmd_buffer
->state
.descriptors_dirty
)
2624 dirty
= flush_descriptor_sets(cmd_buffer
);
2626 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2627 /* Because we're pushing UBOs, we have to push whenever either
2628 * descriptors or push constants is dirty.
2630 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2631 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2632 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2636 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2638 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2639 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2641 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2642 ANV_CMD_DIRTY_PIPELINE
)) {
2643 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2644 pipeline
->depth_clamp_enable
);
2647 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2648 ANV_CMD_DIRTY_RENDER_TARGETS
))
2649 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2651 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2653 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2657 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2658 struct anv_address addr
,
2659 uint32_t size
, uint32_t index
)
2661 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2662 GENX(3DSTATE_VERTEX_BUFFERS
));
2664 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2665 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2666 .VertexBufferIndex
= index
,
2667 .AddressModifyEnable
= true,
2670 .MemoryObjectControlState
= GENX(MOCS
),
2671 .BufferStartingAddress
= addr
,
2674 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2675 .BufferStartingAddress
= addr
,
2676 .EndAddress
= anv_address_add(addr
, size
),
2682 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2683 struct anv_address addr
)
2685 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2689 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2690 uint32_t base_vertex
, uint32_t base_instance
)
2692 struct anv_state id_state
=
2693 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2695 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2696 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2698 anv_state_flush(cmd_buffer
->device
, id_state
);
2700 struct anv_address addr
= {
2701 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2702 .offset
= id_state
.offset
,
2705 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2709 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2711 struct anv_state state
=
2712 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2714 ((uint32_t *)state
.map
)[0] = draw_index
;
2716 anv_state_flush(cmd_buffer
->device
, state
);
2718 struct anv_address addr
= {
2719 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2720 .offset
= state
.offset
,
2723 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2727 VkCommandBuffer commandBuffer
,
2728 uint32_t vertexCount
,
2729 uint32_t instanceCount
,
2730 uint32_t firstVertex
,
2731 uint32_t firstInstance
)
2733 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2734 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2735 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2737 if (anv_batch_has_error(&cmd_buffer
->batch
))
2740 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2742 if (vs_prog_data
->uses_firstvertex
||
2743 vs_prog_data
->uses_baseinstance
)
2744 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2745 if (vs_prog_data
->uses_drawid
)
2746 emit_draw_index(cmd_buffer
, 0);
2748 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2749 * different views. We need to multiply instanceCount by the view count.
2751 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2753 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2754 prim
.VertexAccessType
= SEQUENTIAL
;
2755 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2756 prim
.VertexCountPerInstance
= vertexCount
;
2757 prim
.StartVertexLocation
= firstVertex
;
2758 prim
.InstanceCount
= instanceCount
;
2759 prim
.StartInstanceLocation
= firstInstance
;
2760 prim
.BaseVertexLocation
= 0;
2764 void genX(CmdDrawIndexed
)(
2765 VkCommandBuffer commandBuffer
,
2766 uint32_t indexCount
,
2767 uint32_t instanceCount
,
2768 uint32_t firstIndex
,
2769 int32_t vertexOffset
,
2770 uint32_t firstInstance
)
2772 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2773 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2774 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2776 if (anv_batch_has_error(&cmd_buffer
->batch
))
2779 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2781 if (vs_prog_data
->uses_firstvertex
||
2782 vs_prog_data
->uses_baseinstance
)
2783 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2784 if (vs_prog_data
->uses_drawid
)
2785 emit_draw_index(cmd_buffer
, 0);
2787 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2788 * different views. We need to multiply instanceCount by the view count.
2790 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2792 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2793 prim
.VertexAccessType
= RANDOM
;
2794 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2795 prim
.VertexCountPerInstance
= indexCount
;
2796 prim
.StartVertexLocation
= firstIndex
;
2797 prim
.InstanceCount
= instanceCount
;
2798 prim
.StartInstanceLocation
= firstInstance
;
2799 prim
.BaseVertexLocation
= vertexOffset
;
2803 /* Auto-Draw / Indirect Registers */
2804 #define GEN7_3DPRIM_END_OFFSET 0x2420
2805 #define GEN7_3DPRIM_START_VERTEX 0x2430
2806 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2807 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2808 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2809 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2811 /* MI_MATH only exists on Haswell+ */
2812 #if GEN_IS_HASWELL || GEN_GEN >= 8
2814 /* Emit dwords to multiply GPR0 by N */
2816 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2818 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2820 #define append_alu(opcode, operand1, operand2) \
2821 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2824 unsigned top_bit
= 31 - __builtin_clz(N
);
2825 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2826 /* We get our initial data in GPR0 and we write the final data out to
2827 * GPR0 but we use GPR1 as our scratch register.
2829 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2830 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2832 /* Shift the current value left by 1 */
2833 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2834 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2835 append_alu(MI_ALU_ADD
, 0, 0);
2838 /* Store ACCU to R1 and add R0 to R1 */
2839 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2840 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2841 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2842 append_alu(MI_ALU_ADD
, 0, 0);
2845 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2852 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2854 uint32_t num_dwords
;
2855 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2857 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2858 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2861 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2864 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2865 struct anv_address addr
,
2868 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2870 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, anv_address_add(addr
, 0));
2872 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2873 if (view_count
> 1) {
2874 #if GEN_IS_HASWELL || GEN_GEN >= 8
2875 emit_lrm(batch
, CS_GPR(0), anv_address_add(addr
, 4));
2876 emit_mul_gpr0(batch
, view_count
);
2877 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2879 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2880 "MI_MATH is not supported on Ivy Bridge");
2881 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
2884 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
2887 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, anv_address_add(addr
, 8));
2890 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, anv_address_add(addr
, 12));
2891 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 16));
2893 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 12));
2894 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2898 void genX(CmdDrawIndirect
)(
2899 VkCommandBuffer commandBuffer
,
2901 VkDeviceSize offset
,
2905 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2906 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2907 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2908 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2910 if (anv_batch_has_error(&cmd_buffer
->batch
))
2913 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2915 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2916 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2918 if (vs_prog_data
->uses_firstvertex
||
2919 vs_prog_data
->uses_baseinstance
)
2920 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
2921 if (vs_prog_data
->uses_drawid
)
2922 emit_draw_index(cmd_buffer
, i
);
2924 load_indirect_parameters(cmd_buffer
, draw
, false);
2926 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2927 prim
.IndirectParameterEnable
= true;
2928 prim
.VertexAccessType
= SEQUENTIAL
;
2929 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2936 void genX(CmdDrawIndexedIndirect
)(
2937 VkCommandBuffer commandBuffer
,
2939 VkDeviceSize offset
,
2943 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2944 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2945 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2946 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2948 if (anv_batch_has_error(&cmd_buffer
->batch
))
2951 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2953 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2954 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2956 /* TODO: We need to stomp base vertex to 0 somehow */
2957 if (vs_prog_data
->uses_firstvertex
||
2958 vs_prog_data
->uses_baseinstance
)
2959 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
2960 if (vs_prog_data
->uses_drawid
)
2961 emit_draw_index(cmd_buffer
, i
);
2963 load_indirect_parameters(cmd_buffer
, draw
, true);
2965 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2966 prim
.IndirectParameterEnable
= true;
2967 prim
.VertexAccessType
= RANDOM
;
2968 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2976 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2978 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2979 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2982 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2983 if (result
!= VK_SUCCESS
) {
2984 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2986 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2987 if (result
!= VK_SUCCESS
)
2990 /* Re-emit state base addresses so we get the new surface state base
2991 * address before we start emitting binding tables etc.
2993 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2995 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2996 if (result
!= VK_SUCCESS
) {
2997 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3002 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3003 if (result
!= VK_SUCCESS
) {
3004 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3008 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3009 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3010 .BindingTablePointer
= surfaces
.offset
,
3011 .SamplerStatePointer
= samplers
.offset
,
3013 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3015 struct anv_state state
=
3016 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3017 pipeline
->interface_descriptor_data
,
3018 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3021 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3022 anv_batch_emit(&cmd_buffer
->batch
,
3023 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3024 mid
.InterfaceDescriptorTotalLength
= size
;
3025 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3032 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3034 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3035 MAYBE_UNUSED VkResult result
;
3037 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3039 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3041 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3043 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3044 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3046 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3047 * the only bits that are changed are scoreboard related: Scoreboard
3048 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3049 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3052 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3053 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3055 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3058 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3059 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3060 /* FIXME: figure out descriptors for gen7 */
3061 result
= flush_compute_descriptor_set(cmd_buffer
);
3062 if (result
!= VK_SUCCESS
)
3065 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3068 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3069 struct anv_state push_state
=
3070 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3072 if (push_state
.alloc_size
) {
3073 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3074 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3075 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3079 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3082 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3084 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3090 verify_cmd_parser(const struct anv_device
*device
,
3091 int required_version
,
3092 const char *function
)
3094 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3095 return vk_errorf(device
->instance
, device
->instance
,
3096 VK_ERROR_FEATURE_NOT_PRESENT
,
3097 "cmd parser version %d is required for %s",
3098 required_version
, function
);
3107 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3108 uint32_t baseGroupX
,
3109 uint32_t baseGroupY
,
3110 uint32_t baseGroupZ
)
3112 if (anv_batch_has_error(&cmd_buffer
->batch
))
3116 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3117 base_work_group_id
);
3118 if (result
!= VK_SUCCESS
) {
3119 cmd_buffer
->batch
.status
= result
;
3123 struct anv_push_constants
*push
=
3124 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3125 if (push
->base_work_group_id
[0] != baseGroupX
||
3126 push
->base_work_group_id
[1] != baseGroupY
||
3127 push
->base_work_group_id
[2] != baseGroupZ
) {
3128 push
->base_work_group_id
[0] = baseGroupX
;
3129 push
->base_work_group_id
[1] = baseGroupY
;
3130 push
->base_work_group_id
[2] = baseGroupZ
;
3132 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3136 void genX(CmdDispatch
)(
3137 VkCommandBuffer commandBuffer
,
3142 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3145 void genX(CmdDispatchBase
)(
3146 VkCommandBuffer commandBuffer
,
3147 uint32_t baseGroupX
,
3148 uint32_t baseGroupY
,
3149 uint32_t baseGroupZ
,
3150 uint32_t groupCountX
,
3151 uint32_t groupCountY
,
3152 uint32_t groupCountZ
)
3154 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3155 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3156 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3158 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3159 baseGroupY
, baseGroupZ
);
3161 if (anv_batch_has_error(&cmd_buffer
->batch
))
3164 if (prog_data
->uses_num_work_groups
) {
3165 struct anv_state state
=
3166 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3167 uint32_t *sizes
= state
.map
;
3168 sizes
[0] = groupCountX
;
3169 sizes
[1] = groupCountY
;
3170 sizes
[2] = groupCountZ
;
3171 anv_state_flush(cmd_buffer
->device
, state
);
3172 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3173 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3174 .offset
= state
.offset
,
3178 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3180 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3181 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3182 ggw
.ThreadDepthCounterMaximum
= 0;
3183 ggw
.ThreadHeightCounterMaximum
= 0;
3184 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3185 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3186 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3187 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3188 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3189 ggw
.BottomExecutionMask
= 0xffffffff;
3192 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3195 #define GPGPU_DISPATCHDIMX 0x2500
3196 #define GPGPU_DISPATCHDIMY 0x2504
3197 #define GPGPU_DISPATCHDIMZ 0x2508
3199 void genX(CmdDispatchIndirect
)(
3200 VkCommandBuffer commandBuffer
,
3202 VkDeviceSize offset
)
3204 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3205 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3206 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3207 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3208 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3209 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3211 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3214 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3215 * indirect dispatch registers to be written.
3217 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3218 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3222 if (prog_data
->uses_num_work_groups
)
3223 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3225 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3227 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, anv_address_add(addr
, 0));
3228 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, anv_address_add(addr
, 4));
3229 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, anv_address_add(addr
, 8));
3232 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3233 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3234 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3235 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3237 /* Load compute_dispatch_indirect_x_size into SRC0 */
3238 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 0));
3240 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3241 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3242 mip
.LoadOperation
= LOAD_LOAD
;
3243 mip
.CombineOperation
= COMBINE_SET
;
3244 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3247 /* Load compute_dispatch_indirect_y_size into SRC0 */
3248 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 4));
3250 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3251 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3252 mip
.LoadOperation
= LOAD_LOAD
;
3253 mip
.CombineOperation
= COMBINE_OR
;
3254 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3257 /* Load compute_dispatch_indirect_z_size into SRC0 */
3258 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 8));
3260 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3261 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3262 mip
.LoadOperation
= LOAD_LOAD
;
3263 mip
.CombineOperation
= COMBINE_OR
;
3264 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3267 /* predicate = !predicate; */
3268 #define COMPARE_FALSE 1
3269 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3270 mip
.LoadOperation
= LOAD_LOADINV
;
3271 mip
.CombineOperation
= COMBINE_OR
;
3272 mip
.CompareOperation
= COMPARE_FALSE
;
3276 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3277 ggw
.IndirectParameterEnable
= true;
3278 ggw
.PredicateEnable
= GEN_GEN
<= 7;
3279 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3280 ggw
.ThreadDepthCounterMaximum
= 0;
3281 ggw
.ThreadHeightCounterMaximum
= 0;
3282 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3283 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3284 ggw
.BottomExecutionMask
= 0xffffffff;
3287 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3291 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3294 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3296 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3299 #if GEN_GEN >= 8 && GEN_GEN < 10
3300 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3302 * Software must clear the COLOR_CALC_STATE Valid field in
3303 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3304 * with Pipeline Select set to GPGPU.
3306 * The internal hardware docs recommend the same workaround for Gen9
3309 if (pipeline
== GPGPU
)
3310 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3313 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3314 * PIPELINE_SELECT [DevBWR+]":
3318 * Software must ensure all the write caches are flushed through a
3319 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3320 * command to invalidate read only caches prior to programming
3321 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3323 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3324 pc
.RenderTargetCacheFlushEnable
= true;
3325 pc
.DepthCacheFlushEnable
= true;
3326 pc
.DCFlushEnable
= true;
3327 pc
.PostSyncOperation
= NoWrite
;
3328 pc
.CommandStreamerStallEnable
= true;
3331 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3332 pc
.TextureCacheInvalidationEnable
= true;
3333 pc
.ConstantCacheInvalidationEnable
= true;
3334 pc
.StateCacheInvalidationEnable
= true;
3335 pc
.InstructionCacheInvalidateEnable
= true;
3336 pc
.PostSyncOperation
= NoWrite
;
3339 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3343 ps
.PipelineSelection
= pipeline
;
3347 if (devinfo
->is_geminilake
) {
3350 * "This chicken bit works around a hardware issue with barrier logic
3351 * encountered when switching between GPGPU and 3D pipelines. To
3352 * workaround the issue, this mode bit should be set after a pipeline
3356 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3358 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3359 : GLK_BARRIER_MODE_3D_HULL
,
3360 .GLKBarrierModeMask
= 1);
3361 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3365 cmd_buffer
->state
.current_pipeline
= pipeline
;
3369 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3371 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3375 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3377 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3381 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3386 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3388 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3389 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3390 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3391 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3392 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3393 * Depth Flush Bit set, followed by another pipelined depth stall
3394 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3395 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3396 * via a preceding MI_FLUSH)."
3398 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3399 pipe
.DepthStallEnable
= true;
3401 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3402 pipe
.DepthCacheFlushEnable
= true;
3404 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3405 pipe
.DepthStallEnable
= true;
3410 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3412 struct anv_device
*device
= cmd_buffer
->device
;
3413 const struct anv_image_view
*iview
=
3414 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3415 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3417 /* FIXME: Width and Height are wrong */
3419 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3421 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3422 device
->isl_dev
.ds
.size
/ 4);
3426 struct isl_depth_stencil_hiz_emit_info info
= {
3427 .mocs
= device
->default_mocs
,
3431 info
.view
= &iview
->planes
[0].isl
;
3433 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3434 uint32_t depth_plane
=
3435 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3436 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3438 info
.depth_surf
= &surface
->isl
;
3440 info
.depth_address
=
3441 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3442 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3443 image
->planes
[depth_plane
].address
.bo
,
3444 image
->planes
[depth_plane
].address
.offset
+
3448 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3449 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3450 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3451 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3454 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3455 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3456 image
->planes
[depth_plane
].address
.bo
,
3457 image
->planes
[depth_plane
].address
.offset
+
3458 image
->planes
[depth_plane
].aux_surface
.offset
);
3460 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3464 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3465 uint32_t stencil_plane
=
3466 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3467 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3469 info
.stencil_surf
= &surface
->isl
;
3471 info
.stencil_address
=
3472 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3473 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3474 image
->planes
[stencil_plane
].address
.bo
,
3475 image
->planes
[stencil_plane
].address
.offset
+
3479 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3481 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3485 * This ANDs the view mask of the current subpass with the pending clear
3486 * views in the attachment to get the mask of views active in the subpass
3487 * that still need to be cleared.
3489 static inline uint32_t
3490 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3491 const struct anv_attachment_state
*att_state
)
3493 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3497 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3498 const struct anv_attachment_state
*att_state
)
3500 if (!cmd_state
->subpass
->view_mask
)
3503 uint32_t pending_clear_mask
=
3504 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3506 return pending_clear_mask
& 1;
3510 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3513 const uint32_t last_subpass_idx
=
3514 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3515 const struct anv_subpass
*last_subpass
=
3516 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3517 return last_subpass
== cmd_state
->subpass
;
3521 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3522 uint32_t subpass_id
)
3524 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3525 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3526 cmd_state
->subpass
= subpass
;
3528 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3530 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3531 * different views. If the client asks for instancing, we need to use the
3532 * Instance Data Step Rate to ensure that we repeat the client's
3533 * per-instance data once for each view. Since this bit is in
3534 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3538 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3540 /* It is possible to start a render pass with an old pipeline. Because the
3541 * render pass and subpass index are both baked into the pipeline, this is
3542 * highly unlikely. In order to do so, it requires that you have a render
3543 * pass with a single subpass and that you use that render pass twice
3544 * back-to-back and use the same pipeline at the start of the second render
3545 * pass as at the end of the first. In order to avoid unpredictable issues
3546 * with this edge case, we just dirty the pipeline at the start of every
3549 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3551 /* Accumulate any subpass flushes that need to happen before the subpass */
3552 cmd_buffer
->state
.pending_pipe_bits
|=
3553 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3555 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3556 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3558 bool is_multiview
= subpass
->view_mask
!= 0;
3560 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3561 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3562 if (a
== VK_ATTACHMENT_UNUSED
)
3565 assert(a
< cmd_state
->pass
->attachment_count
);
3566 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3568 struct anv_image_view
*iview
= fb
->attachments
[a
];
3569 const struct anv_image
*image
= iview
->image
;
3571 /* A resolve is necessary before use as an input attachment if the clear
3572 * color or auxiliary buffer usage isn't supported by the sampler.
3574 const bool input_needs_resolve
=
3575 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3576 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3578 VkImageLayout target_layout
;
3579 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3580 !input_needs_resolve
) {
3581 /* Layout transitions before the final only help to enable sampling
3582 * as an input attachment. If the input attachment supports sampling
3583 * using the auxiliary surface, we can skip such transitions by
3584 * making the target layout one that is CCS-aware.
3586 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3588 target_layout
= subpass
->attachments
[i
].layout
;
3591 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3592 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3594 uint32_t base_layer
, layer_count
;
3595 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3597 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3598 iview
->planes
[0].isl
.base_level
);
3600 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3601 layer_count
= fb
->layers
;
3604 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3605 iview
->planes
[0].isl
.base_level
, 1,
3606 base_layer
, layer_count
,
3607 att_state
->current_layout
, target_layout
);
3608 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3609 transition_depth_buffer(cmd_buffer
, image
,
3610 att_state
->current_layout
, target_layout
);
3611 att_state
->aux_usage
=
3612 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3613 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3615 att_state
->current_layout
= target_layout
;
3617 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3618 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3620 /* Multi-planar images are not supported as attachments */
3621 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3622 assert(image
->n_planes
== 1);
3624 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
3625 uint32_t clear_layer_count
= fb
->layers
;
3627 if (att_state
->fast_clear
&&
3628 do_first_layer_clear(cmd_state
, att_state
)) {
3629 /* We only support fast-clears on the first layer */
3630 assert(iview
->planes
[0].isl
.base_level
== 0);
3631 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3633 union isl_color_value clear_color
= {};
3634 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
3635 if (iview
->image
->samples
== 1) {
3636 anv_image_ccs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3637 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3641 anv_image_mcs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3642 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3647 clear_layer_count
--;
3649 att_state
->pending_clear_views
&= ~1;
3651 if (att_state
->clear_color_is_zero
) {
3652 /* This image has the auxiliary buffer enabled. We can mark the
3653 * subresource as not needing a resolve because the clear color
3654 * will match what's in every RENDER_SURFACE_STATE object when
3655 * it's being used for sampling.
3657 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3658 VK_IMAGE_ASPECT_COLOR_BIT
,
3659 ANV_FAST_CLEAR_DEFAULT_VALUE
);
3661 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3662 VK_IMAGE_ASPECT_COLOR_BIT
,
3663 ANV_FAST_CLEAR_ANY
);
3667 /* From the VkFramebufferCreateInfo spec:
3669 * "If the render pass uses multiview, then layers must be one and each
3670 * attachment requires a number of layers that is greater than the
3671 * maximum bit index set in the view mask in the subpasses in which it
3674 * So if multiview is active we ignore the number of layers in the
3675 * framebuffer and instead we honor the view mask from the subpass.
3678 assert(image
->n_planes
== 1);
3679 uint32_t pending_clear_mask
=
3680 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3683 for_each_bit(layer_idx
, pending_clear_mask
) {
3685 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3687 anv_image_clear_color(cmd_buffer
, image
,
3688 VK_IMAGE_ASPECT_COLOR_BIT
,
3689 att_state
->aux_usage
,
3690 iview
->planes
[0].isl
.format
,
3691 iview
->planes
[0].isl
.swizzle
,
3692 iview
->planes
[0].isl
.base_level
,
3695 vk_to_isl_color(att_state
->clear_value
.color
));
3698 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3699 } else if (clear_layer_count
> 0) {
3700 assert(image
->n_planes
== 1);
3701 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3702 att_state
->aux_usage
,
3703 iview
->planes
[0].isl
.format
,
3704 iview
->planes
[0].isl
.swizzle
,
3705 iview
->planes
[0].isl
.base_level
,
3706 base_clear_layer
, clear_layer_count
,
3708 vk_to_isl_color(att_state
->clear_value
.color
));
3710 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
3711 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3712 if (att_state
->fast_clear
&& !is_multiview
) {
3713 /* We currently only support HiZ for single-layer images */
3714 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3715 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
3716 assert(iview
->planes
[0].isl
.base_level
== 0);
3717 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3718 assert(fb
->layers
== 1);
3721 anv_image_hiz_clear(cmd_buffer
, image
,
3722 att_state
->pending_clear_aspects
,
3723 iview
->planes
[0].isl
.base_level
,
3724 iview
->planes
[0].isl
.base_array_layer
,
3725 fb
->layers
, render_area
,
3726 att_state
->clear_value
.depthStencil
.stencil
);
3727 } else if (is_multiview
) {
3728 uint32_t pending_clear_mask
=
3729 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3732 for_each_bit(layer_idx
, pending_clear_mask
) {
3734 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3736 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3737 att_state
->pending_clear_aspects
,
3738 att_state
->aux_usage
,
3739 iview
->planes
[0].isl
.base_level
,
3742 att_state
->clear_value
.depthStencil
.depth
,
3743 att_state
->clear_value
.depthStencil
.stencil
);
3746 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3748 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3749 att_state
->pending_clear_aspects
,
3750 att_state
->aux_usage
,
3751 iview
->planes
[0].isl
.base_level
,
3752 iview
->planes
[0].isl
.base_array_layer
,
3753 fb
->layers
, render_area
,
3754 att_state
->clear_value
.depthStencil
.depth
,
3755 att_state
->clear_value
.depthStencil
.stencil
);
3758 assert(att_state
->pending_clear_aspects
== 0);
3762 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
3763 image
->planes
[0].aux_surface
.isl
.size
> 0 &&
3764 iview
->planes
[0].isl
.base_level
== 0 &&
3765 iview
->planes
[0].isl
.base_array_layer
== 0) {
3766 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
3767 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3768 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3769 false /* copy to ss */);
3772 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
3773 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3774 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3775 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3776 false /* copy to ss */);
3780 if (subpass
->attachments
[i
].usage
==
3781 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
3782 /* We assume that if we're starting a subpass, we're going to do some
3783 * rendering so we may end up with compressed data.
3785 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
3786 VK_IMAGE_ASPECT_COLOR_BIT
,
3787 att_state
->aux_usage
,
3788 iview
->planes
[0].isl
.base_level
,
3789 iview
->planes
[0].isl
.base_array_layer
,
3791 } else if (subpass
->attachments
[i
].usage
==
3792 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
3793 /* We may be writing depth or stencil so we need to mark the surface.
3794 * Unfortunately, there's no way to know at this point whether the
3795 * depth or stencil tests used will actually write to the surface.
3797 * Even though stencil may be plane 1, it always shares a base_level
3800 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
3801 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3802 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3803 VK_IMAGE_ASPECT_DEPTH_BIT
,
3804 att_state
->aux_usage
,
3805 ds_view
->base_level
,
3806 ds_view
->base_array_layer
,
3809 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
3810 /* Even though stencil may be plane 1, it always shares a
3811 * base_level with depth.
3813 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3814 VK_IMAGE_ASPECT_STENCIL_BIT
,
3816 ds_view
->base_level
,
3817 ds_view
->base_array_layer
,
3822 /* If multiview is enabled, then we are only done clearing when we no
3823 * longer have pending layers to clear, or when we have processed the
3824 * last subpass that uses this attachment.
3826 if (!is_multiview
||
3827 att_state
->pending_clear_views
== 0 ||
3828 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
3829 att_state
->pending_clear_aspects
= 0;
3832 att_state
->pending_load_aspects
= 0;
3835 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3839 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
3841 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3842 struct anv_subpass
*subpass
= cmd_state
->subpass
;
3843 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3845 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3847 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3848 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3849 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3850 if (a
== VK_ATTACHMENT_UNUSED
)
3853 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3856 assert(a
< cmd_state
->pass
->attachment_count
);
3857 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3858 struct anv_image_view
*iview
= fb
->attachments
[a
];
3859 const struct anv_image
*image
= iview
->image
;
3861 /* Transition the image into the final layout for this render pass */
3862 VkImageLayout target_layout
=
3863 cmd_state
->pass
->attachments
[a
].final_layout
;
3865 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3866 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3868 uint32_t base_layer
, layer_count
;
3869 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3871 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3872 iview
->planes
[0].isl
.base_level
);
3874 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3875 layer_count
= fb
->layers
;
3878 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3879 iview
->planes
[0].isl
.base_level
, 1,
3880 base_layer
, layer_count
,
3881 att_state
->current_layout
, target_layout
);
3882 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3883 transition_depth_buffer(cmd_buffer
, image
,
3884 att_state
->current_layout
, target_layout
);
3888 /* Accumulate any subpass flushes that need to happen after the subpass.
3889 * Yes, they do get accumulated twice in the NextSubpass case but since
3890 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
3891 * ORing the bits in twice so it's harmless.
3893 cmd_buffer
->state
.pending_pipe_bits
|=
3894 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
3897 void genX(CmdBeginRenderPass
)(
3898 VkCommandBuffer commandBuffer
,
3899 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3900 VkSubpassContents contents
)
3902 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3903 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3904 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3906 cmd_buffer
->state
.framebuffer
= framebuffer
;
3907 cmd_buffer
->state
.pass
= pass
;
3908 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3910 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3912 /* If we failed to setup the attachments we should not try to go further */
3913 if (result
!= VK_SUCCESS
) {
3914 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3918 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3920 cmd_buffer_begin_subpass(cmd_buffer
, 0);
3923 void genX(CmdBeginRenderPass2KHR
)(
3924 VkCommandBuffer commandBuffer
,
3925 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
3926 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
3928 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
3929 pSubpassBeginInfo
->contents
);
3932 void genX(CmdNextSubpass
)(
3933 VkCommandBuffer commandBuffer
,
3934 VkSubpassContents contents
)
3936 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3938 if (anv_batch_has_error(&cmd_buffer
->batch
))
3941 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3943 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
3944 cmd_buffer_end_subpass(cmd_buffer
);
3945 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3948 void genX(CmdNextSubpass2KHR
)(
3949 VkCommandBuffer commandBuffer
,
3950 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
3951 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3953 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
3956 void genX(CmdEndRenderPass
)(
3957 VkCommandBuffer commandBuffer
)
3959 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3961 if (anv_batch_has_error(&cmd_buffer
->batch
))
3964 cmd_buffer_end_subpass(cmd_buffer
);
3966 cmd_buffer
->state
.hiz_enabled
= false;
3969 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
3972 /* Remove references to render pass specific state. This enables us to
3973 * detect whether or not we're in a renderpass.
3975 cmd_buffer
->state
.framebuffer
= NULL
;
3976 cmd_buffer
->state
.pass
= NULL
;
3977 cmd_buffer
->state
.subpass
= NULL
;
3980 void genX(CmdEndRenderPass2KHR
)(
3981 VkCommandBuffer commandBuffer
,
3982 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3984 genX(CmdEndRenderPass
)(commandBuffer
);