intel: Add workaround for stencil state.
[mesa.git] / src / intel / vulkan / genX_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26
27 #include "anv_private.h"
28 #include "vk_format_info.h"
29 #include "vk_util.h"
30 #include "util/fast_idiv_by_const.h"
31
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
36
37 /* We reserve GPR 14 and 15 for conditional rendering */
38 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
39 #define __gen_get_batch_dwords anv_batch_emit_dwords
40 #define __gen_address_offset anv_address_add
41 #include "common/gen_mi_builder.h"
42
43 static void
44 emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
45 {
46 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
47 lri.RegisterOffset = reg;
48 lri.DataDWord = imm;
49 }
50 }
51
52 void
53 genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
54 {
55 struct anv_device *device = cmd_buffer->device;
56 uint32_t mocs = device->isl_dev.mocs.internal;
57
58 /* If we are emitting a new state base address we probably need to re-emit
59 * binding tables.
60 */
61 cmd_buffer->state.descriptors_dirty |= ~0;
62
63 /* Emit a render target cache flush.
64 *
65 * This isn't documented anywhere in the PRM. However, it seems to be
66 * necessary prior to changing the surface state base adress. Without
67 * this, we get GPU hangs when using multi-level command buffers which
68 * clear depth, reset state base address, and then go render stuff.
69 */
70 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
71 pc.DCFlushEnable = true;
72 pc.RenderTargetCacheFlushEnable = true;
73 pc.CommandStreamerStallEnable = true;
74 #if GEN_GEN >= 12
75 pc.TileCacheFlushEnable = true;
76 #endif
77 }
78
79 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
80 sba.GeneralStateBaseAddress = (struct anv_address) { NULL, 0 };
81 sba.GeneralStateMOCS = mocs;
82 sba.GeneralStateBaseAddressModifyEnable = true;
83
84 sba.StatelessDataPortAccessMOCS = mocs;
85
86 sba.SurfaceStateBaseAddress =
87 anv_cmd_buffer_surface_base_address(cmd_buffer);
88 sba.SurfaceStateMOCS = mocs;
89 sba.SurfaceStateBaseAddressModifyEnable = true;
90
91 sba.DynamicStateBaseAddress =
92 (struct anv_address) { device->dynamic_state_pool.block_pool.bo, 0 };
93 sba.DynamicStateMOCS = mocs;
94 sba.DynamicStateBaseAddressModifyEnable = true;
95
96 sba.IndirectObjectBaseAddress = (struct anv_address) { NULL, 0 };
97 sba.IndirectObjectMOCS = mocs;
98 sba.IndirectObjectBaseAddressModifyEnable = true;
99
100 sba.InstructionBaseAddress =
101 (struct anv_address) { device->instruction_state_pool.block_pool.bo, 0 };
102 sba.InstructionMOCS = mocs;
103 sba.InstructionBaseAddressModifyEnable = true;
104
105 # if (GEN_GEN >= 8)
106 /* Broadwell requires that we specify a buffer size for a bunch of
107 * these fields. However, since we will be growing the BO's live, we
108 * just set them all to the maximum.
109 */
110 sba.GeneralStateBufferSize = 0xfffff;
111 sba.GeneralStateBufferSizeModifyEnable = true;
112 sba.DynamicStateBufferSize = 0xfffff;
113 sba.DynamicStateBufferSizeModifyEnable = true;
114 sba.IndirectObjectBufferSize = 0xfffff;
115 sba.IndirectObjectBufferSizeModifyEnable = true;
116 sba.InstructionBufferSize = 0xfffff;
117 sba.InstructionBuffersizeModifyEnable = true;
118 # else
119 /* On gen7, we have upper bounds instead. According to the docs,
120 * setting an upper bound of zero means that no bounds checking is
121 * performed so, in theory, we should be able to leave them zero.
122 * However, border color is broken and the GPU bounds-checks anyway.
123 * To avoid this and other potential problems, we may as well set it
124 * for everything.
125 */
126 sba.GeneralStateAccessUpperBound =
127 (struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
128 sba.GeneralStateAccessUpperBoundModifyEnable = true;
129 sba.DynamicStateAccessUpperBound =
130 (struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
131 sba.DynamicStateAccessUpperBoundModifyEnable = true;
132 sba.InstructionAccessUpperBound =
133 (struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
134 sba.InstructionAccessUpperBoundModifyEnable = true;
135 # endif
136 # if (GEN_GEN >= 9)
137 if (cmd_buffer->device->instance->physicalDevice.use_softpin) {
138 sba.BindlessSurfaceStateBaseAddress = (struct anv_address) {
139 .bo = device->surface_state_pool.block_pool.bo,
140 .offset = 0,
141 };
142 sba.BindlessSurfaceStateSize = (1 << 20) - 1;
143 } else {
144 sba.BindlessSurfaceStateBaseAddress = ANV_NULL_ADDRESS;
145 sba.BindlessSurfaceStateSize = 0;
146 }
147 sba.BindlessSurfaceStateMOCS = mocs;
148 sba.BindlessSurfaceStateBaseAddressModifyEnable = true;
149 # endif
150 # if (GEN_GEN >= 10)
151 sba.BindlessSamplerStateBaseAddress = (struct anv_address) { NULL, 0 };
152 sba.BindlessSamplerStateMOCS = mocs;
153 sba.BindlessSamplerStateBaseAddressModifyEnable = true;
154 sba.BindlessSamplerStateBufferSize = 0;
155 # endif
156 }
157
158 /* After re-setting the surface state base address, we have to do some
159 * cache flusing so that the sampler engine will pick up the new
160 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
161 * Shared Function > 3D Sampler > State > State Caching (page 96):
162 *
163 * Coherency with system memory in the state cache, like the texture
164 * cache is handled partially by software. It is expected that the
165 * command stream or shader will issue Cache Flush operation or
166 * Cache_Flush sampler message to ensure that the L1 cache remains
167 * coherent with system memory.
168 *
169 * [...]
170 *
171 * Whenever the value of the Dynamic_State_Base_Addr,
172 * Surface_State_Base_Addr are altered, the L1 state cache must be
173 * invalidated to ensure the new surface or sampler state is fetched
174 * from system memory.
175 *
176 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
177 * which, according the PIPE_CONTROL instruction documentation in the
178 * Broadwell PRM:
179 *
180 * Setting this bit is independent of any other bit in this packet.
181 * This bit controls the invalidation of the L1 and L2 state caches
182 * at the top of the pipe i.e. at the parsing time.
183 *
184 * Unfortunately, experimentation seems to indicate that state cache
185 * invalidation through a PIPE_CONTROL does nothing whatsoever in
186 * regards to surface state and binding tables. In stead, it seems that
187 * invalidating the texture cache is what is actually needed.
188 *
189 * XXX: As far as we have been able to determine through
190 * experimentation, shows that flush the texture cache appears to be
191 * sufficient. The theory here is that all of the sampling/rendering
192 * units cache the binding table in the texture cache. However, we have
193 * yet to be able to actually confirm this.
194 */
195 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
196 pc.TextureCacheInvalidationEnable = true;
197 pc.ConstantCacheInvalidationEnable = true;
198 pc.StateCacheInvalidationEnable = true;
199 }
200 }
201
202 static void
203 add_surface_reloc(struct anv_cmd_buffer *cmd_buffer,
204 struct anv_state state, struct anv_address addr)
205 {
206 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
207
208 VkResult result =
209 anv_reloc_list_add(&cmd_buffer->surface_relocs, &cmd_buffer->pool->alloc,
210 state.offset + isl_dev->ss.addr_offset,
211 addr.bo, addr.offset, NULL);
212 if (result != VK_SUCCESS)
213 anv_batch_set_error(&cmd_buffer->batch, result);
214 }
215
216 static void
217 add_surface_state_relocs(struct anv_cmd_buffer *cmd_buffer,
218 struct anv_surface_state state)
219 {
220 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
221
222 assert(!anv_address_is_null(state.address));
223 add_surface_reloc(cmd_buffer, state.state, state.address);
224
225 if (!anv_address_is_null(state.aux_address)) {
226 VkResult result =
227 anv_reloc_list_add(&cmd_buffer->surface_relocs,
228 &cmd_buffer->pool->alloc,
229 state.state.offset + isl_dev->ss.aux_addr_offset,
230 state.aux_address.bo,
231 state.aux_address.offset,
232 NULL);
233 if (result != VK_SUCCESS)
234 anv_batch_set_error(&cmd_buffer->batch, result);
235 }
236
237 if (!anv_address_is_null(state.clear_address)) {
238 VkResult result =
239 anv_reloc_list_add(&cmd_buffer->surface_relocs,
240 &cmd_buffer->pool->alloc,
241 state.state.offset +
242 isl_dev->ss.clear_color_state_offset,
243 state.clear_address.bo,
244 state.clear_address.offset,
245 NULL);
246 if (result != VK_SUCCESS)
247 anv_batch_set_error(&cmd_buffer->batch, result);
248 }
249 }
250
251 static void
252 color_attachment_compute_aux_usage(struct anv_device * device,
253 struct anv_cmd_state * cmd_state,
254 uint32_t att, VkRect2D render_area,
255 union isl_color_value *fast_clear_color)
256 {
257 struct anv_attachment_state *att_state = &cmd_state->attachments[att];
258 struct anv_image_view *iview = cmd_state->attachments[att].image_view;
259
260 assert(iview->n_planes == 1);
261
262 if (iview->planes[0].isl.base_array_layer >=
263 anv_image_aux_layers(iview->image, VK_IMAGE_ASPECT_COLOR_BIT,
264 iview->planes[0].isl.base_level)) {
265 /* There is no aux buffer which corresponds to the level and layer(s)
266 * being accessed.
267 */
268 att_state->aux_usage = ISL_AUX_USAGE_NONE;
269 att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
270 att_state->fast_clear = false;
271 return;
272 }
273
274 att_state->aux_usage =
275 anv_layout_to_aux_usage(&device->info, iview->image,
276 VK_IMAGE_ASPECT_COLOR_BIT,
277 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL);
278
279 /* If we don't have aux, then we should have returned early in the layer
280 * check above. If we got here, we must have something.
281 */
282 assert(att_state->aux_usage != ISL_AUX_USAGE_NONE);
283
284 if (att_state->aux_usage == ISL_AUX_USAGE_CCS_E ||
285 att_state->aux_usage == ISL_AUX_USAGE_MCS) {
286 att_state->input_aux_usage = att_state->aux_usage;
287 } else {
288 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
289 *
290 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
291 * setting is only allowed if Surface Format supported for Fast
292 * Clear. In addition, if the surface is bound to the sampling
293 * engine, Surface Format must be supported for Render Target
294 * Compression for surfaces bound to the sampling engine."
295 *
296 * In other words, we can only sample from a fast-cleared image if it
297 * also supports color compression.
298 */
299 if (isl_format_supports_ccs_e(&device->info, iview->planes[0].isl.format) &&
300 isl_format_supports_ccs_d(&device->info, iview->planes[0].isl.format)) {
301 att_state->input_aux_usage = ISL_AUX_USAGE_CCS_D;
302
303 /* While fast-clear resolves and partial resolves are fairly cheap in the
304 * case where you render to most of the pixels, full resolves are not
305 * because they potentially involve reading and writing the entire
306 * framebuffer. If we can't texture with CCS_E, we should leave it off and
307 * limit ourselves to fast clears.
308 */
309 if (cmd_state->pass->attachments[att].first_subpass_layout ==
310 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL) {
311 anv_perf_warn(device->instance, iview->image,
312 "Not temporarily enabling CCS_E.");
313 }
314 } else {
315 att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
316 }
317 }
318
319 assert(iview->image->planes[0].aux_surface.isl.usage &
320 (ISL_SURF_USAGE_CCS_BIT | ISL_SURF_USAGE_MCS_BIT));
321
322 union isl_color_value clear_color = {};
323 anv_clear_color_from_att_state(&clear_color, att_state, iview);
324
325 att_state->clear_color_is_zero_one =
326 isl_color_value_is_zero_one(clear_color, iview->planes[0].isl.format);
327 att_state->clear_color_is_zero =
328 isl_color_value_is_zero(clear_color, iview->planes[0].isl.format);
329
330 if (att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
331 /* Start by getting the fast clear type. We use the first subpass
332 * layout here because we don't want to fast-clear if the first subpass
333 * to use the attachment can't handle fast-clears.
334 */
335 enum anv_fast_clear_type fast_clear_type =
336 anv_layout_to_fast_clear_type(&device->info, iview->image,
337 VK_IMAGE_ASPECT_COLOR_BIT,
338 cmd_state->pass->attachments[att].first_subpass_layout);
339 switch (fast_clear_type) {
340 case ANV_FAST_CLEAR_NONE:
341 att_state->fast_clear = false;
342 break;
343 case ANV_FAST_CLEAR_DEFAULT_VALUE:
344 att_state->fast_clear = att_state->clear_color_is_zero;
345 break;
346 case ANV_FAST_CLEAR_ANY:
347 att_state->fast_clear = true;
348 break;
349 }
350
351 /* Potentially, we could do partial fast-clears but doing so has crazy
352 * alignment restrictions. It's easier to just restrict to full size
353 * fast clears for now.
354 */
355 if (render_area.offset.x != 0 ||
356 render_area.offset.y != 0 ||
357 render_area.extent.width != iview->extent.width ||
358 render_area.extent.height != iview->extent.height)
359 att_state->fast_clear = false;
360
361 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
362 if (GEN_GEN <= 8 && !att_state->clear_color_is_zero_one)
363 att_state->fast_clear = false;
364
365 /* We only allow fast clears to the first slice of an image (level 0,
366 * layer 0) and only for the entire slice. This guarantees us that, at
367 * any given time, there is only one clear color on any given image at
368 * any given time. At the time of our testing (Jan 17, 2018), there
369 * were no known applications which would benefit from fast-clearing
370 * more than just the first slice.
371 */
372 if (att_state->fast_clear &&
373 (iview->planes[0].isl.base_level > 0 ||
374 iview->planes[0].isl.base_array_layer > 0)) {
375 anv_perf_warn(device->instance, iview->image,
376 "Rendering with multi-lod or multi-layer framebuffer "
377 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
378 "baseArrayLayer > 0. Not fast clearing.");
379 att_state->fast_clear = false;
380 } else if (att_state->fast_clear && cmd_state->framebuffer->layers > 1) {
381 anv_perf_warn(device->instance, iview->image,
382 "Rendering to a multi-layer framebuffer with "
383 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
384 }
385
386 if (att_state->fast_clear)
387 *fast_clear_color = clear_color;
388 } else {
389 att_state->fast_clear = false;
390 }
391 }
392
393 static void
394 depth_stencil_attachment_compute_aux_usage(struct anv_device *device,
395 struct anv_cmd_state *cmd_state,
396 uint32_t att, VkRect2D render_area)
397 {
398 struct anv_render_pass_attachment *pass_att =
399 &cmd_state->pass->attachments[att];
400 struct anv_attachment_state *att_state = &cmd_state->attachments[att];
401 struct anv_image_view *iview = cmd_state->attachments[att].image_view;
402
403 /* These will be initialized after the first subpass transition. */
404 att_state->aux_usage = ISL_AUX_USAGE_NONE;
405 att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
406
407 if (GEN_GEN == 7) {
408 /* We don't do any HiZ or depth fast-clears on gen7 yet */
409 att_state->fast_clear = false;
410 return;
411 }
412
413 if (!(att_state->pending_clear_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
414 /* If we're just clearing stencil, we can always HiZ clear */
415 att_state->fast_clear = true;
416 return;
417 }
418
419 /* Default to false for now */
420 att_state->fast_clear = false;
421
422 /* We must have depth in order to have HiZ */
423 if (!(iview->image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
424 return;
425
426 const enum isl_aux_usage first_subpass_aux_usage =
427 anv_layout_to_aux_usage(&device->info, iview->image,
428 VK_IMAGE_ASPECT_DEPTH_BIT,
429 pass_att->first_subpass_layout);
430 if (!blorp_can_hiz_clear_depth(&device->info,
431 &iview->image->planes[0].surface.isl,
432 first_subpass_aux_usage,
433 iview->planes[0].isl.base_level,
434 iview->planes[0].isl.base_array_layer,
435 render_area.offset.x,
436 render_area.offset.y,
437 render_area.offset.x +
438 render_area.extent.width,
439 render_area.offset.y +
440 render_area.extent.height))
441 return;
442
443 if (att_state->clear_value.depthStencil.depth != ANV_HZ_FC_VAL)
444 return;
445
446 if (GEN_GEN == 8 && anv_can_sample_with_hiz(&device->info, iview->image)) {
447 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
448 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
449 * only supports returning 0.0f. Gens prior to gen8 do not support this
450 * feature at all.
451 */
452 return;
453 }
454
455 /* If we got here, then we can fast clear */
456 att_state->fast_clear = true;
457 }
458
459 static bool
460 need_input_attachment_state(const struct anv_render_pass_attachment *att)
461 {
462 if (!(att->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT))
463 return false;
464
465 /* We only allocate input attachment states for color surfaces. Compression
466 * is not yet enabled for depth textures and stencil doesn't allow
467 * compression so we can just use the texture surface state from the view.
468 */
469 return vk_format_is_color(att->format);
470 }
471
472 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
473 * the initial layout is undefined, the HiZ buffer and depth buffer will
474 * represent the same data at the end of this operation.
475 */
476 static void
477 transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
478 const struct anv_image *image,
479 VkImageLayout initial_layout,
480 VkImageLayout final_layout)
481 {
482 const bool hiz_enabled = ISL_AUX_USAGE_HIZ ==
483 anv_layout_to_aux_usage(&cmd_buffer->device->info, image,
484 VK_IMAGE_ASPECT_DEPTH_BIT, initial_layout);
485 const bool enable_hiz = ISL_AUX_USAGE_HIZ ==
486 anv_layout_to_aux_usage(&cmd_buffer->device->info, image,
487 VK_IMAGE_ASPECT_DEPTH_BIT, final_layout);
488
489 enum isl_aux_op hiz_op;
490 if (hiz_enabled && !enable_hiz) {
491 hiz_op = ISL_AUX_OP_FULL_RESOLVE;
492 } else if (!hiz_enabled && enable_hiz) {
493 hiz_op = ISL_AUX_OP_AMBIGUATE;
494 } else {
495 assert(hiz_enabled == enable_hiz);
496 /* If the same buffer will be used, no resolves are necessary. */
497 hiz_op = ISL_AUX_OP_NONE;
498 }
499
500 if (hiz_op != ISL_AUX_OP_NONE)
501 anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
502 0, 0, 1, hiz_op);
503 }
504
505 static inline bool
506 vk_image_layout_stencil_write_optimal(VkImageLayout layout)
507 {
508 return layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
509 layout == VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL ||
510 layout == VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR;
511 }
512
513 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
514 * the initial layout is undefined, the HiZ buffer and depth buffer will
515 * represent the same data at the end of this operation.
516 */
517 static void
518 transition_stencil_buffer(struct anv_cmd_buffer *cmd_buffer,
519 const struct anv_image *image,
520 uint32_t base_level, uint32_t level_count,
521 uint32_t base_layer, uint32_t layer_count,
522 VkImageLayout initial_layout,
523 VkImageLayout final_layout)
524 {
525 #if GEN_GEN == 7
526 uint32_t plane = anv_image_aspect_to_plane(image->aspects,
527 VK_IMAGE_ASPECT_STENCIL_BIT);
528
529 /* On gen7, we have to store a texturable version of the stencil buffer in
530 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
531 * forth at strategic points. Stencil writes are only allowed in following
532 * layouts:
533 *
534 * - VK_IMAGE_LAYOUT_GENERAL
535 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
536 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
537 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
538 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
539 *
540 * For general, we have no nice opportunity to transition so we do the copy
541 * to the shadow unconditionally at the end of the subpass. For transfer
542 * destinations, we can update it as part of the transfer op. For the other
543 * layouts, we delay the copy until a transition into some other layout.
544 */
545 if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
546 vk_image_layout_stencil_write_optimal(initial_layout) &&
547 !vk_image_layout_stencil_write_optimal(final_layout)) {
548 anv_image_copy_to_shadow(cmd_buffer, image,
549 VK_IMAGE_ASPECT_STENCIL_BIT,
550 base_level, level_count,
551 base_layer, layer_count);
552 }
553 #endif /* GEN_GEN == 7 */
554 }
555
556 #define MI_PREDICATE_SRC0 0x2400
557 #define MI_PREDICATE_SRC1 0x2408
558 #define MI_PREDICATE_RESULT 0x2418
559
560 static void
561 set_image_compressed_bit(struct anv_cmd_buffer *cmd_buffer,
562 const struct anv_image *image,
563 VkImageAspectFlagBits aspect,
564 uint32_t level,
565 uint32_t base_layer, uint32_t layer_count,
566 bool compressed)
567 {
568 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
569
570 /* We only have compression tracking for CCS_E */
571 if (image->planes[plane].aux_usage != ISL_AUX_USAGE_CCS_E)
572 return;
573
574 for (uint32_t a = 0; a < layer_count; a++) {
575 uint32_t layer = base_layer + a;
576 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
577 sdi.Address = anv_image_get_compression_state_addr(cmd_buffer->device,
578 image, aspect,
579 level, layer);
580 sdi.ImmediateData = compressed ? UINT32_MAX : 0;
581 }
582 }
583 }
584
585 static void
586 set_image_fast_clear_state(struct anv_cmd_buffer *cmd_buffer,
587 const struct anv_image *image,
588 VkImageAspectFlagBits aspect,
589 enum anv_fast_clear_type fast_clear)
590 {
591 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
592 sdi.Address = anv_image_get_fast_clear_type_addr(cmd_buffer->device,
593 image, aspect);
594 sdi.ImmediateData = fast_clear;
595 }
596
597 /* Whenever we have fast-clear, we consider that slice to be compressed.
598 * This makes building predicates much easier.
599 */
600 if (fast_clear != ANV_FAST_CLEAR_NONE)
601 set_image_compressed_bit(cmd_buffer, image, aspect, 0, 0, 1, true);
602 }
603
604 /* This is only really practical on haswell and above because it requires
605 * MI math in order to get it correct.
606 */
607 #if GEN_GEN >= 8 || GEN_IS_HASWELL
608 static void
609 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
610 const struct anv_image *image,
611 VkImageAspectFlagBits aspect,
612 uint32_t level, uint32_t array_layer,
613 enum isl_aux_op resolve_op,
614 enum anv_fast_clear_type fast_clear_supported)
615 {
616 struct gen_mi_builder b;
617 gen_mi_builder_init(&b, &cmd_buffer->batch);
618
619 const struct gen_mi_value fast_clear_type =
620 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer->device,
621 image, aspect));
622
623 if (resolve_op == ISL_AUX_OP_FULL_RESOLVE) {
624 /* In this case, we're doing a full resolve which means we want the
625 * resolve to happen if any compression (including fast-clears) is
626 * present.
627 *
628 * In order to simplify the logic a bit, we make the assumption that,
629 * if the first slice has been fast-cleared, it is also marked as
630 * compressed. See also set_image_fast_clear_state.
631 */
632 const struct gen_mi_value compression_state =
633 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer->device,
634 image, aspect,
635 level, array_layer));
636 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
637 compression_state);
638 gen_mi_store(&b, compression_state, gen_mi_imm(0));
639
640 if (level == 0 && array_layer == 0) {
641 /* If the predicate is true, we want to write 0 to the fast clear type
642 * and, if it's false, leave it alone. We can do this by writing
643 *
644 * clear_type = clear_type & ~predicate;
645 */
646 struct gen_mi_value new_fast_clear_type =
647 gen_mi_iand(&b, fast_clear_type,
648 gen_mi_inot(&b, gen_mi_reg64(MI_PREDICATE_SRC0)));
649 gen_mi_store(&b, fast_clear_type, new_fast_clear_type);
650 }
651 } else if (level == 0 && array_layer == 0) {
652 /* In this case, we are doing a partial resolve to get rid of fast-clear
653 * colors. We don't care about the compression state but we do care
654 * about how much fast clear is allowed by the final layout.
655 */
656 assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
657 assert(fast_clear_supported < ANV_FAST_CLEAR_ANY);
658
659 /* We need to compute (fast_clear_supported < image->fast_clear) */
660 struct gen_mi_value pred =
661 gen_mi_ult(&b, gen_mi_imm(fast_clear_supported), fast_clear_type);
662 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
663 gen_mi_value_ref(&b, pred));
664
665 /* If the predicate is true, we want to write 0 to the fast clear type
666 * and, if it's false, leave it alone. We can do this by writing
667 *
668 * clear_type = clear_type & ~predicate;
669 */
670 struct gen_mi_value new_fast_clear_type =
671 gen_mi_iand(&b, fast_clear_type, gen_mi_inot(&b, pred));
672 gen_mi_store(&b, fast_clear_type, new_fast_clear_type);
673 } else {
674 /* In this case, we're trying to do a partial resolve on a slice that
675 * doesn't have clear color. There's nothing to do.
676 */
677 assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
678 return;
679 }
680
681 /* Set src1 to 0 and use a != condition */
682 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
683
684 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
685 mip.LoadOperation = LOAD_LOADINV;
686 mip.CombineOperation = COMBINE_SET;
687 mip.CompareOperation = COMPARE_SRCS_EQUAL;
688 }
689 }
690 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
691
692 #if GEN_GEN <= 8
693 static void
694 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
695 const struct anv_image *image,
696 VkImageAspectFlagBits aspect,
697 uint32_t level, uint32_t array_layer,
698 enum isl_aux_op resolve_op,
699 enum anv_fast_clear_type fast_clear_supported)
700 {
701 struct gen_mi_builder b;
702 gen_mi_builder_init(&b, &cmd_buffer->batch);
703
704 struct gen_mi_value fast_clear_type_mem =
705 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer->device,
706 image, aspect));
707
708 /* This only works for partial resolves and only when the clear color is
709 * all or nothing. On the upside, this emits less command streamer code
710 * and works on Ivybridge and Bay Trail.
711 */
712 assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
713 assert(fast_clear_supported != ANV_FAST_CLEAR_ANY);
714
715 /* We don't support fast clears on anything other than the first slice. */
716 if (level > 0 || array_layer > 0)
717 return;
718
719 /* On gen8, we don't have a concept of default clear colors because we
720 * can't sample from CCS surfaces. It's enough to just load the fast clear
721 * state into the predicate register.
722 */
723 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), fast_clear_type_mem);
724 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
725 gen_mi_store(&b, fast_clear_type_mem, gen_mi_imm(0));
726
727 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
728 mip.LoadOperation = LOAD_LOADINV;
729 mip.CombineOperation = COMBINE_SET;
730 mip.CompareOperation = COMPARE_SRCS_EQUAL;
731 }
732 }
733 #endif /* GEN_GEN <= 8 */
734
735 static void
736 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer *cmd_buffer,
737 const struct anv_image *image,
738 enum isl_format format,
739 VkImageAspectFlagBits aspect,
740 uint32_t level, uint32_t array_layer,
741 enum isl_aux_op resolve_op,
742 enum anv_fast_clear_type fast_clear_supported)
743 {
744 const uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
745
746 #if GEN_GEN >= 9
747 anv_cmd_compute_resolve_predicate(cmd_buffer, image,
748 aspect, level, array_layer,
749 resolve_op, fast_clear_supported);
750 #else /* GEN_GEN <= 8 */
751 anv_cmd_simple_resolve_predicate(cmd_buffer, image,
752 aspect, level, array_layer,
753 resolve_op, fast_clear_supported);
754 #endif
755
756 /* CCS_D only supports full resolves and BLORP will assert on us if we try
757 * to do a partial resolve on a CCS_D surface.
758 */
759 if (resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE &&
760 image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE)
761 resolve_op = ISL_AUX_OP_FULL_RESOLVE;
762
763 anv_image_ccs_op(cmd_buffer, image, format, aspect, level,
764 array_layer, 1, resolve_op, NULL, true);
765 }
766
767 static void
768 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer *cmd_buffer,
769 const struct anv_image *image,
770 enum isl_format format,
771 VkImageAspectFlagBits aspect,
772 uint32_t array_layer,
773 enum isl_aux_op resolve_op,
774 enum anv_fast_clear_type fast_clear_supported)
775 {
776 assert(aspect == VK_IMAGE_ASPECT_COLOR_BIT);
777 assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
778
779 #if GEN_GEN >= 8 || GEN_IS_HASWELL
780 anv_cmd_compute_resolve_predicate(cmd_buffer, image,
781 aspect, 0, array_layer,
782 resolve_op, fast_clear_supported);
783
784 anv_image_mcs_op(cmd_buffer, image, format, aspect,
785 array_layer, 1, resolve_op, NULL, true);
786 #else
787 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
788 #endif
789 }
790
791 void
792 genX(cmd_buffer_mark_image_written)(struct anv_cmd_buffer *cmd_buffer,
793 const struct anv_image *image,
794 VkImageAspectFlagBits aspect,
795 enum isl_aux_usage aux_usage,
796 uint32_t level,
797 uint32_t base_layer,
798 uint32_t layer_count)
799 {
800 /* The aspect must be exactly one of the image aspects. */
801 assert(util_bitcount(aspect) == 1 && (aspect & image->aspects));
802
803 /* The only compression types with more than just fast-clears are MCS,
804 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
805 * track the current fast-clear and compression state. This leaves us
806 * with just MCS and CCS_E.
807 */
808 if (aux_usage != ISL_AUX_USAGE_CCS_E &&
809 aux_usage != ISL_AUX_USAGE_MCS)
810 return;
811
812 set_image_compressed_bit(cmd_buffer, image, aspect,
813 level, base_layer, layer_count, true);
814 }
815
816 static void
817 init_fast_clear_color(struct anv_cmd_buffer *cmd_buffer,
818 const struct anv_image *image,
819 VkImageAspectFlagBits aspect)
820 {
821 assert(cmd_buffer && image);
822 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
823
824 set_image_fast_clear_state(cmd_buffer, image, aspect,
825 ANV_FAST_CLEAR_NONE);
826
827 /* Initialize the struct fields that are accessed for fast-clears so that
828 * the HW restrictions on the field values are satisfied.
829 */
830 struct anv_address addr =
831 anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
832
833 if (GEN_GEN >= 9) {
834 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
835 const unsigned num_dwords = GEN_GEN >= 10 ?
836 isl_dev->ss.clear_color_state_size / 4 :
837 isl_dev->ss.clear_value_size / 4;
838 for (unsigned i = 0; i < num_dwords; i++) {
839 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
840 sdi.Address = addr;
841 sdi.Address.offset += i * 4;
842 sdi.ImmediateData = 0;
843 }
844 }
845 } else {
846 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
847 sdi.Address = addr;
848 if (GEN_GEN >= 8 || GEN_IS_HASWELL) {
849 /* Pre-SKL, the dword containing the clear values also contains
850 * other fields, so we need to initialize those fields to match the
851 * values that would be in a color attachment.
852 */
853 sdi.ImmediateData = ISL_CHANNEL_SELECT_RED << 25 |
854 ISL_CHANNEL_SELECT_GREEN << 22 |
855 ISL_CHANNEL_SELECT_BLUE << 19 |
856 ISL_CHANNEL_SELECT_ALPHA << 16;
857 } else if (GEN_GEN == 7) {
858 /* On IVB, the dword containing the clear values also contains
859 * other fields that must be zero or can be zero.
860 */
861 sdi.ImmediateData = 0;
862 }
863 }
864 }
865 }
866
867 /* Copy the fast-clear value dword(s) between a surface state object and an
868 * image's fast clear state buffer.
869 */
870 static void
871 genX(copy_fast_clear_dwords)(struct anv_cmd_buffer *cmd_buffer,
872 struct anv_state surface_state,
873 const struct anv_image *image,
874 VkImageAspectFlagBits aspect,
875 bool copy_from_surface_state)
876 {
877 assert(cmd_buffer && image);
878 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
879
880 struct anv_address ss_clear_addr = {
881 .bo = cmd_buffer->device->surface_state_pool.block_pool.bo,
882 .offset = surface_state.offset +
883 cmd_buffer->device->isl_dev.ss.clear_value_offset,
884 };
885 const struct anv_address entry_addr =
886 anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
887 unsigned copy_size = cmd_buffer->device->isl_dev.ss.clear_value_size;
888
889 #if GEN_GEN == 7
890 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
891 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
892 * in-flight when they are issued even if the memory touched is not
893 * currently active for rendering. The weird bit is that it is not the
894 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
895 * rendering hangs such that the next stalling command after the
896 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
897 *
898 * It is unclear exactly why this hang occurs. Both MI commands come with
899 * warnings about the 3D pipeline but that doesn't seem to fully explain
900 * it. My (Jason's) best theory is that it has something to do with the
901 * fact that we're using a GPU state register as our temporary and that
902 * something with reading/writing it is causing problems.
903 *
904 * In order to work around this issue, we emit a PIPE_CONTROL with the
905 * command streamer stall bit set.
906 */
907 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
908 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
909 #endif
910
911 struct gen_mi_builder b;
912 gen_mi_builder_init(&b, &cmd_buffer->batch);
913
914 if (copy_from_surface_state) {
915 gen_mi_memcpy(&b, entry_addr, ss_clear_addr, copy_size);
916 } else {
917 gen_mi_memcpy(&b, ss_clear_addr, entry_addr, copy_size);
918
919 /* Updating a surface state object may require that the state cache be
920 * invalidated. From the SKL PRM, Shared Functions -> State -> State
921 * Caching:
922 *
923 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
924 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
925 * modified [...], the L1 state cache must be invalidated to ensure
926 * the new surface or sampler state is fetched from system memory.
927 *
928 * In testing, SKL doesn't actually seem to need this, but HSW does.
929 */
930 cmd_buffer->state.pending_pipe_bits |=
931 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
932 }
933 }
934
935 /**
936 * @brief Transitions a color buffer from one layout to another.
937 *
938 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
939 * more information.
940 *
941 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
942 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
943 * this represents the maximum layers to transition at each
944 * specified miplevel.
945 */
946 static void
947 transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
948 const struct anv_image *image,
949 VkImageAspectFlagBits aspect,
950 const uint32_t base_level, uint32_t level_count,
951 uint32_t base_layer, uint32_t layer_count,
952 VkImageLayout initial_layout,
953 VkImageLayout final_layout)
954 {
955 const struct gen_device_info *devinfo = &cmd_buffer->device->info;
956 /* Validate the inputs. */
957 assert(cmd_buffer);
958 assert(image && image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
959 /* These values aren't supported for simplicity's sake. */
960 assert(level_count != VK_REMAINING_MIP_LEVELS &&
961 layer_count != VK_REMAINING_ARRAY_LAYERS);
962 /* Ensure the subresource range is valid. */
963 UNUSED uint64_t last_level_num = base_level + level_count;
964 const uint32_t max_depth = anv_minify(image->extent.depth, base_level);
965 UNUSED const uint32_t image_layers = MAX2(image->array_size, max_depth);
966 assert((uint64_t)base_layer + layer_count <= image_layers);
967 assert(last_level_num <= image->levels);
968 /* The spec disallows these final layouts. */
969 assert(final_layout != VK_IMAGE_LAYOUT_UNDEFINED &&
970 final_layout != VK_IMAGE_LAYOUT_PREINITIALIZED);
971
972 /* No work is necessary if the layout stays the same or if this subresource
973 * range lacks auxiliary data.
974 */
975 if (initial_layout == final_layout)
976 return;
977
978 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
979
980 if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
981 final_layout == VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL) {
982 /* This surface is a linear compressed image with a tiled shadow surface
983 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
984 * we need to ensure the shadow copy is up-to-date.
985 */
986 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
987 assert(image->planes[plane].surface.isl.tiling == ISL_TILING_LINEAR);
988 assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR);
989 assert(isl_format_is_compressed(image->planes[plane].surface.isl.format));
990 assert(plane == 0);
991 anv_image_copy_to_shadow(cmd_buffer, image,
992 VK_IMAGE_ASPECT_COLOR_BIT,
993 base_level, level_count,
994 base_layer, layer_count);
995 }
996
997 if (base_layer >= anv_image_aux_layers(image, aspect, base_level))
998 return;
999
1000 assert(image->tiling == VK_IMAGE_TILING_OPTIMAL);
1001
1002 if (initial_layout == VK_IMAGE_LAYOUT_UNDEFINED ||
1003 initial_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
1004 /* A subresource in the undefined layout may have been aliased and
1005 * populated with any arrangement of bits. Therefore, we must initialize
1006 * the related aux buffer and clear buffer entry with desirable values.
1007 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1008 * images with VK_IMAGE_TILING_OPTIMAL.
1009 *
1010 * Initialize the relevant clear buffer entries.
1011 */
1012 if (base_level == 0 && base_layer == 0)
1013 init_fast_clear_color(cmd_buffer, image, aspect);
1014
1015 /* Initialize the aux buffers to enable correct rendering. In order to
1016 * ensure that things such as storage images work correctly, aux buffers
1017 * need to be initialized to valid data.
1018 *
1019 * Having an aux buffer with invalid data is a problem for two reasons:
1020 *
1021 * 1) Having an invalid value in the buffer can confuse the hardware.
1022 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1023 * invalid and leads to the hardware doing strange things. It
1024 * doesn't hang as far as we can tell but rendering corruption can
1025 * occur.
1026 *
1027 * 2) If this transition is into the GENERAL layout and we then use the
1028 * image as a storage image, then we must have the aux buffer in the
1029 * pass-through state so that, if we then go to texture from the
1030 * image, we get the results of our storage image writes and not the
1031 * fast clear color or other random data.
1032 *
1033 * For CCS both of the problems above are real demonstrable issues. In
1034 * that case, the only thing we can do is to perform an ambiguate to
1035 * transition the aux surface into the pass-through state.
1036 *
1037 * For MCS, (2) is never an issue because we don't support multisampled
1038 * storage images. In theory, issue (1) is a problem with MCS but we've
1039 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1040 * theory, be interpreted as something but we don't know that all bit
1041 * patterns are actually valid. For 2x and 8x, you could easily end up
1042 * with the MCS referring to an invalid plane because not all bits of
1043 * the MCS value are actually used. Even though we've never seen issues
1044 * in the wild, it's best to play it safe and initialize the MCS. We
1045 * can use a fast-clear for MCS because we only ever touch from render
1046 * and texture (no image load store).
1047 */
1048 if (image->samples == 1) {
1049 for (uint32_t l = 0; l < level_count; l++) {
1050 const uint32_t level = base_level + l;
1051
1052 uint32_t aux_layers = anv_image_aux_layers(image, aspect, level);
1053 if (base_layer >= aux_layers)
1054 break; /* We will only get fewer layers as level increases */
1055 uint32_t level_layer_count =
1056 MIN2(layer_count, aux_layers - base_layer);
1057
1058 anv_image_ccs_op(cmd_buffer, image,
1059 image->planes[plane].surface.isl.format,
1060 aspect, level, base_layer, level_layer_count,
1061 ISL_AUX_OP_AMBIGUATE, NULL, false);
1062
1063 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) {
1064 set_image_compressed_bit(cmd_buffer, image, aspect,
1065 level, base_layer, level_layer_count,
1066 false);
1067 }
1068 }
1069 } else {
1070 if (image->samples == 4 || image->samples == 16) {
1071 anv_perf_warn(cmd_buffer->device->instance, image,
1072 "Doing a potentially unnecessary fast-clear to "
1073 "define an MCS buffer.");
1074 }
1075
1076 assert(base_level == 0 && level_count == 1);
1077 anv_image_mcs_op(cmd_buffer, image,
1078 image->planes[plane].surface.isl.format,
1079 aspect, base_layer, layer_count,
1080 ISL_AUX_OP_FAST_CLEAR, NULL, false);
1081 }
1082 return;
1083 }
1084
1085 const enum isl_aux_usage initial_aux_usage =
1086 anv_layout_to_aux_usage(devinfo, image, aspect, initial_layout);
1087 const enum isl_aux_usage final_aux_usage =
1088 anv_layout_to_aux_usage(devinfo, image, aspect, final_layout);
1089
1090 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1091 * We can handle transitions between CCS_D/E to and from NONE. What we
1092 * don't yet handle is switching between CCS_E and CCS_D within a given
1093 * image. Doing so in a performant way requires more detailed aux state
1094 * tracking such as what is done in i965. For now, just assume that we
1095 * only have one type of compression.
1096 */
1097 assert(initial_aux_usage == ISL_AUX_USAGE_NONE ||
1098 final_aux_usage == ISL_AUX_USAGE_NONE ||
1099 initial_aux_usage == final_aux_usage);
1100
1101 /* If initial aux usage is NONE, there is nothing to resolve */
1102 if (initial_aux_usage == ISL_AUX_USAGE_NONE)
1103 return;
1104
1105 enum isl_aux_op resolve_op = ISL_AUX_OP_NONE;
1106
1107 /* If the initial layout supports more fast clear than the final layout
1108 * then we need at least a partial resolve.
1109 */
1110 const enum anv_fast_clear_type initial_fast_clear =
1111 anv_layout_to_fast_clear_type(devinfo, image, aspect, initial_layout);
1112 const enum anv_fast_clear_type final_fast_clear =
1113 anv_layout_to_fast_clear_type(devinfo, image, aspect, final_layout);
1114 if (final_fast_clear < initial_fast_clear)
1115 resolve_op = ISL_AUX_OP_PARTIAL_RESOLVE;
1116
1117 if (initial_aux_usage == ISL_AUX_USAGE_CCS_E &&
1118 final_aux_usage != ISL_AUX_USAGE_CCS_E)
1119 resolve_op = ISL_AUX_OP_FULL_RESOLVE;
1120
1121 if (resolve_op == ISL_AUX_OP_NONE)
1122 return;
1123
1124 /* Perform a resolve to synchronize data between the main and aux buffer.
1125 * Before we begin, we must satisfy the cache flushing requirement specified
1126 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1127 *
1128 * Any transition from any value in {Clear, Render, Resolve} to a
1129 * different value in {Clear, Render, Resolve} requires end of pipe
1130 * synchronization.
1131 *
1132 * We perform a flush of the write cache before and after the clear and
1133 * resolve operations to meet this requirement.
1134 *
1135 * Unlike other drawing, fast clear operations are not properly
1136 * synchronized. The first PIPE_CONTROL here likely ensures that the
1137 * contents of the previous render or clear hit the render target before we
1138 * resolve and the second likely ensures that the resolve is complete before
1139 * we do any more rendering or clearing.
1140 */
1141 cmd_buffer->state.pending_pipe_bits |=
1142 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1143
1144 for (uint32_t l = 0; l < level_count; l++) {
1145 uint32_t level = base_level + l;
1146
1147 uint32_t aux_layers = anv_image_aux_layers(image, aspect, level);
1148 if (base_layer >= aux_layers)
1149 break; /* We will only get fewer layers as level increases */
1150 uint32_t level_layer_count =
1151 MIN2(layer_count, aux_layers - base_layer);
1152
1153 for (uint32_t a = 0; a < level_layer_count; a++) {
1154 uint32_t array_layer = base_layer + a;
1155 if (image->samples == 1) {
1156 anv_cmd_predicated_ccs_resolve(cmd_buffer, image,
1157 image->planes[plane].surface.isl.format,
1158 aspect, level, array_layer, resolve_op,
1159 final_fast_clear);
1160 } else {
1161 /* We only support fast-clear on the first layer so partial
1162 * resolves should not be used on other layers as they will use
1163 * the clear color stored in memory that is only valid for layer0.
1164 */
1165 if (resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE &&
1166 array_layer != 0)
1167 continue;
1168
1169 anv_cmd_predicated_mcs_resolve(cmd_buffer, image,
1170 image->planes[plane].surface.isl.format,
1171 aspect, array_layer, resolve_op,
1172 final_fast_clear);
1173 }
1174 }
1175 }
1176
1177 cmd_buffer->state.pending_pipe_bits |=
1178 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1179 }
1180
1181 /**
1182 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1183 */
1184 static VkResult
1185 genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer *cmd_buffer,
1186 struct anv_render_pass *pass,
1187 const VkRenderPassBeginInfo *begin)
1188 {
1189 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
1190 struct anv_cmd_state *state = &cmd_buffer->state;
1191 struct anv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1192
1193 vk_free(&cmd_buffer->pool->alloc, state->attachments);
1194
1195 if (pass->attachment_count > 0) {
1196 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1197 pass->attachment_count *
1198 sizeof(state->attachments[0]),
1199 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1200 if (state->attachments == NULL) {
1201 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1202 return anv_batch_set_error(&cmd_buffer->batch,
1203 VK_ERROR_OUT_OF_HOST_MEMORY);
1204 }
1205 } else {
1206 state->attachments = NULL;
1207 }
1208
1209 /* Reserve one for the NULL state. */
1210 unsigned num_states = 1;
1211 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1212 if (vk_format_is_color(pass->attachments[i].format))
1213 num_states++;
1214
1215 if (need_input_attachment_state(&pass->attachments[i]))
1216 num_states++;
1217 }
1218
1219 const uint32_t ss_stride = align_u32(isl_dev->ss.size, isl_dev->ss.align);
1220 state->render_pass_states =
1221 anv_state_stream_alloc(&cmd_buffer->surface_state_stream,
1222 num_states * ss_stride, isl_dev->ss.align);
1223
1224 struct anv_state next_state = state->render_pass_states;
1225 next_state.alloc_size = isl_dev->ss.size;
1226
1227 state->null_surface_state = next_state;
1228 next_state.offset += ss_stride;
1229 next_state.map += ss_stride;
1230
1231 const VkRenderPassAttachmentBeginInfoKHR *begin_attachment =
1232 vk_find_struct_const(begin, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR);
1233
1234 if (begin && !begin_attachment)
1235 assert(pass->attachment_count == framebuffer->attachment_count);
1236
1237 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1238 if (vk_format_is_color(pass->attachments[i].format)) {
1239 state->attachments[i].color.state = next_state;
1240 next_state.offset += ss_stride;
1241 next_state.map += ss_stride;
1242 }
1243
1244 if (need_input_attachment_state(&pass->attachments[i])) {
1245 state->attachments[i].input.state = next_state;
1246 next_state.offset += ss_stride;
1247 next_state.map += ss_stride;
1248 }
1249
1250 if (begin_attachment && begin_attachment->attachmentCount != 0) {
1251 assert(begin_attachment->attachmentCount == pass->attachment_count);
1252 ANV_FROM_HANDLE(anv_image_view, iview, begin_attachment->pAttachments[i]);
1253 cmd_buffer->state.attachments[i].image_view = iview;
1254 } else if (framebuffer && i < framebuffer->attachment_count) {
1255 cmd_buffer->state.attachments[i].image_view = framebuffer->attachments[i];
1256 }
1257 }
1258 assert(next_state.offset == state->render_pass_states.offset +
1259 state->render_pass_states.alloc_size);
1260
1261 if (begin) {
1262 isl_null_fill_state(isl_dev, state->null_surface_state.map,
1263 isl_extent3d(framebuffer->width,
1264 framebuffer->height,
1265 framebuffer->layers));
1266
1267 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1268 struct anv_render_pass_attachment *att = &pass->attachments[i];
1269 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1270 VkImageAspectFlags clear_aspects = 0;
1271 VkImageAspectFlags load_aspects = 0;
1272
1273 if (att_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
1274 /* color attachment */
1275 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1276 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1277 } else if (att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
1278 load_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1279 }
1280 } else {
1281 /* depthstencil attachment */
1282 if (att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
1283 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1284 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1285 } else if (att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
1286 load_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1287 }
1288 }
1289 if (att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1290 if (att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1291 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1292 } else if (att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
1293 load_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1294 }
1295 }
1296 }
1297
1298 state->attachments[i].current_layout = att->initial_layout;
1299 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
1300 state->attachments[i].pending_clear_aspects = clear_aspects;
1301 state->attachments[i].pending_load_aspects = load_aspects;
1302 if (clear_aspects)
1303 state->attachments[i].clear_value = begin->pClearValues[i];
1304
1305 struct anv_image_view *iview = cmd_buffer->state.attachments[i].image_view;
1306 anv_assert(iview->vk_format == att->format);
1307
1308 const uint32_t num_layers = iview->planes[0].isl.array_len;
1309 state->attachments[i].pending_clear_views = (1 << num_layers) - 1;
1310
1311 union isl_color_value clear_color = { .u32 = { 0, } };
1312 if (att_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
1313 anv_assert(iview->n_planes == 1);
1314 assert(att_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1315 color_attachment_compute_aux_usage(cmd_buffer->device,
1316 state, i, begin->renderArea,
1317 &clear_color);
1318
1319 anv_image_fill_surface_state(cmd_buffer->device,
1320 iview->image,
1321 VK_IMAGE_ASPECT_COLOR_BIT,
1322 &iview->planes[0].isl,
1323 ISL_SURF_USAGE_RENDER_TARGET_BIT,
1324 state->attachments[i].aux_usage,
1325 &clear_color,
1326 0,
1327 &state->attachments[i].color,
1328 NULL);
1329
1330 add_surface_state_relocs(cmd_buffer, state->attachments[i].color);
1331 } else {
1332 depth_stencil_attachment_compute_aux_usage(cmd_buffer->device,
1333 state, i,
1334 begin->renderArea);
1335 }
1336
1337 if (need_input_attachment_state(&pass->attachments[i])) {
1338 anv_image_fill_surface_state(cmd_buffer->device,
1339 iview->image,
1340 VK_IMAGE_ASPECT_COLOR_BIT,
1341 &iview->planes[0].isl,
1342 ISL_SURF_USAGE_TEXTURE_BIT,
1343 state->attachments[i].input_aux_usage,
1344 &clear_color,
1345 0,
1346 &state->attachments[i].input,
1347 NULL);
1348
1349 add_surface_state_relocs(cmd_buffer, state->attachments[i].input);
1350 }
1351 }
1352 }
1353
1354 return VK_SUCCESS;
1355 }
1356
1357 VkResult
1358 genX(BeginCommandBuffer)(
1359 VkCommandBuffer commandBuffer,
1360 const VkCommandBufferBeginInfo* pBeginInfo)
1361 {
1362 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1363
1364 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1365 * command buffer's state. Otherwise, we must *reset* its state. In both
1366 * cases we reset it.
1367 *
1368 * From the Vulkan 1.0 spec:
1369 *
1370 * If a command buffer is in the executable state and the command buffer
1371 * was allocated from a command pool with the
1372 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1373 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1374 * as if vkResetCommandBuffer had been called with
1375 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1376 * the command buffer in the recording state.
1377 */
1378 anv_cmd_buffer_reset(cmd_buffer);
1379
1380 cmd_buffer->usage_flags = pBeginInfo->flags;
1381
1382 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY ||
1383 !(cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT));
1384
1385 genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
1386
1387 /* We sometimes store vertex data in the dynamic state buffer for blorp
1388 * operations and our dynamic state stream may re-use data from previous
1389 * command buffers. In order to prevent stale cache data, we flush the VF
1390 * cache. We could do this on every blorp call but that's not really
1391 * needed as all of the data will get written by the CPU prior to the GPU
1392 * executing anything. The chances are fairly high that they will use
1393 * blorp at least once per primary command buffer so it shouldn't be
1394 * wasted.
1395 */
1396 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY)
1397 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1398
1399 /* We send an "Indirect State Pointers Disable" packet at
1400 * EndCommandBuffer, so all push contant packets are ignored during a
1401 * context restore. Documentation says after that command, we need to
1402 * emit push constants again before any rendering operation. So we
1403 * flag them dirty here to make sure they get emitted.
1404 */
1405 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_ALL_GRAPHICS;
1406
1407 VkResult result = VK_SUCCESS;
1408 if (cmd_buffer->usage_flags &
1409 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1410 assert(pBeginInfo->pInheritanceInfo);
1411 cmd_buffer->state.pass =
1412 anv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1413 cmd_buffer->state.subpass =
1414 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1415
1416 /* This is optional in the inheritance info. */
1417 cmd_buffer->state.framebuffer =
1418 anv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1419
1420 result = genX(cmd_buffer_setup_attachments)(cmd_buffer,
1421 cmd_buffer->state.pass, NULL);
1422
1423 /* Record that HiZ is enabled if we can. */
1424 if (cmd_buffer->state.framebuffer) {
1425 const struct anv_image_view * const iview =
1426 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
1427
1428 if (iview) {
1429 VkImageLayout layout =
1430 cmd_buffer->state.subpass->depth_stencil_attachment->layout;
1431
1432 enum isl_aux_usage aux_usage =
1433 anv_layout_to_aux_usage(&cmd_buffer->device->info, iview->image,
1434 VK_IMAGE_ASPECT_DEPTH_BIT, layout);
1435
1436 cmd_buffer->state.hiz_enabled = aux_usage == ISL_AUX_USAGE_HIZ;
1437 }
1438 }
1439
1440 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
1441 }
1442
1443 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1444 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) {
1445 const VkCommandBufferInheritanceConditionalRenderingInfoEXT *conditional_rendering_info =
1446 vk_find_struct_const(pBeginInfo->pInheritanceInfo->pNext, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT);
1447
1448 /* If secondary buffer supports conditional rendering
1449 * we should emit commands as if conditional rendering is enabled.
1450 */
1451 cmd_buffer->state.conditional_render_enabled =
1452 conditional_rendering_info && conditional_rendering_info->conditionalRenderingEnable;
1453 }
1454 #endif
1455
1456 return result;
1457 }
1458
1459 /* From the PRM, Volume 2a:
1460 *
1461 * "Indirect State Pointers Disable
1462 *
1463 * At the completion of the post-sync operation associated with this pipe
1464 * control packet, the indirect state pointers in the hardware are
1465 * considered invalid; the indirect pointers are not saved in the context.
1466 * If any new indirect state commands are executed in the command stream
1467 * while the pipe control is pending, the new indirect state commands are
1468 * preserved.
1469 *
1470 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1471 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1472 * commands are only considered as Indirect State Pointers. Once ISP is
1473 * issued in a context, SW must initialize by programming push constant
1474 * commands for all the shaders (at least to zero length) before attempting
1475 * any rendering operation for the same context."
1476 *
1477 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1478 * even though they point to a BO that has been already unreferenced at
1479 * the end of the previous batch buffer. This has been fine so far since
1480 * we are protected by these scratch page (every address not covered by
1481 * a BO should be pointing to the scratch page). But on CNL, it is
1482 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1483 * instruction.
1484 *
1485 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1486 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1487 * context restore, so the mentioned hang doesn't happen. However,
1488 * software must program push constant commands for all stages prior to
1489 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1490 *
1491 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1492 * constants have been loaded into the EUs prior to disable the push constants
1493 * so that it doesn't hang a previous 3DPRIMITIVE.
1494 */
1495 static void
1496 emit_isp_disable(struct anv_cmd_buffer *cmd_buffer)
1497 {
1498 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1499 pc.StallAtPixelScoreboard = true;
1500 pc.CommandStreamerStallEnable = true;
1501 }
1502 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1503 pc.IndirectStatePointersDisable = true;
1504 pc.CommandStreamerStallEnable = true;
1505 }
1506 }
1507
1508 VkResult
1509 genX(EndCommandBuffer)(
1510 VkCommandBuffer commandBuffer)
1511 {
1512 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1513
1514 if (anv_batch_has_error(&cmd_buffer->batch))
1515 return cmd_buffer->batch.status;
1516
1517 /* We want every command buffer to start with the PMA fix in a known state,
1518 * so we disable it at the end of the command buffer.
1519 */
1520 genX(cmd_buffer_enable_pma_fix)(cmd_buffer, false);
1521
1522 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
1523
1524 emit_isp_disable(cmd_buffer);
1525
1526 anv_cmd_buffer_end_batch_buffer(cmd_buffer);
1527
1528 return VK_SUCCESS;
1529 }
1530
1531 void
1532 genX(CmdExecuteCommands)(
1533 VkCommandBuffer commandBuffer,
1534 uint32_t commandBufferCount,
1535 const VkCommandBuffer* pCmdBuffers)
1536 {
1537 ANV_FROM_HANDLE(anv_cmd_buffer, primary, commandBuffer);
1538
1539 assert(primary->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1540
1541 if (anv_batch_has_error(&primary->batch))
1542 return;
1543
1544 /* The secondary command buffers will assume that the PMA fix is disabled
1545 * when they begin executing. Make sure this is true.
1546 */
1547 genX(cmd_buffer_enable_pma_fix)(primary, false);
1548
1549 /* The secondary command buffer doesn't know which textures etc. have been
1550 * flushed prior to their execution. Apply those flushes now.
1551 */
1552 genX(cmd_buffer_apply_pipe_flushes)(primary);
1553
1554 for (uint32_t i = 0; i < commandBufferCount; i++) {
1555 ANV_FROM_HANDLE(anv_cmd_buffer, secondary, pCmdBuffers[i]);
1556
1557 assert(secondary->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY);
1558 assert(!anv_batch_has_error(&secondary->batch));
1559
1560 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1561 if (secondary->state.conditional_render_enabled) {
1562 if (!primary->state.conditional_render_enabled) {
1563 /* Secondary buffer is constructed as if it will be executed
1564 * with conditional rendering, we should satisfy this dependency
1565 * regardless of conditional rendering being enabled in primary.
1566 */
1567 struct gen_mi_builder b;
1568 gen_mi_builder_init(&b, &primary->batch);
1569 gen_mi_store(&b, gen_mi_reg64(ANV_PREDICATE_RESULT_REG),
1570 gen_mi_imm(UINT64_MAX));
1571 }
1572 }
1573 #endif
1574
1575 if (secondary->usage_flags &
1576 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1577 /* If we're continuing a render pass from the primary, we need to
1578 * copy the surface states for the current subpass into the storage
1579 * we allocated for them in BeginCommandBuffer.
1580 */
1581 struct anv_bo *ss_bo =
1582 primary->device->surface_state_pool.block_pool.bo;
1583 struct anv_state src_state = primary->state.render_pass_states;
1584 struct anv_state dst_state = secondary->state.render_pass_states;
1585 assert(src_state.alloc_size == dst_state.alloc_size);
1586
1587 genX(cmd_buffer_so_memcpy)(primary,
1588 (struct anv_address) {
1589 .bo = ss_bo,
1590 .offset = dst_state.offset,
1591 },
1592 (struct anv_address) {
1593 .bo = ss_bo,
1594 .offset = src_state.offset,
1595 },
1596 src_state.alloc_size);
1597 }
1598
1599 anv_cmd_buffer_add_secondary(primary, secondary);
1600 }
1601
1602 /* The secondary may have selected a different pipeline (3D or compute) and
1603 * may have changed the current L3$ configuration. Reset our tracking
1604 * variables to invalid values to ensure that we re-emit these in the case
1605 * where we do any draws or compute dispatches from the primary after the
1606 * secondary has returned.
1607 */
1608 primary->state.current_pipeline = UINT32_MAX;
1609 primary->state.current_l3_config = NULL;
1610 primary->state.current_hash_scale = 0;
1611
1612 /* Each of the secondary command buffers will use its own state base
1613 * address. We need to re-emit state base address for the primary after
1614 * all of the secondaries are done.
1615 *
1616 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1617 * address calls?
1618 */
1619 genX(cmd_buffer_emit_state_base_address)(primary);
1620 }
1621
1622 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1623 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1624 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1625
1626 /**
1627 * Program the hardware to use the specified L3 configuration.
1628 */
1629 void
1630 genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
1631 const struct gen_l3_config *cfg)
1632 {
1633 assert(cfg);
1634 if (cfg == cmd_buffer->state.current_l3_config)
1635 return;
1636
1637 if (unlikely(INTEL_DEBUG & DEBUG_L3)) {
1638 intel_logd("L3 config transition: ");
1639 gen_dump_l3_config(cfg, stderr);
1640 }
1641
1642 UNUSED const bool has_slm = cfg->n[GEN_L3P_SLM];
1643
1644 /* According to the hardware docs, the L3 partitioning can only be changed
1645 * while the pipeline is completely drained and the caches are flushed,
1646 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1647 */
1648 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1649 pc.DCFlushEnable = true;
1650 pc.PostSyncOperation = NoWrite;
1651 pc.CommandStreamerStallEnable = true;
1652 }
1653
1654 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1655 * invalidation of the relevant caches. Note that because RO invalidation
1656 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1657 * command is processed by the CS) we cannot combine it with the previous
1658 * stalling flush as the hardware documentation suggests, because that
1659 * would cause the CS to stall on previous rendering *after* RO
1660 * invalidation and wouldn't prevent the RO caches from being polluted by
1661 * concurrent rendering before the stall completes. This intentionally
1662 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1663 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1664 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1665 * already guarantee that there is no concurrent GPGPU kernel execution
1666 * (see SKL HSD 2132585).
1667 */
1668 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1669 pc.TextureCacheInvalidationEnable = true;
1670 pc.ConstantCacheInvalidationEnable = true;
1671 pc.InstructionCacheInvalidateEnable = true;
1672 pc.StateCacheInvalidationEnable = true;
1673 pc.PostSyncOperation = NoWrite;
1674 }
1675
1676 /* Now send a third stalling flush to make sure that invalidation is
1677 * complete when the L3 configuration registers are modified.
1678 */
1679 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1680 pc.DCFlushEnable = true;
1681 pc.PostSyncOperation = NoWrite;
1682 pc.CommandStreamerStallEnable = true;
1683 }
1684
1685 #if GEN_GEN >= 8
1686
1687 assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
1688
1689 #if GEN_GEN >= 12
1690 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1691 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1692 #else
1693 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1694 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1695 #endif
1696
1697 uint32_t l3cr;
1698 anv_pack_struct(&l3cr, L3_ALLOCATION_REG,
1699 #if GEN_GEN < 12
1700 .SLMEnable = has_slm,
1701 #endif
1702 #if GEN_GEN == 11
1703 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1704 * in L3CNTLREG register. The default setting of the bit is not the
1705 * desirable behavior.
1706 */
1707 .ErrorDetectionBehaviorControl = true,
1708 .UseFullWays = true,
1709 #endif
1710 .URBAllocation = cfg->n[GEN_L3P_URB],
1711 .ROAllocation = cfg->n[GEN_L3P_RO],
1712 .DCAllocation = cfg->n[GEN_L3P_DC],
1713 .AllAllocation = cfg->n[GEN_L3P_ALL]);
1714
1715 /* Set up the L3 partitioning. */
1716 emit_lri(&cmd_buffer->batch, L3_ALLOCATION_REG_num, l3cr);
1717
1718 #else
1719
1720 const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL];
1721 const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] ||
1722 cfg->n[GEN_L3P_ALL];
1723 const bool has_c = cfg->n[GEN_L3P_C] || cfg->n[GEN_L3P_RO] ||
1724 cfg->n[GEN_L3P_ALL];
1725 const bool has_t = cfg->n[GEN_L3P_T] || cfg->n[GEN_L3P_RO] ||
1726 cfg->n[GEN_L3P_ALL];
1727
1728 assert(!cfg->n[GEN_L3P_ALL]);
1729
1730 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1731 * the matching space on the remaining banks has to be allocated to a
1732 * client (URB for all validated configurations) set to the
1733 * lower-bandwidth 2-bank address hashing mode.
1734 */
1735 const struct gen_device_info *devinfo = &cmd_buffer->device->info;
1736 const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
1737 assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
1738
1739 /* Minimum number of ways that can be allocated to the URB. */
1740 const unsigned n0_urb = devinfo->is_baytrail ? 32 : 0;
1741 assert(cfg->n[GEN_L3P_URB] >= n0_urb);
1742
1743 uint32_t l3sqcr1, l3cr2, l3cr3;
1744 anv_pack_struct(&l3sqcr1, GENX(L3SQCREG1),
1745 .ConvertDC_UC = !has_dc,
1746 .ConvertIS_UC = !has_is,
1747 .ConvertC_UC = !has_c,
1748 .ConvertT_UC = !has_t);
1749 l3sqcr1 |=
1750 GEN_IS_HASWELL ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
1751 devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
1752 IVB_L3SQCREG1_SQGHPCI_DEFAULT;
1753
1754 anv_pack_struct(&l3cr2, GENX(L3CNTLREG2),
1755 .SLMEnable = has_slm,
1756 .URBLowBandwidth = urb_low_bw,
1757 .URBAllocation = cfg->n[GEN_L3P_URB] - n0_urb,
1758 #if !GEN_IS_HASWELL
1759 .ALLAllocation = cfg->n[GEN_L3P_ALL],
1760 #endif
1761 .ROAllocation = cfg->n[GEN_L3P_RO],
1762 .DCAllocation = cfg->n[GEN_L3P_DC]);
1763
1764 anv_pack_struct(&l3cr3, GENX(L3CNTLREG3),
1765 .ISAllocation = cfg->n[GEN_L3P_IS],
1766 .ISLowBandwidth = 0,
1767 .CAllocation = cfg->n[GEN_L3P_C],
1768 .CLowBandwidth = 0,
1769 .TAllocation = cfg->n[GEN_L3P_T],
1770 .TLowBandwidth = 0);
1771
1772 /* Set up the L3 partitioning. */
1773 emit_lri(&cmd_buffer->batch, GENX(L3SQCREG1_num), l3sqcr1);
1774 emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG2_num), l3cr2);
1775 emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG3_num), l3cr3);
1776
1777 #if GEN_IS_HASWELL
1778 if (cmd_buffer->device->instance->physicalDevice.cmd_parser_version >= 4) {
1779 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1780 * them disabled to avoid crashing the system hard.
1781 */
1782 uint32_t scratch1, chicken3;
1783 anv_pack_struct(&scratch1, GENX(SCRATCH1),
1784 .L3AtomicDisable = !has_dc);
1785 anv_pack_struct(&chicken3, GENX(CHICKEN3),
1786 .L3AtomicDisableMask = true,
1787 .L3AtomicDisable = !has_dc);
1788 emit_lri(&cmd_buffer->batch, GENX(SCRATCH1_num), scratch1);
1789 emit_lri(&cmd_buffer->batch, GENX(CHICKEN3_num), chicken3);
1790 }
1791 #endif
1792
1793 #endif
1794
1795 cmd_buffer->state.current_l3_config = cfg;
1796 }
1797
1798 void
1799 genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
1800 {
1801 enum anv_pipe_bits bits = cmd_buffer->state.pending_pipe_bits;
1802
1803 /* Flushes are pipelined while invalidations are handled immediately.
1804 * Therefore, if we're flushing anything then we need to schedule a stall
1805 * before any invalidations can happen.
1806 */
1807 if (bits & ANV_PIPE_FLUSH_BITS)
1808 bits |= ANV_PIPE_NEEDS_CS_STALL_BIT;
1809
1810 /* If we're going to do an invalidate and we have a pending CS stall that
1811 * has yet to be resolved, we do the CS stall now.
1812 */
1813 if ((bits & ANV_PIPE_INVALIDATE_BITS) &&
1814 (bits & ANV_PIPE_NEEDS_CS_STALL_BIT)) {
1815 bits |= ANV_PIPE_CS_STALL_BIT;
1816 bits &= ~ANV_PIPE_NEEDS_CS_STALL_BIT;
1817 }
1818
1819 if (GEN_GEN >= 12 &&
1820 ((bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT) ||
1821 (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT))) {
1822 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
1823 * Enable):
1824 *
1825 * Unified Cache (Tile Cache Disabled):
1826 *
1827 * When the Color and Depth (Z) streams are enabled to be cached in
1828 * the DC space of L2, Software must use "Render Target Cache Flush
1829 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
1830 * Flush" for getting the color and depth (Z) write data to be
1831 * globally observable. In this mode of operation it is not required
1832 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
1833 */
1834 bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
1835 }
1836
1837 if (bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_CS_STALL_BIT)) {
1838 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
1839 #if GEN_GEN >= 12
1840 pipe.TileCacheFlushEnable = bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT;
1841 #endif
1842 pipe.DepthCacheFlushEnable = bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1843 pipe.DCFlushEnable = bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1844 pipe.RenderTargetCacheFlushEnable =
1845 bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1846
1847 pipe.DepthStallEnable = bits & ANV_PIPE_DEPTH_STALL_BIT;
1848 pipe.CommandStreamerStallEnable = bits & ANV_PIPE_CS_STALL_BIT;
1849 pipe.StallAtPixelScoreboard = bits & ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
1850
1851 /*
1852 * According to the Broadwell documentation, any PIPE_CONTROL with the
1853 * "Command Streamer Stall" bit set must also have another bit set,
1854 * with five different options:
1855 *
1856 * - Render Target Cache Flush
1857 * - Depth Cache Flush
1858 * - Stall at Pixel Scoreboard
1859 * - Post-Sync Operation
1860 * - Depth Stall
1861 * - DC Flush Enable
1862 *
1863 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1864 * mesa and it seems to work fine. The choice is fairly arbitrary.
1865 */
1866 if ((bits & ANV_PIPE_CS_STALL_BIT) &&
1867 !(bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_DEPTH_STALL_BIT |
1868 ANV_PIPE_STALL_AT_SCOREBOARD_BIT)))
1869 pipe.StallAtPixelScoreboard = true;
1870 }
1871
1872 /* If a render target flush was emitted, then we can toggle off the bit
1873 * saying that render target writes are ongoing.
1874 */
1875 if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1876 bits &= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES);
1877
1878 bits &= ~(ANV_PIPE_FLUSH_BITS | ANV_PIPE_CS_STALL_BIT);
1879 }
1880
1881 if (bits & ANV_PIPE_INVALIDATE_BITS) {
1882 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1883 *
1884 * "If the VF Cache Invalidation Enable is set to a 1 in a
1885 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1886 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1887 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1888 * a 1."
1889 *
1890 * This appears to hang Broadwell, so we restrict it to just gen9.
1891 */
1892 if (GEN_GEN == 9 && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT))
1893 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe);
1894
1895 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
1896 pipe.StateCacheInvalidationEnable =
1897 bits & ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
1898 pipe.ConstantCacheInvalidationEnable =
1899 bits & ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1900 pipe.VFCacheInvalidationEnable =
1901 bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1902 pipe.TextureCacheInvalidationEnable =
1903 bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1904 pipe.InstructionCacheInvalidateEnable =
1905 bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT;
1906
1907 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1908 *
1909 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1910 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1911 * “Write Timestamp”.
1912 */
1913 if (GEN_GEN == 9 && pipe.VFCacheInvalidationEnable) {
1914 pipe.PostSyncOperation = WriteImmediateData;
1915 pipe.Address =
1916 (struct anv_address) { cmd_buffer->device->workaround_bo, 0 };
1917 }
1918 }
1919
1920 bits &= ~ANV_PIPE_INVALIDATE_BITS;
1921 }
1922
1923 cmd_buffer->state.pending_pipe_bits = bits;
1924 }
1925
1926 void genX(CmdPipelineBarrier)(
1927 VkCommandBuffer commandBuffer,
1928 VkPipelineStageFlags srcStageMask,
1929 VkPipelineStageFlags destStageMask,
1930 VkBool32 byRegion,
1931 uint32_t memoryBarrierCount,
1932 const VkMemoryBarrier* pMemoryBarriers,
1933 uint32_t bufferMemoryBarrierCount,
1934 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
1935 uint32_t imageMemoryBarrierCount,
1936 const VkImageMemoryBarrier* pImageMemoryBarriers)
1937 {
1938 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1939
1940 /* XXX: Right now, we're really dumb and just flush whatever categories
1941 * the app asks for. One of these days we may make this a bit better
1942 * but right now that's all the hardware allows for in most areas.
1943 */
1944 VkAccessFlags src_flags = 0;
1945 VkAccessFlags dst_flags = 0;
1946
1947 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
1948 src_flags |= pMemoryBarriers[i].srcAccessMask;
1949 dst_flags |= pMemoryBarriers[i].dstAccessMask;
1950 }
1951
1952 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
1953 src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
1954 dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
1955 }
1956
1957 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
1958 src_flags |= pImageMemoryBarriers[i].srcAccessMask;
1959 dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
1960 ANV_FROM_HANDLE(anv_image, image, pImageMemoryBarriers[i].image);
1961 const VkImageSubresourceRange *range =
1962 &pImageMemoryBarriers[i].subresourceRange;
1963
1964 uint32_t base_layer, layer_count;
1965 if (image->type == VK_IMAGE_TYPE_3D) {
1966 base_layer = 0;
1967 layer_count = anv_minify(image->extent.depth, range->baseMipLevel);
1968 } else {
1969 base_layer = range->baseArrayLayer;
1970 layer_count = anv_get_layerCount(image, range);
1971 }
1972
1973 if (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT) {
1974 transition_depth_buffer(cmd_buffer, image,
1975 pImageMemoryBarriers[i].oldLayout,
1976 pImageMemoryBarriers[i].newLayout);
1977 }
1978
1979 if (range->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT) {
1980 transition_stencil_buffer(cmd_buffer, image,
1981 range->baseMipLevel,
1982 anv_get_levelCount(image, range),
1983 base_layer, layer_count,
1984 pImageMemoryBarriers[i].oldLayout,
1985 pImageMemoryBarriers[i].newLayout);
1986 }
1987
1988 if (range->aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
1989 VkImageAspectFlags color_aspects =
1990 anv_image_expand_aspects(image, range->aspectMask);
1991 uint32_t aspect_bit;
1992 anv_foreach_image_aspect_bit(aspect_bit, image, color_aspects) {
1993 transition_color_buffer(cmd_buffer, image, 1UL << aspect_bit,
1994 range->baseMipLevel,
1995 anv_get_levelCount(image, range),
1996 base_layer, layer_count,
1997 pImageMemoryBarriers[i].oldLayout,
1998 pImageMemoryBarriers[i].newLayout);
1999 }
2000 }
2001 }
2002
2003 cmd_buffer->state.pending_pipe_bits |=
2004 anv_pipe_flush_bits_for_access_flags(src_flags) |
2005 anv_pipe_invalidate_bits_for_access_flags(dst_flags);
2006 }
2007
2008 static void
2009 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer *cmd_buffer)
2010 {
2011 VkShaderStageFlags stages =
2012 cmd_buffer->state.gfx.base.pipeline->active_stages;
2013
2014 /* In order to avoid thrash, we assume that vertex and fragment stages
2015 * always exist. In the rare case where one is missing *and* the other
2016 * uses push concstants, this may be suboptimal. However, avoiding stalls
2017 * seems more important.
2018 */
2019 stages |= VK_SHADER_STAGE_FRAGMENT_BIT | VK_SHADER_STAGE_VERTEX_BIT;
2020
2021 if (stages == cmd_buffer->state.push_constant_stages)
2022 return;
2023
2024 #if GEN_GEN >= 8
2025 const unsigned push_constant_kb = 32;
2026 #elif GEN_IS_HASWELL
2027 const unsigned push_constant_kb = cmd_buffer->device->info.gt == 3 ? 32 : 16;
2028 #else
2029 const unsigned push_constant_kb = 16;
2030 #endif
2031
2032 const unsigned num_stages =
2033 util_bitcount(stages & VK_SHADER_STAGE_ALL_GRAPHICS);
2034 unsigned size_per_stage = push_constant_kb / num_stages;
2035
2036 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2037 * units of 2KB. Incidentally, these are the same platforms that have
2038 * 32KB worth of push constant space.
2039 */
2040 if (push_constant_kb == 32)
2041 size_per_stage &= ~1u;
2042
2043 uint32_t kb_used = 0;
2044 for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) {
2045 unsigned push_size = (stages & (1 << i)) ? size_per_stage : 0;
2046 anv_batch_emit(&cmd_buffer->batch,
2047 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) {
2048 alloc._3DCommandSubOpcode = 18 + i;
2049 alloc.ConstantBufferOffset = (push_size > 0) ? kb_used : 0;
2050 alloc.ConstantBufferSize = push_size;
2051 }
2052 kb_used += push_size;
2053 }
2054
2055 anv_batch_emit(&cmd_buffer->batch,
2056 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS), alloc) {
2057 alloc.ConstantBufferOffset = kb_used;
2058 alloc.ConstantBufferSize = push_constant_kb - kb_used;
2059 }
2060
2061 cmd_buffer->state.push_constant_stages = stages;
2062
2063 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2064 *
2065 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2066 * the next 3DPRIMITIVE command after programming the
2067 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2068 *
2069 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2070 * pipeline setup, we need to dirty push constants.
2071 */
2072 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_ALL_GRAPHICS;
2073 }
2074
2075 static struct anv_address
2076 anv_descriptor_set_address(struct anv_cmd_buffer *cmd_buffer,
2077 struct anv_descriptor_set *set)
2078 {
2079 if (set->pool) {
2080 /* This is a normal descriptor set */
2081 return (struct anv_address) {
2082 .bo = set->pool->bo,
2083 .offset = set->desc_mem.offset,
2084 };
2085 } else {
2086 /* This is a push descriptor set. We have to flag it as used on the GPU
2087 * so that the next time we push descriptors, we grab a new memory.
2088 */
2089 struct anv_push_descriptor_set *push_set =
2090 (struct anv_push_descriptor_set *)set;
2091 push_set->set_used_on_gpu = true;
2092
2093 return (struct anv_address) {
2094 .bo = cmd_buffer->dynamic_state_stream.state_pool->block_pool.bo,
2095 .offset = set->desc_mem.offset,
2096 };
2097 }
2098 }
2099
2100 static VkResult
2101 emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
2102 gl_shader_stage stage,
2103 struct anv_state *bt_state)
2104 {
2105 struct anv_subpass *subpass = cmd_buffer->state.subpass;
2106 struct anv_cmd_pipeline_state *pipe_state;
2107 struct anv_pipeline *pipeline;
2108 uint32_t state_offset;
2109
2110 switch (stage) {
2111 case MESA_SHADER_COMPUTE:
2112 pipe_state = &cmd_buffer->state.compute.base;
2113 break;
2114 default:
2115 pipe_state = &cmd_buffer->state.gfx.base;
2116 break;
2117 }
2118 pipeline = pipe_state->pipeline;
2119
2120 if (!anv_pipeline_has_stage(pipeline, stage)) {
2121 *bt_state = (struct anv_state) { 0, };
2122 return VK_SUCCESS;
2123 }
2124
2125 struct anv_pipeline_bind_map *map = &pipeline->shaders[stage]->bind_map;
2126 if (map->surface_count == 0) {
2127 *bt_state = (struct anv_state) { 0, };
2128 return VK_SUCCESS;
2129 }
2130
2131 *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer,
2132 map->surface_count,
2133 &state_offset);
2134 uint32_t *bt_map = bt_state->map;
2135
2136 if (bt_state->map == NULL)
2137 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2138
2139 /* We only need to emit relocs if we're not using softpin. If we are using
2140 * softpin then we always keep all user-allocated memory objects resident.
2141 */
2142 const bool need_client_mem_relocs =
2143 !cmd_buffer->device->instance->physicalDevice.use_softpin;
2144
2145 for (uint32_t s = 0; s < map->surface_count; s++) {
2146 struct anv_pipeline_binding *binding = &map->surface_to_descriptor[s];
2147
2148 struct anv_state surface_state;
2149
2150 switch (binding->set) {
2151 case ANV_DESCRIPTOR_SET_NULL:
2152 bt_map[s] = 0;
2153 break;
2154
2155 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS:
2156 /* Color attachment binding */
2157 assert(stage == MESA_SHADER_FRAGMENT);
2158 if (binding->index < subpass->color_count) {
2159 const unsigned att =
2160 subpass->color_attachments[binding->index].attachment;
2161
2162 /* From the Vulkan 1.0.46 spec:
2163 *
2164 * "If any color or depth/stencil attachments are
2165 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2166 * attachments."
2167 */
2168 if (att == VK_ATTACHMENT_UNUSED) {
2169 surface_state = cmd_buffer->state.null_surface_state;
2170 } else {
2171 surface_state = cmd_buffer->state.attachments[att].color.state;
2172 }
2173 } else {
2174 surface_state = cmd_buffer->state.null_surface_state;
2175 }
2176
2177 bt_map[s] = surface_state.offset + state_offset;
2178 break;
2179
2180 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS: {
2181 struct anv_state surface_state =
2182 anv_cmd_buffer_alloc_surface_state(cmd_buffer);
2183
2184 struct anv_address constant_data = {
2185 .bo = pipeline->device->dynamic_state_pool.block_pool.bo,
2186 .offset = pipeline->shaders[stage]->constant_data.offset,
2187 };
2188 unsigned constant_data_size =
2189 pipeline->shaders[stage]->constant_data_size;
2190
2191 const enum isl_format format =
2192 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER);
2193 anv_fill_buffer_surface_state(cmd_buffer->device,
2194 surface_state, format,
2195 constant_data, constant_data_size, 1);
2196
2197 bt_map[s] = surface_state.offset + state_offset;
2198 add_surface_reloc(cmd_buffer, surface_state, constant_data);
2199 break;
2200 }
2201
2202 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS: {
2203 /* This is always the first binding for compute shaders */
2204 assert(stage == MESA_SHADER_COMPUTE && s == 0);
2205
2206 struct anv_state surface_state =
2207 anv_cmd_buffer_alloc_surface_state(cmd_buffer);
2208
2209 const enum isl_format format =
2210 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER);
2211 anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
2212 format,
2213 cmd_buffer->state.compute.num_workgroups,
2214 12, 1);
2215 bt_map[s] = surface_state.offset + state_offset;
2216 if (need_client_mem_relocs) {
2217 add_surface_reloc(cmd_buffer, surface_state,
2218 cmd_buffer->state.compute.num_workgroups);
2219 }
2220 break;
2221 }
2222
2223 case ANV_DESCRIPTOR_SET_DESCRIPTORS: {
2224 /* This is a descriptor set buffer so the set index is actually
2225 * given by binding->binding. (Yes, that's confusing.)
2226 */
2227 struct anv_descriptor_set *set =
2228 pipe_state->descriptors[binding->index];
2229 assert(set->desc_mem.alloc_size);
2230 assert(set->desc_surface_state.alloc_size);
2231 bt_map[s] = set->desc_surface_state.offset + state_offset;
2232 add_surface_reloc(cmd_buffer, set->desc_surface_state,
2233 anv_descriptor_set_address(cmd_buffer, set));
2234 break;
2235 }
2236
2237 default: {
2238 assert(binding->set < MAX_SETS);
2239 const struct anv_descriptor *desc =
2240 &pipe_state->descriptors[binding->set]->descriptors[binding->index];
2241
2242 switch (desc->type) {
2243 case VK_DESCRIPTOR_TYPE_SAMPLER:
2244 /* Nothing for us to do here */
2245 continue;
2246
2247 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2248 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE: {
2249 struct anv_surface_state sstate =
2250 (desc->layout == VK_IMAGE_LAYOUT_GENERAL) ?
2251 desc->image_view->planes[binding->plane].general_sampler_surface_state :
2252 desc->image_view->planes[binding->plane].optimal_sampler_surface_state;
2253 surface_state = sstate.state;
2254 assert(surface_state.alloc_size);
2255 if (need_client_mem_relocs)
2256 add_surface_state_relocs(cmd_buffer, sstate);
2257 break;
2258 }
2259 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
2260 assert(stage == MESA_SHADER_FRAGMENT);
2261 if ((desc->image_view->aspect_mask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0) {
2262 /* For depth and stencil input attachments, we treat it like any
2263 * old texture that a user may have bound.
2264 */
2265 assert(desc->image_view->n_planes == 1);
2266 struct anv_surface_state sstate =
2267 (desc->layout == VK_IMAGE_LAYOUT_GENERAL) ?
2268 desc->image_view->planes[0].general_sampler_surface_state :
2269 desc->image_view->planes[0].optimal_sampler_surface_state;
2270 surface_state = sstate.state;
2271 assert(surface_state.alloc_size);
2272 if (need_client_mem_relocs)
2273 add_surface_state_relocs(cmd_buffer, sstate);
2274 } else {
2275 /* For color input attachments, we create the surface state at
2276 * vkBeginRenderPass time so that we can include aux and clear
2277 * color information.
2278 */
2279 assert(binding->input_attachment_index < subpass->input_count);
2280 const unsigned subpass_att = binding->input_attachment_index;
2281 const unsigned att = subpass->input_attachments[subpass_att].attachment;
2282 surface_state = cmd_buffer->state.attachments[att].input.state;
2283 }
2284 break;
2285
2286 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: {
2287 struct anv_surface_state sstate = (binding->write_only)
2288 ? desc->image_view->planes[binding->plane].writeonly_storage_surface_state
2289 : desc->image_view->planes[binding->plane].storage_surface_state;
2290 surface_state = sstate.state;
2291 assert(surface_state.alloc_size);
2292 if (need_client_mem_relocs)
2293 add_surface_state_relocs(cmd_buffer, sstate);
2294 break;
2295 }
2296
2297 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2298 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2299 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2300 surface_state = desc->buffer_view->surface_state;
2301 assert(surface_state.alloc_size);
2302 if (need_client_mem_relocs) {
2303 add_surface_reloc(cmd_buffer, surface_state,
2304 desc->buffer_view->address);
2305 }
2306 break;
2307
2308 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2309 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: {
2310 /* Compute the offset within the buffer */
2311 struct anv_push_constants *push =
2312 &cmd_buffer->state.push_constants[stage];
2313
2314 uint32_t dynamic_offset =
2315 push->dynamic_offsets[binding->dynamic_offset_index];
2316 uint64_t offset = desc->offset + dynamic_offset;
2317 /* Clamp to the buffer size */
2318 offset = MIN2(offset, desc->buffer->size);
2319 /* Clamp the range to the buffer size */
2320 uint32_t range = MIN2(desc->range, desc->buffer->size - offset);
2321
2322 struct anv_address address =
2323 anv_address_add(desc->buffer->address, offset);
2324
2325 surface_state =
2326 anv_state_stream_alloc(&cmd_buffer->surface_state_stream, 64, 64);
2327 enum isl_format format =
2328 anv_isl_format_for_descriptor_type(desc->type);
2329
2330 anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
2331 format, address, range, 1);
2332 if (need_client_mem_relocs)
2333 add_surface_reloc(cmd_buffer, surface_state, address);
2334 break;
2335 }
2336
2337 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2338 surface_state = (binding->write_only)
2339 ? desc->buffer_view->writeonly_storage_surface_state
2340 : desc->buffer_view->storage_surface_state;
2341 assert(surface_state.alloc_size);
2342 if (need_client_mem_relocs) {
2343 add_surface_reloc(cmd_buffer, surface_state,
2344 desc->buffer_view->address);
2345 }
2346 break;
2347
2348 default:
2349 assert(!"Invalid descriptor type");
2350 continue;
2351 }
2352 bt_map[s] = surface_state.offset + state_offset;
2353 break;
2354 }
2355 }
2356 }
2357
2358 return VK_SUCCESS;
2359 }
2360
2361 static VkResult
2362 emit_samplers(struct anv_cmd_buffer *cmd_buffer,
2363 gl_shader_stage stage,
2364 struct anv_state *state)
2365 {
2366 struct anv_cmd_pipeline_state *pipe_state =
2367 stage == MESA_SHADER_COMPUTE ? &cmd_buffer->state.compute.base :
2368 &cmd_buffer->state.gfx.base;
2369 struct anv_pipeline *pipeline = pipe_state->pipeline;
2370
2371 if (!anv_pipeline_has_stage(pipeline, stage)) {
2372 *state = (struct anv_state) { 0, };
2373 return VK_SUCCESS;
2374 }
2375
2376 struct anv_pipeline_bind_map *map = &pipeline->shaders[stage]->bind_map;
2377 if (map->sampler_count == 0) {
2378 *state = (struct anv_state) { 0, };
2379 return VK_SUCCESS;
2380 }
2381
2382 uint32_t size = map->sampler_count * 16;
2383 *state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 32);
2384
2385 if (state->map == NULL)
2386 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2387
2388 for (uint32_t s = 0; s < map->sampler_count; s++) {
2389 struct anv_pipeline_binding *binding = &map->sampler_to_descriptor[s];
2390 const struct anv_descriptor *desc =
2391 &pipe_state->descriptors[binding->set]->descriptors[binding->index];
2392
2393 if (desc->type != VK_DESCRIPTOR_TYPE_SAMPLER &&
2394 desc->type != VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
2395 continue;
2396
2397 struct anv_sampler *sampler = desc->sampler;
2398
2399 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2400 * happens to be zero.
2401 */
2402 if (sampler == NULL)
2403 continue;
2404
2405 memcpy(state->map + (s * 16),
2406 sampler->state[binding->plane], sizeof(sampler->state[0]));
2407 }
2408
2409 return VK_SUCCESS;
2410 }
2411
2412 static uint32_t
2413 flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer)
2414 {
2415 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
2416
2417 VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
2418 pipeline->active_stages;
2419
2420 VkResult result = VK_SUCCESS;
2421 anv_foreach_stage(s, dirty) {
2422 result = emit_samplers(cmd_buffer, s, &cmd_buffer->state.samplers[s]);
2423 if (result != VK_SUCCESS)
2424 break;
2425 result = emit_binding_table(cmd_buffer, s,
2426 &cmd_buffer->state.binding_tables[s]);
2427 if (result != VK_SUCCESS)
2428 break;
2429 }
2430
2431 if (result != VK_SUCCESS) {
2432 assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
2433
2434 result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
2435 if (result != VK_SUCCESS)
2436 return 0;
2437
2438 /* Re-emit state base addresses so we get the new surface state base
2439 * address before we start emitting binding tables etc.
2440 */
2441 genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
2442
2443 /* Re-emit all active binding tables */
2444 dirty |= pipeline->active_stages;
2445 anv_foreach_stage(s, dirty) {
2446 result = emit_samplers(cmd_buffer, s, &cmd_buffer->state.samplers[s]);
2447 if (result != VK_SUCCESS) {
2448 anv_batch_set_error(&cmd_buffer->batch, result);
2449 return 0;
2450 }
2451 result = emit_binding_table(cmd_buffer, s,
2452 &cmd_buffer->state.binding_tables[s]);
2453 if (result != VK_SUCCESS) {
2454 anv_batch_set_error(&cmd_buffer->batch, result);
2455 return 0;
2456 }
2457 }
2458 }
2459
2460 cmd_buffer->state.descriptors_dirty &= ~dirty;
2461
2462 return dirty;
2463 }
2464
2465 static void
2466 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
2467 uint32_t stages)
2468 {
2469 static const uint32_t sampler_state_opcodes[] = {
2470 [MESA_SHADER_VERTEX] = 43,
2471 [MESA_SHADER_TESS_CTRL] = 44, /* HS */
2472 [MESA_SHADER_TESS_EVAL] = 45, /* DS */
2473 [MESA_SHADER_GEOMETRY] = 46,
2474 [MESA_SHADER_FRAGMENT] = 47,
2475 [MESA_SHADER_COMPUTE] = 0,
2476 };
2477
2478 static const uint32_t binding_table_opcodes[] = {
2479 [MESA_SHADER_VERTEX] = 38,
2480 [MESA_SHADER_TESS_CTRL] = 39,
2481 [MESA_SHADER_TESS_EVAL] = 40,
2482 [MESA_SHADER_GEOMETRY] = 41,
2483 [MESA_SHADER_FRAGMENT] = 42,
2484 [MESA_SHADER_COMPUTE] = 0,
2485 };
2486
2487 anv_foreach_stage(s, stages) {
2488 assert(s < ARRAY_SIZE(binding_table_opcodes));
2489 assert(binding_table_opcodes[s] > 0);
2490
2491 if (cmd_buffer->state.samplers[s].alloc_size > 0) {
2492 anv_batch_emit(&cmd_buffer->batch,
2493 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ssp) {
2494 ssp._3DCommandSubOpcode = sampler_state_opcodes[s];
2495 ssp.PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset;
2496 }
2497 }
2498
2499 /* Always emit binding table pointers if we're asked to, since on SKL
2500 * this is what flushes push constants. */
2501 anv_batch_emit(&cmd_buffer->batch,
2502 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), btp) {
2503 btp._3DCommandSubOpcode = binding_table_opcodes[s];
2504 btp.PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset;
2505 }
2506 }
2507 }
2508
2509 static void
2510 cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer,
2511 VkShaderStageFlags dirty_stages)
2512 {
2513 const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
2514 const struct anv_pipeline *pipeline = gfx_state->base.pipeline;
2515
2516 static const uint32_t push_constant_opcodes[] = {
2517 [MESA_SHADER_VERTEX] = 21,
2518 [MESA_SHADER_TESS_CTRL] = 25, /* HS */
2519 [MESA_SHADER_TESS_EVAL] = 26, /* DS */
2520 [MESA_SHADER_GEOMETRY] = 22,
2521 [MESA_SHADER_FRAGMENT] = 23,
2522 [MESA_SHADER_COMPUTE] = 0,
2523 };
2524
2525 VkShaderStageFlags flushed = 0;
2526
2527 anv_foreach_stage(stage, dirty_stages) {
2528 assert(stage < ARRAY_SIZE(push_constant_opcodes));
2529 assert(push_constant_opcodes[stage] > 0);
2530
2531 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS), c) {
2532 c._3DCommandSubOpcode = push_constant_opcodes[stage];
2533
2534 if (anv_pipeline_has_stage(pipeline, stage)) {
2535 const struct anv_pipeline_bind_map *bind_map =
2536 &pipeline->shaders[stage]->bind_map;
2537
2538 for (unsigned i = 0; i < 4; i++) {
2539 const struct anv_push_range *range = &bind_map->push_ranges[i];
2540 if (range->length == 0)
2541 continue;
2542
2543 struct anv_address addr;
2544 switch (range->set) {
2545 case ANV_DESCRIPTOR_SET_DESCRIPTORS: {
2546 /* This is a descriptor set buffer so the set index is
2547 * actually given by binding->binding. (Yes, that's
2548 * confusing.)
2549 */
2550 struct anv_descriptor_set *set =
2551 gfx_state->base.descriptors[range->index];
2552 addr = anv_descriptor_set_address(cmd_buffer, set);
2553 break;
2554 }
2555
2556 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS: {
2557 struct anv_state state =
2558 anv_cmd_buffer_push_constants(cmd_buffer, stage);
2559 addr = (struct anv_address) {
2560 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
2561 .offset = state.offset,
2562 };
2563 break;
2564 }
2565
2566 default: {
2567 assert(range->set < MAX_SETS);
2568 struct anv_descriptor_set *set =
2569 gfx_state->base.descriptors[range->set];
2570 const struct anv_descriptor *desc =
2571 &set->descriptors[range->index];
2572
2573 if (desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
2574 addr = desc->buffer_view->address;
2575 } else {
2576 assert(desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC);
2577 struct anv_push_constants *push =
2578 &cmd_buffer->state.push_constants[stage];
2579 uint32_t dynamic_offset =
2580 push->dynamic_offsets[range->dynamic_offset_index];
2581 addr = anv_address_add(desc->buffer->address,
2582 desc->offset + dynamic_offset);
2583 }
2584 }
2585 }
2586
2587 c.ConstantBody.ReadLength[i] = range->length;
2588 c.ConstantBody.Buffer[i] =
2589 anv_address_add(addr, range->start * 32);
2590 }
2591 }
2592 }
2593
2594 flushed |= mesa_to_vk_shader_stage(stage);
2595 }
2596
2597 cmd_buffer->state.push_constants_dirty &= ~flushed;
2598 }
2599
2600 #if GEN_GEN >= 12
2601 void
2602 genX(cmd_buffer_aux_map_state)(struct anv_cmd_buffer *cmd_buffer)
2603 {
2604 void *aux_map_ctx = cmd_buffer->device->aux_map_ctx;
2605 if (!aux_map_ctx)
2606 return;
2607 uint32_t aux_map_state_num = gen_aux_map_get_state_num(aux_map_ctx);
2608 if (cmd_buffer->state.last_aux_map_state != aux_map_state_num) {
2609 /* If the aux-map state number increased, then we need to rewrite the
2610 * register. Rewriting the register is used to both set the aux-map
2611 * translation table address, and also to invalidate any previously
2612 * cached translations.
2613 */
2614 uint64_t base_addr = gen_aux_map_get_base(aux_map_ctx);
2615 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
2616 lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num);
2617 lri.DataDWord = base_addr & 0xffffffff;
2618 }
2619 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
2620 lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4;
2621 lri.DataDWord = base_addr >> 32;
2622 }
2623 cmd_buffer->state.last_aux_map_state = aux_map_state_num;
2624 }
2625 }
2626 #endif
2627
2628 void
2629 genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
2630 {
2631 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
2632 uint32_t *p;
2633
2634 uint32_t vb_emit = cmd_buffer->state.gfx.vb_dirty & pipeline->vb_used;
2635 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE)
2636 vb_emit |= pipeline->vb_used;
2637
2638 assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
2639
2640 genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->urb.l3_config);
2641
2642 genX(cmd_buffer_emit_hashing_mode)(cmd_buffer, UINT_MAX, UINT_MAX, 1);
2643
2644 genX(flush_pipeline_select_3d)(cmd_buffer);
2645
2646 #if GEN_GEN >= 12
2647 genX(cmd_buffer_aux_map_state)(cmd_buffer);
2648 #endif
2649
2650 if (vb_emit) {
2651 const uint32_t num_buffers = __builtin_popcount(vb_emit);
2652 const uint32_t num_dwords = 1 + num_buffers * 4;
2653
2654 p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
2655 GENX(3DSTATE_VERTEX_BUFFERS));
2656 uint32_t vb, i = 0;
2657 for_each_bit(vb, vb_emit) {
2658 struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
2659 uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
2660
2661 struct GENX(VERTEX_BUFFER_STATE) state = {
2662 .VertexBufferIndex = vb,
2663
2664 .MOCS = anv_mocs_for_bo(cmd_buffer->device, buffer->address.bo),
2665 #if GEN_GEN <= 7
2666 .BufferAccessType = pipeline->vb[vb].instanced ? INSTANCEDATA : VERTEXDATA,
2667 .InstanceDataStepRate = pipeline->vb[vb].instance_divisor,
2668 #endif
2669
2670 .AddressModifyEnable = true,
2671 .BufferPitch = pipeline->vb[vb].stride,
2672 .BufferStartingAddress = anv_address_add(buffer->address, offset),
2673
2674 #if GEN_GEN >= 8
2675 .BufferSize = buffer->size - offset
2676 #else
2677 .EndAddress = anv_address_add(buffer->address, buffer->size - 1),
2678 #endif
2679 };
2680
2681 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, &p[1 + i * 4], &state);
2682 i++;
2683 }
2684 }
2685
2686 cmd_buffer->state.gfx.vb_dirty &= ~vb_emit;
2687
2688 #if GEN_GEN >= 8
2689 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_XFB_ENABLE) {
2690 /* We don't need any per-buffer dirty tracking because you're not
2691 * allowed to bind different XFB buffers while XFB is enabled.
2692 */
2693 for (unsigned idx = 0; idx < MAX_XFB_BUFFERS; idx++) {
2694 struct anv_xfb_binding *xfb = &cmd_buffer->state.xfb_bindings[idx];
2695 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) {
2696 #if GEN_GEN < 12
2697 sob.SOBufferIndex = idx;
2698 #else
2699 sob._3DCommandOpcode = 0;
2700 sob._3DCommandSubOpcode = SO_BUFFER_INDEX_0_CMD + idx;
2701 #endif
2702
2703 if (cmd_buffer->state.xfb_enabled && xfb->buffer && xfb->size != 0) {
2704 sob.SOBufferEnable = true;
2705 sob.MOCS = cmd_buffer->device->isl_dev.mocs.internal,
2706 sob.StreamOffsetWriteEnable = false;
2707 sob.SurfaceBaseAddress = anv_address_add(xfb->buffer->address,
2708 xfb->offset);
2709 /* Size is in DWords - 1 */
2710 sob.SurfaceSize = xfb->size / 4 - 1;
2711 }
2712 }
2713 }
2714
2715 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2716 if (GEN_GEN >= 10)
2717 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
2718 }
2719 #endif
2720
2721 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) {
2722 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
2723
2724 /* If the pipeline changed, we may need to re-allocate push constant
2725 * space in the URB.
2726 */
2727 cmd_buffer_alloc_push_constants(cmd_buffer);
2728 }
2729
2730 #if GEN_GEN <= 7
2731 if (cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_VERTEX_BIT ||
2732 cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_VERTEX_BIT) {
2733 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2734 *
2735 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2736 * stall needs to be sent just prior to any 3DSTATE_VS,
2737 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2738 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2739 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2740 * PIPE_CONTROL needs to be sent before any combination of VS
2741 * associated 3DSTATE."
2742 */
2743 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
2744 pc.DepthStallEnable = true;
2745 pc.PostSyncOperation = WriteImmediateData;
2746 pc.Address =
2747 (struct anv_address) { cmd_buffer->device->workaround_bo, 0 };
2748 }
2749 }
2750 #endif
2751
2752 /* Render targets live in the same binding table as fragment descriptors */
2753 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_RENDER_TARGETS)
2754 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
2755
2756 /* We emit the binding tables and sampler tables first, then emit push
2757 * constants and then finally emit binding table and sampler table
2758 * pointers. It has to happen in this order, since emitting the binding
2759 * tables may change the push constants (in case of storage images). After
2760 * emitting push constants, on SKL+ we have to emit the corresponding
2761 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2762 */
2763 uint32_t dirty = 0;
2764 if (cmd_buffer->state.descriptors_dirty)
2765 dirty = flush_descriptor_sets(cmd_buffer);
2766
2767 if (dirty || cmd_buffer->state.push_constants_dirty) {
2768 /* Because we're pushing UBOs, we have to push whenever either
2769 * descriptors or push constants is dirty.
2770 */
2771 dirty |= cmd_buffer->state.push_constants_dirty;
2772 dirty &= ANV_STAGE_MASK & VK_SHADER_STAGE_ALL_GRAPHICS;
2773 cmd_buffer_flush_push_constants(cmd_buffer, dirty);
2774 }
2775
2776 if (dirty)
2777 cmd_buffer_emit_descriptor_pointers(cmd_buffer, dirty);
2778
2779 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
2780 gen8_cmd_buffer_emit_viewport(cmd_buffer);
2781
2782 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2783 ANV_CMD_DIRTY_PIPELINE)) {
2784 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer,
2785 pipeline->depth_clamp_enable);
2786 }
2787
2788 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_SCISSOR |
2789 ANV_CMD_DIRTY_RENDER_TARGETS))
2790 gen7_cmd_buffer_emit_scissor(cmd_buffer);
2791
2792 genX(cmd_buffer_flush_dynamic_state)(cmd_buffer);
2793
2794 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
2795 }
2796
2797 static void
2798 emit_vertex_bo(struct anv_cmd_buffer *cmd_buffer,
2799 struct anv_address addr,
2800 uint32_t size, uint32_t index)
2801 {
2802 uint32_t *p = anv_batch_emitn(&cmd_buffer->batch, 5,
2803 GENX(3DSTATE_VERTEX_BUFFERS));
2804
2805 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, p + 1,
2806 &(struct GENX(VERTEX_BUFFER_STATE)) {
2807 .VertexBufferIndex = index,
2808 .AddressModifyEnable = true,
2809 .BufferPitch = 0,
2810 .MOCS = addr.bo ? anv_mocs_for_bo(cmd_buffer->device, addr.bo) : 0,
2811 .NullVertexBuffer = size == 0,
2812 #if (GEN_GEN >= 8)
2813 .BufferStartingAddress = addr,
2814 .BufferSize = size
2815 #else
2816 .BufferStartingAddress = addr,
2817 .EndAddress = anv_address_add(addr, size),
2818 #endif
2819 });
2820 }
2821
2822 static void
2823 emit_base_vertex_instance_bo(struct anv_cmd_buffer *cmd_buffer,
2824 struct anv_address addr)
2825 {
2826 emit_vertex_bo(cmd_buffer, addr, addr.bo ? 8 : 0, ANV_SVGS_VB_INDEX);
2827 }
2828
2829 static void
2830 emit_base_vertex_instance(struct anv_cmd_buffer *cmd_buffer,
2831 uint32_t base_vertex, uint32_t base_instance)
2832 {
2833 if (base_vertex == 0 && base_instance == 0) {
2834 emit_base_vertex_instance_bo(cmd_buffer, ANV_NULL_ADDRESS);
2835 } else {
2836 struct anv_state id_state =
2837 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 8, 4);
2838
2839 ((uint32_t *)id_state.map)[0] = base_vertex;
2840 ((uint32_t *)id_state.map)[1] = base_instance;
2841
2842 struct anv_address addr = {
2843 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
2844 .offset = id_state.offset,
2845 };
2846
2847 emit_base_vertex_instance_bo(cmd_buffer, addr);
2848 }
2849 }
2850
2851 static void
2852 emit_draw_index(struct anv_cmd_buffer *cmd_buffer, uint32_t draw_index)
2853 {
2854 struct anv_state state =
2855 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 4, 4);
2856
2857 ((uint32_t *)state.map)[0] = draw_index;
2858
2859 struct anv_address addr = {
2860 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
2861 .offset = state.offset,
2862 };
2863
2864 emit_vertex_bo(cmd_buffer, addr, 4, ANV_DRAWID_VB_INDEX);
2865 }
2866
2867 void genX(CmdDraw)(
2868 VkCommandBuffer commandBuffer,
2869 uint32_t vertexCount,
2870 uint32_t instanceCount,
2871 uint32_t firstVertex,
2872 uint32_t firstInstance)
2873 {
2874 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
2875 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
2876 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
2877
2878 if (anv_batch_has_error(&cmd_buffer->batch))
2879 return;
2880
2881 genX(cmd_buffer_flush_state)(cmd_buffer);
2882
2883 if (cmd_buffer->state.conditional_render_enabled)
2884 genX(cmd_emit_conditional_render_predicate)(cmd_buffer);
2885
2886 if (vs_prog_data->uses_firstvertex ||
2887 vs_prog_data->uses_baseinstance)
2888 emit_base_vertex_instance(cmd_buffer, firstVertex, firstInstance);
2889 if (vs_prog_data->uses_drawid)
2890 emit_draw_index(cmd_buffer, 0);
2891
2892 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2893 * different views. We need to multiply instanceCount by the view count.
2894 */
2895 instanceCount *= anv_subpass_view_count(cmd_buffer->state.subpass);
2896
2897 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
2898 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
2899 prim.VertexAccessType = SEQUENTIAL;
2900 prim.PrimitiveTopologyType = pipeline->topology;
2901 prim.VertexCountPerInstance = vertexCount;
2902 prim.StartVertexLocation = firstVertex;
2903 prim.InstanceCount = instanceCount;
2904 prim.StartInstanceLocation = firstInstance;
2905 prim.BaseVertexLocation = 0;
2906 }
2907 }
2908
2909 void genX(CmdDrawIndexed)(
2910 VkCommandBuffer commandBuffer,
2911 uint32_t indexCount,
2912 uint32_t instanceCount,
2913 uint32_t firstIndex,
2914 int32_t vertexOffset,
2915 uint32_t firstInstance)
2916 {
2917 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
2918 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
2919 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
2920
2921 if (anv_batch_has_error(&cmd_buffer->batch))
2922 return;
2923
2924 genX(cmd_buffer_flush_state)(cmd_buffer);
2925
2926 if (cmd_buffer->state.conditional_render_enabled)
2927 genX(cmd_emit_conditional_render_predicate)(cmd_buffer);
2928
2929 if (vs_prog_data->uses_firstvertex ||
2930 vs_prog_data->uses_baseinstance)
2931 emit_base_vertex_instance(cmd_buffer, vertexOffset, firstInstance);
2932 if (vs_prog_data->uses_drawid)
2933 emit_draw_index(cmd_buffer, 0);
2934
2935 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2936 * different views. We need to multiply instanceCount by the view count.
2937 */
2938 instanceCount *= anv_subpass_view_count(cmd_buffer->state.subpass);
2939
2940 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
2941 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
2942 prim.VertexAccessType = RANDOM;
2943 prim.PrimitiveTopologyType = pipeline->topology;
2944 prim.VertexCountPerInstance = indexCount;
2945 prim.StartVertexLocation = firstIndex;
2946 prim.InstanceCount = instanceCount;
2947 prim.StartInstanceLocation = firstInstance;
2948 prim.BaseVertexLocation = vertexOffset;
2949 }
2950 }
2951
2952 /* Auto-Draw / Indirect Registers */
2953 #define GEN7_3DPRIM_END_OFFSET 0x2420
2954 #define GEN7_3DPRIM_START_VERTEX 0x2430
2955 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2956 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2957 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2958 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2959
2960 void genX(CmdDrawIndirectByteCountEXT)(
2961 VkCommandBuffer commandBuffer,
2962 uint32_t instanceCount,
2963 uint32_t firstInstance,
2964 VkBuffer counterBuffer,
2965 VkDeviceSize counterBufferOffset,
2966 uint32_t counterOffset,
2967 uint32_t vertexStride)
2968 {
2969 #if GEN_IS_HASWELL || GEN_GEN >= 8
2970 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
2971 ANV_FROM_HANDLE(anv_buffer, counter_buffer, counterBuffer);
2972 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
2973 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
2974
2975 /* firstVertex is always zero for this draw function */
2976 const uint32_t firstVertex = 0;
2977
2978 if (anv_batch_has_error(&cmd_buffer->batch))
2979 return;
2980
2981 genX(cmd_buffer_flush_state)(cmd_buffer);
2982
2983 if (vs_prog_data->uses_firstvertex ||
2984 vs_prog_data->uses_baseinstance)
2985 emit_base_vertex_instance(cmd_buffer, firstVertex, firstInstance);
2986 if (vs_prog_data->uses_drawid)
2987 emit_draw_index(cmd_buffer, 0);
2988
2989 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2990 * different views. We need to multiply instanceCount by the view count.
2991 */
2992 instanceCount *= anv_subpass_view_count(cmd_buffer->state.subpass);
2993
2994 struct gen_mi_builder b;
2995 gen_mi_builder_init(&b, &cmd_buffer->batch);
2996 struct gen_mi_value count =
2997 gen_mi_mem32(anv_address_add(counter_buffer->address,
2998 counterBufferOffset));
2999 if (counterOffset)
3000 count = gen_mi_isub(&b, count, gen_mi_imm(counterOffset));
3001 count = gen_mi_udiv32_imm(&b, count, vertexStride);
3002 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT), count);
3003
3004 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX),
3005 gen_mi_imm(firstVertex));
3006 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT),
3007 gen_mi_imm(instanceCount));
3008 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE),
3009 gen_mi_imm(firstInstance));
3010 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX), gen_mi_imm(0));
3011
3012 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
3013 prim.IndirectParameterEnable = true;
3014 prim.VertexAccessType = SEQUENTIAL;
3015 prim.PrimitiveTopologyType = pipeline->topology;
3016 }
3017 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3018 }
3019
3020 static void
3021 load_indirect_parameters(struct anv_cmd_buffer *cmd_buffer,
3022 struct anv_address addr,
3023 bool indexed)
3024 {
3025 struct gen_mi_builder b;
3026 gen_mi_builder_init(&b, &cmd_buffer->batch);
3027
3028 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT),
3029 gen_mi_mem32(anv_address_add(addr, 0)));
3030
3031 struct gen_mi_value instance_count = gen_mi_mem32(anv_address_add(addr, 4));
3032 unsigned view_count = anv_subpass_view_count(cmd_buffer->state.subpass);
3033 if (view_count > 1) {
3034 #if GEN_IS_HASWELL || GEN_GEN >= 8
3035 instance_count = gen_mi_imul_imm(&b, instance_count, view_count);
3036 #else
3037 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3038 "MI_MATH is not supported on Ivy Bridge");
3039 #endif
3040 }
3041 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT), instance_count);
3042
3043 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX),
3044 gen_mi_mem32(anv_address_add(addr, 8)));
3045
3046 if (indexed) {
3047 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX),
3048 gen_mi_mem32(anv_address_add(addr, 12)));
3049 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE),
3050 gen_mi_mem32(anv_address_add(addr, 16)));
3051 } else {
3052 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE),
3053 gen_mi_mem32(anv_address_add(addr, 12)));
3054 gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX), gen_mi_imm(0));
3055 }
3056 }
3057
3058 void genX(CmdDrawIndirect)(
3059 VkCommandBuffer commandBuffer,
3060 VkBuffer _buffer,
3061 VkDeviceSize offset,
3062 uint32_t drawCount,
3063 uint32_t stride)
3064 {
3065 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3066 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
3067 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
3068 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
3069
3070 if (anv_batch_has_error(&cmd_buffer->batch))
3071 return;
3072
3073 genX(cmd_buffer_flush_state)(cmd_buffer);
3074
3075 if (cmd_buffer->state.conditional_render_enabled)
3076 genX(cmd_emit_conditional_render_predicate)(cmd_buffer);
3077
3078 for (uint32_t i = 0; i < drawCount; i++) {
3079 struct anv_address draw = anv_address_add(buffer->address, offset);
3080
3081 if (vs_prog_data->uses_firstvertex ||
3082 vs_prog_data->uses_baseinstance)
3083 emit_base_vertex_instance_bo(cmd_buffer, anv_address_add(draw, 8));
3084 if (vs_prog_data->uses_drawid)
3085 emit_draw_index(cmd_buffer, i);
3086
3087 load_indirect_parameters(cmd_buffer, draw, false);
3088
3089 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
3090 prim.IndirectParameterEnable = true;
3091 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
3092 prim.VertexAccessType = SEQUENTIAL;
3093 prim.PrimitiveTopologyType = pipeline->topology;
3094 }
3095
3096 offset += stride;
3097 }
3098 }
3099
3100 void genX(CmdDrawIndexedIndirect)(
3101 VkCommandBuffer commandBuffer,
3102 VkBuffer _buffer,
3103 VkDeviceSize offset,
3104 uint32_t drawCount,
3105 uint32_t stride)
3106 {
3107 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3108 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
3109 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
3110 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
3111
3112 if (anv_batch_has_error(&cmd_buffer->batch))
3113 return;
3114
3115 genX(cmd_buffer_flush_state)(cmd_buffer);
3116
3117 if (cmd_buffer->state.conditional_render_enabled)
3118 genX(cmd_emit_conditional_render_predicate)(cmd_buffer);
3119
3120 for (uint32_t i = 0; i < drawCount; i++) {
3121 struct anv_address draw = anv_address_add(buffer->address, offset);
3122
3123 /* TODO: We need to stomp base vertex to 0 somehow */
3124 if (vs_prog_data->uses_firstvertex ||
3125 vs_prog_data->uses_baseinstance)
3126 emit_base_vertex_instance_bo(cmd_buffer, anv_address_add(draw, 12));
3127 if (vs_prog_data->uses_drawid)
3128 emit_draw_index(cmd_buffer, i);
3129
3130 load_indirect_parameters(cmd_buffer, draw, true);
3131
3132 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
3133 prim.IndirectParameterEnable = true;
3134 prim.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
3135 prim.VertexAccessType = RANDOM;
3136 prim.PrimitiveTopologyType = pipeline->topology;
3137 }
3138
3139 offset += stride;
3140 }
3141 }
3142
3143 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3144
3145 static void
3146 prepare_for_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer,
3147 struct anv_address count_address,
3148 const bool conditional_render_enabled)
3149 {
3150 struct gen_mi_builder b;
3151 gen_mi_builder_init(&b, &cmd_buffer->batch);
3152
3153 if (conditional_render_enabled) {
3154 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3155 gen_mi_store(&b, gen_mi_reg64(TMP_DRAW_COUNT_REG),
3156 gen_mi_mem32(count_address));
3157 #endif
3158 } else {
3159 /* Upload the current draw count from the draw parameters buffer to
3160 * MI_PREDICATE_SRC0.
3161 */
3162 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
3163 gen_mi_mem32(count_address));
3164
3165 gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC1 + 4), gen_mi_imm(0));
3166 }
3167 }
3168
3169 static void
3170 emit_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer,
3171 uint32_t draw_index)
3172 {
3173 struct gen_mi_builder b;
3174 gen_mi_builder_init(&b, &cmd_buffer->batch);
3175
3176 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3177 gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC1), gen_mi_imm(draw_index));
3178
3179 if (draw_index == 0) {
3180 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
3181 mip.LoadOperation = LOAD_LOADINV;
3182 mip.CombineOperation = COMBINE_SET;
3183 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3184 }
3185 } else {
3186 /* While draw_index < draw_count the predicate's result will be
3187 * (draw_index == draw_count) ^ TRUE = TRUE
3188 * When draw_index == draw_count the result is
3189 * (TRUE) ^ TRUE = FALSE
3190 * After this all results will be:
3191 * (FALSE) ^ FALSE = FALSE
3192 */
3193 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
3194 mip.LoadOperation = LOAD_LOAD;
3195 mip.CombineOperation = COMBINE_XOR;
3196 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3197 }
3198 }
3199 }
3200
3201 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3202 static void
3203 emit_draw_count_predicate_with_conditional_render(
3204 struct anv_cmd_buffer *cmd_buffer,
3205 uint32_t draw_index)
3206 {
3207 struct gen_mi_builder b;
3208 gen_mi_builder_init(&b, &cmd_buffer->batch);
3209
3210 struct gen_mi_value pred = gen_mi_ult(&b, gen_mi_imm(draw_index),
3211 gen_mi_reg64(TMP_DRAW_COUNT_REG));
3212 pred = gen_mi_iand(&b, pred, gen_mi_reg64(ANV_PREDICATE_RESULT_REG));
3213
3214 #if GEN_GEN >= 8
3215 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_RESULT), pred);
3216 #else
3217 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3218 * so we emit MI_PREDICATE to set it.
3219 */
3220
3221 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), pred);
3222 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
3223
3224 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
3225 mip.LoadOperation = LOAD_LOADINV;
3226 mip.CombineOperation = COMBINE_SET;
3227 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3228 }
3229 #endif
3230 }
3231 #endif
3232
3233 void genX(CmdDrawIndirectCountKHR)(
3234 VkCommandBuffer commandBuffer,
3235 VkBuffer _buffer,
3236 VkDeviceSize offset,
3237 VkBuffer _countBuffer,
3238 VkDeviceSize countBufferOffset,
3239 uint32_t maxDrawCount,
3240 uint32_t stride)
3241 {
3242 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3243 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
3244 ANV_FROM_HANDLE(anv_buffer, count_buffer, _countBuffer);
3245 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
3246 struct anv_pipeline *pipeline = cmd_state->gfx.base.pipeline;
3247 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
3248
3249 if (anv_batch_has_error(&cmd_buffer->batch))
3250 return;
3251
3252 genX(cmd_buffer_flush_state)(cmd_buffer);
3253
3254 struct anv_address count_address =
3255 anv_address_add(count_buffer->address, countBufferOffset);
3256
3257 prepare_for_draw_count_predicate(cmd_buffer, count_address,
3258 cmd_state->conditional_render_enabled);
3259
3260 for (uint32_t i = 0; i < maxDrawCount; i++) {
3261 struct anv_address draw = anv_address_add(buffer->address, offset);
3262
3263 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3264 if (cmd_state->conditional_render_enabled) {
3265 emit_draw_count_predicate_with_conditional_render(cmd_buffer, i);
3266 } else {
3267 emit_draw_count_predicate(cmd_buffer, i);
3268 }
3269 #else
3270 emit_draw_count_predicate(cmd_buffer, i);
3271 #endif
3272
3273 if (vs_prog_data->uses_firstvertex ||
3274 vs_prog_data->uses_baseinstance)
3275 emit_base_vertex_instance_bo(cmd_buffer, anv_address_add(draw, 8));
3276 if (vs_prog_data->uses_drawid)
3277 emit_draw_index(cmd_buffer, i);
3278
3279 load_indirect_parameters(cmd_buffer, draw, false);
3280
3281 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
3282 prim.IndirectParameterEnable = true;
3283 prim.PredicateEnable = true;
3284 prim.VertexAccessType = SEQUENTIAL;
3285 prim.PrimitiveTopologyType = pipeline->topology;
3286 }
3287
3288 offset += stride;
3289 }
3290 }
3291
3292 void genX(CmdDrawIndexedIndirectCountKHR)(
3293 VkCommandBuffer commandBuffer,
3294 VkBuffer _buffer,
3295 VkDeviceSize offset,
3296 VkBuffer _countBuffer,
3297 VkDeviceSize countBufferOffset,
3298 uint32_t maxDrawCount,
3299 uint32_t stride)
3300 {
3301 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3302 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
3303 ANV_FROM_HANDLE(anv_buffer, count_buffer, _countBuffer);
3304 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
3305 struct anv_pipeline *pipeline = cmd_state->gfx.base.pipeline;
3306 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
3307
3308 if (anv_batch_has_error(&cmd_buffer->batch))
3309 return;
3310
3311 genX(cmd_buffer_flush_state)(cmd_buffer);
3312
3313 struct anv_address count_address =
3314 anv_address_add(count_buffer->address, countBufferOffset);
3315
3316 prepare_for_draw_count_predicate(cmd_buffer, count_address,
3317 cmd_state->conditional_render_enabled);
3318
3319 for (uint32_t i = 0; i < maxDrawCount; i++) {
3320 struct anv_address draw = anv_address_add(buffer->address, offset);
3321
3322 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3323 if (cmd_state->conditional_render_enabled) {
3324 emit_draw_count_predicate_with_conditional_render(cmd_buffer, i);
3325 } else {
3326 emit_draw_count_predicate(cmd_buffer, i);
3327 }
3328 #else
3329 emit_draw_count_predicate(cmd_buffer, i);
3330 #endif
3331
3332 /* TODO: We need to stomp base vertex to 0 somehow */
3333 if (vs_prog_data->uses_firstvertex ||
3334 vs_prog_data->uses_baseinstance)
3335 emit_base_vertex_instance_bo(cmd_buffer, anv_address_add(draw, 12));
3336 if (vs_prog_data->uses_drawid)
3337 emit_draw_index(cmd_buffer, i);
3338
3339 load_indirect_parameters(cmd_buffer, draw, true);
3340
3341 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
3342 prim.IndirectParameterEnable = true;
3343 prim.PredicateEnable = true;
3344 prim.VertexAccessType = RANDOM;
3345 prim.PrimitiveTopologyType = pipeline->topology;
3346 }
3347
3348 offset += stride;
3349 }
3350 }
3351
3352 void genX(CmdBeginTransformFeedbackEXT)(
3353 VkCommandBuffer commandBuffer,
3354 uint32_t firstCounterBuffer,
3355 uint32_t counterBufferCount,
3356 const VkBuffer* pCounterBuffers,
3357 const VkDeviceSize* pCounterBufferOffsets)
3358 {
3359 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3360
3361 assert(firstCounterBuffer < MAX_XFB_BUFFERS);
3362 assert(counterBufferCount <= MAX_XFB_BUFFERS);
3363 assert(firstCounterBuffer + counterBufferCount <= MAX_XFB_BUFFERS);
3364
3365 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3366 *
3367 * "Ssoftware must ensure that no HW stream output operations can be in
3368 * process or otherwise pending at the point that the MI_LOAD/STORE
3369 * commands are processed. This will likely require a pipeline flush."
3370 */
3371 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
3372 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
3373
3374 for (uint32_t idx = 0; idx < MAX_XFB_BUFFERS; idx++) {
3375 /* If we have a counter buffer, this is a resume so we need to load the
3376 * value into the streamout offset register. Otherwise, this is a begin
3377 * and we need to reset it to zero.
3378 */
3379 if (pCounterBuffers &&
3380 idx >= firstCounterBuffer &&
3381 idx - firstCounterBuffer < counterBufferCount &&
3382 pCounterBuffers[idx - firstCounterBuffer] != VK_NULL_HANDLE) {
3383 uint32_t cb_idx = idx - firstCounterBuffer;
3384 ANV_FROM_HANDLE(anv_buffer, counter_buffer, pCounterBuffers[cb_idx]);
3385 uint64_t offset = pCounterBufferOffsets ?
3386 pCounterBufferOffsets[cb_idx] : 0;
3387
3388 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
3389 lrm.RegisterAddress = GENX(SO_WRITE_OFFSET0_num) + idx * 4;
3390 lrm.MemoryAddress = anv_address_add(counter_buffer->address,
3391 offset);
3392 }
3393 } else {
3394 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
3395 lri.RegisterOffset = GENX(SO_WRITE_OFFSET0_num) + idx * 4;
3396 lri.DataDWord = 0;
3397 }
3398 }
3399 }
3400
3401 cmd_buffer->state.xfb_enabled = true;
3402 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_XFB_ENABLE;
3403 }
3404
3405 void genX(CmdEndTransformFeedbackEXT)(
3406 VkCommandBuffer commandBuffer,
3407 uint32_t firstCounterBuffer,
3408 uint32_t counterBufferCount,
3409 const VkBuffer* pCounterBuffers,
3410 const VkDeviceSize* pCounterBufferOffsets)
3411 {
3412 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3413
3414 assert(firstCounterBuffer < MAX_XFB_BUFFERS);
3415 assert(counterBufferCount <= MAX_XFB_BUFFERS);
3416 assert(firstCounterBuffer + counterBufferCount <= MAX_XFB_BUFFERS);
3417
3418 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3419 *
3420 * "Ssoftware must ensure that no HW stream output operations can be in
3421 * process or otherwise pending at the point that the MI_LOAD/STORE
3422 * commands are processed. This will likely require a pipeline flush."
3423 */
3424 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
3425 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
3426
3427 for (uint32_t cb_idx = 0; cb_idx < counterBufferCount; cb_idx++) {
3428 unsigned idx = firstCounterBuffer + cb_idx;
3429
3430 /* If we have a counter buffer, this is a resume so we need to load the
3431 * value into the streamout offset register. Otherwise, this is a begin
3432 * and we need to reset it to zero.
3433 */
3434 if (pCounterBuffers &&
3435 cb_idx < counterBufferCount &&
3436 pCounterBuffers[cb_idx] != VK_NULL_HANDLE) {
3437 ANV_FROM_HANDLE(anv_buffer, counter_buffer, pCounterBuffers[cb_idx]);
3438 uint64_t offset = pCounterBufferOffsets ?
3439 pCounterBufferOffsets[cb_idx] : 0;
3440
3441 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) {
3442 srm.MemoryAddress = anv_address_add(counter_buffer->address,
3443 offset);
3444 srm.RegisterAddress = GENX(SO_WRITE_OFFSET0_num) + idx * 4;
3445 }
3446 }
3447 }
3448
3449 cmd_buffer->state.xfb_enabled = false;
3450 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_XFB_ENABLE;
3451 }
3452
3453 static VkResult
3454 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
3455 {
3456 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
3457 struct anv_state surfaces = { 0, }, samplers = { 0, };
3458 VkResult result;
3459
3460 result = emit_binding_table(cmd_buffer, MESA_SHADER_COMPUTE, &surfaces);
3461 if (result != VK_SUCCESS) {
3462 assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
3463
3464 result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
3465 if (result != VK_SUCCESS)
3466 return result;
3467
3468 /* Re-emit state base addresses so we get the new surface state base
3469 * address before we start emitting binding tables etc.
3470 */
3471 genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
3472
3473 result = emit_binding_table(cmd_buffer, MESA_SHADER_COMPUTE, &surfaces);
3474 if (result != VK_SUCCESS) {
3475 anv_batch_set_error(&cmd_buffer->batch, result);
3476 return result;
3477 }
3478 }
3479
3480 result = emit_samplers(cmd_buffer, MESA_SHADER_COMPUTE, &samplers);
3481 if (result != VK_SUCCESS) {
3482 anv_batch_set_error(&cmd_buffer->batch, result);
3483 return result;
3484 }
3485
3486 uint32_t iface_desc_data_dw[GENX(INTERFACE_DESCRIPTOR_DATA_length)];
3487 struct GENX(INTERFACE_DESCRIPTOR_DATA) desc = {
3488 .BindingTablePointer = surfaces.offset,
3489 .SamplerStatePointer = samplers.offset,
3490 };
3491 GENX(INTERFACE_DESCRIPTOR_DATA_pack)(NULL, iface_desc_data_dw, &desc);
3492
3493 struct anv_state state =
3494 anv_cmd_buffer_merge_dynamic(cmd_buffer, iface_desc_data_dw,
3495 pipeline->interface_descriptor_data,
3496 GENX(INTERFACE_DESCRIPTOR_DATA_length),
3497 64);
3498
3499 uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
3500 anv_batch_emit(&cmd_buffer->batch,
3501 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
3502 mid.InterfaceDescriptorTotalLength = size;
3503 mid.InterfaceDescriptorDataStartAddress = state.offset;
3504 }
3505
3506 return VK_SUCCESS;
3507 }
3508
3509 void
3510 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
3511 {
3512 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
3513 VkResult result;
3514
3515 assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
3516
3517 genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->urb.l3_config);
3518
3519 genX(flush_pipeline_select_gpgpu)(cmd_buffer);
3520
3521 #if GEN_GEN >= 12
3522 genX(cmd_buffer_aux_map_state)(cmd_buffer);
3523 #endif
3524
3525 if (cmd_buffer->state.compute.pipeline_dirty) {
3526 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3527 *
3528 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3529 * the only bits that are changed are scoreboard related: Scoreboard
3530 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3531 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3532 * sufficient."
3533 */
3534 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
3535 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
3536
3537 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
3538
3539 /* The workgroup size of the pipeline affects our push constant layout
3540 * so flag push constants as dirty if we change the pipeline.
3541 */
3542 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
3543 }
3544
3545 if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
3546 cmd_buffer->state.compute.pipeline_dirty) {
3547 /* FIXME: figure out descriptors for gen7 */
3548 result = flush_compute_descriptor_set(cmd_buffer);
3549 if (result != VK_SUCCESS)
3550 return;
3551
3552 cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
3553 }
3554
3555 if (cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_COMPUTE_BIT) {
3556 struct anv_state push_state =
3557 anv_cmd_buffer_cs_push_constants(cmd_buffer);
3558
3559 if (push_state.alloc_size) {
3560 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
3561 curbe.CURBETotalDataLength = push_state.alloc_size;
3562 curbe.CURBEDataStartAddress = push_state.offset;
3563 }
3564 }
3565
3566 cmd_buffer->state.push_constants_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
3567 }
3568
3569 cmd_buffer->state.compute.pipeline_dirty = false;
3570
3571 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
3572 }
3573
3574 #if GEN_GEN == 7
3575
3576 static VkResult
3577 verify_cmd_parser(const struct anv_device *device,
3578 int required_version,
3579 const char *function)
3580 {
3581 if (device->instance->physicalDevice.cmd_parser_version < required_version) {
3582 return vk_errorf(device->instance, device->instance,
3583 VK_ERROR_FEATURE_NOT_PRESENT,
3584 "cmd parser version %d is required for %s",
3585 required_version, function);
3586 } else {
3587 return VK_SUCCESS;
3588 }
3589 }
3590
3591 #endif
3592
3593 static void
3594 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer *cmd_buffer,
3595 uint32_t baseGroupX,
3596 uint32_t baseGroupY,
3597 uint32_t baseGroupZ)
3598 {
3599 if (anv_batch_has_error(&cmd_buffer->batch))
3600 return;
3601
3602 struct anv_push_constants *push =
3603 &cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
3604 if (push->cs.base_work_group_id[0] != baseGroupX ||
3605 push->cs.base_work_group_id[1] != baseGroupY ||
3606 push->cs.base_work_group_id[2] != baseGroupZ) {
3607 push->cs.base_work_group_id[0] = baseGroupX;
3608 push->cs.base_work_group_id[1] = baseGroupY;
3609 push->cs.base_work_group_id[2] = baseGroupZ;
3610
3611 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
3612 }
3613 }
3614
3615 void genX(CmdDispatch)(
3616 VkCommandBuffer commandBuffer,
3617 uint32_t x,
3618 uint32_t y,
3619 uint32_t z)
3620 {
3621 genX(CmdDispatchBase)(commandBuffer, 0, 0, 0, x, y, z);
3622 }
3623
3624 void genX(CmdDispatchBase)(
3625 VkCommandBuffer commandBuffer,
3626 uint32_t baseGroupX,
3627 uint32_t baseGroupY,
3628 uint32_t baseGroupZ,
3629 uint32_t groupCountX,
3630 uint32_t groupCountY,
3631 uint32_t groupCountZ)
3632 {
3633 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3634 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
3635 const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
3636
3637 anv_cmd_buffer_push_base_group_id(cmd_buffer, baseGroupX,
3638 baseGroupY, baseGroupZ);
3639
3640 if (anv_batch_has_error(&cmd_buffer->batch))
3641 return;
3642
3643 if (prog_data->uses_num_work_groups) {
3644 struct anv_state state =
3645 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 12, 4);
3646 uint32_t *sizes = state.map;
3647 sizes[0] = groupCountX;
3648 sizes[1] = groupCountY;
3649 sizes[2] = groupCountZ;
3650 cmd_buffer->state.compute.num_workgroups = (struct anv_address) {
3651 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
3652 .offset = state.offset,
3653 };
3654 }
3655
3656 genX(cmd_buffer_flush_compute_state)(cmd_buffer);
3657
3658 if (cmd_buffer->state.conditional_render_enabled)
3659 genX(cmd_emit_conditional_render_predicate)(cmd_buffer);
3660
3661 anv_batch_emit(&cmd_buffer->batch, GENX(GPGPU_WALKER), ggw) {
3662 ggw.PredicateEnable = cmd_buffer->state.conditional_render_enabled;
3663 ggw.SIMDSize = prog_data->simd_size / 16;
3664 ggw.ThreadDepthCounterMaximum = 0;
3665 ggw.ThreadHeightCounterMaximum = 0;
3666 ggw.ThreadWidthCounterMaximum = prog_data->threads - 1;
3667 ggw.ThreadGroupIDXDimension = groupCountX;
3668 ggw.ThreadGroupIDYDimension = groupCountY;
3669 ggw.ThreadGroupIDZDimension = groupCountZ;
3670 ggw.RightExecutionMask = pipeline->cs_right_mask;
3671 ggw.BottomExecutionMask = 0xffffffff;
3672 }
3673
3674 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_STATE_FLUSH), msf);
3675 }
3676
3677 #define GPGPU_DISPATCHDIMX 0x2500
3678 #define GPGPU_DISPATCHDIMY 0x2504
3679 #define GPGPU_DISPATCHDIMZ 0x2508
3680
3681 void genX(CmdDispatchIndirect)(
3682 VkCommandBuffer commandBuffer,
3683 VkBuffer _buffer,
3684 VkDeviceSize offset)
3685 {
3686 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
3687 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
3688 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
3689 const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
3690 struct anv_address addr = anv_address_add(buffer->address, offset);
3691 struct anv_batch *batch = &cmd_buffer->batch;
3692
3693 anv_cmd_buffer_push_base_group_id(cmd_buffer, 0, 0, 0);
3694
3695 #if GEN_GEN == 7
3696 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3697 * indirect dispatch registers to be written.
3698 */
3699 if (verify_cmd_parser(cmd_buffer->device, 5,
3700 "vkCmdDispatchIndirect") != VK_SUCCESS)
3701 return;
3702 #endif
3703
3704 if (prog_data->uses_num_work_groups)
3705 cmd_buffer->state.compute.num_workgroups = addr;
3706
3707 genX(cmd_buffer_flush_compute_state)(cmd_buffer);
3708
3709 struct gen_mi_builder b;
3710 gen_mi_builder_init(&b, &cmd_buffer->batch);
3711
3712 struct gen_mi_value size_x = gen_mi_mem32(anv_address_add(addr, 0));
3713 struct gen_mi_value size_y = gen_mi_mem32(anv_address_add(addr, 4));
3714 struct gen_mi_value size_z = gen_mi_mem32(anv_address_add(addr, 8));
3715
3716 gen_mi_store(&b, gen_mi_reg32(GPGPU_DISPATCHDIMX), size_x);
3717 gen_mi_store(&b, gen_mi_reg32(GPGPU_DISPATCHDIMY), size_y);
3718 gen_mi_store(&b, gen_mi_reg32(GPGPU_DISPATCHDIMZ), size_z);
3719
3720 #if GEN_GEN <= 7
3721 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3722 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), size_x);
3723 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
3724 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
3725 mip.LoadOperation = LOAD_LOAD;
3726 mip.CombineOperation = COMBINE_SET;
3727 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3728 }
3729
3730 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3731 gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC0), size_y);
3732 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
3733 mip.LoadOperation = LOAD_LOAD;
3734 mip.CombineOperation = COMBINE_OR;
3735 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3736 }
3737
3738 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3739 gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC0), size_z);
3740 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
3741 mip.LoadOperation = LOAD_LOAD;
3742 mip.CombineOperation = COMBINE_OR;
3743 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3744 }
3745
3746 /* predicate = !predicate; */
3747 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
3748 mip.LoadOperation = LOAD_LOADINV;
3749 mip.CombineOperation = COMBINE_OR;
3750 mip.CompareOperation = COMPARE_FALSE;
3751 }
3752
3753 #if GEN_IS_HASWELL
3754 if (cmd_buffer->state.conditional_render_enabled) {
3755 /* predicate &= !(conditional_rendering_predicate == 0); */
3756 gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC0),
3757 gen_mi_reg32(ANV_PREDICATE_RESULT_REG));
3758 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
3759 mip.LoadOperation = LOAD_LOADINV;
3760 mip.CombineOperation = COMBINE_AND;
3761 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3762 }
3763 }
3764 #endif
3765
3766 #else /* GEN_GEN > 7 */
3767 if (cmd_buffer->state.conditional_render_enabled)
3768 genX(cmd_emit_conditional_render_predicate)(cmd_buffer);
3769 #endif
3770
3771 anv_batch_emit(batch, GENX(GPGPU_WALKER), ggw) {
3772 ggw.IndirectParameterEnable = true;
3773 ggw.PredicateEnable = GEN_GEN <= 7 ||
3774 cmd_buffer->state.conditional_render_enabled;
3775 ggw.SIMDSize = prog_data->simd_size / 16;
3776 ggw.ThreadDepthCounterMaximum = 0;
3777 ggw.ThreadHeightCounterMaximum = 0;
3778 ggw.ThreadWidthCounterMaximum = prog_data->threads - 1;
3779 ggw.RightExecutionMask = pipeline->cs_right_mask;
3780 ggw.BottomExecutionMask = 0xffffffff;
3781 }
3782
3783 anv_batch_emit(batch, GENX(MEDIA_STATE_FLUSH), msf);
3784 }
3785
3786 static void
3787 genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
3788 uint32_t pipeline)
3789 {
3790 UNUSED const struct gen_device_info *devinfo = &cmd_buffer->device->info;
3791
3792 if (cmd_buffer->state.current_pipeline == pipeline)
3793 return;
3794
3795 #if GEN_GEN >= 8 && GEN_GEN < 10
3796 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3797 *
3798 * Software must clear the COLOR_CALC_STATE Valid field in
3799 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3800 * with Pipeline Select set to GPGPU.
3801 *
3802 * The internal hardware docs recommend the same workaround for Gen9
3803 * hardware too.
3804 */
3805 if (pipeline == GPGPU)
3806 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
3807 #endif
3808
3809 #if GEN_GEN == 9
3810 if (pipeline == _3D) {
3811 /* There is a mid-object preemption workaround which requires you to
3812 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
3813 * even without preemption, we have issues with geometry flickering when
3814 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
3815 * really know why.
3816 */
3817 const uint32_t subslices =
3818 MAX2(cmd_buffer->device->instance->physicalDevice.subslice_total, 1);
3819 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_VFE_STATE), vfe) {
3820 vfe.MaximumNumberofThreads =
3821 devinfo->max_cs_threads * subslices - 1;
3822 vfe.NumberofURBEntries = 2;
3823 vfe.URBEntryAllocationSize = 2;
3824 }
3825 }
3826 #endif
3827
3828 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3829 * PIPELINE_SELECT [DevBWR+]":
3830 *
3831 * Project: DEVSNB+
3832 *
3833 * Software must ensure all the write caches are flushed through a
3834 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3835 * command to invalidate read only caches prior to programming
3836 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3837 */
3838 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
3839 pc.RenderTargetCacheFlushEnable = true;
3840 pc.DepthCacheFlushEnable = true;
3841 pc.DCFlushEnable = true;
3842 pc.PostSyncOperation = NoWrite;
3843 pc.CommandStreamerStallEnable = true;
3844 #if GEN_GEN >= 12
3845 pc.TileCacheFlushEnable = true;
3846 #endif
3847 }
3848
3849 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
3850 pc.TextureCacheInvalidationEnable = true;
3851 pc.ConstantCacheInvalidationEnable = true;
3852 pc.StateCacheInvalidationEnable = true;
3853 pc.InstructionCacheInvalidateEnable = true;
3854 pc.PostSyncOperation = NoWrite;
3855 #if GEN_GEN >= 12
3856 pc.TileCacheFlushEnable = true;
3857 #endif
3858 }
3859
3860 anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {
3861 #if GEN_GEN >= 9
3862 ps.MaskBits = 3;
3863 #endif
3864 ps.PipelineSelection = pipeline;
3865 }
3866
3867 #if GEN_GEN == 9
3868 if (devinfo->is_geminilake) {
3869 /* Project: DevGLK
3870 *
3871 * "This chicken bit works around a hardware issue with barrier logic
3872 * encountered when switching between GPGPU and 3D pipelines. To
3873 * workaround the issue, this mode bit should be set after a pipeline
3874 * is selected."
3875 */
3876 uint32_t scec;
3877 anv_pack_struct(&scec, GENX(SLICE_COMMON_ECO_CHICKEN1),
3878 .GLKBarrierMode =
3879 pipeline == GPGPU ? GLK_BARRIER_MODE_GPGPU
3880 : GLK_BARRIER_MODE_3D_HULL,
3881 .GLKBarrierModeMask = 1);
3882 emit_lri(&cmd_buffer->batch, GENX(SLICE_COMMON_ECO_CHICKEN1_num), scec);
3883 }
3884 #endif
3885
3886 cmd_buffer->state.current_pipeline = pipeline;
3887 }
3888
3889 void
3890 genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer)
3891 {
3892 genX(flush_pipeline_select)(cmd_buffer, _3D);
3893 }
3894
3895 void
3896 genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer)
3897 {
3898 genX(flush_pipeline_select)(cmd_buffer, GPGPU);
3899 }
3900
3901 void
3902 genX(cmd_buffer_emit_gen7_depth_flush)(struct anv_cmd_buffer *cmd_buffer)
3903 {
3904 if (GEN_GEN >= 8)
3905 return;
3906
3907 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3908 *
3909 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3910 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3911 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3912 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3913 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3914 * Depth Flush Bit set, followed by another pipelined depth stall
3915 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3916 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3917 * via a preceding MI_FLUSH)."
3918 */
3919 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
3920 pipe.DepthStallEnable = true;
3921 }
3922 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
3923 pipe.DepthCacheFlushEnable = true;
3924 #if GEN_GEN >= 12
3925 pipe.TileCacheFlushEnable = true;
3926 #endif
3927 }
3928 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
3929 pipe.DepthStallEnable = true;
3930 }
3931 }
3932
3933 /**
3934 * Update the pixel hashing modes that determine the balancing of PS threads
3935 * across subslices and slices.
3936 *
3937 * \param width Width bound of the rendering area (already scaled down if \p
3938 * scale is greater than 1).
3939 * \param height Height bound of the rendering area (already scaled down if \p
3940 * scale is greater than 1).
3941 * \param scale The number of framebuffer samples that could potentially be
3942 * affected by an individual channel of the PS thread. This is
3943 * typically one for single-sampled rendering, but for operations
3944 * like CCS resolves and fast clears a single PS invocation may
3945 * update a huge number of pixels, in which case a finer
3946 * balancing is desirable in order to maximally utilize the
3947 * bandwidth available. UINT_MAX can be used as shorthand for
3948 * "finest hashing mode available".
3949 */
3950 void
3951 genX(cmd_buffer_emit_hashing_mode)(struct anv_cmd_buffer *cmd_buffer,
3952 unsigned width, unsigned height,
3953 unsigned scale)
3954 {
3955 #if GEN_GEN == 9
3956 const struct gen_device_info *devinfo = &cmd_buffer->device->info;
3957 const unsigned slice_hashing[] = {
3958 /* Because all Gen9 platforms with more than one slice require
3959 * three-way subslice hashing, a single "normal" 16x16 slice hashing
3960 * block is guaranteed to suffer from substantial imbalance, with one
3961 * subslice receiving twice as much work as the other two in the
3962 * slice.
3963 *
3964 * The performance impact of that would be particularly severe when
3965 * three-way hashing is also in use for slice balancing (which is the
3966 * case for all Gen9 GT4 platforms), because one of the slices
3967 * receives one every three 16x16 blocks in either direction, which
3968 * is roughly the periodicity of the underlying subslice imbalance
3969 * pattern ("roughly" because in reality the hardware's
3970 * implementation of three-way hashing doesn't do exact modulo 3
3971 * arithmetic, which somewhat decreases the magnitude of this effect
3972 * in practice). This leads to a systematic subslice imbalance
3973 * within that slice regardless of the size of the primitive. The
3974 * 32x32 hashing mode guarantees that the subslice imbalance within a
3975 * single slice hashing block is minimal, largely eliminating this
3976 * effect.
3977 */
3978 _32x32,
3979 /* Finest slice hashing mode available. */
3980 NORMAL
3981 };
3982 const unsigned subslice_hashing[] = {
3983 /* 16x16 would provide a slight cache locality benefit especially
3984 * visible in the sampler L1 cache efficiency of low-bandwidth
3985 * non-LLC platforms, but it comes at the cost of greater subslice
3986 * imbalance for primitives of dimensions approximately intermediate
3987 * between 16x4 and 16x16.
3988 */
3989 _16x4,
3990 /* Finest subslice hashing mode available. */
3991 _8x4
3992 };
3993 /* Dimensions of the smallest hashing block of a given hashing mode. If
3994 * the rendering area is smaller than this there can't possibly be any
3995 * benefit from switching to this mode, so we optimize out the
3996 * transition.
3997 */
3998 const unsigned min_size[][2] = {
3999 { 16, 4 },
4000 { 8, 4 }
4001 };
4002 const unsigned idx = scale > 1;
4003
4004 if (cmd_buffer->state.current_hash_scale != scale &&
4005 (width > min_size[idx][0] || height > min_size[idx][1])) {
4006 uint32_t gt_mode;
4007
4008 anv_pack_struct(&gt_mode, GENX(GT_MODE),
4009 .SliceHashing = (devinfo->num_slices > 1 ? slice_hashing[idx] : 0),
4010 .SliceHashingMask = (devinfo->num_slices > 1 ? -1 : 0),
4011 .SubsliceHashing = subslice_hashing[idx],
4012 .SubsliceHashingMask = -1);
4013
4014 cmd_buffer->state.pending_pipe_bits |=
4015 ANV_PIPE_CS_STALL_BIT | ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
4016 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
4017
4018 emit_lri(&cmd_buffer->batch, GENX(GT_MODE_num), gt_mode);
4019
4020 cmd_buffer->state.current_hash_scale = scale;
4021 }
4022 #endif
4023 }
4024
4025 static void
4026 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
4027 {
4028 struct anv_device *device = cmd_buffer->device;
4029 const struct anv_image_view *iview =
4030 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
4031 const struct anv_image *image = iview ? iview->image : NULL;
4032
4033 /* FIXME: Width and Height are wrong */
4034
4035 genX(cmd_buffer_emit_gen7_depth_flush)(cmd_buffer);
4036
4037 uint32_t *dw = anv_batch_emit_dwords(&cmd_buffer->batch,
4038 device->isl_dev.ds.size / 4);
4039 if (dw == NULL)
4040 return;
4041
4042 struct isl_depth_stencil_hiz_emit_info info = { };
4043
4044 if (iview)
4045 info.view = &iview->planes[0].isl;
4046
4047 if (image && (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
4048 uint32_t depth_plane =
4049 anv_image_aspect_to_plane(image->aspects, VK_IMAGE_ASPECT_DEPTH_BIT);
4050 const struct anv_surface *surface = &image->planes[depth_plane].surface;
4051
4052 info.depth_surf = &surface->isl;
4053
4054 info.depth_address =
4055 anv_batch_emit_reloc(&cmd_buffer->batch,
4056 dw + device->isl_dev.ds.depth_offset / 4,
4057 image->planes[depth_plane].address.bo,
4058 image->planes[depth_plane].address.offset +
4059 surface->offset);
4060 info.mocs =
4061 anv_mocs_for_bo(device, image->planes[depth_plane].address.bo);
4062
4063 const uint32_t ds =
4064 cmd_buffer->state.subpass->depth_stencil_attachment->attachment;
4065 info.hiz_usage = cmd_buffer->state.attachments[ds].aux_usage;
4066 if (info.hiz_usage == ISL_AUX_USAGE_HIZ) {
4067 info.hiz_surf = &image->planes[depth_plane].aux_surface.isl;
4068
4069 info.hiz_address =
4070 anv_batch_emit_reloc(&cmd_buffer->batch,
4071 dw + device->isl_dev.ds.hiz_offset / 4,
4072 image->planes[depth_plane].address.bo,
4073 image->planes[depth_plane].address.offset +
4074 image->planes[depth_plane].aux_surface.offset);
4075
4076 info.depth_clear_value = ANV_HZ_FC_VAL;
4077 }
4078 }
4079
4080 if (image && (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT)) {
4081 uint32_t stencil_plane =
4082 anv_image_aspect_to_plane(image->aspects, VK_IMAGE_ASPECT_STENCIL_BIT);
4083 const struct anv_surface *surface = &image->planes[stencil_plane].surface;
4084
4085 info.stencil_surf = &surface->isl;
4086
4087 info.stencil_address =
4088 anv_batch_emit_reloc(&cmd_buffer->batch,
4089 dw + device->isl_dev.ds.stencil_offset / 4,
4090 image->planes[stencil_plane].address.bo,
4091 image->planes[stencil_plane].address.offset +
4092 surface->offset);
4093 info.mocs =
4094 anv_mocs_for_bo(device, image->planes[stencil_plane].address.bo);
4095 }
4096
4097 isl_emit_depth_stencil_hiz_s(&device->isl_dev, dw, &info);
4098
4099 if (GEN_GEN >= 12) {
4100 /* GEN:BUG:1408224581
4101 *
4102 * Workaround: Gen12LP Astep only An additional pipe control with
4103 * post-sync = store dword operation would be required.( w/a is to
4104 * have an additional pipe control after the stencil state whenever
4105 * the surface state bits of this state is changing).
4106 */
4107 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
4108 pc.PostSyncOperation = WriteImmediateData;
4109 pc.Address =
4110 (struct anv_address) { cmd_buffer->device->workaround_bo, 0 };
4111 }
4112 }
4113 cmd_buffer->state.hiz_enabled = info.hiz_usage == ISL_AUX_USAGE_HIZ;
4114 }
4115
4116 /**
4117 * This ANDs the view mask of the current subpass with the pending clear
4118 * views in the attachment to get the mask of views active in the subpass
4119 * that still need to be cleared.
4120 */
4121 static inline uint32_t
4122 get_multiview_subpass_clear_mask(const struct anv_cmd_state *cmd_state,
4123 const struct anv_attachment_state *att_state)
4124 {
4125 return cmd_state->subpass->view_mask & att_state->pending_clear_views;
4126 }
4127
4128 static inline bool
4129 do_first_layer_clear(const struct anv_cmd_state *cmd_state,
4130 const struct anv_attachment_state *att_state)
4131 {
4132 if (!cmd_state->subpass->view_mask)
4133 return true;
4134
4135 uint32_t pending_clear_mask =
4136 get_multiview_subpass_clear_mask(cmd_state, att_state);
4137
4138 return pending_clear_mask & 1;
4139 }
4140
4141 static inline bool
4142 current_subpass_is_last_for_attachment(const struct anv_cmd_state *cmd_state,
4143 uint32_t att_idx)
4144 {
4145 const uint32_t last_subpass_idx =
4146 cmd_state->pass->attachments[att_idx].last_subpass_idx;
4147 const struct anv_subpass *last_subpass =
4148 &cmd_state->pass->subpasses[last_subpass_idx];
4149 return last_subpass == cmd_state->subpass;
4150 }
4151
4152 static void
4153 cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
4154 uint32_t subpass_id)
4155 {
4156 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
4157 struct anv_subpass *subpass = &cmd_state->pass->subpasses[subpass_id];
4158 cmd_state->subpass = subpass;
4159
4160 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
4161
4162 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4163 * different views. If the client asks for instancing, we need to use the
4164 * Instance Data Step Rate to ensure that we repeat the client's
4165 * per-instance data once for each view. Since this bit is in
4166 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4167 * of each subpass.
4168 */
4169 if (GEN_GEN == 7)
4170 cmd_buffer->state.gfx.vb_dirty |= ~0;
4171
4172 /* It is possible to start a render pass with an old pipeline. Because the
4173 * render pass and subpass index are both baked into the pipeline, this is
4174 * highly unlikely. In order to do so, it requires that you have a render
4175 * pass with a single subpass and that you use that render pass twice
4176 * back-to-back and use the same pipeline at the start of the second render
4177 * pass as at the end of the first. In order to avoid unpredictable issues
4178 * with this edge case, we just dirty the pipeline at the start of every
4179 * subpass.
4180 */
4181 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
4182
4183 /* Accumulate any subpass flushes that need to happen before the subpass */
4184 cmd_buffer->state.pending_pipe_bits |=
4185 cmd_buffer->state.pass->subpass_flushes[subpass_id];
4186
4187 VkRect2D render_area = cmd_buffer->state.render_area;
4188 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
4189
4190 bool is_multiview = subpass->view_mask != 0;
4191
4192 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4193 const uint32_t a = subpass->attachments[i].attachment;
4194 if (a == VK_ATTACHMENT_UNUSED)
4195 continue;
4196
4197 assert(a < cmd_state->pass->attachment_count);
4198 struct anv_attachment_state *att_state = &cmd_state->attachments[a];
4199
4200 struct anv_image_view *iview = cmd_state->attachments[a].image_view;
4201 const struct anv_image *image = iview->image;
4202
4203 /* A resolve is necessary before use as an input attachment if the clear
4204 * color or auxiliary buffer usage isn't supported by the sampler.
4205 */
4206 const bool input_needs_resolve =
4207 (att_state->fast_clear && !att_state->clear_color_is_zero_one) ||
4208 att_state->input_aux_usage != att_state->aux_usage;
4209
4210 VkImageLayout target_layout, target_stencil_layout;
4211 if (iview->aspect_mask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV &&
4212 !input_needs_resolve) {
4213 /* Layout transitions before the final only help to enable sampling
4214 * as an input attachment. If the input attachment supports sampling
4215 * using the auxiliary surface, we can skip such transitions by
4216 * making the target layout one that is CCS-aware.
4217 */
4218 target_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
4219 } else {
4220 target_layout = subpass->attachments[i].layout;
4221 target_stencil_layout = subpass->attachments[i].stencil_layout;
4222 }
4223
4224 uint32_t base_layer, layer_count;
4225 if (image->type == VK_IMAGE_TYPE_3D) {
4226 base_layer = 0;
4227 layer_count = anv_minify(iview->image->extent.depth,
4228 iview->planes[0].isl.base_level);
4229 } else {
4230 base_layer = iview->planes[0].isl.base_array_layer;
4231 layer_count = fb->layers;
4232 }
4233
4234 if (image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
4235 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
4236 transition_color_buffer(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
4237 iview->planes[0].isl.base_level, 1,
4238 base_layer, layer_count,
4239 att_state->current_layout, target_layout);
4240 }
4241
4242 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
4243 transition_depth_buffer(cmd_buffer, image,
4244 att_state->current_layout, target_layout);
4245 att_state->aux_usage =
4246 anv_layout_to_aux_usage(&cmd_buffer->device->info, image,
4247 VK_IMAGE_ASPECT_DEPTH_BIT, target_layout);
4248 }
4249
4250 if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
4251 transition_stencil_buffer(cmd_buffer, image,
4252 iview->planes[0].isl.base_level, 1,
4253 base_layer, layer_count,
4254 att_state->current_stencil_layout,
4255 target_stencil_layout);
4256 }
4257 att_state->current_layout = target_layout;
4258 att_state->current_stencil_layout = target_stencil_layout;
4259
4260 if (att_state->pending_clear_aspects & VK_IMAGE_ASPECT_COLOR_BIT) {
4261 assert(att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
4262
4263 /* Multi-planar images are not supported as attachments */
4264 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
4265 assert(image->n_planes == 1);
4266
4267 uint32_t base_clear_layer = iview->planes[0].isl.base_array_layer;
4268 uint32_t clear_layer_count = fb->layers;
4269
4270 if (att_state->fast_clear &&
4271 do_first_layer_clear(cmd_state, att_state)) {
4272 /* We only support fast-clears on the first layer */
4273 assert(iview->planes[0].isl.base_level == 0);
4274 assert(iview->planes[0].isl.base_array_layer == 0);
4275
4276 union isl_color_value clear_color = {};
4277 anv_clear_color_from_att_state(&clear_color, att_state, iview);
4278 if (iview->image->samples == 1) {
4279 anv_image_ccs_op(cmd_buffer, image,
4280 iview->planes[0].isl.format,
4281 VK_IMAGE_ASPECT_COLOR_BIT,
4282 0, 0, 1, ISL_AUX_OP_FAST_CLEAR,
4283 &clear_color,
4284 false);
4285 } else {
4286 anv_image_mcs_op(cmd_buffer, image,
4287 iview->planes[0].isl.format,
4288 VK_IMAGE_ASPECT_COLOR_BIT,
4289 0, 1, ISL_AUX_OP_FAST_CLEAR,
4290 &clear_color,
4291 false);
4292 }
4293 base_clear_layer++;
4294 clear_layer_count--;
4295 if (is_multiview)
4296 att_state->pending_clear_views &= ~1;
4297
4298 if (att_state->clear_color_is_zero) {
4299 /* This image has the auxiliary buffer enabled. We can mark the
4300 * subresource as not needing a resolve because the clear color
4301 * will match what's in every RENDER_SURFACE_STATE object when
4302 * it's being used for sampling.
4303 */
4304 set_image_fast_clear_state(cmd_buffer, iview->image,
4305 VK_IMAGE_ASPECT_COLOR_BIT,
4306 ANV_FAST_CLEAR_DEFAULT_VALUE);
4307 } else {
4308 set_image_fast_clear_state(cmd_buffer, iview->image,
4309 VK_IMAGE_ASPECT_COLOR_BIT,
4310 ANV_FAST_CLEAR_ANY);
4311 }
4312 }
4313
4314 /* From the VkFramebufferCreateInfo spec:
4315 *
4316 * "If the render pass uses multiview, then layers must be one and each
4317 * attachment requires a number of layers that is greater than the
4318 * maximum bit index set in the view mask in the subpasses in which it
4319 * is used."
4320 *
4321 * So if multiview is active we ignore the number of layers in the
4322 * framebuffer and instead we honor the view mask from the subpass.
4323 */
4324 if (is_multiview) {
4325 assert(image->n_planes == 1);
4326 uint32_t pending_clear_mask =
4327 get_multiview_subpass_clear_mask(cmd_state, att_state);
4328
4329 uint32_t layer_idx;
4330 for_each_bit(layer_idx, pending_clear_mask) {
4331 uint32_t layer =
4332 iview->planes[0].isl.base_array_layer + layer_idx;
4333
4334 anv_image_clear_color(cmd_buffer, image,
4335 VK_IMAGE_ASPECT_COLOR_BIT,
4336 att_state->aux_usage,
4337 iview->planes[0].isl.format,
4338 iview->planes[0].isl.swizzle,
4339 iview->planes[0].isl.base_level,
4340 layer, 1,
4341 render_area,
4342 vk_to_isl_color(att_state->clear_value.color));
4343 }
4344
4345 att_state->pending_clear_views &= ~pending_clear_mask;
4346 } else if (clear_layer_count > 0) {
4347 assert(image->n_planes == 1);
4348 anv_image_clear_color(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
4349 att_state->aux_usage,
4350 iview->planes[0].isl.format,
4351 iview->planes[0].isl.swizzle,
4352 iview->planes[0].isl.base_level,
4353 base_clear_layer, clear_layer_count,
4354 render_area,
4355 vk_to_isl_color(att_state->clear_value.color));
4356 }
4357 } else if (att_state->pending_clear_aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
4358 VK_IMAGE_ASPECT_STENCIL_BIT)) {
4359 if (att_state->fast_clear && !is_multiview) {
4360 /* We currently only support HiZ for single-layer images */
4361 if (att_state->pending_clear_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
4362 assert(iview->image->planes[0].aux_usage == ISL_AUX_USAGE_HIZ);
4363 assert(iview->planes[0].isl.base_level == 0);
4364 assert(iview->planes[0].isl.base_array_layer == 0);
4365 assert(fb->layers == 1);
4366 }
4367
4368 anv_image_hiz_clear(cmd_buffer, image,
4369 att_state->pending_clear_aspects,
4370 iview->planes[0].isl.base_level,
4371 iview->planes[0].isl.base_array_layer,
4372 fb->layers, render_area,
4373 att_state->clear_value.depthStencil.stencil);
4374 } else if (is_multiview) {
4375 uint32_t pending_clear_mask =
4376 get_multiview_subpass_clear_mask(cmd_state, att_state);
4377
4378 uint32_t layer_idx;
4379 for_each_bit(layer_idx, pending_clear_mask) {
4380 uint32_t layer =
4381 iview->planes[0].isl.base_array_layer + layer_idx;
4382
4383 anv_image_clear_depth_stencil(cmd_buffer, image,
4384 att_state->pending_clear_aspects,
4385 att_state->aux_usage,
4386 iview->planes[0].isl.base_level,
4387 layer, 1,
4388 render_area,
4389 att_state->clear_value.depthStencil.depth,
4390 att_state->clear_value.depthStencil.stencil);
4391 }
4392
4393 att_state->pending_clear_views &= ~pending_clear_mask;
4394 } else {
4395 anv_image_clear_depth_stencil(cmd_buffer, image,
4396 att_state->pending_clear_aspects,
4397 att_state->aux_usage,
4398 iview->planes[0].isl.base_level,
4399 iview->planes[0].isl.base_array_layer,
4400 fb->layers, render_area,
4401 att_state->clear_value.depthStencil.depth,
4402 att_state->clear_value.depthStencil.stencil);
4403 }
4404 } else {
4405 assert(att_state->pending_clear_aspects == 0);
4406 }
4407
4408 if (GEN_GEN < 10 &&
4409 (att_state->pending_load_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) &&
4410 image->planes[0].aux_surface.isl.size_B > 0 &&
4411 iview->planes[0].isl.base_level == 0 &&
4412 iview->planes[0].isl.base_array_layer == 0) {
4413 if (att_state->aux_usage != ISL_AUX_USAGE_NONE) {
4414 genX(copy_fast_clear_dwords)(cmd_buffer, att_state->color.state,
4415 image, VK_IMAGE_ASPECT_COLOR_BIT,
4416 false /* copy to ss */);
4417 }
4418
4419 if (need_input_attachment_state(&cmd_state->pass->attachments[a]) &&
4420 att_state->input_aux_usage != ISL_AUX_USAGE_NONE) {
4421 genX(copy_fast_clear_dwords)(cmd_buffer, att_state->input.state,
4422 image, VK_IMAGE_ASPECT_COLOR_BIT,
4423 false /* copy to ss */);
4424 }
4425 }
4426
4427 if (subpass->attachments[i].usage ==
4428 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) {
4429 /* We assume that if we're starting a subpass, we're going to do some
4430 * rendering so we may end up with compressed data.
4431 */
4432 genX(cmd_buffer_mark_image_written)(cmd_buffer, iview->image,
4433 VK_IMAGE_ASPECT_COLOR_BIT,
4434 att_state->aux_usage,
4435 iview->planes[0].isl.base_level,
4436 iview->planes[0].isl.base_array_layer,
4437 fb->layers);
4438 } else if (subpass->attachments[i].usage ==
4439 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT) {
4440 /* We may be writing depth or stencil so we need to mark the surface.
4441 * Unfortunately, there's no way to know at this point whether the
4442 * depth or stencil tests used will actually write to the surface.
4443 *
4444 * Even though stencil may be plane 1, it always shares a base_level
4445 * with depth.
4446 */
4447 const struct isl_view *ds_view = &iview->planes[0].isl;
4448 if (iview->aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) {
4449 genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
4450 VK_IMAGE_ASPECT_DEPTH_BIT,
4451 att_state->aux_usage,
4452 ds_view->base_level,
4453 ds_view->base_array_layer,
4454 fb->layers);
4455 }
4456 if (iview->aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) {
4457 /* Even though stencil may be plane 1, it always shares a
4458 * base_level with depth.
4459 */
4460 genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
4461 VK_IMAGE_ASPECT_STENCIL_BIT,
4462 ISL_AUX_USAGE_NONE,
4463 ds_view->base_level,
4464 ds_view->base_array_layer,
4465 fb->layers);
4466 }
4467 }
4468
4469 /* If multiview is enabled, then we are only done clearing when we no
4470 * longer have pending layers to clear, or when we have processed the
4471 * last subpass that uses this attachment.
4472 */
4473 if (!is_multiview ||
4474 att_state->pending_clear_views == 0 ||
4475 current_subpass_is_last_for_attachment(cmd_state, a)) {
4476 att_state->pending_clear_aspects = 0;
4477 }
4478
4479 att_state->pending_load_aspects = 0;
4480 }
4481
4482 cmd_buffer_emit_depth_stencil(cmd_buffer);
4483
4484 #if GEN_GEN >= 11
4485 /* The PIPE_CONTROL command description says:
4486 *
4487 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
4488 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
4489 * Target Cache Flush by enabling this bit. When render target flush
4490 * is set due to new association of BTI, PS Scoreboard Stall bit must
4491 * be set in this packet."
4492 */
4493 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
4494 pc.RenderTargetCacheFlushEnable = true;
4495 pc.StallAtPixelScoreboard = true;
4496 #if GEN_GEN >= 12
4497 pc.TileCacheFlushEnable = true;
4498 #endif
4499 }
4500 #endif
4501 }
4502
4503 static enum blorp_filter
4504 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode)
4505 {
4506 switch (vk_mode) {
4507 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
4508 return BLORP_FILTER_SAMPLE_0;
4509 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
4510 return BLORP_FILTER_AVERAGE;
4511 case VK_RESOLVE_MODE_MIN_BIT_KHR:
4512 return BLORP_FILTER_MIN_SAMPLE;
4513 case VK_RESOLVE_MODE_MAX_BIT_KHR:
4514 return BLORP_FILTER_MAX_SAMPLE;
4515 default:
4516 return BLORP_FILTER_NONE;
4517 }
4518 }
4519
4520 static void
4521 cmd_buffer_end_subpass(struct anv_cmd_buffer *cmd_buffer)
4522 {
4523 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
4524 struct anv_subpass *subpass = cmd_state->subpass;
4525 uint32_t subpass_id = anv_get_subpass_id(&cmd_buffer->state);
4526 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
4527
4528 if (subpass->has_color_resolve) {
4529 /* We are about to do some MSAA resolves. We need to flush so that the
4530 * result of writes to the MSAA color attachments show up in the sampler
4531 * when we blit to the single-sampled resolve target.
4532 */
4533 cmd_buffer->state.pending_pipe_bits |=
4534 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
4535 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
4536
4537 for (uint32_t i = 0; i < subpass->color_count; ++i) {
4538 uint32_t src_att = subpass->color_attachments[i].attachment;
4539 uint32_t dst_att = subpass->resolve_attachments[i].attachment;
4540
4541 if (dst_att == VK_ATTACHMENT_UNUSED)
4542 continue;
4543
4544 assert(src_att < cmd_buffer->state.pass->attachment_count);
4545 assert(dst_att < cmd_buffer->state.pass->attachment_count);
4546
4547 if (cmd_buffer->state.attachments[dst_att].pending_clear_aspects) {
4548 /* From the Vulkan 1.0 spec:
4549 *
4550 * If the first use of an attachment in a render pass is as a
4551 * resolve attachment, then the loadOp is effectively ignored
4552 * as the resolve is guaranteed to overwrite all pixels in the
4553 * render area.
4554 */
4555 cmd_buffer->state.attachments[dst_att].pending_clear_aspects = 0;
4556 }
4557
4558 struct anv_image_view *src_iview = cmd_state->attachments[src_att].image_view;
4559 struct anv_image_view *dst_iview = cmd_state->attachments[dst_att].image_view;
4560
4561 const VkRect2D render_area = cmd_buffer->state.render_area;
4562
4563 enum isl_aux_usage src_aux_usage =
4564 cmd_buffer->state.attachments[src_att].aux_usage;
4565 enum isl_aux_usage dst_aux_usage =
4566 cmd_buffer->state.attachments[dst_att].aux_usage;
4567
4568 assert(src_iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT &&
4569 dst_iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT);
4570
4571 anv_image_msaa_resolve(cmd_buffer,
4572 src_iview->image, src_aux_usage,
4573 src_iview->planes[0].isl.base_level,
4574 src_iview->planes[0].isl.base_array_layer,
4575 dst_iview->image, dst_aux_usage,
4576 dst_iview->planes[0].isl.base_level,
4577 dst_iview->planes[0].isl.base_array_layer,
4578 VK_IMAGE_ASPECT_COLOR_BIT,
4579 render_area.offset.x, render_area.offset.y,
4580 render_area.offset.x, render_area.offset.y,
4581 render_area.extent.width,
4582 render_area.extent.height,
4583 fb->layers, BLORP_FILTER_NONE);
4584 }
4585 }
4586
4587 if (subpass->ds_resolve_attachment) {
4588 /* We are about to do some MSAA resolves. We need to flush so that the
4589 * result of writes to the MSAA depth attachments show up in the sampler
4590 * when we blit to the single-sampled resolve target.
4591 */
4592 cmd_buffer->state.pending_pipe_bits |=
4593 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
4594 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
4595
4596 uint32_t src_att = subpass->depth_stencil_attachment->attachment;
4597 uint32_t dst_att = subpass->ds_resolve_attachment->attachment;
4598
4599 assert(src_att < cmd_buffer->state.pass->attachment_count);
4600 assert(dst_att < cmd_buffer->state.pass->attachment_count);
4601
4602 if (cmd_buffer->state.attachments[dst_att].pending_clear_aspects) {
4603 /* From the Vulkan 1.0 spec:
4604 *
4605 * If the first use of an attachment in a render pass is as a
4606 * resolve attachment, then the loadOp is effectively ignored
4607 * as the resolve is guaranteed to overwrite all pixels in the
4608 * render area.
4609 */
4610 cmd_buffer->state.attachments[dst_att].pending_clear_aspects = 0;
4611 }
4612
4613 struct anv_image_view *src_iview = cmd_state->attachments[src_att].image_view;
4614 struct anv_image_view *dst_iview = cmd_state->attachments[dst_att].image_view;
4615
4616 const VkRect2D render_area = cmd_buffer->state.render_area;
4617
4618 struct anv_attachment_state *src_state =
4619 &cmd_state->attachments[src_att];
4620 struct anv_attachment_state *dst_state =
4621 &cmd_state->attachments[dst_att];
4622
4623 if ((src_iview->image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
4624 subpass->depth_resolve_mode != VK_RESOLVE_MODE_NONE_KHR) {
4625
4626 /* MSAA resolves sample from the source attachment. Transition the
4627 * depth attachment first to get rid of any HiZ that we may not be
4628 * able to handle.
4629 */
4630 transition_depth_buffer(cmd_buffer, src_iview->image,
4631 src_state->current_layout,
4632 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL);
4633 src_state->aux_usage =
4634 anv_layout_to_aux_usage(&cmd_buffer->device->info, src_iview->image,
4635 VK_IMAGE_ASPECT_DEPTH_BIT,
4636 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL);
4637 src_state->current_layout = VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL;
4638
4639 /* MSAA resolves write to the resolve attachment as if it were any
4640 * other transfer op. Transition the resolve attachment accordingly.
4641 */
4642 VkImageLayout dst_initial_layout = dst_state->current_layout;
4643
4644 /* If our render area is the entire size of the image, we're going to
4645 * blow it all away so we can claim the initial layout is UNDEFINED
4646 * and we'll get a HiZ ambiguate instead of a resolve.
4647 */
4648 if (dst_iview->image->type != VK_IMAGE_TYPE_3D &&
4649 render_area.offset.x == 0 && render_area.offset.y == 0 &&
4650 render_area.extent.width == dst_iview->extent.width &&
4651 render_area.extent.height == dst_iview->extent.height)
4652 dst_initial_layout = VK_IMAGE_LAYOUT_UNDEFINED;
4653
4654 transition_depth_buffer(cmd_buffer, dst_iview->image,
4655 dst_initial_layout,
4656 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
4657 dst_state->aux_usage =
4658 anv_layout_to_aux_usage(&cmd_buffer->device->info, dst_iview->image,
4659 VK_IMAGE_ASPECT_DEPTH_BIT,
4660 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
4661 dst_state->current_layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL;
4662
4663 enum blorp_filter filter =
4664 vk_to_blorp_resolve_mode(subpass->depth_resolve_mode);
4665
4666 anv_image_msaa_resolve(cmd_buffer,
4667 src_iview->image, src_state->aux_usage,
4668 src_iview->planes[0].isl.base_level,
4669 src_iview->planes[0].isl.base_array_layer,
4670 dst_iview->image, dst_state->aux_usage,
4671 dst_iview->planes[0].isl.base_level,
4672 dst_iview->planes[0].isl.base_array_layer,
4673 VK_IMAGE_ASPECT_DEPTH_BIT,
4674 render_area.offset.x, render_area.offset.y,
4675 render_area.offset.x, render_area.offset.y,
4676 render_area.extent.width,
4677 render_area.extent.height,
4678 fb->layers, filter);
4679 }
4680
4681 if ((src_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
4682 subpass->stencil_resolve_mode != VK_RESOLVE_MODE_NONE_KHR) {
4683
4684 src_state->current_stencil_layout = VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL;
4685 dst_state->current_stencil_layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL;
4686
4687 enum isl_aux_usage src_aux_usage = ISL_AUX_USAGE_NONE;
4688 enum isl_aux_usage dst_aux_usage = ISL_AUX_USAGE_NONE;
4689
4690 enum blorp_filter filter =
4691 vk_to_blorp_resolve_mode(subpass->stencil_resolve_mode);
4692
4693 anv_image_msaa_resolve(cmd_buffer,
4694 src_iview->image, src_aux_usage,
4695 src_iview->planes[0].isl.base_level,
4696 src_iview->planes[0].isl.base_array_layer,
4697 dst_iview->image, dst_aux_usage,
4698 dst_iview->planes[0].isl.base_level,
4699 dst_iview->planes[0].isl.base_array_layer,
4700 VK_IMAGE_ASPECT_STENCIL_BIT,
4701 render_area.offset.x, render_area.offset.y,
4702 render_area.offset.x, render_area.offset.y,
4703 render_area.extent.width,
4704 render_area.extent.height,
4705 fb->layers, filter);
4706 }
4707 }
4708
4709 #if GEN_GEN == 7
4710 /* On gen7, we have to store a texturable version of the stencil buffer in
4711 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
4712 * forth at strategic points. Stencil writes are only allowed in following
4713 * layouts:
4714 *
4715 * - VK_IMAGE_LAYOUT_GENERAL
4716 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
4717 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
4718 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
4719 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
4720 *
4721 * For general, we have no nice opportunity to transition so we do the copy
4722 * to the shadow unconditionally at the end of the subpass. For transfer
4723 * destinations, we can update it as part of the transfer op. For the other
4724 * layouts, we delay the copy until a transition into some other layout.
4725 */
4726 if (subpass->depth_stencil_attachment) {
4727 uint32_t a = subpass->depth_stencil_attachment->attachment;
4728 assert(a != VK_ATTACHMENT_UNUSED);
4729
4730 struct anv_attachment_state *att_state = &cmd_state->attachments[a];
4731 struct anv_image_view *iview = cmd_state->attachments[a].image_view;;
4732 const struct anv_image *image = iview->image;
4733
4734 if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
4735 uint32_t plane = anv_image_aspect_to_plane(image->aspects,
4736 VK_IMAGE_ASPECT_STENCIL_BIT);
4737
4738 if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
4739 att_state->current_stencil_layout == VK_IMAGE_LAYOUT_GENERAL) {
4740 assert(image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
4741 anv_image_copy_to_shadow(cmd_buffer, image,
4742 VK_IMAGE_ASPECT_STENCIL_BIT,
4743 iview->planes[plane].isl.base_level, 1,
4744 iview->planes[plane].isl.base_array_layer,
4745 fb->layers);
4746 }
4747 }
4748 }
4749 #endif /* GEN_GEN == 7 */
4750
4751 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4752 const uint32_t a = subpass->attachments[i].attachment;
4753 if (a == VK_ATTACHMENT_UNUSED)
4754 continue;
4755
4756 if (cmd_state->pass->attachments[a].last_subpass_idx != subpass_id)
4757 continue;
4758
4759 assert(a < cmd_state->pass->attachment_count);
4760 struct anv_attachment_state *att_state = &cmd_state->attachments[a];
4761 struct anv_image_view *iview = cmd_state->attachments[a].image_view;
4762 const struct anv_image *image = iview->image;
4763
4764 if ((image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) &&
4765 image->vk_format != iview->vk_format) {
4766 enum anv_fast_clear_type fast_clear_type =
4767 anv_layout_to_fast_clear_type(&cmd_buffer->device->info,
4768 image, VK_IMAGE_ASPECT_COLOR_BIT,
4769 att_state->current_layout);
4770
4771 /* If any clear color was used, flush it down the aux surfaces. If we
4772 * don't do it now using the view's format we might use the clear
4773 * color incorrectly in the following resolves (for example with an
4774 * SRGB view & a UNORM image).
4775 */
4776 if (fast_clear_type != ANV_FAST_CLEAR_NONE) {
4777 anv_perf_warn(cmd_buffer->device->instance, iview,
4778 "Doing a partial resolve to get rid of clear color at the "
4779 "end of a renderpass due to an image/view format mismatch");
4780
4781 uint32_t base_layer, layer_count;
4782 if (image->type == VK_IMAGE_TYPE_3D) {
4783 base_layer = 0;
4784 layer_count = anv_minify(iview->image->extent.depth,
4785 iview->planes[0].isl.base_level);
4786 } else {
4787 base_layer = iview->planes[0].isl.base_array_layer;
4788 layer_count = fb->layers;
4789 }
4790
4791 for (uint32_t a = 0; a < layer_count; a++) {
4792 uint32_t array_layer = base_layer + a;
4793 if (image->samples == 1) {
4794 anv_cmd_predicated_ccs_resolve(cmd_buffer, image,
4795 iview->planes[0].isl.format,
4796 VK_IMAGE_ASPECT_COLOR_BIT,
4797 iview->planes[0].isl.base_level,
4798 array_layer,
4799 ISL_AUX_OP_PARTIAL_RESOLVE,
4800 ANV_FAST_CLEAR_NONE);
4801 } else {
4802 anv_cmd_predicated_mcs_resolve(cmd_buffer, image,
4803 iview->planes[0].isl.format,
4804 VK_IMAGE_ASPECT_COLOR_BIT,
4805 base_layer,
4806 ISL_AUX_OP_PARTIAL_RESOLVE,
4807 ANV_FAST_CLEAR_NONE);
4808 }
4809 }
4810 }
4811 }
4812
4813 /* Transition the image into the final layout for this render pass */
4814 VkImageLayout target_layout =
4815 cmd_state->pass->attachments[a].final_layout;
4816 VkImageLayout target_stencil_layout =
4817 cmd_state->pass->attachments[a].stencil_final_layout;
4818
4819 uint32_t base_layer, layer_count;
4820 if (image->type == VK_IMAGE_TYPE_3D) {
4821 base_layer = 0;
4822 layer_count = anv_minify(iview->image->extent.depth,
4823 iview->planes[0].isl.base_level);
4824 } else {
4825 base_layer = iview->planes[0].isl.base_array_layer;
4826 layer_count = fb->layers;
4827 }
4828
4829 if (image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
4830 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
4831 transition_color_buffer(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
4832 iview->planes[0].isl.base_level, 1,
4833 base_layer, layer_count,
4834 att_state->current_layout, target_layout);
4835 }
4836
4837 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
4838 transition_depth_buffer(cmd_buffer, image,
4839 att_state->current_layout, target_layout);
4840 }
4841
4842 if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
4843 transition_stencil_buffer(cmd_buffer, image,
4844 iview->planes[0].isl.base_level, 1,
4845 base_layer, layer_count,
4846 att_state->current_stencil_layout,
4847 target_stencil_layout);
4848 }
4849 }
4850
4851 /* Accumulate any subpass flushes that need to happen after the subpass.
4852 * Yes, they do get accumulated twice in the NextSubpass case but since
4853 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4854 * ORing the bits in twice so it's harmless.
4855 */
4856 cmd_buffer->state.pending_pipe_bits |=
4857 cmd_buffer->state.pass->subpass_flushes[subpass_id + 1];
4858 }
4859
4860 void genX(CmdBeginRenderPass)(
4861 VkCommandBuffer commandBuffer,
4862 const VkRenderPassBeginInfo* pRenderPassBegin,
4863 VkSubpassContents contents)
4864 {
4865 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
4866 ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
4867 ANV_FROM_HANDLE(anv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4868
4869 cmd_buffer->state.framebuffer = framebuffer;
4870 cmd_buffer->state.pass = pass;
4871 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4872 VkResult result =
4873 genX(cmd_buffer_setup_attachments)(cmd_buffer, pass, pRenderPassBegin);
4874
4875 /* If we failed to setup the attachments we should not try to go further */
4876 if (result != VK_SUCCESS) {
4877 assert(anv_batch_has_error(&cmd_buffer->batch));
4878 return;
4879 }
4880
4881 genX(flush_pipeline_select_3d)(cmd_buffer);
4882
4883 cmd_buffer_begin_subpass(cmd_buffer, 0);
4884 }
4885
4886 void genX(CmdBeginRenderPass2KHR)(
4887 VkCommandBuffer commandBuffer,
4888 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4889 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4890 {
4891 genX(CmdBeginRenderPass)(commandBuffer, pRenderPassBeginInfo,
4892 pSubpassBeginInfo->contents);
4893 }
4894
4895 void genX(CmdNextSubpass)(
4896 VkCommandBuffer commandBuffer,
4897 VkSubpassContents contents)
4898 {
4899 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
4900
4901 if (anv_batch_has_error(&cmd_buffer->batch))
4902 return;
4903
4904 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4905
4906 uint32_t prev_subpass = anv_get_subpass_id(&cmd_buffer->state);
4907 cmd_buffer_end_subpass(cmd_buffer);
4908 cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4909 }
4910
4911 void genX(CmdNextSubpass2KHR)(
4912 VkCommandBuffer commandBuffer,
4913 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4914 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4915 {
4916 genX(CmdNextSubpass)(commandBuffer, pSubpassBeginInfo->contents);
4917 }
4918
4919 void genX(CmdEndRenderPass)(
4920 VkCommandBuffer commandBuffer)
4921 {
4922 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
4923
4924 if (anv_batch_has_error(&cmd_buffer->batch))
4925 return;
4926
4927 cmd_buffer_end_subpass(cmd_buffer);
4928
4929 cmd_buffer->state.hiz_enabled = false;
4930
4931 #ifndef NDEBUG
4932 anv_dump_add_attachments(cmd_buffer);
4933 #endif
4934
4935 /* Remove references to render pass specific state. This enables us to
4936 * detect whether or not we're in a renderpass.
4937 */
4938 cmd_buffer->state.framebuffer = NULL;
4939 cmd_buffer->state.pass = NULL;
4940 cmd_buffer->state.subpass = NULL;
4941 }
4942
4943 void genX(CmdEndRenderPass2KHR)(
4944 VkCommandBuffer commandBuffer,
4945 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4946 {
4947 genX(CmdEndRenderPass)(commandBuffer);
4948 }
4949
4950 void
4951 genX(cmd_emit_conditional_render_predicate)(struct anv_cmd_buffer *cmd_buffer)
4952 {
4953 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4954 struct gen_mi_builder b;
4955 gen_mi_builder_init(&b, &cmd_buffer->batch);
4956
4957 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
4958 gen_mi_reg32(ANV_PREDICATE_RESULT_REG));
4959 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
4960
4961 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
4962 mip.LoadOperation = LOAD_LOADINV;
4963 mip.CombineOperation = COMBINE_SET;
4964 mip.CompareOperation = COMPARE_SRCS_EQUAL;
4965 }
4966 #endif
4967 }
4968
4969 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4970 void genX(CmdBeginConditionalRenderingEXT)(
4971 VkCommandBuffer commandBuffer,
4972 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4973 {
4974 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
4975 ANV_FROM_HANDLE(anv_buffer, buffer, pConditionalRenderingBegin->buffer);
4976 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
4977 struct anv_address value_address =
4978 anv_address_add(buffer->address, pConditionalRenderingBegin->offset);
4979
4980 const bool isInverted = pConditionalRenderingBegin->flags &
4981 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT;
4982
4983 cmd_state->conditional_render_enabled = true;
4984
4985 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
4986
4987 struct gen_mi_builder b;
4988 gen_mi_builder_init(&b, &cmd_buffer->batch);
4989
4990 /* Section 19.4 of the Vulkan 1.1.85 spec says:
4991 *
4992 * If the value of the predicate in buffer memory changes
4993 * while conditional rendering is active, the rendering commands
4994 * may be discarded in an implementation-dependent way.
4995 * Some implementations may latch the value of the predicate
4996 * upon beginning conditional rendering while others
4997 * may read it before every rendering command.
4998 *
4999 * So it's perfectly fine to read a value from the buffer once.
5000 */
5001 struct gen_mi_value value = gen_mi_mem32(value_address);
5002
5003 /* Precompute predicate result, it is necessary to support secondary
5004 * command buffers since it is unknown if conditional rendering is
5005 * inverted when populating them.
5006 */
5007 gen_mi_store(&b, gen_mi_reg64(ANV_PREDICATE_RESULT_REG),
5008 isInverted ? gen_mi_uge(&b, gen_mi_imm(0), value) :
5009 gen_mi_ult(&b, gen_mi_imm(0), value));
5010 }
5011
5012 void genX(CmdEndConditionalRenderingEXT)(
5013 VkCommandBuffer commandBuffer)
5014 {
5015 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
5016 struct anv_cmd_state *cmd_state = &cmd_buffer->state;
5017
5018 cmd_state->conditional_render_enabled = false;
5019 }
5020 #endif
5021
5022 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5023 * command streamer for later execution.
5024 */
5025 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5026 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5027 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5028 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5029 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5030 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5031 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5032 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5033 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5034 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5035 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5036 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5037 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5038 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5039 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5040
5041 void genX(CmdSetEvent)(
5042 VkCommandBuffer commandBuffer,
5043 VkEvent _event,
5044 VkPipelineStageFlags stageMask)
5045 {
5046 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
5047 ANV_FROM_HANDLE(anv_event, event, _event);
5048
5049 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
5050 if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
5051 pc.StallAtPixelScoreboard = true;
5052 pc.CommandStreamerStallEnable = true;
5053 }
5054
5055 pc.DestinationAddressType = DAT_PPGTT,
5056 pc.PostSyncOperation = WriteImmediateData,
5057 pc.Address = (struct anv_address) {
5058 cmd_buffer->device->dynamic_state_pool.block_pool.bo,
5059 event->state.offset
5060 };
5061 pc.ImmediateData = VK_EVENT_SET;
5062 }
5063 }
5064
5065 void genX(CmdResetEvent)(
5066 VkCommandBuffer commandBuffer,
5067 VkEvent _event,
5068 VkPipelineStageFlags stageMask)
5069 {
5070 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
5071 ANV_FROM_HANDLE(anv_event, event, _event);
5072
5073 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
5074 if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
5075 pc.StallAtPixelScoreboard = true;
5076 pc.CommandStreamerStallEnable = true;
5077 }
5078
5079 pc.DestinationAddressType = DAT_PPGTT;
5080 pc.PostSyncOperation = WriteImmediateData;
5081 pc.Address = (struct anv_address) {
5082 cmd_buffer->device->dynamic_state_pool.block_pool.bo,
5083 event->state.offset
5084 };
5085 pc.ImmediateData = VK_EVENT_RESET;
5086 }
5087 }
5088
5089 void genX(CmdWaitEvents)(
5090 VkCommandBuffer commandBuffer,
5091 uint32_t eventCount,
5092 const VkEvent* pEvents,
5093 VkPipelineStageFlags srcStageMask,
5094 VkPipelineStageFlags destStageMask,
5095 uint32_t memoryBarrierCount,
5096 const VkMemoryBarrier* pMemoryBarriers,
5097 uint32_t bufferMemoryBarrierCount,
5098 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5099 uint32_t imageMemoryBarrierCount,
5100 const VkImageMemoryBarrier* pImageMemoryBarriers)
5101 {
5102 #if GEN_GEN >= 8
5103 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
5104
5105 for (uint32_t i = 0; i < eventCount; i++) {
5106 ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
5107
5108 anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT), sem) {
5109 sem.WaitMode = PollingMode,
5110 sem.CompareOperation = COMPARE_SAD_EQUAL_SDD,
5111 sem.SemaphoreDataDword = VK_EVENT_SET,
5112 sem.SemaphoreAddress = (struct anv_address) {
5113 cmd_buffer->device->dynamic_state_pool.block_pool.bo,
5114 event->state.offset
5115 };
5116 }
5117 }
5118 #else
5119 anv_finishme("Implement events on gen7");
5120 #endif
5121
5122 genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
5123 false, /* byRegion */
5124 memoryBarrierCount, pMemoryBarriers,
5125 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5126 imageMemoryBarrierCount, pImageMemoryBarriers);
5127 }
5128
5129 VkResult genX(CmdSetPerformanceOverrideINTEL)(
5130 VkCommandBuffer commandBuffer,
5131 const VkPerformanceOverrideInfoINTEL* pOverrideInfo)
5132 {
5133 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
5134
5135 switch (pOverrideInfo->type) {
5136 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL: {
5137 uint32_t dw;
5138
5139 #if GEN_GEN >= 9
5140 anv_pack_struct(&dw, GENX(CS_DEBUG_MODE2),
5141 ._3DRenderingInstructionDisable = pOverrideInfo->enable,
5142 .MediaInstructionDisable = pOverrideInfo->enable,
5143 ._3DRenderingInstructionDisableMask = true,
5144 .MediaInstructionDisableMask = true);
5145 emit_lri(&cmd_buffer->batch, GENX(CS_DEBUG_MODE2_num), dw);
5146 #else
5147 anv_pack_struct(&dw, GENX(INSTPM),
5148 ._3DRenderingInstructionDisable = pOverrideInfo->enable,
5149 .MediaInstructionDisable = pOverrideInfo->enable,
5150 ._3DRenderingInstructionDisableMask = true,
5151 .MediaInstructionDisableMask = true);
5152 emit_lri(&cmd_buffer->batch, GENX(INSTPM_num), dw);
5153 #endif
5154 break;
5155 }
5156
5157 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL:
5158 if (pOverrideInfo->enable) {
5159 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
5160 cmd_buffer->state.pending_pipe_bits |=
5161 ANV_PIPE_FLUSH_BITS |
5162 ANV_PIPE_INVALIDATE_BITS;
5163 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
5164 }
5165 break;
5166
5167 default:
5168 unreachable("Invalid override");
5169 }
5170
5171 return VK_SUCCESS;
5172 }
5173
5174 VkResult genX(CmdSetPerformanceStreamMarkerINTEL)(
5175 VkCommandBuffer commandBuffer,
5176 const VkPerformanceStreamMarkerInfoINTEL* pMarkerInfo)
5177 {
5178 /* TODO: Waiting on the register to write, might depend on generation. */
5179
5180 return VK_SUCCESS;
5181 }