2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
29 #include "common/gen_l3_config.h"
30 #include "genxml/gen_macros.h"
31 #include "genxml/genX_pack.h"
34 emit_lrm(struct anv_batch
*batch
,
35 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
37 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
38 lrm
.RegisterAddress
= reg
;
39 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
44 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
46 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
47 lri
.RegisterOffset
= reg
;
53 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
55 struct anv_device
*device
= cmd_buffer
->device
;
57 /* XXX: Do we need this on more than just BDW? */
59 /* Emit a render target cache flush.
61 * This isn't documented anywhere in the PRM. However, it seems to be
62 * necessary prior to changing the surface state base adress. Without
63 * this, we get GPU hangs when using multi-level command buffers which
64 * clear depth, reset state base address, and then go render stuff.
66 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
67 pc
.RenderTargetCacheFlushEnable
= true;
71 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
72 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
73 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
74 sba
.GeneralStateBaseAddressModifyEnable
= true;
76 sba
.SurfaceStateBaseAddress
=
77 anv_cmd_buffer_surface_base_address(cmd_buffer
);
78 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
79 sba
.SurfaceStateBaseAddressModifyEnable
= true;
81 sba
.DynamicStateBaseAddress
=
82 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
83 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
84 sba
.DynamicStateBaseAddressModifyEnable
= true;
86 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
87 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
88 sba
.IndirectObjectBaseAddressModifyEnable
= true;
90 sba
.InstructionBaseAddress
=
91 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
92 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
93 sba
.InstructionBaseAddressModifyEnable
= true;
96 /* Broadwell requires that we specify a buffer size for a bunch of
97 * these fields. However, since we will be growing the BO's live, we
98 * just set them all to the maximum.
100 sba
.GeneralStateBufferSize
= 0xfffff;
101 sba
.GeneralStateBufferSizeModifyEnable
= true;
102 sba
.DynamicStateBufferSize
= 0xfffff;
103 sba
.DynamicStateBufferSizeModifyEnable
= true;
104 sba
.IndirectObjectBufferSize
= 0xfffff;
105 sba
.IndirectObjectBufferSizeModifyEnable
= true;
106 sba
.InstructionBufferSize
= 0xfffff;
107 sba
.InstructionBuffersizeModifyEnable
= true;
111 /* After re-setting the surface state base address, we have to do some
112 * cache flusing so that the sampler engine will pick up the new
113 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
114 * Shared Function > 3D Sampler > State > State Caching (page 96):
116 * Coherency with system memory in the state cache, like the texture
117 * cache is handled partially by software. It is expected that the
118 * command stream or shader will issue Cache Flush operation or
119 * Cache_Flush sampler message to ensure that the L1 cache remains
120 * coherent with system memory.
124 * Whenever the value of the Dynamic_State_Base_Addr,
125 * Surface_State_Base_Addr are altered, the L1 state cache must be
126 * invalidated to ensure the new surface or sampler state is fetched
127 * from system memory.
129 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
130 * which, according the PIPE_CONTROL instruction documentation in the
133 * Setting this bit is independent of any other bit in this packet.
134 * This bit controls the invalidation of the L1 and L2 state caches
135 * at the top of the pipe i.e. at the parsing time.
137 * Unfortunately, experimentation seems to indicate that state cache
138 * invalidation through a PIPE_CONTROL does nothing whatsoever in
139 * regards to surface state and binding tables. In stead, it seems that
140 * invalidating the texture cache is what is actually needed.
142 * XXX: As far as we have been able to determine through
143 * experimentation, shows that flush the texture cache appears to be
144 * sufficient. The theory here is that all of the sampling/rendering
145 * units cache the binding table in the texture cache. However, we have
146 * yet to be able to actually confirm this.
148 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
149 pc
.TextureCacheInvalidationEnable
= true;
154 genX(BeginCommandBuffer
)(
155 VkCommandBuffer commandBuffer
,
156 const VkCommandBufferBeginInfo
* pBeginInfo
)
158 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
160 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
161 * command buffer's state. Otherwise, we must *reset* its state. In both
164 * From the Vulkan 1.0 spec:
166 * If a command buffer is in the executable state and the command buffer
167 * was allocated from a command pool with the
168 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
169 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
170 * as if vkResetCommandBuffer had been called with
171 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
172 * the command buffer in the recording state.
174 anv_cmd_buffer_reset(cmd_buffer
);
176 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
178 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
179 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
181 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
183 if (cmd_buffer
->usage_flags
&
184 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
185 cmd_buffer
->state
.framebuffer
=
186 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
187 cmd_buffer
->state
.pass
=
188 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
189 cmd_buffer
->state
.subpass
=
190 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
192 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
199 genX(EndCommandBuffer
)(
200 VkCommandBuffer commandBuffer
)
202 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
204 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
210 genX(CmdExecuteCommands
)(
211 VkCommandBuffer commandBuffer
,
212 uint32_t commandBufferCount
,
213 const VkCommandBuffer
* pCmdBuffers
)
215 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
217 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
219 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
220 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
222 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
224 anv_cmd_buffer_add_secondary(primary
, secondary
);
227 /* Each of the secondary command buffers will use its own state base
228 * address. We need to re-emit state base address for the primary after
229 * all of the secondaries are done.
231 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
234 genX(cmd_buffer_emit_state_base_address
)(primary
);
237 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
238 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
239 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
242 * Program the hardware to use the specified L3 configuration.
245 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
246 const struct gen_l3_config
*cfg
)
249 if (cfg
== cmd_buffer
->state
.current_l3_config
)
252 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
253 fprintf(stderr
, "L3 config transition: ");
254 gen_dump_l3_config(cfg
, stderr
);
257 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
259 /* According to the hardware docs, the L3 partitioning can only be changed
260 * while the pipeline is completely drained and the caches are flushed,
261 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
263 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
264 pc
.DCFlushEnable
= true;
265 pc
.PostSyncOperation
= NoWrite
;
266 pc
.CommandStreamerStallEnable
= true;
269 /* ...followed by a second pipelined PIPE_CONTROL that initiates
270 * invalidation of the relevant caches. Note that because RO invalidation
271 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
272 * command is processed by the CS) we cannot combine it with the previous
273 * stalling flush as the hardware documentation suggests, because that
274 * would cause the CS to stall on previous rendering *after* RO
275 * invalidation and wouldn't prevent the RO caches from being polluted by
276 * concurrent rendering before the stall completes. This intentionally
277 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
278 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
279 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
280 * already guarantee that there is no concurrent GPGPU kernel execution
281 * (see SKL HSD 2132585).
283 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
284 pc
.TextureCacheInvalidationEnable
= true;
285 pc
.ConstantCacheInvalidationEnable
= true;
286 pc
.InstructionCacheInvalidateEnable
= true;
287 pc
.StateCacheInvalidationEnable
= true;
288 pc
.PostSyncOperation
= NoWrite
;
291 /* Now send a third stalling flush to make sure that invalidation is
292 * complete when the L3 configuration registers are modified.
294 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
295 pc
.DCFlushEnable
= true;
296 pc
.PostSyncOperation
= NoWrite
;
297 pc
.CommandStreamerStallEnable
= true;
302 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
305 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
306 .SLMEnable
= has_slm
,
307 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
308 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
309 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
310 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
312 /* Set up the L3 partitioning. */
313 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
317 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
318 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
320 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
322 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
325 assert(!cfg
->n
[GEN_L3P_ALL
]);
327 /* When enabled SLM only uses a portion of the L3 on half of the banks,
328 * the matching space on the remaining banks has to be allocated to a
329 * client (URB for all validated configurations) set to the
330 * lower-bandwidth 2-bank address hashing mode.
332 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
333 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
334 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
336 /* Minimum number of ways that can be allocated to the URB. */
337 const unsigned n0_urb
= (devinfo
->is_baytrail
? 32 : 0);
338 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
340 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
341 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
342 .ConvertDC_UC
= !has_dc
,
343 .ConvertIS_UC
= !has_is
,
344 .ConvertC_UC
= !has_c
,
345 .ConvertT_UC
= !has_t
);
347 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
348 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
349 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
351 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
352 .SLMEnable
= has_slm
,
353 .URBLowBandwidth
= urb_low_bw
,
354 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
356 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
358 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
359 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
361 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
362 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
364 .CAllocation
= cfg
->n
[GEN_L3P_C
],
366 .TAllocation
= cfg
->n
[GEN_L3P_T
],
369 /* Set up the L3 partitioning. */
370 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
371 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
372 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
375 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
376 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
377 * them disabled to avoid crashing the system hard.
379 uint32_t scratch1
, chicken3
;
380 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
381 .L3AtomicDisable
= !has_dc
);
382 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
383 .L3AtomicDisableMask
= true,
384 .L3AtomicDisable
= !has_dc
);
385 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
386 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
392 cmd_buffer
->state
.current_l3_config
= cfg
;
396 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
398 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
400 /* Flushes are pipelined while invalidations are handled immediately.
401 * Therefore, if we're flushing anything then we need to schedule a stall
402 * before any invalidations can happen.
404 if (bits
& ANV_PIPE_FLUSH_BITS
)
405 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
407 /* If we're going to do an invalidate and we have a pending CS stall that
408 * has yet to be resolved, we do the CS stall now.
410 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
411 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
412 bits
|= ANV_PIPE_CS_STALL_BIT
;
413 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
416 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
417 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
418 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
419 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
420 pipe
.RenderTargetCacheFlushEnable
=
421 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
423 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
424 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
425 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
428 * According to the Broadwell documentation, any PIPE_CONTROL with the
429 * "Command Streamer Stall" bit set must also have another bit set,
430 * with five different options:
432 * - Render Target Cache Flush
433 * - Depth Cache Flush
434 * - Stall at Pixel Scoreboard
435 * - Post-Sync Operation
439 * I chose "Stall at Pixel Scoreboard" since that's what we use in
440 * mesa and it seems to work fine. The choice is fairly arbitrary.
442 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
443 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
444 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
445 pipe
.StallAtPixelScoreboard
= true;
448 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
451 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
452 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
453 pipe
.StateCacheInvalidationEnable
=
454 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
455 pipe
.ConstantCacheInvalidationEnable
=
456 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
457 pipe
.VFCacheInvalidationEnable
=
458 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
459 pipe
.TextureCacheInvalidationEnable
=
460 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
461 pipe
.InstructionCacheInvalidateEnable
=
462 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
465 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
468 cmd_buffer
->state
.pending_pipe_bits
= bits
;
471 void genX(CmdPipelineBarrier
)(
472 VkCommandBuffer commandBuffer
,
473 VkPipelineStageFlags srcStageMask
,
474 VkPipelineStageFlags destStageMask
,
476 uint32_t memoryBarrierCount
,
477 const VkMemoryBarrier
* pMemoryBarriers
,
478 uint32_t bufferMemoryBarrierCount
,
479 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
480 uint32_t imageMemoryBarrierCount
,
481 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
483 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
486 /* XXX: Right now, we're really dumb and just flush whatever categories
487 * the app asks for. One of these days we may make this a bit better
488 * but right now that's all the hardware allows for in most areas.
490 VkAccessFlags src_flags
= 0;
491 VkAccessFlags dst_flags
= 0;
493 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
494 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
495 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
498 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
499 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
500 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
503 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
504 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
505 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
508 enum anv_pipe_bits pipe_bits
= 0;
510 for_each_bit(b
, src_flags
) {
511 switch ((VkAccessFlagBits
)(1 << b
)) {
512 case VK_ACCESS_SHADER_WRITE_BIT
:
513 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
515 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
516 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
518 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
519 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
521 case VK_ACCESS_TRANSFER_WRITE_BIT
:
522 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
523 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
526 break; /* Nothing to do */
530 for_each_bit(b
, dst_flags
) {
531 switch ((VkAccessFlagBits
)(1 << b
)) {
532 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
533 case VK_ACCESS_INDEX_READ_BIT
:
534 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
535 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
537 case VK_ACCESS_UNIFORM_READ_BIT
:
538 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
539 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
541 case VK_ACCESS_SHADER_READ_BIT
:
542 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
543 case VK_ACCESS_TRANSFER_READ_BIT
:
544 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
547 break; /* Nothing to do */
551 cmd_buffer
->state
.pending_pipe_bits
|= pipe_bits
;
555 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
557 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
559 /* In order to avoid thrash, we assume that vertex and fragment stages
560 * always exist. In the rare case where one is missing *and* the other
561 * uses push concstants, this may be suboptimal. However, avoiding stalls
562 * seems more important.
564 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
566 if (stages
== cmd_buffer
->state
.push_constant_stages
)
570 const unsigned push_constant_kb
= 32;
572 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
574 const unsigned push_constant_kb
= 16;
577 const unsigned num_stages
=
578 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
579 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
581 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
582 * units of 2KB. Incidentally, these are the same platforms that have
583 * 32KB worth of push constant space.
585 if (push_constant_kb
== 32)
586 size_per_stage
&= ~1u;
588 uint32_t kb_used
= 0;
589 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
590 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
591 anv_batch_emit(&cmd_buffer
->batch
,
592 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
593 alloc
._3DCommandSubOpcode
= 18 + i
;
594 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
595 alloc
.ConstantBufferSize
= push_size
;
597 kb_used
+= push_size
;
600 anv_batch_emit(&cmd_buffer
->batch
,
601 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
602 alloc
.ConstantBufferOffset
= kb_used
;
603 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
606 cmd_buffer
->state
.push_constant_stages
= stages
;
608 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
610 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
611 * the next 3DPRIMITIVE command after programming the
612 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
614 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
615 * pipeline setup, we need to dirty push constants.
617 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
620 static struct anv_state
621 alloc_null_surface_state(struct anv_cmd_buffer
*cmd_buffer
,
622 struct anv_framebuffer
*fb
)
624 struct anv_state state
=
625 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
627 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
628 .SurfaceType
= SURFTYPE_NULL
,
629 .SurfaceArray
= fb
->layers
> 0,
630 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
634 .TiledSurface
= true,
636 .Width
= fb
->width
- 1,
637 .Height
= fb
->height
- 1,
638 .Depth
= fb
->layers
- 1,
639 .RenderTargetViewExtent
= fb
->layers
- 1,
642 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
.map
, &null_ss
);
644 if (!cmd_buffer
->device
->info
.has_llc
)
645 anv_state_clflush(state
);
652 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
653 gl_shader_stage stage
,
654 struct anv_state
*bt_state
)
656 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
657 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
658 struct anv_pipeline
*pipeline
;
659 uint32_t bias
, state_offset
;
662 case MESA_SHADER_COMPUTE
:
663 pipeline
= cmd_buffer
->state
.compute_pipeline
;
667 pipeline
= cmd_buffer
->state
.pipeline
;
672 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
673 *bt_state
= (struct anv_state
) { 0, };
677 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
678 if (bias
+ map
->surface_count
== 0) {
679 *bt_state
= (struct anv_state
) { 0, };
683 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
684 bias
+ map
->surface_count
,
686 uint32_t *bt_map
= bt_state
->map
;
688 if (bt_state
->map
== NULL
)
689 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
691 if (stage
== MESA_SHADER_COMPUTE
&&
692 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
693 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
694 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
696 struct anv_state surface_state
;
698 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
700 const enum isl_format format
=
701 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
702 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
703 format
, bo_offset
, 12, 1);
705 bt_map
[0] = surface_state
.offset
+ state_offset
;
706 anv_cmd_buffer_add_surface_state_reloc(cmd_buffer
, surface_state
,
710 if (map
->surface_count
== 0)
713 if (map
->image_count
> 0) {
715 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
716 if (result
!= VK_SUCCESS
)
719 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
723 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
724 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
726 struct anv_state surface_state
;
730 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
731 /* Color attachment binding */
732 assert(stage
== MESA_SHADER_FRAGMENT
);
733 assert(binding
->binding
== 0);
734 if (binding
->index
< subpass
->color_count
) {
735 const struct anv_image_view
*iview
=
736 fb
->attachments
[subpass
->color_attachments
[binding
->index
]];
738 assert(iview
->color_rt_surface_state
.alloc_size
);
739 surface_state
= iview
->color_rt_surface_state
;
740 anv_cmd_buffer_add_surface_state_reloc(cmd_buffer
, surface_state
,
741 iview
->bo
, iview
->offset
);
743 /* Null render target */
744 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
745 surface_state
= alloc_null_surface_state(cmd_buffer
, fb
);
748 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
752 struct anv_descriptor_set
*set
=
753 cmd_buffer
->state
.descriptors
[binding
->set
];
754 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
755 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
757 switch (desc
->type
) {
758 case VK_DESCRIPTOR_TYPE_SAMPLER
:
759 /* Nothing for us to do here */
762 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
763 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
764 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
765 surface_state
= desc
->image_view
->sampler_surface_state
;
766 assert(surface_state
.alloc_size
);
767 bo
= desc
->image_view
->bo
;
768 bo_offset
= desc
->image_view
->offset
;
771 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
772 surface_state
= desc
->image_view
->storage_surface_state
;
773 assert(surface_state
.alloc_size
);
774 bo
= desc
->image_view
->bo
;
775 bo_offset
= desc
->image_view
->offset
;
777 struct brw_image_param
*image_param
=
778 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
780 *image_param
= desc
->image_view
->storage_image_param
;
781 image_param
->surface_idx
= bias
+ s
;
785 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
786 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
787 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
788 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
789 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
790 surface_state
= desc
->buffer_view
->surface_state
;
791 assert(surface_state
.alloc_size
);
792 bo
= desc
->buffer_view
->bo
;
793 bo_offset
= desc
->buffer_view
->offset
;
796 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
797 surface_state
= desc
->buffer_view
->storage_surface_state
;
798 assert(surface_state
.alloc_size
);
799 bo
= desc
->buffer_view
->bo
;
800 bo_offset
= desc
->buffer_view
->offset
;
802 struct brw_image_param
*image_param
=
803 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
805 *image_param
= desc
->buffer_view
->storage_image_param
;
806 image_param
->surface_idx
= bias
+ s
;
810 assert(!"Invalid descriptor type");
814 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
815 anv_cmd_buffer_add_surface_state_reloc(cmd_buffer
, surface_state
,
818 assert(image
== map
->image_count
);
821 if (!cmd_buffer
->device
->info
.has_llc
)
822 anv_state_clflush(*bt_state
);
828 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
829 gl_shader_stage stage
,
830 struct anv_state
*state
)
832 struct anv_pipeline
*pipeline
;
834 if (stage
== MESA_SHADER_COMPUTE
)
835 pipeline
= cmd_buffer
->state
.compute_pipeline
;
837 pipeline
= cmd_buffer
->state
.pipeline
;
839 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
840 *state
= (struct anv_state
) { 0, };
844 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
845 if (map
->sampler_count
== 0) {
846 *state
= (struct anv_state
) { 0, };
850 uint32_t size
= map
->sampler_count
* 16;
851 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
853 if (state
->map
== NULL
)
854 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
856 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
857 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
858 struct anv_descriptor_set
*set
=
859 cmd_buffer
->state
.descriptors
[binding
->set
];
860 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
861 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
863 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
864 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
867 struct anv_sampler
*sampler
= desc
->sampler
;
869 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
870 * happens to be zero.
875 memcpy(state
->map
+ (s
* 16),
876 sampler
->state
, sizeof(sampler
->state
));
879 if (!cmd_buffer
->device
->info
.has_llc
)
880 anv_state_clflush(*state
);
886 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
888 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
889 cmd_buffer
->state
.pipeline
->active_stages
;
891 VkResult result
= VK_SUCCESS
;
892 anv_foreach_stage(s
, dirty
) {
893 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
894 if (result
!= VK_SUCCESS
)
896 result
= emit_binding_table(cmd_buffer
, s
,
897 &cmd_buffer
->state
.binding_tables
[s
]);
898 if (result
!= VK_SUCCESS
)
902 if (result
!= VK_SUCCESS
) {
903 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
905 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
906 assert(result
== VK_SUCCESS
);
908 /* Re-emit state base addresses so we get the new surface state base
909 * address before we start emitting binding tables etc.
911 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
913 /* Re-emit all active binding tables */
914 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
915 anv_foreach_stage(s
, dirty
) {
916 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
917 if (result
!= VK_SUCCESS
)
919 result
= emit_binding_table(cmd_buffer
, s
,
920 &cmd_buffer
->state
.binding_tables
[s
]);
921 if (result
!= VK_SUCCESS
)
926 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
932 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
935 static const uint32_t sampler_state_opcodes
[] = {
936 [MESA_SHADER_VERTEX
] = 43,
937 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
938 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
939 [MESA_SHADER_GEOMETRY
] = 46,
940 [MESA_SHADER_FRAGMENT
] = 47,
941 [MESA_SHADER_COMPUTE
] = 0,
944 static const uint32_t binding_table_opcodes
[] = {
945 [MESA_SHADER_VERTEX
] = 38,
946 [MESA_SHADER_TESS_CTRL
] = 39,
947 [MESA_SHADER_TESS_EVAL
] = 40,
948 [MESA_SHADER_GEOMETRY
] = 41,
949 [MESA_SHADER_FRAGMENT
] = 42,
950 [MESA_SHADER_COMPUTE
] = 0,
953 anv_foreach_stage(s
, stages
) {
954 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
955 anv_batch_emit(&cmd_buffer
->batch
,
956 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
957 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
958 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
962 /* Always emit binding table pointers if we're asked to, since on SKL
963 * this is what flushes push constants. */
964 anv_batch_emit(&cmd_buffer
->batch
,
965 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
966 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
967 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
973 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
975 static const uint32_t push_constant_opcodes
[] = {
976 [MESA_SHADER_VERTEX
] = 21,
977 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
978 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
979 [MESA_SHADER_GEOMETRY
] = 22,
980 [MESA_SHADER_FRAGMENT
] = 23,
981 [MESA_SHADER_COMPUTE
] = 0,
984 VkShaderStageFlags flushed
= 0;
986 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
987 if (stage
== MESA_SHADER_COMPUTE
)
990 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
992 if (state
.offset
== 0) {
993 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
994 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
996 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
997 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
998 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1000 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
1001 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1003 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
1004 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1010 flushed
|= mesa_to_vk_shader_stage(stage
);
1013 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1019 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1021 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1024 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1026 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1028 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1030 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1033 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1034 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1036 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1037 GENX(3DSTATE_VERTEX_BUFFERS
));
1039 for_each_bit(vb
, vb_emit
) {
1040 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1041 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1043 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1044 .VertexBufferIndex
= vb
,
1047 .MemoryObjectControlState
= GENX(MOCS
),
1049 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1050 .InstanceDataStepRate
= 1,
1051 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1054 .AddressModifyEnable
= true,
1055 .BufferPitch
= pipeline
->binding_stride
[vb
],
1056 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1059 .BufferSize
= buffer
->size
- offset
1061 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1065 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1070 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1072 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1073 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1075 /* The exact descriptor layout is pulled from the pipeline, so we need
1076 * to re-emit binding tables on every pipeline change.
1078 cmd_buffer
->state
.descriptors_dirty
|=
1079 cmd_buffer
->state
.pipeline
->active_stages
;
1081 /* If the pipeline changed, we may need to re-allocate push constant
1084 cmd_buffer_alloc_push_constants(cmd_buffer
);
1088 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1089 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1090 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1092 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1093 * stall needs to be sent just prior to any 3DSTATE_VS,
1094 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1095 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1096 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1097 * PIPE_CONTROL needs to be sent before any combination of VS
1098 * associated 3DSTATE."
1100 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1101 pc
.DepthStallEnable
= true;
1102 pc
.PostSyncOperation
= WriteImmediateData
;
1104 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1109 /* Render targets live in the same binding table as fragment descriptors */
1110 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1111 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1113 /* We emit the binding tables and sampler tables first, then emit push
1114 * constants and then finally emit binding table and sampler table
1115 * pointers. It has to happen in this order, since emitting the binding
1116 * tables may change the push constants (in case of storage images). After
1117 * emitting push constants, on SKL+ we have to emit the corresponding
1118 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1121 if (cmd_buffer
->state
.descriptors_dirty
)
1122 dirty
= flush_descriptor_sets(cmd_buffer
);
1124 if (cmd_buffer
->state
.push_constants_dirty
) {
1126 /* On Sky Lake and later, the binding table pointers commands are
1127 * what actually flush the changes to push constant state so we need
1128 * to dirty them so they get re-emitted below.
1130 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1132 cmd_buffer_flush_push_constants(cmd_buffer
);
1137 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1139 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1140 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1142 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1143 ANV_CMD_DIRTY_PIPELINE
)) {
1144 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1145 pipeline
->depth_clamp_enable
);
1148 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1149 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1151 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1153 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1157 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1158 struct anv_bo
*bo
, uint32_t offset
)
1160 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1161 GENX(3DSTATE_VERTEX_BUFFERS
));
1163 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1164 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1165 .VertexBufferIndex
= 32, /* Reserved for this */
1166 .AddressModifyEnable
= true,
1169 .MemoryObjectControlState
= GENX(MOCS
),
1170 .BufferStartingAddress
= { bo
, offset
},
1173 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1174 .BufferStartingAddress
= { bo
, offset
},
1175 .EndAddress
= { bo
, offset
+ 8 },
1181 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1182 uint32_t base_vertex
, uint32_t base_instance
)
1184 struct anv_state id_state
=
1185 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1187 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1188 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1190 if (!cmd_buffer
->device
->info
.has_llc
)
1191 anv_state_clflush(id_state
);
1193 emit_base_vertex_instance_bo(cmd_buffer
,
1194 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
1198 VkCommandBuffer commandBuffer
,
1199 uint32_t vertexCount
,
1200 uint32_t instanceCount
,
1201 uint32_t firstVertex
,
1202 uint32_t firstInstance
)
1204 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1205 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1206 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1208 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1210 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1211 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1213 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1214 prim
.VertexAccessType
= SEQUENTIAL
;
1215 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1216 prim
.VertexCountPerInstance
= vertexCount
;
1217 prim
.StartVertexLocation
= firstVertex
;
1218 prim
.InstanceCount
= instanceCount
;
1219 prim
.StartInstanceLocation
= firstInstance
;
1220 prim
.BaseVertexLocation
= 0;
1224 void genX(CmdDrawIndexed
)(
1225 VkCommandBuffer commandBuffer
,
1226 uint32_t indexCount
,
1227 uint32_t instanceCount
,
1228 uint32_t firstIndex
,
1229 int32_t vertexOffset
,
1230 uint32_t firstInstance
)
1232 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1233 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1234 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1236 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1238 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1239 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1241 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1242 prim
.VertexAccessType
= RANDOM
;
1243 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1244 prim
.VertexCountPerInstance
= indexCount
;
1245 prim
.StartVertexLocation
= firstIndex
;
1246 prim
.InstanceCount
= instanceCount
;
1247 prim
.StartInstanceLocation
= firstInstance
;
1248 prim
.BaseVertexLocation
= vertexOffset
;
1252 /* Auto-Draw / Indirect Registers */
1253 #define GEN7_3DPRIM_END_OFFSET 0x2420
1254 #define GEN7_3DPRIM_START_VERTEX 0x2430
1255 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1256 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1257 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1258 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1260 void genX(CmdDrawIndirect
)(
1261 VkCommandBuffer commandBuffer
,
1263 VkDeviceSize offset
,
1267 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1268 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1269 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1270 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1271 struct anv_bo
*bo
= buffer
->bo
;
1272 uint32_t bo_offset
= buffer
->offset
+ offset
;
1274 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1276 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1277 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
1279 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1280 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1281 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1282 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
1283 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
1285 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1286 prim
.IndirectParameterEnable
= true;
1287 prim
.VertexAccessType
= SEQUENTIAL
;
1288 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1292 void genX(CmdDrawIndexedIndirect
)(
1293 VkCommandBuffer commandBuffer
,
1295 VkDeviceSize offset
,
1299 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1300 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1301 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1302 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1303 struct anv_bo
*bo
= buffer
->bo
;
1304 uint32_t bo_offset
= buffer
->offset
+ offset
;
1306 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1308 /* TODO: We need to stomp base vertex to 0 somehow */
1309 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1310 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
1312 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1313 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1314 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1315 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
1316 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
1318 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1319 prim
.IndirectParameterEnable
= true;
1320 prim
.VertexAccessType
= RANDOM
;
1321 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1326 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
1328 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1329 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
1332 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
1333 if (result
!= VK_SUCCESS
)
1335 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1336 if (result
!= VK_SUCCESS
)
1339 struct anv_state push_state
= anv_cmd_buffer_cs_push_constants(cmd_buffer
);
1341 if (push_state
.alloc_size
) {
1342 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
1343 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
1344 curbe
.CURBEDataStartAddress
= push_state
.offset
;
1348 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
1349 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1350 .BindingTablePointer
= surfaces
.offset
,
1351 .SamplerStatePointer
= samplers
.offset
,
1353 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
1355 struct anv_state state
=
1356 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
1357 pipeline
->interface_descriptor_data
,
1358 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
1361 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
1362 anv_batch_emit(&cmd_buffer
->batch
,
1363 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
1364 mid
.InterfaceDescriptorTotalLength
= size
;
1365 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
1372 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1374 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1375 MAYBE_UNUSED VkResult result
;
1377 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
1379 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1381 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
1383 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)
1384 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1386 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
1387 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
1388 /* FIXME: figure out descriptors for gen7 */
1389 result
= flush_compute_descriptor_set(cmd_buffer
);
1390 assert(result
== VK_SUCCESS
);
1391 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
1394 cmd_buffer
->state
.compute_dirty
= 0;
1396 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1402 verify_cmd_parser(const struct anv_device
*device
,
1403 int required_version
,
1404 const char *function
)
1406 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
1407 vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
1408 "cmd parser version %d is required for %s",
1409 required_version
, function
);
1418 void genX(CmdDispatch
)(
1419 VkCommandBuffer commandBuffer
,
1424 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1425 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1426 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1428 if (prog_data
->uses_num_work_groups
) {
1429 struct anv_state state
=
1430 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
1431 uint32_t *sizes
= state
.map
;
1435 if (!cmd_buffer
->device
->info
.has_llc
)
1436 anv_state_clflush(state
);
1437 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
1438 cmd_buffer
->state
.num_workgroups_bo
=
1439 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
1442 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1444 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
1445 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1446 ggw
.ThreadDepthCounterMaximum
= 0;
1447 ggw
.ThreadHeightCounterMaximum
= 0;
1448 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1449 ggw
.ThreadGroupIDXDimension
= x
;
1450 ggw
.ThreadGroupIDYDimension
= y
;
1451 ggw
.ThreadGroupIDZDimension
= z
;
1452 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1453 ggw
.BottomExecutionMask
= 0xffffffff;
1456 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1459 #define GPGPU_DISPATCHDIMX 0x2500
1460 #define GPGPU_DISPATCHDIMY 0x2504
1461 #define GPGPU_DISPATCHDIMZ 0x2508
1463 #define MI_PREDICATE_SRC0 0x2400
1464 #define MI_PREDICATE_SRC1 0x2408
1466 void genX(CmdDispatchIndirect
)(
1467 VkCommandBuffer commandBuffer
,
1469 VkDeviceSize offset
)
1471 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1472 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1473 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1474 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1475 struct anv_bo
*bo
= buffer
->bo
;
1476 uint32_t bo_offset
= buffer
->offset
+ offset
;
1477 struct anv_batch
*batch
= &cmd_buffer
->batch
;
1480 /* Linux 4.4 added command parser version 5 which allows the GPGPU
1481 * indirect dispatch registers to be written.
1483 if (!verify_cmd_parser(cmd_buffer
->device
, 5, "vkCmdDispatchIndirect"))
1487 if (prog_data
->uses_num_work_groups
) {
1488 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
1489 cmd_buffer
->state
.num_workgroups_bo
= bo
;
1492 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1494 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
1495 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
1496 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
1499 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
1500 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
1501 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
1502 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
1504 /* Load compute_dispatch_indirect_x_size into SRC0 */
1505 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
1507 /* predicate = (compute_dispatch_indirect_x_size == 0); */
1508 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1509 mip
.LoadOperation
= LOAD_LOAD
;
1510 mip
.CombineOperation
= COMBINE_SET
;
1511 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1514 /* Load compute_dispatch_indirect_y_size into SRC0 */
1515 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
1517 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
1518 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1519 mip
.LoadOperation
= LOAD_LOAD
;
1520 mip
.CombineOperation
= COMBINE_OR
;
1521 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1524 /* Load compute_dispatch_indirect_z_size into SRC0 */
1525 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
1527 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
1528 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1529 mip
.LoadOperation
= LOAD_LOAD
;
1530 mip
.CombineOperation
= COMBINE_OR
;
1531 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1534 /* predicate = !predicate; */
1535 #define COMPARE_FALSE 1
1536 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1537 mip
.LoadOperation
= LOAD_LOADINV
;
1538 mip
.CombineOperation
= COMBINE_OR
;
1539 mip
.CompareOperation
= COMPARE_FALSE
;
1543 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
1544 ggw
.IndirectParameterEnable
= true;
1545 ggw
.PredicateEnable
= GEN_GEN
<= 7;
1546 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1547 ggw
.ThreadDepthCounterMaximum
= 0;
1548 ggw
.ThreadHeightCounterMaximum
= 0;
1549 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1550 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1551 ggw
.BottomExecutionMask
= 0xffffffff;
1554 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1558 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
1561 #if GEN_GEN >= 8 && GEN_GEN < 10
1562 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
1564 * Software must clear the COLOR_CALC_STATE Valid field in
1565 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
1566 * with Pipeline Select set to GPGPU.
1568 * The internal hardware docs recommend the same workaround for Gen9
1571 if (pipeline
== GPGPU
)
1572 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
1574 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
1575 * PIPELINE_SELECT [DevBWR+]":
1579 * Software must ensure all the write caches are flushed through a
1580 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
1581 * command to invalidate read only caches prior to programming
1582 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
1584 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1585 pc
.RenderTargetCacheFlushEnable
= true;
1586 pc
.DepthCacheFlushEnable
= true;
1587 pc
.DCFlushEnable
= true;
1588 pc
.PostSyncOperation
= NoWrite
;
1589 pc
.CommandStreamerStallEnable
= true;
1592 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1593 pc
.TextureCacheInvalidationEnable
= true;
1594 pc
.ConstantCacheInvalidationEnable
= true;
1595 pc
.StateCacheInvalidationEnable
= true;
1596 pc
.InstructionCacheInvalidateEnable
= true;
1597 pc
.PostSyncOperation
= NoWrite
;
1603 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
1605 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
1606 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
1608 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
1612 ps
.PipelineSelection
= _3D
;
1615 cmd_buffer
->state
.current_pipeline
= _3D
;
1620 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
1622 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
1623 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
1625 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
1629 ps
.PipelineSelection
= GPGPU
;
1632 cmd_buffer
->state
.current_pipeline
= GPGPU
;
1637 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
1639 struct anv_device
*device
= cmd_buffer
->device
;
1640 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1641 const struct anv_image_view
*iview
=
1642 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1643 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
1644 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1645 const bool has_hiz
= image
!= NULL
&& anv_image_has_hiz(image
);
1646 const bool has_stencil
=
1647 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1649 /* FIXME: Implement the PMA stall W/A */
1650 /* FIXME: Width and Height are wrong */
1652 /* Emit 3DSTATE_DEPTH_BUFFER */
1654 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
1655 db
.SurfaceType
= SURFTYPE_2D
;
1656 db
.DepthWriteEnable
= true;
1657 db
.StencilWriteEnable
= has_stencil
;
1659 if (cmd_buffer
->state
.pass
->subpass_count
== 1) {
1660 db
.HierarchicalDepthBufferEnable
= has_hiz
;
1662 anv_finishme("Multiple-subpass HiZ not implemented");
1665 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
1666 &image
->depth_surface
.isl
);
1668 db
.SurfaceBaseAddress
= (struct anv_address
) {
1670 .offset
= image
->offset
+ image
->depth_surface
.offset
,
1672 db
.DepthBufferObjectControlState
= GENX(MOCS
);
1674 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
1675 db
.Height
= image
->extent
.height
- 1;
1676 db
.Width
= image
->extent
.width
- 1;
1677 db
.LOD
= iview
->isl
.base_level
;
1678 db
.Depth
= image
->array_size
- 1; /* FIXME: 3-D */
1679 db
.MinimumArrayElement
= iview
->isl
.base_array_layer
;
1683 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2;
1685 db
.RenderTargetViewExtent
= 1 - 1;
1688 /* Even when no depth buffer is present, the hardware requires that
1689 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
1691 * If a null depth buffer is bound, the driver must instead bind depth as:
1692 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
1693 * 3DSTATE_DEPTH.Width = 1
1694 * 3DSTATE_DEPTH.Height = 1
1695 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
1696 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
1697 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
1698 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
1699 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
1701 * The PRM is wrong, though. The width and height must be programmed to
1702 * actual framebuffer's width and height, even when neither depth buffer
1703 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
1704 * be combined with a stencil buffer so we use D32_FLOAT instead.
1706 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
1707 db
.SurfaceType
= SURFTYPE_2D
;
1708 db
.SurfaceFormat
= D32_FLOAT
;
1709 db
.Width
= fb
->width
- 1;
1710 db
.Height
= fb
->height
- 1;
1711 db
.StencilWriteEnable
= has_stencil
;
1716 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
) {
1717 hdb
.HierarchicalDepthBufferObjectControlState
= GENX(MOCS
);
1718 hdb
.SurfacePitch
= image
->hiz_surface
.isl
.row_pitch
- 1;
1719 hdb
.SurfaceBaseAddress
= (struct anv_address
) {
1721 .offset
= image
->offset
+ image
->hiz_surface
.offset
,
1724 /* From the SKL PRM Vol2a:
1726 * The interpretation of this field is dependent on Surface Type
1728 * - SURFTYPE_1D: distance in pixels between array slices
1729 * - SURFTYPE_2D/CUBE: distance in rows between array slices
1730 * - SURFTYPE_3D: distance in rows between R - slices
1733 image
->hiz_surface
.isl
.dim
== ISL_SURF_DIM_1D
?
1734 isl_surf_get_array_pitch_el(&image
->hiz_surface
.isl
) >> 2 :
1735 isl_surf_get_array_pitch_el_rows(&image
->hiz_surface
.isl
) >> 2;
1739 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
);
1742 /* Emit 3DSTATE_STENCIL_BUFFER */
1744 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
1745 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1746 sb
.StencilBufferEnable
= true;
1748 sb
.StencilBufferObjectControlState
= GENX(MOCS
);
1750 sb
.SurfacePitch
= image
->stencil_surface
.isl
.row_pitch
- 1;
1753 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2;
1755 sb
.SurfaceBaseAddress
= (struct anv_address
) {
1757 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
1761 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
1764 /* From the IVB PRM Vol2P1, 11.5.5.4 3DSTATE_CLEAR_PARAMS:
1766 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along with
1767 * the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
1768 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)
1770 * Testing also shows that some variant of this restriction may exist HSW+.
1771 * On BDW+, it is not possible to emit 2 of these packets consecutively when
1772 * both have DepthClearValueValid set. An analysis of such state programming
1773 * on SKL showed that the GPU doesn't register the latter packet's clear
1776 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
) {
1778 cp
.DepthClearValueValid
= true;
1780 cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
1781 cp
.DepthClearValue
=
1782 cmd_buffer
->state
.attachments
[ds
].clear_value
.depthStencil
.depth
;
1788 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
1789 struct anv_subpass
*subpass
)
1791 cmd_buffer
->state
.subpass
= subpass
;
1793 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1795 cmd_buffer_emit_depth_stencil(cmd_buffer
);
1796 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_HIZ_RESOLVE
);
1797 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_DEPTH_CLEAR
);
1799 anv_cmd_buffer_clear_subpass(cmd_buffer
);
1802 void genX(CmdBeginRenderPass
)(
1803 VkCommandBuffer commandBuffer
,
1804 const VkRenderPassBeginInfo
* pRenderPassBegin
,
1805 VkSubpassContents contents
)
1807 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1808 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
1809 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
1811 cmd_buffer
->state
.framebuffer
= framebuffer
;
1812 cmd_buffer
->state
.pass
= pass
;
1813 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
1814 anv_cmd_state_setup_attachments(cmd_buffer
, pRenderPassBegin
);
1816 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1818 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
1821 void genX(CmdNextSubpass
)(
1822 VkCommandBuffer commandBuffer
,
1823 VkSubpassContents contents
)
1825 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1827 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1829 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
1830 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
1833 void genX(CmdEndRenderPass
)(
1834 VkCommandBuffer commandBuffer
)
1836 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1838 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_DEPTH_RESOLVE
);
1839 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
1842 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
1847 emit_ps_depth_count(struct anv_cmd_buffer
*cmd_buffer
,
1848 struct anv_bo
*bo
, uint32_t offset
)
1850 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1851 pc
.DestinationAddressType
= DAT_PPGTT
;
1852 pc
.PostSyncOperation
= WritePSDepthCount
;
1853 pc
.DepthStallEnable
= true;
1854 pc
.Address
= (struct anv_address
) { bo
, offset
};
1856 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
1857 pc
.CommandStreamerStallEnable
= true;
1862 emit_query_availability(struct anv_cmd_buffer
*cmd_buffer
,
1863 struct anv_bo
*bo
, uint32_t offset
)
1865 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1866 pc
.DestinationAddressType
= DAT_PPGTT
;
1867 pc
.PostSyncOperation
= WriteImmediateData
;
1868 pc
.Address
= (struct anv_address
) { bo
, offset
};
1869 pc
.ImmediateData
= 1;
1873 void genX(CmdBeginQuery
)(
1874 VkCommandBuffer commandBuffer
,
1875 VkQueryPool queryPool
,
1877 VkQueryControlFlags flags
)
1879 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1880 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1882 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
1883 * that the pipelining of the depth write breaks. What we see is that
1884 * samples from the render pass clear leaks into the first query
1885 * immediately after the clear. Doing a pipecontrol with a post-sync
1886 * operation and DepthStallEnable seems to work around the issue.
1888 if (cmd_buffer
->state
.need_query_wa
) {
1889 cmd_buffer
->state
.need_query_wa
= false;
1890 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1891 pc
.DepthCacheFlushEnable
= true;
1892 pc
.DepthStallEnable
= true;
1896 switch (pool
->type
) {
1897 case VK_QUERY_TYPE_OCCLUSION
:
1898 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
1899 query
* sizeof(struct anv_query_pool_slot
));
1902 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1908 void genX(CmdEndQuery
)(
1909 VkCommandBuffer commandBuffer
,
1910 VkQueryPool queryPool
,
1913 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1914 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1916 switch (pool
->type
) {
1917 case VK_QUERY_TYPE_OCCLUSION
:
1918 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
1919 query
* sizeof(struct anv_query_pool_slot
) + 8);
1921 emit_query_availability(cmd_buffer
, &pool
->bo
,
1922 query
* sizeof(struct anv_query_pool_slot
) + 16);
1925 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1931 #define TIMESTAMP 0x2358
1933 void genX(CmdWriteTimestamp
)(
1934 VkCommandBuffer commandBuffer
,
1935 VkPipelineStageFlagBits pipelineStage
,
1936 VkQueryPool queryPool
,
1939 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1940 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1941 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
1943 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
1945 switch (pipelineStage
) {
1946 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
1947 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
1948 srm
.RegisterAddress
= TIMESTAMP
;
1949 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
};
1951 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
1952 srm
.RegisterAddress
= TIMESTAMP
+ 4;
1953 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
+ 4 };
1958 /* Everything else is bottom-of-pipe */
1959 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1960 pc
.DestinationAddressType
= DAT_PPGTT
;
1961 pc
.PostSyncOperation
= WriteTimestamp
;
1962 pc
.Address
= (struct anv_address
) { &pool
->bo
, offset
};
1964 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
1965 pc
.CommandStreamerStallEnable
= true;
1970 emit_query_availability(cmd_buffer
, &pool
->bo
, query
+ 16);
1973 #if GEN_GEN > 7 || GEN_IS_HASWELL
1975 #define alu_opcode(v) __gen_uint((v), 20, 31)
1976 #define alu_operand1(v) __gen_uint((v), 10, 19)
1977 #define alu_operand2(v) __gen_uint((v), 0, 9)
1978 #define alu(opcode, operand1, operand2) \
1979 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
1981 #define OPCODE_NOOP 0x000
1982 #define OPCODE_LOAD 0x080
1983 #define OPCODE_LOADINV 0x480
1984 #define OPCODE_LOAD0 0x081
1985 #define OPCODE_LOAD1 0x481
1986 #define OPCODE_ADD 0x100
1987 #define OPCODE_SUB 0x101
1988 #define OPCODE_AND 0x102
1989 #define OPCODE_OR 0x103
1990 #define OPCODE_XOR 0x104
1991 #define OPCODE_STORE 0x180
1992 #define OPCODE_STOREINV 0x580
1994 #define OPERAND_R0 0x00
1995 #define OPERAND_R1 0x01
1996 #define OPERAND_R2 0x02
1997 #define OPERAND_R3 0x03
1998 #define OPERAND_R4 0x04
1999 #define OPERAND_SRCA 0x20
2000 #define OPERAND_SRCB 0x21
2001 #define OPERAND_ACCU 0x31
2002 #define OPERAND_ZF 0x32
2003 #define OPERAND_CF 0x33
2005 #define CS_GPR(n) (0x2600 + (n) * 8)
2008 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
2009 struct anv_bo
*bo
, uint32_t offset
)
2011 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2012 lrm
.RegisterAddress
= reg
,
2013 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2015 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2016 lrm
.RegisterAddress
= reg
+ 4;
2017 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2022 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
2023 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
2025 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2026 srm
.RegisterAddress
= reg
;
2027 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2030 if (flags
& VK_QUERY_RESULT_64_BIT
) {
2031 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2032 srm
.RegisterAddress
= reg
+ 4;
2033 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2038 void genX(CmdCopyQueryPoolResults
)(
2039 VkCommandBuffer commandBuffer
,
2040 VkQueryPool queryPool
,
2041 uint32_t firstQuery
,
2042 uint32_t queryCount
,
2043 VkBuffer destBuffer
,
2044 VkDeviceSize destOffset
,
2045 VkDeviceSize destStride
,
2046 VkQueryResultFlags flags
)
2048 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2049 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2050 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
2051 uint32_t slot_offset
, dst_offset
;
2053 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
2054 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2055 pc
.CommandStreamerStallEnable
= true;
2056 pc
.StallAtPixelScoreboard
= true;
2060 dst_offset
= buffer
->offset
+ destOffset
;
2061 for (uint32_t i
= 0; i
< queryCount
; i
++) {
2063 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
2064 switch (pool
->type
) {
2065 case VK_QUERY_TYPE_OCCLUSION
:
2066 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2067 CS_GPR(0), &pool
->bo
, slot_offset
);
2068 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2069 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
2071 /* FIXME: We need to clamp the result for 32 bit. */
2073 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
2074 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
2075 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
2076 dw
[3] = alu(OPCODE_SUB
, 0, 0);
2077 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
2080 case VK_QUERY_TYPE_TIMESTAMP
:
2081 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2082 CS_GPR(2), &pool
->bo
, slot_offset
);
2086 unreachable("unhandled query type");
2089 store_query_result(&cmd_buffer
->batch
,
2090 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
2092 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
2093 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
2094 &pool
->bo
, slot_offset
+ 16);
2095 if (flags
& VK_QUERY_RESULT_64_BIT
)
2096 store_query_result(&cmd_buffer
->batch
,
2097 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
2099 store_query_result(&cmd_buffer
->batch
,
2100 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
2103 dst_offset
+= destStride
;
2108 void genX(CmdCopyQueryPoolResults
)(
2109 VkCommandBuffer commandBuffer
,
2110 VkQueryPool queryPool
,
2111 uint32_t firstQuery
,
2112 uint32_t queryCount
,
2113 VkBuffer destBuffer
,
2114 VkDeviceSize destOffset
,
2115 VkDeviceSize destStride
,
2116 VkQueryResultFlags flags
)
2118 anv_finishme("Queries not yet supported on Ivy Bridge");