2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_l3_config.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
36 /* We reserve GPR 14 and 15 for conditional rendering */
37 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
38 #define __gen_get_batch_dwords anv_batch_emit_dwords
39 #define __gen_address_offset anv_address_add
40 #include "common/gen_mi_builder.h"
43 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
45 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
46 lri
.RegisterOffset
= reg
;
52 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
54 struct anv_device
*device
= cmd_buffer
->device
;
56 /* If we are emitting a new state base address we probably need to re-emit
59 cmd_buffer
->state
.descriptors_dirty
|= ~0;
61 /* Emit a render target cache flush.
63 * This isn't documented anywhere in the PRM. However, it seems to be
64 * necessary prior to changing the surface state base adress. Without
65 * this, we get GPU hangs when using multi-level command buffers which
66 * clear depth, reset state base address, and then go render stuff.
68 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
69 pc
.DCFlushEnable
= true;
70 pc
.RenderTargetCacheFlushEnable
= true;
71 pc
.CommandStreamerStallEnable
= true;
74 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
75 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
76 sba
.GeneralStateMOCS
= GENX(MOCS
);
77 sba
.GeneralStateBaseAddressModifyEnable
= true;
79 sba
.StatelessDataPortAccessMOCS
= GENX(MOCS
);
81 sba
.SurfaceStateBaseAddress
=
82 anv_cmd_buffer_surface_base_address(cmd_buffer
);
83 sba
.SurfaceStateMOCS
= GENX(MOCS
);
84 sba
.SurfaceStateBaseAddressModifyEnable
= true;
86 sba
.DynamicStateBaseAddress
=
87 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
88 sba
.DynamicStateMOCS
= GENX(MOCS
);
89 sba
.DynamicStateBaseAddressModifyEnable
= true;
91 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
92 sba
.IndirectObjectMOCS
= GENX(MOCS
);
93 sba
.IndirectObjectBaseAddressModifyEnable
= true;
95 sba
.InstructionBaseAddress
=
96 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
97 sba
.InstructionMOCS
= GENX(MOCS
);
98 sba
.InstructionBaseAddressModifyEnable
= true;
101 /* Broadwell requires that we specify a buffer size for a bunch of
102 * these fields. However, since we will be growing the BO's live, we
103 * just set them all to the maximum.
105 sba
.GeneralStateBufferSize
= 0xfffff;
106 sba
.GeneralStateBufferSizeModifyEnable
= true;
107 sba
.DynamicStateBufferSize
= 0xfffff;
108 sba
.DynamicStateBufferSizeModifyEnable
= true;
109 sba
.IndirectObjectBufferSize
= 0xfffff;
110 sba
.IndirectObjectBufferSizeModifyEnable
= true;
111 sba
.InstructionBufferSize
= 0xfffff;
112 sba
.InstructionBuffersizeModifyEnable
= true;
114 /* On gen7, we have upper bounds instead. According to the docs,
115 * setting an upper bound of zero means that no bounds checking is
116 * performed so, in theory, we should be able to leave them zero.
117 * However, border color is broken and the GPU bounds-checks anyway.
118 * To avoid this and other potential problems, we may as well set it
121 sba
.GeneralStateAccessUpperBound
=
122 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
123 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
124 sba
.DynamicStateAccessUpperBound
=
125 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
126 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
127 sba
.InstructionAccessUpperBound
=
128 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
129 sba
.InstructionAccessUpperBoundModifyEnable
= true;
132 if (cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
) {
133 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
134 .bo
= device
->surface_state_pool
.block_pool
.bo
,
137 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
139 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
140 sba
.BindlessSurfaceStateSize
= 0;
142 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
143 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
146 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
147 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
148 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
149 sba
.BindlessSamplerStateBufferSize
= 0;
153 /* After re-setting the surface state base address, we have to do some
154 * cache flusing so that the sampler engine will pick up the new
155 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
156 * Shared Function > 3D Sampler > State > State Caching (page 96):
158 * Coherency with system memory in the state cache, like the texture
159 * cache is handled partially by software. It is expected that the
160 * command stream or shader will issue Cache Flush operation or
161 * Cache_Flush sampler message to ensure that the L1 cache remains
162 * coherent with system memory.
166 * Whenever the value of the Dynamic_State_Base_Addr,
167 * Surface_State_Base_Addr are altered, the L1 state cache must be
168 * invalidated to ensure the new surface or sampler state is fetched
169 * from system memory.
171 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
172 * which, according the PIPE_CONTROL instruction documentation in the
175 * Setting this bit is independent of any other bit in this packet.
176 * This bit controls the invalidation of the L1 and L2 state caches
177 * at the top of the pipe i.e. at the parsing time.
179 * Unfortunately, experimentation seems to indicate that state cache
180 * invalidation through a PIPE_CONTROL does nothing whatsoever in
181 * regards to surface state and binding tables. In stead, it seems that
182 * invalidating the texture cache is what is actually needed.
184 * XXX: As far as we have been able to determine through
185 * experimentation, shows that flush the texture cache appears to be
186 * sufficient. The theory here is that all of the sampling/rendering
187 * units cache the binding table in the texture cache. However, we have
188 * yet to be able to actually confirm this.
190 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
191 pc
.TextureCacheInvalidationEnable
= true;
192 pc
.ConstantCacheInvalidationEnable
= true;
193 pc
.StateCacheInvalidationEnable
= true;
198 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
199 struct anv_state state
, struct anv_address addr
)
201 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
204 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
205 state
.offset
+ isl_dev
->ss
.addr_offset
,
206 addr
.bo
, addr
.offset
);
207 if (result
!= VK_SUCCESS
)
208 anv_batch_set_error(&cmd_buffer
->batch
, result
);
212 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
213 struct anv_surface_state state
)
215 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
217 assert(!anv_address_is_null(state
.address
));
218 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
220 if (!anv_address_is_null(state
.aux_address
)) {
222 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
223 &cmd_buffer
->pool
->alloc
,
224 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
225 state
.aux_address
.bo
, state
.aux_address
.offset
);
226 if (result
!= VK_SUCCESS
)
227 anv_batch_set_error(&cmd_buffer
->batch
, result
);
230 if (!anv_address_is_null(state
.clear_address
)) {
232 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
233 &cmd_buffer
->pool
->alloc
,
235 isl_dev
->ss
.clear_color_state_offset
,
236 state
.clear_address
.bo
, state
.clear_address
.offset
);
237 if (result
!= VK_SUCCESS
)
238 anv_batch_set_error(&cmd_buffer
->batch
, result
);
243 color_attachment_compute_aux_usage(struct anv_device
* device
,
244 struct anv_cmd_state
* cmd_state
,
245 uint32_t att
, VkRect2D render_area
,
246 union isl_color_value
*fast_clear_color
)
248 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
249 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
251 assert(iview
->n_planes
== 1);
253 if (iview
->planes
[0].isl
.base_array_layer
>=
254 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
255 iview
->planes
[0].isl
.base_level
)) {
256 /* There is no aux buffer which corresponds to the level and layer(s)
259 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
260 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
261 att_state
->fast_clear
= false;
265 att_state
->aux_usage
=
266 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
267 VK_IMAGE_ASPECT_COLOR_BIT
,
268 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
270 /* If we don't have aux, then we should have returned early in the layer
271 * check above. If we got here, we must have something.
273 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
275 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
276 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
277 att_state
->input_aux_usage
= att_state
->aux_usage
;
279 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
281 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
282 * setting is only allowed if Surface Format supported for Fast
283 * Clear. In addition, if the surface is bound to the sampling
284 * engine, Surface Format must be supported for Render Target
285 * Compression for surfaces bound to the sampling engine."
287 * In other words, we can only sample from a fast-cleared image if it
288 * also supports color compression.
290 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
291 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
293 /* While fast-clear resolves and partial resolves are fairly cheap in the
294 * case where you render to most of the pixels, full resolves are not
295 * because they potentially involve reading and writing the entire
296 * framebuffer. If we can't texture with CCS_E, we should leave it off and
297 * limit ourselves to fast clears.
299 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
300 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
301 anv_perf_warn(device
->instance
, iview
->image
,
302 "Not temporarily enabling CCS_E.");
305 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
309 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
310 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
312 union isl_color_value clear_color
= {};
313 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
315 att_state
->clear_color_is_zero_one
=
316 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
317 att_state
->clear_color_is_zero
=
318 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
320 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
321 /* Start by getting the fast clear type. We use the first subpass
322 * layout here because we don't want to fast-clear if the first subpass
323 * to use the attachment can't handle fast-clears.
325 enum anv_fast_clear_type fast_clear_type
=
326 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
327 VK_IMAGE_ASPECT_COLOR_BIT
,
328 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
329 switch (fast_clear_type
) {
330 case ANV_FAST_CLEAR_NONE
:
331 att_state
->fast_clear
= false;
333 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
334 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
336 case ANV_FAST_CLEAR_ANY
:
337 att_state
->fast_clear
= true;
341 /* Potentially, we could do partial fast-clears but doing so has crazy
342 * alignment restrictions. It's easier to just restrict to full size
343 * fast clears for now.
345 if (render_area
.offset
.x
!= 0 ||
346 render_area
.offset
.y
!= 0 ||
347 render_area
.extent
.width
!= iview
->extent
.width
||
348 render_area
.extent
.height
!= iview
->extent
.height
)
349 att_state
->fast_clear
= false;
351 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
352 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
353 att_state
->fast_clear
= false;
355 /* We only allow fast clears to the first slice of an image (level 0,
356 * layer 0) and only for the entire slice. This guarantees us that, at
357 * any given time, there is only one clear color on any given image at
358 * any given time. At the time of our testing (Jan 17, 2018), there
359 * were no known applications which would benefit from fast-clearing
360 * more than just the first slice.
362 if (att_state
->fast_clear
&&
363 (iview
->planes
[0].isl
.base_level
> 0 ||
364 iview
->planes
[0].isl
.base_array_layer
> 0)) {
365 anv_perf_warn(device
->instance
, iview
->image
,
366 "Rendering with multi-lod or multi-layer framebuffer "
367 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
368 "baseArrayLayer > 0. Not fast clearing.");
369 att_state
->fast_clear
= false;
370 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
371 anv_perf_warn(device
->instance
, iview
->image
,
372 "Rendering to a multi-layer framebuffer with "
373 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
376 if (att_state
->fast_clear
)
377 *fast_clear_color
= clear_color
;
379 att_state
->fast_clear
= false;
384 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
385 struct anv_cmd_state
*cmd_state
,
386 uint32_t att
, VkRect2D render_area
)
388 struct anv_render_pass_attachment
*pass_att
=
389 &cmd_state
->pass
->attachments
[att
];
390 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
391 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
393 /* These will be initialized after the first subpass transition. */
394 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
395 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
398 /* We don't do any HiZ or depth fast-clears on gen7 yet */
399 att_state
->fast_clear
= false;
403 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
404 /* If we're just clearing stencil, we can always HiZ clear */
405 att_state
->fast_clear
= true;
409 /* Default to false for now */
410 att_state
->fast_clear
= false;
412 /* We must have depth in order to have HiZ */
413 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
416 const enum isl_aux_usage first_subpass_aux_usage
=
417 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
418 VK_IMAGE_ASPECT_DEPTH_BIT
,
419 pass_att
->first_subpass_layout
);
420 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
423 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
424 iview
->planes
[0].isl
.format
,
425 iview
->image
->samples
,
426 render_area
.offset
.x
,
427 render_area
.offset
.y
,
428 render_area
.offset
.x
+
429 render_area
.extent
.width
,
430 render_area
.offset
.y
+
431 render_area
.extent
.height
))
434 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
437 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
438 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
439 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
440 * only supports returning 0.0f. Gens prior to gen8 do not support this
446 /* If we got here, then we can fast clear */
447 att_state
->fast_clear
= true;
451 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
453 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
456 /* We only allocate input attachment states for color surfaces. Compression
457 * is not yet enabled for depth textures and stencil doesn't allow
458 * compression so we can just use the texture surface state from the view.
460 return vk_format_is_color(att
->format
);
463 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
464 * the initial layout is undefined, the HiZ buffer and depth buffer will
465 * represent the same data at the end of this operation.
468 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
469 const struct anv_image
*image
,
470 VkImageLayout initial_layout
,
471 VkImageLayout final_layout
)
473 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
474 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
475 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
476 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
477 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
478 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
480 enum isl_aux_op hiz_op
;
481 if (hiz_enabled
&& !enable_hiz
) {
482 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
483 } else if (!hiz_enabled
&& enable_hiz
) {
484 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
486 assert(hiz_enabled
== enable_hiz
);
487 /* If the same buffer will be used, no resolves are necessary. */
488 hiz_op
= ISL_AUX_OP_NONE
;
491 if (hiz_op
!= ISL_AUX_OP_NONE
)
492 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
497 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
499 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
500 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
;
503 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
504 * the initial layout is undefined, the HiZ buffer and depth buffer will
505 * represent the same data at the end of this operation.
508 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
509 const struct anv_image
*image
,
510 uint32_t base_level
, uint32_t level_count
,
511 uint32_t base_layer
, uint32_t layer_count
,
512 VkImageLayout initial_layout
,
513 VkImageLayout final_layout
)
516 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
517 VK_IMAGE_ASPECT_STENCIL_BIT
);
519 /* On gen7, we have to store a texturable version of the stencil buffer in
520 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
521 * forth at strategic points. Stencil writes are only allowed in three
524 * - VK_IMAGE_LAYOUT_GENERAL
525 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
526 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
527 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
529 * For general, we have no nice opportunity to transition so we do the copy
530 * to the shadow unconditionally at the end of the subpass. For transfer
531 * destinations, we can update it as part of the transfer op. For the
532 * other two, we delay the copy until a transition into some other layout.
534 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
535 vk_image_layout_stencil_write_optimal(initial_layout
) &&
536 !vk_image_layout_stencil_write_optimal(final_layout
)) {
537 anv_image_copy_to_shadow(cmd_buffer
, image
,
538 VK_IMAGE_ASPECT_STENCIL_BIT
,
539 base_level
, level_count
,
540 base_layer
, layer_count
);
542 #endif /* GEN_GEN == 7 */
545 #define MI_PREDICATE_SRC0 0x2400
546 #define MI_PREDICATE_SRC1 0x2408
547 #define MI_PREDICATE_RESULT 0x2418
550 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
551 const struct anv_image
*image
,
552 VkImageAspectFlagBits aspect
,
554 uint32_t base_layer
, uint32_t layer_count
,
557 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
559 /* We only have compression tracking for CCS_E */
560 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
563 for (uint32_t a
= 0; a
< layer_count
; a
++) {
564 uint32_t layer
= base_layer
+ a
;
565 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
566 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
569 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
575 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
576 const struct anv_image
*image
,
577 VkImageAspectFlagBits aspect
,
578 enum anv_fast_clear_type fast_clear
)
580 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
581 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
583 sdi
.ImmediateData
= fast_clear
;
586 /* Whenever we have fast-clear, we consider that slice to be compressed.
587 * This makes building predicates much easier.
589 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
590 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
593 #if GEN_IS_HASWELL || GEN_GEN >= 8
594 static inline uint32_t
595 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
597 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
599 .Operand1
= operand1
,
600 .Operand2
= operand2
,
604 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
610 /* This is only really practical on haswell and above because it requires
611 * MI math in order to get it correct.
613 #if GEN_GEN >= 8 || GEN_IS_HASWELL
615 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
616 const struct anv_image
*image
,
617 VkImageAspectFlagBits aspect
,
618 uint32_t level
, uint32_t array_layer
,
619 enum isl_aux_op resolve_op
,
620 enum anv_fast_clear_type fast_clear_supported
)
622 struct gen_mi_builder b
;
623 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
625 const struct gen_mi_value fast_clear_type
=
626 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
629 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
630 /* In this case, we're doing a full resolve which means we want the
631 * resolve to happen if any compression (including fast-clears) is
634 * In order to simplify the logic a bit, we make the assumption that,
635 * if the first slice has been fast-cleared, it is also marked as
636 * compressed. See also set_image_fast_clear_state.
638 const struct gen_mi_value compression_state
=
639 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
641 level
, array_layer
));
642 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
644 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
646 if (level
== 0 && array_layer
== 0) {
647 /* If the predicate is true, we want to write 0 to the fast clear type
648 * and, if it's false, leave it alone. We can do this by writing
650 * clear_type = clear_type & ~predicate;
652 struct gen_mi_value new_fast_clear_type
=
653 gen_mi_iand(&b
, fast_clear_type
,
654 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
655 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
657 } else if (level
== 0 && array_layer
== 0) {
658 /* In this case, we are doing a partial resolve to get rid of fast-clear
659 * colors. We don't care about the compression state but we do care
660 * about how much fast clear is allowed by the final layout.
662 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
663 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
665 /* We need to compute (fast_clear_supported < image->fast_clear) */
666 struct gen_mi_value pred
=
667 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
668 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
669 gen_mi_value_ref(&b
, pred
));
671 /* If the predicate is true, we want to write 0 to the fast clear type
672 * and, if it's false, leave it alone. We can do this by writing
674 * clear_type = clear_type & ~predicate;
676 struct gen_mi_value new_fast_clear_type
=
677 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
678 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
680 /* In this case, we're trying to do a partial resolve on a slice that
681 * doesn't have clear color. There's nothing to do.
683 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
687 /* Set src1 to 0 and use a != condition */
688 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
690 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
691 mip
.LoadOperation
= LOAD_LOADINV
;
692 mip
.CombineOperation
= COMBINE_SET
;
693 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
696 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
700 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
701 const struct anv_image
*image
,
702 VkImageAspectFlagBits aspect
,
703 uint32_t level
, uint32_t array_layer
,
704 enum isl_aux_op resolve_op
,
705 enum anv_fast_clear_type fast_clear_supported
)
707 struct gen_mi_builder b
;
708 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
710 struct gen_mi_value fast_clear_type_mem
=
711 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
714 /* This only works for partial resolves and only when the clear color is
715 * all or nothing. On the upside, this emits less command streamer code
716 * and works on Ivybridge and Bay Trail.
718 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
719 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
721 /* We don't support fast clears on anything other than the first slice. */
722 if (level
> 0 || array_layer
> 0)
725 /* On gen8, we don't have a concept of default clear colors because we
726 * can't sample from CCS surfaces. It's enough to just load the fast clear
727 * state into the predicate register.
729 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
730 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
731 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
733 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
734 mip
.LoadOperation
= LOAD_LOADINV
;
735 mip
.CombineOperation
= COMBINE_SET
;
736 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
739 #endif /* GEN_GEN <= 8 */
742 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
743 const struct anv_image
*image
,
744 enum isl_format format
,
745 VkImageAspectFlagBits aspect
,
746 uint32_t level
, uint32_t array_layer
,
747 enum isl_aux_op resolve_op
,
748 enum anv_fast_clear_type fast_clear_supported
)
750 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
753 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
754 aspect
, level
, array_layer
,
755 resolve_op
, fast_clear_supported
);
756 #else /* GEN_GEN <= 8 */
757 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
758 aspect
, level
, array_layer
,
759 resolve_op
, fast_clear_supported
);
762 /* CCS_D only supports full resolves and BLORP will assert on us if we try
763 * to do a partial resolve on a CCS_D surface.
765 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
766 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
767 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
769 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
770 array_layer
, 1, resolve_op
, NULL
, true);
774 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
775 const struct anv_image
*image
,
776 enum isl_format format
,
777 VkImageAspectFlagBits aspect
,
778 uint32_t array_layer
,
779 enum isl_aux_op resolve_op
,
780 enum anv_fast_clear_type fast_clear_supported
)
782 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
783 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
785 #if GEN_GEN >= 8 || GEN_IS_HASWELL
786 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
787 aspect
, 0, array_layer
,
788 resolve_op
, fast_clear_supported
);
790 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
791 array_layer
, 1, resolve_op
, NULL
, true);
793 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
798 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
799 const struct anv_image
*image
,
800 VkImageAspectFlagBits aspect
,
801 enum isl_aux_usage aux_usage
,
804 uint32_t layer_count
)
806 /* The aspect must be exactly one of the image aspects. */
807 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
809 /* The only compression types with more than just fast-clears are MCS,
810 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
811 * track the current fast-clear and compression state. This leaves us
812 * with just MCS and CCS_E.
814 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
815 aux_usage
!= ISL_AUX_USAGE_MCS
)
818 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
819 level
, base_layer
, layer_count
, true);
823 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
824 const struct anv_image
*image
,
825 VkImageAspectFlagBits aspect
)
827 assert(cmd_buffer
&& image
);
828 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
830 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
831 ANV_FAST_CLEAR_NONE
);
833 /* Initialize the struct fields that are accessed for fast-clears so that
834 * the HW restrictions on the field values are satisfied.
836 struct anv_address addr
=
837 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
840 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
841 const unsigned num_dwords
= GEN_GEN
>= 10 ?
842 isl_dev
->ss
.clear_color_state_size
/ 4 :
843 isl_dev
->ss
.clear_value_size
/ 4;
844 for (unsigned i
= 0; i
< num_dwords
; i
++) {
845 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
847 sdi
.Address
.offset
+= i
* 4;
848 sdi
.ImmediateData
= 0;
852 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
854 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
855 /* Pre-SKL, the dword containing the clear values also contains
856 * other fields, so we need to initialize those fields to match the
857 * values that would be in a color attachment.
859 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
860 ISL_CHANNEL_SELECT_GREEN
<< 22 |
861 ISL_CHANNEL_SELECT_BLUE
<< 19 |
862 ISL_CHANNEL_SELECT_ALPHA
<< 16;
863 } else if (GEN_GEN
== 7) {
864 /* On IVB, the dword containing the clear values also contains
865 * other fields that must be zero or can be zero.
867 sdi
.ImmediateData
= 0;
873 /* Copy the fast-clear value dword(s) between a surface state object and an
874 * image's fast clear state buffer.
877 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
878 struct anv_state surface_state
,
879 const struct anv_image
*image
,
880 VkImageAspectFlagBits aspect
,
881 bool copy_from_surface_state
)
883 assert(cmd_buffer
&& image
);
884 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
886 struct anv_address ss_clear_addr
= {
887 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
888 .offset
= surface_state
.offset
+
889 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
891 const struct anv_address entry_addr
=
892 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
893 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
896 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
897 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
898 * in-flight when they are issued even if the memory touched is not
899 * currently active for rendering. The weird bit is that it is not the
900 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
901 * rendering hangs such that the next stalling command after the
902 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
904 * It is unclear exactly why this hang occurs. Both MI commands come with
905 * warnings about the 3D pipeline but that doesn't seem to fully explain
906 * it. My (Jason's) best theory is that it has something to do with the
907 * fact that we're using a GPU state register as our temporary and that
908 * something with reading/writing it is causing problems.
910 * In order to work around this issue, we emit a PIPE_CONTROL with the
911 * command streamer stall bit set.
913 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
914 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
917 struct gen_mi_builder b
;
918 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
920 if (copy_from_surface_state
) {
921 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
923 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
925 /* Updating a surface state object may require that the state cache be
926 * invalidated. From the SKL PRM, Shared Functions -> State -> State
929 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
930 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
931 * modified [...], the L1 state cache must be invalidated to ensure
932 * the new surface or sampler state is fetched from system memory.
934 * In testing, SKL doesn't actually seem to need this, but HSW does.
936 cmd_buffer
->state
.pending_pipe_bits
|=
937 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
942 * @brief Transitions a color buffer from one layout to another.
944 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
947 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
948 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
949 * this represents the maximum layers to transition at each
950 * specified miplevel.
953 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
954 const struct anv_image
*image
,
955 VkImageAspectFlagBits aspect
,
956 const uint32_t base_level
, uint32_t level_count
,
957 uint32_t base_layer
, uint32_t layer_count
,
958 VkImageLayout initial_layout
,
959 VkImageLayout final_layout
)
961 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
962 /* Validate the inputs. */
964 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
965 /* These values aren't supported for simplicity's sake. */
966 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
967 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
968 /* Ensure the subresource range is valid. */
969 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
970 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
971 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
972 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
973 assert(last_level_num
<= image
->levels
);
974 /* The spec disallows these final layouts. */
975 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
976 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
978 /* No work is necessary if the layout stays the same or if this subresource
979 * range lacks auxiliary data.
981 if (initial_layout
== final_layout
)
984 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
986 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
987 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
988 /* This surface is a linear compressed image with a tiled shadow surface
989 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
990 * we need to ensure the shadow copy is up-to-date.
992 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
993 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
994 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
995 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
997 anv_image_copy_to_shadow(cmd_buffer
, image
,
998 VK_IMAGE_ASPECT_COLOR_BIT
,
999 base_level
, level_count
,
1000 base_layer
, layer_count
);
1003 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
1006 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
1008 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1009 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1010 /* A subresource in the undefined layout may have been aliased and
1011 * populated with any arrangement of bits. Therefore, we must initialize
1012 * the related aux buffer and clear buffer entry with desirable values.
1013 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1014 * images with VK_IMAGE_TILING_OPTIMAL.
1016 * Initialize the relevant clear buffer entries.
1018 if (base_level
== 0 && base_layer
== 0)
1019 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1021 /* Initialize the aux buffers to enable correct rendering. In order to
1022 * ensure that things such as storage images work correctly, aux buffers
1023 * need to be initialized to valid data.
1025 * Having an aux buffer with invalid data is a problem for two reasons:
1027 * 1) Having an invalid value in the buffer can confuse the hardware.
1028 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1029 * invalid and leads to the hardware doing strange things. It
1030 * doesn't hang as far as we can tell but rendering corruption can
1033 * 2) If this transition is into the GENERAL layout and we then use the
1034 * image as a storage image, then we must have the aux buffer in the
1035 * pass-through state so that, if we then go to texture from the
1036 * image, we get the results of our storage image writes and not the
1037 * fast clear color or other random data.
1039 * For CCS both of the problems above are real demonstrable issues. In
1040 * that case, the only thing we can do is to perform an ambiguate to
1041 * transition the aux surface into the pass-through state.
1043 * For MCS, (2) is never an issue because we don't support multisampled
1044 * storage images. In theory, issue (1) is a problem with MCS but we've
1045 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1046 * theory, be interpreted as something but we don't know that all bit
1047 * patterns are actually valid. For 2x and 8x, you could easily end up
1048 * with the MCS referring to an invalid plane because not all bits of
1049 * the MCS value are actually used. Even though we've never seen issues
1050 * in the wild, it's best to play it safe and initialize the MCS. We
1051 * can use a fast-clear for MCS because we only ever touch from render
1052 * and texture (no image load store).
1054 if (image
->samples
== 1) {
1055 for (uint32_t l
= 0; l
< level_count
; l
++) {
1056 const uint32_t level
= base_level
+ l
;
1058 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1059 if (base_layer
>= aux_layers
)
1060 break; /* We will only get fewer layers as level increases */
1061 uint32_t level_layer_count
=
1062 MIN2(layer_count
, aux_layers
- base_layer
);
1064 anv_image_ccs_op(cmd_buffer
, image
,
1065 image
->planes
[plane
].surface
.isl
.format
,
1066 aspect
, level
, base_layer
, level_layer_count
,
1067 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1069 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1070 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1071 level
, base_layer
, level_layer_count
,
1076 if (image
->samples
== 4 || image
->samples
== 16) {
1077 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1078 "Doing a potentially unnecessary fast-clear to "
1079 "define an MCS buffer.");
1082 assert(base_level
== 0 && level_count
== 1);
1083 anv_image_mcs_op(cmd_buffer
, image
,
1084 image
->planes
[plane
].surface
.isl
.format
,
1085 aspect
, base_layer
, layer_count
,
1086 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1091 const enum isl_aux_usage initial_aux_usage
=
1092 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1093 const enum isl_aux_usage final_aux_usage
=
1094 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1096 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1097 * We can handle transitions between CCS_D/E to and from NONE. What we
1098 * don't yet handle is switching between CCS_E and CCS_D within a given
1099 * image. Doing so in a performant way requires more detailed aux state
1100 * tracking such as what is done in i965. For now, just assume that we
1101 * only have one type of compression.
1103 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1104 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1105 initial_aux_usage
== final_aux_usage
);
1107 /* If initial aux usage is NONE, there is nothing to resolve */
1108 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1111 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1113 /* If the initial layout supports more fast clear than the final layout
1114 * then we need at least a partial resolve.
1116 const enum anv_fast_clear_type initial_fast_clear
=
1117 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1118 const enum anv_fast_clear_type final_fast_clear
=
1119 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1120 if (final_fast_clear
< initial_fast_clear
)
1121 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1123 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1124 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1125 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1127 if (resolve_op
== ISL_AUX_OP_NONE
)
1130 /* Perform a resolve to synchronize data between the main and aux buffer.
1131 * Before we begin, we must satisfy the cache flushing requirement specified
1132 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1134 * Any transition from any value in {Clear, Render, Resolve} to a
1135 * different value in {Clear, Render, Resolve} requires end of pipe
1138 * We perform a flush of the write cache before and after the clear and
1139 * resolve operations to meet this requirement.
1141 * Unlike other drawing, fast clear operations are not properly
1142 * synchronized. The first PIPE_CONTROL here likely ensures that the
1143 * contents of the previous render or clear hit the render target before we
1144 * resolve and the second likely ensures that the resolve is complete before
1145 * we do any more rendering or clearing.
1147 cmd_buffer
->state
.pending_pipe_bits
|=
1148 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1150 for (uint32_t l
= 0; l
< level_count
; l
++) {
1151 uint32_t level
= base_level
+ l
;
1153 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1154 if (base_layer
>= aux_layers
)
1155 break; /* We will only get fewer layers as level increases */
1156 uint32_t level_layer_count
=
1157 MIN2(layer_count
, aux_layers
- base_layer
);
1159 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1160 uint32_t array_layer
= base_layer
+ a
;
1161 if (image
->samples
== 1) {
1162 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1163 image
->planes
[plane
].surface
.isl
.format
,
1164 aspect
, level
, array_layer
, resolve_op
,
1167 /* We only support fast-clear on the first layer so partial
1168 * resolves should not be used on other layers as they will use
1169 * the clear color stored in memory that is only valid for layer0.
1171 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1175 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1176 image
->planes
[plane
].surface
.isl
.format
,
1177 aspect
, array_layer
, resolve_op
,
1183 cmd_buffer
->state
.pending_pipe_bits
|=
1184 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1188 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1191 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1192 struct anv_render_pass
*pass
,
1193 const VkRenderPassBeginInfo
*begin
)
1195 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1196 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1197 struct anv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1199 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1201 if (pass
->attachment_count
> 0) {
1202 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1203 pass
->attachment_count
*
1204 sizeof(state
->attachments
[0]),
1205 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1206 if (state
->attachments
== NULL
) {
1207 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1208 return anv_batch_set_error(&cmd_buffer
->batch
,
1209 VK_ERROR_OUT_OF_HOST_MEMORY
);
1212 state
->attachments
= NULL
;
1215 /* Reserve one for the NULL state. */
1216 unsigned num_states
= 1;
1217 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1218 if (vk_format_is_color(pass
->attachments
[i
].format
))
1221 if (need_input_attachment_state(&pass
->attachments
[i
]))
1225 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1226 state
->render_pass_states
=
1227 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1228 num_states
* ss_stride
, isl_dev
->ss
.align
);
1230 struct anv_state next_state
= state
->render_pass_states
;
1231 next_state
.alloc_size
= isl_dev
->ss
.size
;
1233 state
->null_surface_state
= next_state
;
1234 next_state
.offset
+= ss_stride
;
1235 next_state
.map
+= ss_stride
;
1237 const VkRenderPassAttachmentBeginInfoKHR
*begin_attachment
=
1238 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1240 if (begin
&& !begin_attachment
)
1241 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1243 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1244 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1245 state
->attachments
[i
].color
.state
= next_state
;
1246 next_state
.offset
+= ss_stride
;
1247 next_state
.map
+= ss_stride
;
1250 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1251 state
->attachments
[i
].input
.state
= next_state
;
1252 next_state
.offset
+= ss_stride
;
1253 next_state
.map
+= ss_stride
;
1256 if (begin_attachment
&& begin_attachment
->attachmentCount
!= 0) {
1257 assert(begin_attachment
->attachmentCount
== pass
->attachment_count
);
1258 ANV_FROM_HANDLE(anv_image_view
, iview
, begin_attachment
->pAttachments
[i
]);
1259 cmd_buffer
->state
.attachments
[i
].image_view
= iview
;
1260 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1261 cmd_buffer
->state
.attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1264 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1265 state
->render_pass_states
.alloc_size
);
1268 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1269 isl_extent3d(framebuffer
->width
,
1270 framebuffer
->height
,
1271 framebuffer
->layers
));
1273 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1274 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1275 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1276 VkImageAspectFlags clear_aspects
= 0;
1277 VkImageAspectFlags load_aspects
= 0;
1279 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1280 /* color attachment */
1281 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1282 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1283 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1284 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1287 /* depthstencil attachment */
1288 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1289 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1290 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1291 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1292 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1295 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1296 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1297 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1298 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1299 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1304 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1305 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1306 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1308 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1310 struct anv_image_view
*iview
= cmd_buffer
->state
.attachments
[i
].image_view
;
1311 anv_assert(iview
->vk_format
== att
->format
);
1313 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1314 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1316 union isl_color_value clear_color
= { .u32
= { 0, } };
1317 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1318 anv_assert(iview
->n_planes
== 1);
1319 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1320 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1321 state
, i
, begin
->renderArea
,
1324 anv_image_fill_surface_state(cmd_buffer
->device
,
1326 VK_IMAGE_ASPECT_COLOR_BIT
,
1327 &iview
->planes
[0].isl
,
1328 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1329 state
->attachments
[i
].aux_usage
,
1332 &state
->attachments
[i
].color
,
1335 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1337 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1342 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1343 anv_image_fill_surface_state(cmd_buffer
->device
,
1345 VK_IMAGE_ASPECT_COLOR_BIT
,
1346 &iview
->planes
[0].isl
,
1347 ISL_SURF_USAGE_TEXTURE_BIT
,
1348 state
->attachments
[i
].input_aux_usage
,
1351 &state
->attachments
[i
].input
,
1354 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1363 genX(BeginCommandBuffer
)(
1364 VkCommandBuffer commandBuffer
,
1365 const VkCommandBufferBeginInfo
* pBeginInfo
)
1367 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1369 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1370 * command buffer's state. Otherwise, we must *reset* its state. In both
1371 * cases we reset it.
1373 * From the Vulkan 1.0 spec:
1375 * If a command buffer is in the executable state and the command buffer
1376 * was allocated from a command pool with the
1377 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1378 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1379 * as if vkResetCommandBuffer had been called with
1380 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1381 * the command buffer in the recording state.
1383 anv_cmd_buffer_reset(cmd_buffer
);
1385 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1387 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1388 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1390 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1392 /* We sometimes store vertex data in the dynamic state buffer for blorp
1393 * operations and our dynamic state stream may re-use data from previous
1394 * command buffers. In order to prevent stale cache data, we flush the VF
1395 * cache. We could do this on every blorp call but that's not really
1396 * needed as all of the data will get written by the CPU prior to the GPU
1397 * executing anything. The chances are fairly high that they will use
1398 * blorp at least once per primary command buffer so it shouldn't be
1401 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1402 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1404 /* We send an "Indirect State Pointers Disable" packet at
1405 * EndCommandBuffer, so all push contant packets are ignored during a
1406 * context restore. Documentation says after that command, we need to
1407 * emit push constants again before any rendering operation. So we
1408 * flag them dirty here to make sure they get emitted.
1410 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1412 VkResult result
= VK_SUCCESS
;
1413 if (cmd_buffer
->usage_flags
&
1414 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1415 assert(pBeginInfo
->pInheritanceInfo
);
1416 cmd_buffer
->state
.pass
=
1417 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1418 cmd_buffer
->state
.subpass
=
1419 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1421 /* This is optional in the inheritance info. */
1422 cmd_buffer
->state
.framebuffer
=
1423 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1425 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1426 cmd_buffer
->state
.pass
, NULL
);
1428 /* Record that HiZ is enabled if we can. */
1429 if (cmd_buffer
->state
.framebuffer
) {
1430 const struct anv_image_view
* const iview
=
1431 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1434 VkImageLayout layout
=
1435 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1437 enum isl_aux_usage aux_usage
=
1438 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1439 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1441 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1445 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1448 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1449 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1450 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1451 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1453 /* If secondary buffer supports conditional rendering
1454 * we should emit commands as if conditional rendering is enabled.
1456 cmd_buffer
->state
.conditional_render_enabled
=
1457 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1464 /* From the PRM, Volume 2a:
1466 * "Indirect State Pointers Disable
1468 * At the completion of the post-sync operation associated with this pipe
1469 * control packet, the indirect state pointers in the hardware are
1470 * considered invalid; the indirect pointers are not saved in the context.
1471 * If any new indirect state commands are executed in the command stream
1472 * while the pipe control is pending, the new indirect state commands are
1475 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1476 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1477 * commands are only considered as Indirect State Pointers. Once ISP is
1478 * issued in a context, SW must initialize by programming push constant
1479 * commands for all the shaders (at least to zero length) before attempting
1480 * any rendering operation for the same context."
1482 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1483 * even though they point to a BO that has been already unreferenced at
1484 * the end of the previous batch buffer. This has been fine so far since
1485 * we are protected by these scratch page (every address not covered by
1486 * a BO should be pointing to the scratch page). But on CNL, it is
1487 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1490 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1491 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1492 * context restore, so the mentioned hang doesn't happen. However,
1493 * software must program push constant commands for all stages prior to
1494 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1496 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1497 * constants have been loaded into the EUs prior to disable the push constants
1498 * so that it doesn't hang a previous 3DPRIMITIVE.
1501 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1503 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1504 pc
.StallAtPixelScoreboard
= true;
1505 pc
.CommandStreamerStallEnable
= true;
1507 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1508 pc
.IndirectStatePointersDisable
= true;
1509 pc
.CommandStreamerStallEnable
= true;
1514 genX(EndCommandBuffer
)(
1515 VkCommandBuffer commandBuffer
)
1517 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1519 if (anv_batch_has_error(&cmd_buffer
->batch
))
1520 return cmd_buffer
->batch
.status
;
1522 /* We want every command buffer to start with the PMA fix in a known state,
1523 * so we disable it at the end of the command buffer.
1525 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1527 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1529 emit_isp_disable(cmd_buffer
);
1531 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1537 genX(CmdExecuteCommands
)(
1538 VkCommandBuffer commandBuffer
,
1539 uint32_t commandBufferCount
,
1540 const VkCommandBuffer
* pCmdBuffers
)
1542 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1544 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1546 if (anv_batch_has_error(&primary
->batch
))
1549 /* The secondary command buffers will assume that the PMA fix is disabled
1550 * when they begin executing. Make sure this is true.
1552 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1554 /* The secondary command buffer doesn't know which textures etc. have been
1555 * flushed prior to their execution. Apply those flushes now.
1557 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1559 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1560 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1562 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1563 assert(!anv_batch_has_error(&secondary
->batch
));
1565 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1566 if (secondary
->state
.conditional_render_enabled
) {
1567 if (!primary
->state
.conditional_render_enabled
) {
1568 /* Secondary buffer is constructed as if it will be executed
1569 * with conditional rendering, we should satisfy this dependency
1570 * regardless of conditional rendering being enabled in primary.
1572 struct gen_mi_builder b
;
1573 gen_mi_builder_init(&b
, &primary
->batch
);
1574 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1575 gen_mi_imm(UINT64_MAX
));
1580 if (secondary
->usage_flags
&
1581 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1582 /* If we're continuing a render pass from the primary, we need to
1583 * copy the surface states for the current subpass into the storage
1584 * we allocated for them in BeginCommandBuffer.
1586 struct anv_bo
*ss_bo
=
1587 primary
->device
->surface_state_pool
.block_pool
.bo
;
1588 struct anv_state src_state
= primary
->state
.render_pass_states
;
1589 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1590 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1592 genX(cmd_buffer_so_memcpy
)(primary
,
1593 (struct anv_address
) {
1595 .offset
= dst_state
.offset
,
1597 (struct anv_address
) {
1599 .offset
= src_state
.offset
,
1601 src_state
.alloc_size
);
1604 anv_cmd_buffer_add_secondary(primary
, secondary
);
1607 /* The secondary may have selected a different pipeline (3D or compute) and
1608 * may have changed the current L3$ configuration. Reset our tracking
1609 * variables to invalid values to ensure that we re-emit these in the case
1610 * where we do any draws or compute dispatches from the primary after the
1611 * secondary has returned.
1613 primary
->state
.current_pipeline
= UINT32_MAX
;
1614 primary
->state
.current_l3_config
= NULL
;
1616 /* Each of the secondary command buffers will use its own state base
1617 * address. We need to re-emit state base address for the primary after
1618 * all of the secondaries are done.
1620 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1623 genX(cmd_buffer_emit_state_base_address
)(primary
);
1626 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1627 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1628 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1631 * Program the hardware to use the specified L3 configuration.
1634 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1635 const struct gen_l3_config
*cfg
)
1638 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1641 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1642 intel_logd("L3 config transition: ");
1643 gen_dump_l3_config(cfg
, stderr
);
1646 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1648 /* According to the hardware docs, the L3 partitioning can only be changed
1649 * while the pipeline is completely drained and the caches are flushed,
1650 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1652 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1653 pc
.DCFlushEnable
= true;
1654 pc
.PostSyncOperation
= NoWrite
;
1655 pc
.CommandStreamerStallEnable
= true;
1658 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1659 * invalidation of the relevant caches. Note that because RO invalidation
1660 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1661 * command is processed by the CS) we cannot combine it with the previous
1662 * stalling flush as the hardware documentation suggests, because that
1663 * would cause the CS to stall on previous rendering *after* RO
1664 * invalidation and wouldn't prevent the RO caches from being polluted by
1665 * concurrent rendering before the stall completes. This intentionally
1666 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1667 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1668 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1669 * already guarantee that there is no concurrent GPGPU kernel execution
1670 * (see SKL HSD 2132585).
1672 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1673 pc
.TextureCacheInvalidationEnable
= true;
1674 pc
.ConstantCacheInvalidationEnable
= true;
1675 pc
.InstructionCacheInvalidateEnable
= true;
1676 pc
.StateCacheInvalidationEnable
= true;
1677 pc
.PostSyncOperation
= NoWrite
;
1680 /* Now send a third stalling flush to make sure that invalidation is
1681 * complete when the L3 configuration registers are modified.
1683 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1684 pc
.DCFlushEnable
= true;
1685 pc
.PostSyncOperation
= NoWrite
;
1686 pc
.CommandStreamerStallEnable
= true;
1691 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1694 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1695 .SLMEnable
= has_slm
,
1697 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1698 * in L3CNTLREG register. The default setting of the bit is not the
1699 * desirable behavior.
1701 .ErrorDetectionBehaviorControl
= true,
1702 .UseFullWays
= true,
1704 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1705 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1706 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1707 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1709 /* Set up the L3 partitioning. */
1710 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1714 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1715 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1716 cfg
->n
[GEN_L3P_ALL
];
1717 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1718 cfg
->n
[GEN_L3P_ALL
];
1719 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1720 cfg
->n
[GEN_L3P_ALL
];
1722 assert(!cfg
->n
[GEN_L3P_ALL
]);
1724 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1725 * the matching space on the remaining banks has to be allocated to a
1726 * client (URB for all validated configurations) set to the
1727 * lower-bandwidth 2-bank address hashing mode.
1729 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1730 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1731 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1733 /* Minimum number of ways that can be allocated to the URB. */
1734 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1735 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1737 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1738 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1739 .ConvertDC_UC
= !has_dc
,
1740 .ConvertIS_UC
= !has_is
,
1741 .ConvertC_UC
= !has_c
,
1742 .ConvertT_UC
= !has_t
);
1744 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1745 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1746 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1748 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1749 .SLMEnable
= has_slm
,
1750 .URBLowBandwidth
= urb_low_bw
,
1751 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1753 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1755 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1756 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1758 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1759 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1760 .ISLowBandwidth
= 0,
1761 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1763 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1764 .TLowBandwidth
= 0);
1766 /* Set up the L3 partitioning. */
1767 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1768 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1769 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1772 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1773 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1774 * them disabled to avoid crashing the system hard.
1776 uint32_t scratch1
, chicken3
;
1777 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1778 .L3AtomicDisable
= !has_dc
);
1779 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1780 .L3AtomicDisableMask
= true,
1781 .L3AtomicDisable
= !has_dc
);
1782 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1783 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1789 cmd_buffer
->state
.current_l3_config
= cfg
;
1793 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1795 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1797 /* Flushes are pipelined while invalidations are handled immediately.
1798 * Therefore, if we're flushing anything then we need to schedule a stall
1799 * before any invalidations can happen.
1801 if (bits
& ANV_PIPE_FLUSH_BITS
)
1802 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1804 /* If we're going to do an invalidate and we have a pending CS stall that
1805 * has yet to be resolved, we do the CS stall now.
1807 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1808 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1809 bits
|= ANV_PIPE_CS_STALL_BIT
;
1810 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1813 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1814 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1815 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1816 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1817 pipe
.RenderTargetCacheFlushEnable
=
1818 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1820 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1821 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1822 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1825 * According to the Broadwell documentation, any PIPE_CONTROL with the
1826 * "Command Streamer Stall" bit set must also have another bit set,
1827 * with five different options:
1829 * - Render Target Cache Flush
1830 * - Depth Cache Flush
1831 * - Stall at Pixel Scoreboard
1832 * - Post-Sync Operation
1836 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1837 * mesa and it seems to work fine. The choice is fairly arbitrary.
1839 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1840 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1841 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1842 pipe
.StallAtPixelScoreboard
= true;
1845 /* If a render target flush was emitted, then we can toggle off the bit
1846 * saying that render target writes are ongoing.
1848 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1849 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1851 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1854 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1855 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1857 * "If the VF Cache Invalidation Enable is set to a 1 in a
1858 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1859 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1860 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1863 * This appears to hang Broadwell, so we restrict it to just gen9.
1865 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1866 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1868 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1869 pipe
.StateCacheInvalidationEnable
=
1870 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1871 pipe
.ConstantCacheInvalidationEnable
=
1872 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1873 pipe
.VFCacheInvalidationEnable
=
1874 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1875 pipe
.TextureCacheInvalidationEnable
=
1876 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1877 pipe
.InstructionCacheInvalidateEnable
=
1878 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1880 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1882 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1883 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1884 * “Write Timestamp”.
1886 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1887 pipe
.PostSyncOperation
= WriteImmediateData
;
1889 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1893 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1896 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1899 void genX(CmdPipelineBarrier
)(
1900 VkCommandBuffer commandBuffer
,
1901 VkPipelineStageFlags srcStageMask
,
1902 VkPipelineStageFlags destStageMask
,
1904 uint32_t memoryBarrierCount
,
1905 const VkMemoryBarrier
* pMemoryBarriers
,
1906 uint32_t bufferMemoryBarrierCount
,
1907 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1908 uint32_t imageMemoryBarrierCount
,
1909 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1911 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1913 /* XXX: Right now, we're really dumb and just flush whatever categories
1914 * the app asks for. One of these days we may make this a bit better
1915 * but right now that's all the hardware allows for in most areas.
1917 VkAccessFlags src_flags
= 0;
1918 VkAccessFlags dst_flags
= 0;
1920 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1921 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1922 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1925 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1926 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1927 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1930 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1931 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1932 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1933 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1934 const VkImageSubresourceRange
*range
=
1935 &pImageMemoryBarriers
[i
].subresourceRange
;
1937 uint32_t base_layer
, layer_count
;
1938 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1940 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1942 base_layer
= range
->baseArrayLayer
;
1943 layer_count
= anv_get_layerCount(image
, range
);
1946 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1947 transition_depth_buffer(cmd_buffer
, image
,
1948 pImageMemoryBarriers
[i
].oldLayout
,
1949 pImageMemoryBarriers
[i
].newLayout
);
1952 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1953 transition_stencil_buffer(cmd_buffer
, image
,
1954 range
->baseMipLevel
,
1955 anv_get_levelCount(image
, range
),
1956 base_layer
, layer_count
,
1957 pImageMemoryBarriers
[i
].oldLayout
,
1958 pImageMemoryBarriers
[i
].newLayout
);
1961 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1962 VkImageAspectFlags color_aspects
=
1963 anv_image_expand_aspects(image
, range
->aspectMask
);
1964 uint32_t aspect_bit
;
1965 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1966 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1967 range
->baseMipLevel
,
1968 anv_get_levelCount(image
, range
),
1969 base_layer
, layer_count
,
1970 pImageMemoryBarriers
[i
].oldLayout
,
1971 pImageMemoryBarriers
[i
].newLayout
);
1976 cmd_buffer
->state
.pending_pipe_bits
|=
1977 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1978 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1982 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1984 VkShaderStageFlags stages
=
1985 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1987 /* In order to avoid thrash, we assume that vertex and fragment stages
1988 * always exist. In the rare case where one is missing *and* the other
1989 * uses push concstants, this may be suboptimal. However, avoiding stalls
1990 * seems more important.
1992 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1994 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1998 const unsigned push_constant_kb
= 32;
1999 #elif GEN_IS_HASWELL
2000 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2002 const unsigned push_constant_kb
= 16;
2005 const unsigned num_stages
=
2006 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2007 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2009 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2010 * units of 2KB. Incidentally, these are the same platforms that have
2011 * 32KB worth of push constant space.
2013 if (push_constant_kb
== 32)
2014 size_per_stage
&= ~1u;
2016 uint32_t kb_used
= 0;
2017 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2018 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2019 anv_batch_emit(&cmd_buffer
->batch
,
2020 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2021 alloc
._3DCommandSubOpcode
= 18 + i
;
2022 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2023 alloc
.ConstantBufferSize
= push_size
;
2025 kb_used
+= push_size
;
2028 anv_batch_emit(&cmd_buffer
->batch
,
2029 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2030 alloc
.ConstantBufferOffset
= kb_used
;
2031 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2034 cmd_buffer
->state
.push_constant_stages
= stages
;
2036 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2038 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2039 * the next 3DPRIMITIVE command after programming the
2040 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2042 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2043 * pipeline setup, we need to dirty push constants.
2045 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2048 static const struct anv_descriptor
*
2049 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2050 const struct anv_pipeline_binding
*binding
)
2052 assert(binding
->set
< MAX_SETS
);
2053 const struct anv_descriptor_set
*set
=
2054 pipe_state
->descriptors
[binding
->set
];
2055 const uint32_t offset
=
2056 set
->layout
->binding
[binding
->binding
].descriptor_index
;
2057 return &set
->descriptors
[offset
+ binding
->index
];
2061 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2062 const struct anv_pipeline_binding
*binding
)
2064 assert(binding
->set
< MAX_SETS
);
2065 const struct anv_descriptor_set
*set
=
2066 pipe_state
->descriptors
[binding
->set
];
2068 uint32_t dynamic_offset_idx
=
2069 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
2070 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
2073 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
2076 static struct anv_address
2077 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2078 struct anv_descriptor_set
*set
)
2081 /* This is a normal descriptor set */
2082 return (struct anv_address
) {
2083 .bo
= &set
->pool
->bo
,
2084 .offset
= set
->desc_mem
.offset
,
2087 /* This is a push descriptor set. We have to flag it as used on the GPU
2088 * so that the next time we push descriptors, we grab a new memory.
2090 struct anv_push_descriptor_set
*push_set
=
2091 (struct anv_push_descriptor_set
*)set
;
2092 push_set
->set_used_on_gpu
= true;
2094 return (struct anv_address
) {
2095 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2096 .offset
= set
->desc_mem
.offset
,
2102 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2103 gl_shader_stage stage
,
2104 struct anv_state
*bt_state
)
2106 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2107 struct anv_cmd_pipeline_state
*pipe_state
;
2108 struct anv_pipeline
*pipeline
;
2109 uint32_t state_offset
;
2112 case MESA_SHADER_COMPUTE
:
2113 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2116 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2119 pipeline
= pipe_state
->pipeline
;
2121 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2122 *bt_state
= (struct anv_state
) { 0, };
2126 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2127 if (map
->surface_count
== 0) {
2128 *bt_state
= (struct anv_state
) { 0, };
2132 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2135 uint32_t *bt_map
= bt_state
->map
;
2137 if (bt_state
->map
== NULL
)
2138 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2140 /* We only need to emit relocs if we're not using softpin. If we are using
2141 * softpin then we always keep all user-allocated memory objects resident.
2143 const bool need_client_mem_relocs
=
2144 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
;
2146 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2147 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2149 struct anv_state surface_state
;
2151 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2152 /* Color attachment binding */
2153 assert(stage
== MESA_SHADER_FRAGMENT
);
2154 assert(binding
->binding
== 0);
2155 if (binding
->index
< subpass
->color_count
) {
2156 const unsigned att
=
2157 subpass
->color_attachments
[binding
->index
].attachment
;
2159 /* From the Vulkan 1.0.46 spec:
2161 * "If any color or depth/stencil attachments are
2162 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2165 if (att
== VK_ATTACHMENT_UNUSED
) {
2166 surface_state
= cmd_buffer
->state
.null_surface_state
;
2168 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2171 surface_state
= cmd_buffer
->state
.null_surface_state
;
2174 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2176 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2177 struct anv_state surface_state
=
2178 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2180 struct anv_address constant_data
= {
2181 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2182 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2184 unsigned constant_data_size
=
2185 pipeline
->shaders
[stage
]->constant_data_size
;
2187 const enum isl_format format
=
2188 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2189 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2190 surface_state
, format
,
2191 constant_data
, constant_data_size
, 1);
2193 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2194 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2196 } else if (binding
->set
== ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
) {
2197 /* This is always the first binding for compute shaders */
2198 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2199 if (!get_cs_prog_data(pipeline
)->uses_num_work_groups
)
2202 struct anv_state surface_state
=
2203 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2205 const enum isl_format format
=
2206 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2207 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2209 cmd_buffer
->state
.compute
.num_workgroups
,
2211 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2212 if (need_client_mem_relocs
) {
2213 add_surface_reloc(cmd_buffer
, surface_state
,
2214 cmd_buffer
->state
.compute
.num_workgroups
);
2217 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2218 /* This is a descriptor set buffer so the set index is actually
2219 * given by binding->binding. (Yes, that's confusing.)
2221 struct anv_descriptor_set
*set
=
2222 pipe_state
->descriptors
[binding
->binding
];
2223 assert(set
->desc_mem
.alloc_size
);
2224 assert(set
->desc_surface_state
.alloc_size
);
2225 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2226 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2227 anv_descriptor_set_address(cmd_buffer
, set
));
2231 const struct anv_descriptor
*desc
=
2232 anv_descriptor_for_binding(pipe_state
, binding
);
2234 switch (desc
->type
) {
2235 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2236 /* Nothing for us to do here */
2239 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2240 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2241 struct anv_surface_state sstate
=
2242 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2243 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2244 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2245 surface_state
= sstate
.state
;
2246 assert(surface_state
.alloc_size
);
2247 if (need_client_mem_relocs
)
2248 add_surface_state_relocs(cmd_buffer
, sstate
);
2251 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2252 assert(stage
== MESA_SHADER_FRAGMENT
);
2253 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2254 /* For depth and stencil input attachments, we treat it like any
2255 * old texture that a user may have bound.
2257 struct anv_surface_state sstate
=
2258 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2259 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2260 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2261 surface_state
= sstate
.state
;
2262 assert(surface_state
.alloc_size
);
2263 if (need_client_mem_relocs
)
2264 add_surface_state_relocs(cmd_buffer
, sstate
);
2266 /* For color input attachments, we create the surface state at
2267 * vkBeginRenderPass time so that we can include aux and clear
2268 * color information.
2270 assert(binding
->input_attachment_index
< subpass
->input_count
);
2271 const unsigned subpass_att
= binding
->input_attachment_index
;
2272 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2273 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2277 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2278 struct anv_surface_state sstate
= (binding
->write_only
)
2279 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2280 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2281 surface_state
= sstate
.state
;
2282 assert(surface_state
.alloc_size
);
2283 if (need_client_mem_relocs
)
2284 add_surface_state_relocs(cmd_buffer
, sstate
);
2288 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2289 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2290 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2291 surface_state
= desc
->buffer_view
->surface_state
;
2292 assert(surface_state
.alloc_size
);
2293 if (need_client_mem_relocs
) {
2294 add_surface_reloc(cmd_buffer
, surface_state
,
2295 desc
->buffer_view
->address
);
2299 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2300 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2301 /* Compute the offset within the buffer */
2302 uint32_t dynamic_offset
=
2303 dynamic_offset_for_binding(pipe_state
, binding
);
2304 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2305 /* Clamp to the buffer size */
2306 offset
= MIN2(offset
, desc
->buffer
->size
);
2307 /* Clamp the range to the buffer size */
2308 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2310 struct anv_address address
=
2311 anv_address_add(desc
->buffer
->address
, offset
);
2314 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2315 enum isl_format format
=
2316 anv_isl_format_for_descriptor_type(desc
->type
);
2318 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2319 format
, address
, range
, 1);
2320 if (need_client_mem_relocs
)
2321 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2325 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2326 surface_state
= (binding
->write_only
)
2327 ? desc
->buffer_view
->writeonly_storage_surface_state
2328 : desc
->buffer_view
->storage_surface_state
;
2329 assert(surface_state
.alloc_size
);
2330 if (need_client_mem_relocs
) {
2331 add_surface_reloc(cmd_buffer
, surface_state
,
2332 desc
->buffer_view
->address
);
2337 assert(!"Invalid descriptor type");
2341 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2345 /* The PIPE_CONTROL command description says:
2347 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2348 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2349 * Target Cache Flush by enabling this bit. When render target flush
2350 * is set due to new association of BTI, PS Scoreboard Stall bit must
2351 * be set in this packet."
2353 * FINISHME: Currently we shuffle around the surface states in the binding
2354 * table based on if they are getting used or not. So, we've to do below
2355 * pipe control flush for every binding table upload. Make changes so
2356 * that we do it only when we modify render target surface states.
2358 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2359 pc
.RenderTargetCacheFlushEnable
= true;
2360 pc
.StallAtPixelScoreboard
= true;
2368 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2369 gl_shader_stage stage
,
2370 struct anv_state
*state
)
2372 struct anv_cmd_pipeline_state
*pipe_state
=
2373 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2374 &cmd_buffer
->state
.gfx
.base
;
2375 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2377 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2378 *state
= (struct anv_state
) { 0, };
2382 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2383 if (map
->sampler_count
== 0) {
2384 *state
= (struct anv_state
) { 0, };
2388 uint32_t size
= map
->sampler_count
* 16;
2389 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2391 if (state
->map
== NULL
)
2392 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2394 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2395 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2396 const struct anv_descriptor
*desc
=
2397 anv_descriptor_for_binding(pipe_state
, binding
);
2399 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2400 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2403 struct anv_sampler
*sampler
= desc
->sampler
;
2405 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2406 * happens to be zero.
2408 if (sampler
== NULL
)
2411 memcpy(state
->map
+ (s
* 16),
2412 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2419 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2421 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2423 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2424 pipeline
->active_stages
;
2426 VkResult result
= VK_SUCCESS
;
2427 anv_foreach_stage(s
, dirty
) {
2428 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2429 if (result
!= VK_SUCCESS
)
2431 result
= emit_binding_table(cmd_buffer
, s
,
2432 &cmd_buffer
->state
.binding_tables
[s
]);
2433 if (result
!= VK_SUCCESS
)
2437 if (result
!= VK_SUCCESS
) {
2438 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2440 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2441 if (result
!= VK_SUCCESS
)
2444 /* Re-emit state base addresses so we get the new surface state base
2445 * address before we start emitting binding tables etc.
2447 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2449 /* Re-emit all active binding tables */
2450 dirty
|= pipeline
->active_stages
;
2451 anv_foreach_stage(s
, dirty
) {
2452 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2453 if (result
!= VK_SUCCESS
) {
2454 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2457 result
= emit_binding_table(cmd_buffer
, s
,
2458 &cmd_buffer
->state
.binding_tables
[s
]);
2459 if (result
!= VK_SUCCESS
) {
2460 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2466 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2472 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2475 static const uint32_t sampler_state_opcodes
[] = {
2476 [MESA_SHADER_VERTEX
] = 43,
2477 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2478 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2479 [MESA_SHADER_GEOMETRY
] = 46,
2480 [MESA_SHADER_FRAGMENT
] = 47,
2481 [MESA_SHADER_COMPUTE
] = 0,
2484 static const uint32_t binding_table_opcodes
[] = {
2485 [MESA_SHADER_VERTEX
] = 38,
2486 [MESA_SHADER_TESS_CTRL
] = 39,
2487 [MESA_SHADER_TESS_EVAL
] = 40,
2488 [MESA_SHADER_GEOMETRY
] = 41,
2489 [MESA_SHADER_FRAGMENT
] = 42,
2490 [MESA_SHADER_COMPUTE
] = 0,
2493 anv_foreach_stage(s
, stages
) {
2494 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2495 assert(binding_table_opcodes
[s
] > 0);
2497 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2498 anv_batch_emit(&cmd_buffer
->batch
,
2499 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2500 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2501 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2505 /* Always emit binding table pointers if we're asked to, since on SKL
2506 * this is what flushes push constants. */
2507 anv_batch_emit(&cmd_buffer
->batch
,
2508 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2509 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2510 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2516 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2517 VkShaderStageFlags dirty_stages
)
2519 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2520 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2522 static const uint32_t push_constant_opcodes
[] = {
2523 [MESA_SHADER_VERTEX
] = 21,
2524 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2525 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2526 [MESA_SHADER_GEOMETRY
] = 22,
2527 [MESA_SHADER_FRAGMENT
] = 23,
2528 [MESA_SHADER_COMPUTE
] = 0,
2531 VkShaderStageFlags flushed
= 0;
2533 anv_foreach_stage(stage
, dirty_stages
) {
2534 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2535 assert(push_constant_opcodes
[stage
] > 0);
2537 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2538 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2540 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2541 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2542 const struct brw_stage_prog_data
*prog_data
=
2543 pipeline
->shaders
[stage
]->prog_data
;
2544 const struct anv_pipeline_bind_map
*bind_map
=
2545 &pipeline
->shaders
[stage
]->bind_map
;
2547 /* The Skylake PRM contains the following restriction:
2549 * "The driver must ensure The following case does not occur
2550 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2551 * buffer 3 read length equal to zero committed followed by a
2552 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2555 * To avoid this, we program the buffers in the highest slots.
2556 * This way, slot 0 is only used if slot 3 is also used.
2560 for (int i
= 3; i
>= 0; i
--) {
2561 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2562 if (range
->length
== 0)
2565 const unsigned surface
=
2566 prog_data
->binding_table
.ubo_start
+ range
->block
;
2568 assert(surface
<= bind_map
->surface_count
);
2569 const struct anv_pipeline_binding
*binding
=
2570 &bind_map
->surface_to_descriptor
[surface
];
2572 struct anv_address read_addr
;
2574 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2575 struct anv_address constant_data
= {
2576 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2577 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2579 unsigned constant_data_size
=
2580 pipeline
->shaders
[stage
]->constant_data_size
;
2582 read_len
= MIN2(range
->length
,
2583 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2584 read_addr
= anv_address_add(constant_data
,
2586 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2587 /* This is a descriptor set buffer so the set index is
2588 * actually given by binding->binding. (Yes, that's
2591 struct anv_descriptor_set
*set
=
2592 gfx_state
->base
.descriptors
[binding
->binding
];
2593 struct anv_address desc_buffer_addr
=
2594 anv_descriptor_set_address(cmd_buffer
, set
);
2595 const unsigned desc_buffer_size
= set
->desc_mem
.alloc_size
;
2597 read_len
= MIN2(range
->length
,
2598 DIV_ROUND_UP(desc_buffer_size
, 32) - range
->start
);
2599 read_addr
= anv_address_add(desc_buffer_addr
,
2602 const struct anv_descriptor
*desc
=
2603 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2605 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2606 read_len
= MIN2(range
->length
,
2607 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2608 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2611 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2613 uint32_t dynamic_offset
=
2614 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2615 uint32_t buf_offset
=
2616 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2617 uint32_t buf_range
=
2618 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2620 read_len
= MIN2(range
->length
,
2621 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2622 read_addr
= anv_address_add(desc
->buffer
->address
,
2623 buf_offset
+ range
->start
* 32);
2628 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2629 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2634 struct anv_state state
=
2635 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2637 if (state
.alloc_size
> 0) {
2638 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2639 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2640 .offset
= state
.offset
,
2642 c
.ConstantBody
.ReadLength
[n
] =
2643 DIV_ROUND_UP(state
.alloc_size
, 32);
2646 /* For Ivy Bridge, the push constants packets have a different
2647 * rule that would require us to iterate in the other direction
2648 * and possibly mess around with dynamic state base address.
2649 * Don't bother; just emit regular push constants at n = 0.
2651 struct anv_state state
=
2652 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2654 if (state
.alloc_size
> 0) {
2655 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2656 c
.ConstantBody
.ReadLength
[0] =
2657 DIV_ROUND_UP(state
.alloc_size
, 32);
2663 flushed
|= mesa_to_vk_shader_stage(stage
);
2666 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2670 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2672 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2675 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2676 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2677 vb_emit
|= pipeline
->vb_used
;
2679 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2681 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2683 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2686 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2687 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2689 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2690 GENX(3DSTATE_VERTEX_BUFFERS
));
2692 for_each_bit(vb
, vb_emit
) {
2693 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2694 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2696 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2697 .VertexBufferIndex
= vb
,
2699 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2701 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2702 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2705 .AddressModifyEnable
= true,
2706 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2707 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2710 .BufferSize
= buffer
->size
- offset
2712 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2716 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2721 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2724 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2725 /* We don't need any per-buffer dirty tracking because you're not
2726 * allowed to bind different XFB buffers while XFB is enabled.
2728 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2729 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2730 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2731 sob
.SOBufferIndex
= idx
;
2733 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2734 sob
.SOBufferEnable
= true;
2735 sob
.MOCS
= cmd_buffer
->device
->default_mocs
,
2736 sob
.StreamOffsetWriteEnable
= false;
2737 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2739 /* Size is in DWords - 1 */
2740 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2745 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2747 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2751 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2752 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2754 /* The exact descriptor layout is pulled from the pipeline, so we need
2755 * to re-emit binding tables on every pipeline change.
2757 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2759 /* If the pipeline changed, we may need to re-allocate push constant
2762 cmd_buffer_alloc_push_constants(cmd_buffer
);
2766 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2767 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2768 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2770 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2771 * stall needs to be sent just prior to any 3DSTATE_VS,
2772 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2773 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2774 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2775 * PIPE_CONTROL needs to be sent before any combination of VS
2776 * associated 3DSTATE."
2778 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2779 pc
.DepthStallEnable
= true;
2780 pc
.PostSyncOperation
= WriteImmediateData
;
2782 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2787 /* Render targets live in the same binding table as fragment descriptors */
2788 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2789 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2791 /* We emit the binding tables and sampler tables first, then emit push
2792 * constants and then finally emit binding table and sampler table
2793 * pointers. It has to happen in this order, since emitting the binding
2794 * tables may change the push constants (in case of storage images). After
2795 * emitting push constants, on SKL+ we have to emit the corresponding
2796 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2799 if (cmd_buffer
->state
.descriptors_dirty
)
2800 dirty
= flush_descriptor_sets(cmd_buffer
);
2802 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2803 /* Because we're pushing UBOs, we have to push whenever either
2804 * descriptors or push constants is dirty.
2806 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2807 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2808 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2812 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2814 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2815 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2817 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2818 ANV_CMD_DIRTY_PIPELINE
)) {
2819 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2820 pipeline
->depth_clamp_enable
);
2823 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2824 ANV_CMD_DIRTY_RENDER_TARGETS
))
2825 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2827 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2829 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2833 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2834 struct anv_address addr
,
2835 uint32_t size
, uint32_t index
)
2837 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2838 GENX(3DSTATE_VERTEX_BUFFERS
));
2840 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2841 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2842 .VertexBufferIndex
= index
,
2843 .AddressModifyEnable
= true,
2845 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2847 .BufferStartingAddress
= addr
,
2850 .BufferStartingAddress
= addr
,
2851 .EndAddress
= anv_address_add(addr
, size
),
2857 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2858 struct anv_address addr
)
2860 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2864 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2865 uint32_t base_vertex
, uint32_t base_instance
)
2867 struct anv_state id_state
=
2868 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2870 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2871 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2873 struct anv_address addr
= {
2874 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2875 .offset
= id_state
.offset
,
2878 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2882 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2884 struct anv_state state
=
2885 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2887 ((uint32_t *)state
.map
)[0] = draw_index
;
2889 struct anv_address addr
= {
2890 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2891 .offset
= state
.offset
,
2894 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2898 VkCommandBuffer commandBuffer
,
2899 uint32_t vertexCount
,
2900 uint32_t instanceCount
,
2901 uint32_t firstVertex
,
2902 uint32_t firstInstance
)
2904 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2905 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2906 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2908 if (anv_batch_has_error(&cmd_buffer
->batch
))
2911 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2913 if (cmd_buffer
->state
.conditional_render_enabled
)
2914 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2916 if (vs_prog_data
->uses_firstvertex
||
2917 vs_prog_data
->uses_baseinstance
)
2918 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2919 if (vs_prog_data
->uses_drawid
)
2920 emit_draw_index(cmd_buffer
, 0);
2922 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2923 * different views. We need to multiply instanceCount by the view count.
2925 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2927 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2928 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2929 prim
.VertexAccessType
= SEQUENTIAL
;
2930 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2931 prim
.VertexCountPerInstance
= vertexCount
;
2932 prim
.StartVertexLocation
= firstVertex
;
2933 prim
.InstanceCount
= instanceCount
;
2934 prim
.StartInstanceLocation
= firstInstance
;
2935 prim
.BaseVertexLocation
= 0;
2939 void genX(CmdDrawIndexed
)(
2940 VkCommandBuffer commandBuffer
,
2941 uint32_t indexCount
,
2942 uint32_t instanceCount
,
2943 uint32_t firstIndex
,
2944 int32_t vertexOffset
,
2945 uint32_t firstInstance
)
2947 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2948 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2949 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2951 if (anv_batch_has_error(&cmd_buffer
->batch
))
2954 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2956 if (cmd_buffer
->state
.conditional_render_enabled
)
2957 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2959 if (vs_prog_data
->uses_firstvertex
||
2960 vs_prog_data
->uses_baseinstance
)
2961 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2962 if (vs_prog_data
->uses_drawid
)
2963 emit_draw_index(cmd_buffer
, 0);
2965 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2966 * different views. We need to multiply instanceCount by the view count.
2968 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2970 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2971 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2972 prim
.VertexAccessType
= RANDOM
;
2973 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2974 prim
.VertexCountPerInstance
= indexCount
;
2975 prim
.StartVertexLocation
= firstIndex
;
2976 prim
.InstanceCount
= instanceCount
;
2977 prim
.StartInstanceLocation
= firstInstance
;
2978 prim
.BaseVertexLocation
= vertexOffset
;
2982 /* Auto-Draw / Indirect Registers */
2983 #define GEN7_3DPRIM_END_OFFSET 0x2420
2984 #define GEN7_3DPRIM_START_VERTEX 0x2430
2985 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2986 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2987 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2988 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2990 void genX(CmdDrawIndirectByteCountEXT
)(
2991 VkCommandBuffer commandBuffer
,
2992 uint32_t instanceCount
,
2993 uint32_t firstInstance
,
2994 VkBuffer counterBuffer
,
2995 VkDeviceSize counterBufferOffset
,
2996 uint32_t counterOffset
,
2997 uint32_t vertexStride
)
2999 #if GEN_IS_HASWELL || GEN_GEN >= 8
3000 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3001 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3002 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3003 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3005 /* firstVertex is always zero for this draw function */
3006 const uint32_t firstVertex
= 0;
3008 if (anv_batch_has_error(&cmd_buffer
->batch
))
3011 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3013 if (vs_prog_data
->uses_firstvertex
||
3014 vs_prog_data
->uses_baseinstance
)
3015 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3016 if (vs_prog_data
->uses_drawid
)
3017 emit_draw_index(cmd_buffer
, 0);
3019 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3020 * different views. We need to multiply instanceCount by the view count.
3022 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3024 struct gen_mi_builder b
;
3025 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3026 struct gen_mi_value count
=
3027 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3028 counterBufferOffset
));
3030 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3031 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3032 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3034 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3035 gen_mi_imm(firstVertex
));
3036 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3037 gen_mi_imm(instanceCount
));
3038 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3039 gen_mi_imm(firstInstance
));
3040 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3042 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3043 prim
.IndirectParameterEnable
= true;
3044 prim
.VertexAccessType
= SEQUENTIAL
;
3045 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3047 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3051 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3052 struct anv_address addr
,
3055 struct gen_mi_builder b
;
3056 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3058 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3059 gen_mi_mem32(anv_address_add(addr
, 0)));
3061 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3062 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3063 if (view_count
> 1) {
3064 #if GEN_IS_HASWELL || GEN_GEN >= 8
3065 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3067 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3068 "MI_MATH is not supported on Ivy Bridge");
3071 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3073 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3074 gen_mi_mem32(anv_address_add(addr
, 8)));
3077 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3078 gen_mi_mem32(anv_address_add(addr
, 12)));
3079 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3080 gen_mi_mem32(anv_address_add(addr
, 16)));
3082 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3083 gen_mi_mem32(anv_address_add(addr
, 12)));
3084 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3088 void genX(CmdDrawIndirect
)(
3089 VkCommandBuffer commandBuffer
,
3091 VkDeviceSize offset
,
3095 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3096 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3097 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3098 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3100 if (anv_batch_has_error(&cmd_buffer
->batch
))
3103 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3105 if (cmd_buffer
->state
.conditional_render_enabled
)
3106 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3108 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3109 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3111 if (vs_prog_data
->uses_firstvertex
||
3112 vs_prog_data
->uses_baseinstance
)
3113 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3114 if (vs_prog_data
->uses_drawid
)
3115 emit_draw_index(cmd_buffer
, i
);
3117 load_indirect_parameters(cmd_buffer
, draw
, false);
3119 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3120 prim
.IndirectParameterEnable
= true;
3121 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3122 prim
.VertexAccessType
= SEQUENTIAL
;
3123 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3130 void genX(CmdDrawIndexedIndirect
)(
3131 VkCommandBuffer commandBuffer
,
3133 VkDeviceSize offset
,
3137 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3138 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3139 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3140 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3142 if (anv_batch_has_error(&cmd_buffer
->batch
))
3145 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3147 if (cmd_buffer
->state
.conditional_render_enabled
)
3148 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3150 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3151 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3153 /* TODO: We need to stomp base vertex to 0 somehow */
3154 if (vs_prog_data
->uses_firstvertex
||
3155 vs_prog_data
->uses_baseinstance
)
3156 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3157 if (vs_prog_data
->uses_drawid
)
3158 emit_draw_index(cmd_buffer
, i
);
3160 load_indirect_parameters(cmd_buffer
, draw
, true);
3162 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3163 prim
.IndirectParameterEnable
= true;
3164 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3165 prim
.VertexAccessType
= RANDOM
;
3166 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3173 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3176 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3177 struct anv_address count_address
,
3178 const bool conditional_render_enabled
)
3180 struct gen_mi_builder b
;
3181 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3183 if (conditional_render_enabled
) {
3184 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3185 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3186 gen_mi_mem32(count_address
));
3189 /* Upload the current draw count from the draw parameters buffer to
3190 * MI_PREDICATE_SRC0.
3192 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3193 gen_mi_mem32(count_address
));
3195 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3200 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3201 uint32_t draw_index
)
3203 struct gen_mi_builder b
;
3204 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3206 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3207 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3209 if (draw_index
== 0) {
3210 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3211 mip
.LoadOperation
= LOAD_LOADINV
;
3212 mip
.CombineOperation
= COMBINE_SET
;
3213 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3216 /* While draw_index < draw_count the predicate's result will be
3217 * (draw_index == draw_count) ^ TRUE = TRUE
3218 * When draw_index == draw_count the result is
3219 * (TRUE) ^ TRUE = FALSE
3220 * After this all results will be:
3221 * (FALSE) ^ FALSE = FALSE
3223 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3224 mip
.LoadOperation
= LOAD_LOAD
;
3225 mip
.CombineOperation
= COMBINE_XOR
;
3226 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3231 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3233 emit_draw_count_predicate_with_conditional_render(
3234 struct anv_cmd_buffer
*cmd_buffer
,
3235 uint32_t draw_index
)
3237 struct gen_mi_builder b
;
3238 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3240 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3241 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3242 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3245 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3247 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3248 * so we emit MI_PREDICATE to set it.
3251 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3252 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3254 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3255 mip
.LoadOperation
= LOAD_LOADINV
;
3256 mip
.CombineOperation
= COMBINE_SET
;
3257 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3263 void genX(CmdDrawIndirectCountKHR
)(
3264 VkCommandBuffer commandBuffer
,
3266 VkDeviceSize offset
,
3267 VkBuffer _countBuffer
,
3268 VkDeviceSize countBufferOffset
,
3269 uint32_t maxDrawCount
,
3272 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3273 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3274 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3275 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3276 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3277 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3279 if (anv_batch_has_error(&cmd_buffer
->batch
))
3282 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3284 struct anv_address count_address
=
3285 anv_address_add(count_buffer
->address
, countBufferOffset
);
3287 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3288 cmd_state
->conditional_render_enabled
);
3290 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3291 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3293 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3294 if (cmd_state
->conditional_render_enabled
) {
3295 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3297 emit_draw_count_predicate(cmd_buffer
, i
);
3300 emit_draw_count_predicate(cmd_buffer
, i
);
3303 if (vs_prog_data
->uses_firstvertex
||
3304 vs_prog_data
->uses_baseinstance
)
3305 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3306 if (vs_prog_data
->uses_drawid
)
3307 emit_draw_index(cmd_buffer
, i
);
3309 load_indirect_parameters(cmd_buffer
, draw
, false);
3311 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3312 prim
.IndirectParameterEnable
= true;
3313 prim
.PredicateEnable
= true;
3314 prim
.VertexAccessType
= SEQUENTIAL
;
3315 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3322 void genX(CmdDrawIndexedIndirectCountKHR
)(
3323 VkCommandBuffer commandBuffer
,
3325 VkDeviceSize offset
,
3326 VkBuffer _countBuffer
,
3327 VkDeviceSize countBufferOffset
,
3328 uint32_t maxDrawCount
,
3331 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3332 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3333 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3334 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3335 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3336 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3338 if (anv_batch_has_error(&cmd_buffer
->batch
))
3341 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3343 struct anv_address count_address
=
3344 anv_address_add(count_buffer
->address
, countBufferOffset
);
3346 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3347 cmd_state
->conditional_render_enabled
);
3349 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3350 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3352 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3353 if (cmd_state
->conditional_render_enabled
) {
3354 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3356 emit_draw_count_predicate(cmd_buffer
, i
);
3359 emit_draw_count_predicate(cmd_buffer
, i
);
3362 /* TODO: We need to stomp base vertex to 0 somehow */
3363 if (vs_prog_data
->uses_firstvertex
||
3364 vs_prog_data
->uses_baseinstance
)
3365 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3366 if (vs_prog_data
->uses_drawid
)
3367 emit_draw_index(cmd_buffer
, i
);
3369 load_indirect_parameters(cmd_buffer
, draw
, true);
3371 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3372 prim
.IndirectParameterEnable
= true;
3373 prim
.PredicateEnable
= true;
3374 prim
.VertexAccessType
= RANDOM
;
3375 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3382 void genX(CmdBeginTransformFeedbackEXT
)(
3383 VkCommandBuffer commandBuffer
,
3384 uint32_t firstCounterBuffer
,
3385 uint32_t counterBufferCount
,
3386 const VkBuffer
* pCounterBuffers
,
3387 const VkDeviceSize
* pCounterBufferOffsets
)
3389 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3391 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3392 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3393 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3395 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3397 * "Ssoftware must ensure that no HW stream output operations can be in
3398 * process or otherwise pending at the point that the MI_LOAD/STORE
3399 * commands are processed. This will likely require a pipeline flush."
3401 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3402 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3404 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3405 /* If we have a counter buffer, this is a resume so we need to load the
3406 * value into the streamout offset register. Otherwise, this is a begin
3407 * and we need to reset it to zero.
3409 if (pCounterBuffers
&&
3410 idx
>= firstCounterBuffer
&&
3411 idx
- firstCounterBuffer
< counterBufferCount
&&
3412 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3413 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3414 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3415 uint64_t offset
= pCounterBufferOffsets
?
3416 pCounterBufferOffsets
[cb_idx
] : 0;
3418 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3419 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3420 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3424 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3425 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3431 cmd_buffer
->state
.xfb_enabled
= true;
3432 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3435 void genX(CmdEndTransformFeedbackEXT
)(
3436 VkCommandBuffer commandBuffer
,
3437 uint32_t firstCounterBuffer
,
3438 uint32_t counterBufferCount
,
3439 const VkBuffer
* pCounterBuffers
,
3440 const VkDeviceSize
* pCounterBufferOffsets
)
3442 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3444 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3445 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3446 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3448 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3450 * "Ssoftware must ensure that no HW stream output operations can be in
3451 * process or otherwise pending at the point that the MI_LOAD/STORE
3452 * commands are processed. This will likely require a pipeline flush."
3454 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3455 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3457 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3458 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3460 /* If we have a counter buffer, this is a resume so we need to load the
3461 * value into the streamout offset register. Otherwise, this is a begin
3462 * and we need to reset it to zero.
3464 if (pCounterBuffers
&&
3465 cb_idx
< counterBufferCount
&&
3466 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3467 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3468 uint64_t offset
= pCounterBufferOffsets
?
3469 pCounterBufferOffsets
[cb_idx
] : 0;
3471 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3472 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3474 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3479 cmd_buffer
->state
.xfb_enabled
= false;
3480 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3484 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3486 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3487 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3490 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3491 if (result
!= VK_SUCCESS
) {
3492 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3494 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3495 if (result
!= VK_SUCCESS
)
3498 /* Re-emit state base addresses so we get the new surface state base
3499 * address before we start emitting binding tables etc.
3501 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3503 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3504 if (result
!= VK_SUCCESS
) {
3505 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3510 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3511 if (result
!= VK_SUCCESS
) {
3512 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3516 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3517 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3518 .BindingTablePointer
= surfaces
.offset
,
3519 .SamplerStatePointer
= samplers
.offset
,
3521 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3523 struct anv_state state
=
3524 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3525 pipeline
->interface_descriptor_data
,
3526 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3529 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3530 anv_batch_emit(&cmd_buffer
->batch
,
3531 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3532 mid
.InterfaceDescriptorTotalLength
= size
;
3533 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3540 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3542 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3545 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3547 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3549 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3551 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3552 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3554 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3555 * the only bits that are changed are scoreboard related: Scoreboard
3556 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3557 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3560 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3561 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3563 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3566 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3567 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3568 /* FIXME: figure out descriptors for gen7 */
3569 result
= flush_compute_descriptor_set(cmd_buffer
);
3570 if (result
!= VK_SUCCESS
)
3573 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3576 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3577 struct anv_state push_state
=
3578 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3580 if (push_state
.alloc_size
) {
3581 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3582 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3583 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3587 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3590 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3592 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3598 verify_cmd_parser(const struct anv_device
*device
,
3599 int required_version
,
3600 const char *function
)
3602 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3603 return vk_errorf(device
->instance
, device
->instance
,
3604 VK_ERROR_FEATURE_NOT_PRESENT
,
3605 "cmd parser version %d is required for %s",
3606 required_version
, function
);
3615 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3616 uint32_t baseGroupX
,
3617 uint32_t baseGroupY
,
3618 uint32_t baseGroupZ
)
3620 if (anv_batch_has_error(&cmd_buffer
->batch
))
3623 struct anv_push_constants
*push
=
3624 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3625 if (push
->base_work_group_id
[0] != baseGroupX
||
3626 push
->base_work_group_id
[1] != baseGroupY
||
3627 push
->base_work_group_id
[2] != baseGroupZ
) {
3628 push
->base_work_group_id
[0] = baseGroupX
;
3629 push
->base_work_group_id
[1] = baseGroupY
;
3630 push
->base_work_group_id
[2] = baseGroupZ
;
3632 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3636 void genX(CmdDispatch
)(
3637 VkCommandBuffer commandBuffer
,
3642 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3645 void genX(CmdDispatchBase
)(
3646 VkCommandBuffer commandBuffer
,
3647 uint32_t baseGroupX
,
3648 uint32_t baseGroupY
,
3649 uint32_t baseGroupZ
,
3650 uint32_t groupCountX
,
3651 uint32_t groupCountY
,
3652 uint32_t groupCountZ
)
3654 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3655 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3656 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3658 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3659 baseGroupY
, baseGroupZ
);
3661 if (anv_batch_has_error(&cmd_buffer
->batch
))
3664 if (prog_data
->uses_num_work_groups
) {
3665 struct anv_state state
=
3666 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3667 uint32_t *sizes
= state
.map
;
3668 sizes
[0] = groupCountX
;
3669 sizes
[1] = groupCountY
;
3670 sizes
[2] = groupCountZ
;
3671 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3672 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3673 .offset
= state
.offset
,
3677 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3679 if (cmd_buffer
->state
.conditional_render_enabled
)
3680 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3682 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3683 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3684 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3685 ggw
.ThreadDepthCounterMaximum
= 0;
3686 ggw
.ThreadHeightCounterMaximum
= 0;
3687 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3688 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3689 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3690 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3691 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3692 ggw
.BottomExecutionMask
= 0xffffffff;
3695 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3698 #define GPGPU_DISPATCHDIMX 0x2500
3699 #define GPGPU_DISPATCHDIMY 0x2504
3700 #define GPGPU_DISPATCHDIMZ 0x2508
3702 void genX(CmdDispatchIndirect
)(
3703 VkCommandBuffer commandBuffer
,
3705 VkDeviceSize offset
)
3707 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3708 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3709 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3710 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3711 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3712 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3714 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3717 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3718 * indirect dispatch registers to be written.
3720 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3721 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3725 if (prog_data
->uses_num_work_groups
)
3726 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3728 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3730 struct gen_mi_builder b
;
3731 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3733 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
3734 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
3735 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
3737 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
3738 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
3739 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
3742 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3743 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
3744 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3745 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3746 mip
.LoadOperation
= LOAD_LOAD
;
3747 mip
.CombineOperation
= COMBINE_SET
;
3748 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3751 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3752 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
3753 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3754 mip
.LoadOperation
= LOAD_LOAD
;
3755 mip
.CombineOperation
= COMBINE_OR
;
3756 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3759 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3760 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
3761 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3762 mip
.LoadOperation
= LOAD_LOAD
;
3763 mip
.CombineOperation
= COMBINE_OR
;
3764 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3767 /* predicate = !predicate; */
3768 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3769 mip
.LoadOperation
= LOAD_LOADINV
;
3770 mip
.CombineOperation
= COMBINE_OR
;
3771 mip
.CompareOperation
= COMPARE_FALSE
;
3775 if (cmd_buffer
->state
.conditional_render_enabled
) {
3776 /* predicate &= !(conditional_rendering_predicate == 0); */
3777 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
3778 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
3779 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3780 mip
.LoadOperation
= LOAD_LOADINV
;
3781 mip
.CombineOperation
= COMBINE_AND
;
3782 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3787 #else /* GEN_GEN > 7 */
3788 if (cmd_buffer
->state
.conditional_render_enabled
)
3789 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3792 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3793 ggw
.IndirectParameterEnable
= true;
3794 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3795 cmd_buffer
->state
.conditional_render_enabled
;
3796 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3797 ggw
.ThreadDepthCounterMaximum
= 0;
3798 ggw
.ThreadHeightCounterMaximum
= 0;
3799 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3800 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3801 ggw
.BottomExecutionMask
= 0xffffffff;
3804 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3808 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3811 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3813 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3816 #if GEN_GEN >= 8 && GEN_GEN < 10
3817 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3819 * Software must clear the COLOR_CALC_STATE Valid field in
3820 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3821 * with Pipeline Select set to GPGPU.
3823 * The internal hardware docs recommend the same workaround for Gen9
3826 if (pipeline
== GPGPU
)
3827 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3830 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3831 * PIPELINE_SELECT [DevBWR+]":
3835 * Software must ensure all the write caches are flushed through a
3836 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3837 * command to invalidate read only caches prior to programming
3838 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3840 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3841 pc
.RenderTargetCacheFlushEnable
= true;
3842 pc
.DepthCacheFlushEnable
= true;
3843 pc
.DCFlushEnable
= true;
3844 pc
.PostSyncOperation
= NoWrite
;
3845 pc
.CommandStreamerStallEnable
= true;
3848 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3849 pc
.TextureCacheInvalidationEnable
= true;
3850 pc
.ConstantCacheInvalidationEnable
= true;
3851 pc
.StateCacheInvalidationEnable
= true;
3852 pc
.InstructionCacheInvalidateEnable
= true;
3853 pc
.PostSyncOperation
= NoWrite
;
3856 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3860 ps
.PipelineSelection
= pipeline
;
3864 if (devinfo
->is_geminilake
) {
3867 * "This chicken bit works around a hardware issue with barrier logic
3868 * encountered when switching between GPGPU and 3D pipelines. To
3869 * workaround the issue, this mode bit should be set after a pipeline
3873 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3875 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3876 : GLK_BARRIER_MODE_3D_HULL
,
3877 .GLKBarrierModeMask
= 1);
3878 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3882 cmd_buffer
->state
.current_pipeline
= pipeline
;
3886 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3888 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3892 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3894 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3898 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3903 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3905 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3906 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3907 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3908 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3909 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3910 * Depth Flush Bit set, followed by another pipelined depth stall
3911 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3912 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3913 * via a preceding MI_FLUSH)."
3915 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3916 pipe
.DepthStallEnable
= true;
3918 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3919 pipe
.DepthCacheFlushEnable
= true;
3921 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3922 pipe
.DepthStallEnable
= true;
3927 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3929 struct anv_device
*device
= cmd_buffer
->device
;
3930 const struct anv_image_view
*iview
=
3931 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3932 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3934 /* FIXME: Width and Height are wrong */
3936 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3938 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3939 device
->isl_dev
.ds
.size
/ 4);
3943 struct isl_depth_stencil_hiz_emit_info info
= { };
3946 info
.view
= &iview
->planes
[0].isl
;
3948 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3949 uint32_t depth_plane
=
3950 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3951 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3953 info
.depth_surf
= &surface
->isl
;
3955 info
.depth_address
=
3956 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3957 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3958 image
->planes
[depth_plane
].address
.bo
,
3959 image
->planes
[depth_plane
].address
.offset
+
3962 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
3965 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3966 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3967 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3968 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3971 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3972 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3973 image
->planes
[depth_plane
].address
.bo
,
3974 image
->planes
[depth_plane
].address
.offset
+
3975 image
->planes
[depth_plane
].aux_surface
.offset
);
3977 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3981 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3982 uint32_t stencil_plane
=
3983 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3984 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3986 info
.stencil_surf
= &surface
->isl
;
3988 info
.stencil_address
=
3989 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3990 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3991 image
->planes
[stencil_plane
].address
.bo
,
3992 image
->planes
[stencil_plane
].address
.offset
+
3995 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
3998 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4000 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
4004 * This ANDs the view mask of the current subpass with the pending clear
4005 * views in the attachment to get the mask of views active in the subpass
4006 * that still need to be cleared.
4008 static inline uint32_t
4009 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4010 const struct anv_attachment_state
*att_state
)
4012 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4016 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4017 const struct anv_attachment_state
*att_state
)
4019 if (!cmd_state
->subpass
->view_mask
)
4022 uint32_t pending_clear_mask
=
4023 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4025 return pending_clear_mask
& 1;
4029 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4032 const uint32_t last_subpass_idx
=
4033 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4034 const struct anv_subpass
*last_subpass
=
4035 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4036 return last_subpass
== cmd_state
->subpass
;
4040 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4041 uint32_t subpass_id
)
4043 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4044 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4045 cmd_state
->subpass
= subpass
;
4047 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4049 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4050 * different views. If the client asks for instancing, we need to use the
4051 * Instance Data Step Rate to ensure that we repeat the client's
4052 * per-instance data once for each view. Since this bit is in
4053 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4057 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4059 /* It is possible to start a render pass with an old pipeline. Because the
4060 * render pass and subpass index are both baked into the pipeline, this is
4061 * highly unlikely. In order to do so, it requires that you have a render
4062 * pass with a single subpass and that you use that render pass twice
4063 * back-to-back and use the same pipeline at the start of the second render
4064 * pass as at the end of the first. In order to avoid unpredictable issues
4065 * with this edge case, we just dirty the pipeline at the start of every
4068 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4070 /* Accumulate any subpass flushes that need to happen before the subpass */
4071 cmd_buffer
->state
.pending_pipe_bits
|=
4072 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4074 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4075 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4077 bool is_multiview
= subpass
->view_mask
!= 0;
4079 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4080 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4081 if (a
== VK_ATTACHMENT_UNUSED
)
4084 assert(a
< cmd_state
->pass
->attachment_count
);
4085 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4087 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4088 const struct anv_image
*image
= iview
->image
;
4090 /* A resolve is necessary before use as an input attachment if the clear
4091 * color or auxiliary buffer usage isn't supported by the sampler.
4093 const bool input_needs_resolve
=
4094 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4095 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4097 VkImageLayout target_layout
;
4098 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4099 !input_needs_resolve
) {
4100 /* Layout transitions before the final only help to enable sampling
4101 * as an input attachment. If the input attachment supports sampling
4102 * using the auxiliary surface, we can skip such transitions by
4103 * making the target layout one that is CCS-aware.
4105 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4107 target_layout
= subpass
->attachments
[i
].layout
;
4110 uint32_t base_layer
, layer_count
;
4111 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4113 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4114 iview
->planes
[0].isl
.base_level
);
4116 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4117 layer_count
= fb
->layers
;
4120 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4121 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4122 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4123 iview
->planes
[0].isl
.base_level
, 1,
4124 base_layer
, layer_count
,
4125 att_state
->current_layout
, target_layout
);
4128 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4129 transition_depth_buffer(cmd_buffer
, image
,
4130 att_state
->current_layout
, target_layout
);
4131 att_state
->aux_usage
=
4132 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4133 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4136 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4137 transition_stencil_buffer(cmd_buffer
, image
,
4138 iview
->planes
[0].isl
.base_level
, 1,
4139 base_layer
, layer_count
,
4140 att_state
->current_layout
, target_layout
);
4142 att_state
->current_layout
= target_layout
;
4144 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4145 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4147 /* Multi-planar images are not supported as attachments */
4148 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4149 assert(image
->n_planes
== 1);
4151 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4152 uint32_t clear_layer_count
= fb
->layers
;
4154 if (att_state
->fast_clear
&&
4155 do_first_layer_clear(cmd_state
, att_state
)) {
4156 /* We only support fast-clears on the first layer */
4157 assert(iview
->planes
[0].isl
.base_level
== 0);
4158 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4160 union isl_color_value clear_color
= {};
4161 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4162 if (iview
->image
->samples
== 1) {
4163 anv_image_ccs_op(cmd_buffer
, image
,
4164 iview
->planes
[0].isl
.format
,
4165 VK_IMAGE_ASPECT_COLOR_BIT
,
4166 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4170 anv_image_mcs_op(cmd_buffer
, image
,
4171 iview
->planes
[0].isl
.format
,
4172 VK_IMAGE_ASPECT_COLOR_BIT
,
4173 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4178 clear_layer_count
--;
4180 att_state
->pending_clear_views
&= ~1;
4182 if (att_state
->clear_color_is_zero
) {
4183 /* This image has the auxiliary buffer enabled. We can mark the
4184 * subresource as not needing a resolve because the clear color
4185 * will match what's in every RENDER_SURFACE_STATE object when
4186 * it's being used for sampling.
4188 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4189 VK_IMAGE_ASPECT_COLOR_BIT
,
4190 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4192 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4193 VK_IMAGE_ASPECT_COLOR_BIT
,
4194 ANV_FAST_CLEAR_ANY
);
4198 /* From the VkFramebufferCreateInfo spec:
4200 * "If the render pass uses multiview, then layers must be one and each
4201 * attachment requires a number of layers that is greater than the
4202 * maximum bit index set in the view mask in the subpasses in which it
4205 * So if multiview is active we ignore the number of layers in the
4206 * framebuffer and instead we honor the view mask from the subpass.
4209 assert(image
->n_planes
== 1);
4210 uint32_t pending_clear_mask
=
4211 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4214 for_each_bit(layer_idx
, pending_clear_mask
) {
4216 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4218 anv_image_clear_color(cmd_buffer
, image
,
4219 VK_IMAGE_ASPECT_COLOR_BIT
,
4220 att_state
->aux_usage
,
4221 iview
->planes
[0].isl
.format
,
4222 iview
->planes
[0].isl
.swizzle
,
4223 iview
->planes
[0].isl
.base_level
,
4226 vk_to_isl_color(att_state
->clear_value
.color
));
4229 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4230 } else if (clear_layer_count
> 0) {
4231 assert(image
->n_planes
== 1);
4232 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4233 att_state
->aux_usage
,
4234 iview
->planes
[0].isl
.format
,
4235 iview
->planes
[0].isl
.swizzle
,
4236 iview
->planes
[0].isl
.base_level
,
4237 base_clear_layer
, clear_layer_count
,
4239 vk_to_isl_color(att_state
->clear_value
.color
));
4241 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4242 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4243 if (att_state
->fast_clear
&& !is_multiview
) {
4244 /* We currently only support HiZ for single-layer images */
4245 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4246 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4247 assert(iview
->planes
[0].isl
.base_level
== 0);
4248 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4249 assert(fb
->layers
== 1);
4252 anv_image_hiz_clear(cmd_buffer
, image
,
4253 att_state
->pending_clear_aspects
,
4254 iview
->planes
[0].isl
.base_level
,
4255 iview
->planes
[0].isl
.base_array_layer
,
4256 fb
->layers
, render_area
,
4257 att_state
->clear_value
.depthStencil
.stencil
);
4258 } else if (is_multiview
) {
4259 uint32_t pending_clear_mask
=
4260 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4263 for_each_bit(layer_idx
, pending_clear_mask
) {
4265 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4267 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4268 att_state
->pending_clear_aspects
,
4269 att_state
->aux_usage
,
4270 iview
->planes
[0].isl
.base_level
,
4273 att_state
->clear_value
.depthStencil
.depth
,
4274 att_state
->clear_value
.depthStencil
.stencil
);
4277 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4279 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4280 att_state
->pending_clear_aspects
,
4281 att_state
->aux_usage
,
4282 iview
->planes
[0].isl
.base_level
,
4283 iview
->planes
[0].isl
.base_array_layer
,
4284 fb
->layers
, render_area
,
4285 att_state
->clear_value
.depthStencil
.depth
,
4286 att_state
->clear_value
.depthStencil
.stencil
);
4289 assert(att_state
->pending_clear_aspects
== 0);
4293 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4294 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4295 iview
->planes
[0].isl
.base_level
== 0 &&
4296 iview
->planes
[0].isl
.base_array_layer
== 0) {
4297 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4298 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4299 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4300 false /* copy to ss */);
4303 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4304 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4305 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4306 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4307 false /* copy to ss */);
4311 if (subpass
->attachments
[i
].usage
==
4312 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4313 /* We assume that if we're starting a subpass, we're going to do some
4314 * rendering so we may end up with compressed data.
4316 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4317 VK_IMAGE_ASPECT_COLOR_BIT
,
4318 att_state
->aux_usage
,
4319 iview
->planes
[0].isl
.base_level
,
4320 iview
->planes
[0].isl
.base_array_layer
,
4322 } else if (subpass
->attachments
[i
].usage
==
4323 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4324 /* We may be writing depth or stencil so we need to mark the surface.
4325 * Unfortunately, there's no way to know at this point whether the
4326 * depth or stencil tests used will actually write to the surface.
4328 * Even though stencil may be plane 1, it always shares a base_level
4331 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4332 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4333 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4334 VK_IMAGE_ASPECT_DEPTH_BIT
,
4335 att_state
->aux_usage
,
4336 ds_view
->base_level
,
4337 ds_view
->base_array_layer
,
4340 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4341 /* Even though stencil may be plane 1, it always shares a
4342 * base_level with depth.
4344 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4345 VK_IMAGE_ASPECT_STENCIL_BIT
,
4347 ds_view
->base_level
,
4348 ds_view
->base_array_layer
,
4353 /* If multiview is enabled, then we are only done clearing when we no
4354 * longer have pending layers to clear, or when we have processed the
4355 * last subpass that uses this attachment.
4357 if (!is_multiview
||
4358 att_state
->pending_clear_views
== 0 ||
4359 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4360 att_state
->pending_clear_aspects
= 0;
4363 att_state
->pending_load_aspects
= 0;
4366 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4369 static enum blorp_filter
4370 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4373 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4374 return BLORP_FILTER_SAMPLE_0
;
4375 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4376 return BLORP_FILTER_AVERAGE
;
4377 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4378 return BLORP_FILTER_MIN_SAMPLE
;
4379 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4380 return BLORP_FILTER_MAX_SAMPLE
;
4382 return BLORP_FILTER_NONE
;
4387 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4389 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4390 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4391 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4392 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4394 if (subpass
->has_color_resolve
) {
4395 /* We are about to do some MSAA resolves. We need to flush so that the
4396 * result of writes to the MSAA color attachments show up in the sampler
4397 * when we blit to the single-sampled resolve target.
4399 cmd_buffer
->state
.pending_pipe_bits
|=
4400 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4401 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4403 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4404 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4405 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4407 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4410 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4411 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4413 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4414 /* From the Vulkan 1.0 spec:
4416 * If the first use of an attachment in a render pass is as a
4417 * resolve attachment, then the loadOp is effectively ignored
4418 * as the resolve is guaranteed to overwrite all pixels in the
4421 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4424 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
4425 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
4427 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4429 enum isl_aux_usage src_aux_usage
=
4430 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4431 enum isl_aux_usage dst_aux_usage
=
4432 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4434 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4435 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4437 anv_image_msaa_resolve(cmd_buffer
,
4438 src_iview
->image
, src_aux_usage
,
4439 src_iview
->planes
[0].isl
.base_level
,
4440 src_iview
->planes
[0].isl
.base_array_layer
,
4441 dst_iview
->image
, dst_aux_usage
,
4442 dst_iview
->planes
[0].isl
.base_level
,
4443 dst_iview
->planes
[0].isl
.base_array_layer
,
4444 VK_IMAGE_ASPECT_COLOR_BIT
,
4445 render_area
.offset
.x
, render_area
.offset
.y
,
4446 render_area
.offset
.x
, render_area
.offset
.y
,
4447 render_area
.extent
.width
,
4448 render_area
.extent
.height
,
4449 fb
->layers
, BLORP_FILTER_NONE
);
4453 if (subpass
->ds_resolve_attachment
) {
4454 /* We are about to do some MSAA resolves. We need to flush so that the
4455 * result of writes to the MSAA depth attachments show up in the sampler
4456 * when we blit to the single-sampled resolve target.
4458 cmd_buffer
->state
.pending_pipe_bits
|=
4459 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4460 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4462 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4463 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4465 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4466 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4468 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4469 /* From the Vulkan 1.0 spec:
4471 * If the first use of an attachment in a render pass is as a
4472 * resolve attachment, then the loadOp is effectively ignored
4473 * as the resolve is guaranteed to overwrite all pixels in the
4476 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4479 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
4480 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
4482 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4484 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4485 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4487 struct anv_attachment_state
*src_state
=
4488 &cmd_state
->attachments
[src_att
];
4489 struct anv_attachment_state
*dst_state
=
4490 &cmd_state
->attachments
[dst_att
];
4492 /* MSAA resolves sample from the source attachment. Transition the
4493 * depth attachment first to get rid of any HiZ that we may not be
4496 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4497 src_state
->current_layout
,
4498 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4499 src_state
->aux_usage
=
4500 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4501 VK_IMAGE_ASPECT_DEPTH_BIT
,
4502 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4503 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4505 /* MSAA resolves write to the resolve attachment as if it were any
4506 * other transfer op. Transition the resolve attachment accordingly.
4508 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4510 /* If our render area is the entire size of the image, we're going to
4511 * blow it all away so we can claim the initial layout is UNDEFINED
4512 * and we'll get a HiZ ambiguate instead of a resolve.
4514 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4515 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4516 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4517 render_area
.extent
.height
== dst_iview
->extent
.height
)
4518 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4520 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4522 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4523 dst_state
->aux_usage
=
4524 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4525 VK_IMAGE_ASPECT_DEPTH_BIT
,
4526 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4527 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4529 enum blorp_filter filter
=
4530 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4532 anv_image_msaa_resolve(cmd_buffer
,
4533 src_iview
->image
, src_state
->aux_usage
,
4534 src_iview
->planes
[0].isl
.base_level
,
4535 src_iview
->planes
[0].isl
.base_array_layer
,
4536 dst_iview
->image
, dst_state
->aux_usage
,
4537 dst_iview
->planes
[0].isl
.base_level
,
4538 dst_iview
->planes
[0].isl
.base_array_layer
,
4539 VK_IMAGE_ASPECT_DEPTH_BIT
,
4540 render_area
.offset
.x
, render_area
.offset
.y
,
4541 render_area
.offset
.x
, render_area
.offset
.y
,
4542 render_area
.extent
.width
,
4543 render_area
.extent
.height
,
4544 fb
->layers
, filter
);
4547 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4548 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4550 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4551 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4553 enum blorp_filter filter
=
4554 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4556 anv_image_msaa_resolve(cmd_buffer
,
4557 src_iview
->image
, src_aux_usage
,
4558 src_iview
->planes
[0].isl
.base_level
,
4559 src_iview
->planes
[0].isl
.base_array_layer
,
4560 dst_iview
->image
, dst_aux_usage
,
4561 dst_iview
->planes
[0].isl
.base_level
,
4562 dst_iview
->planes
[0].isl
.base_array_layer
,
4563 VK_IMAGE_ASPECT_STENCIL_BIT
,
4564 render_area
.offset
.x
, render_area
.offset
.y
,
4565 render_area
.offset
.x
, render_area
.offset
.y
,
4566 render_area
.extent
.width
,
4567 render_area
.extent
.height
,
4568 fb
->layers
, filter
);
4573 /* On gen7, we have to store a texturable version of the stencil buffer in
4574 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
4575 * forth at strategic points. Stencil writes are only allowed in three
4578 * - VK_IMAGE_LAYOUT_GENERAL
4579 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
4580 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
4581 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
4583 * For general, we have no nice opportunity to transition so we do the copy
4584 * to the shadow unconditionally at the end of the subpass. For transfer
4585 * destinations, we can update it as part of the transfer op. For the
4586 * other two, we delay the copy until a transition into some other layout.
4588 if (subpass
->depth_stencil_attachment
) {
4589 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
4590 assert(a
!= VK_ATTACHMENT_UNUSED
);
4592 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4593 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
4594 const struct anv_image
*image
= iview
->image
;
4596 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4597 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
4598 VK_IMAGE_ASPECT_STENCIL_BIT
);
4600 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
4601 att_state
->current_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
4602 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
4603 anv_image_copy_to_shadow(cmd_buffer
, image
,
4604 VK_IMAGE_ASPECT_STENCIL_BIT
,
4605 iview
->planes
[plane
].isl
.base_level
, 1,
4606 iview
->planes
[plane
].isl
.base_array_layer
,
4611 #endif /* GEN_GEN == 7 */
4613 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4614 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4615 if (a
== VK_ATTACHMENT_UNUSED
)
4618 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4621 assert(a
< cmd_state
->pass
->attachment_count
);
4622 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4623 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4624 const struct anv_image
*image
= iview
->image
;
4626 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4627 image
->vk_format
!= iview
->vk_format
) {
4628 enum anv_fast_clear_type fast_clear_type
=
4629 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4630 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4631 att_state
->current_layout
);
4633 /* If any clear color was used, flush it down the aux surfaces. If we
4634 * don't do it now using the view's format we might use the clear
4635 * color incorrectly in the following resolves (for example with an
4636 * SRGB view & a UNORM image).
4638 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4639 anv_perf_warn(cmd_buffer
->device
->instance
, iview
,
4640 "Doing a partial resolve to get rid of clear color at the "
4641 "end of a renderpass due to an image/view format mismatch");
4643 uint32_t base_layer
, layer_count
;
4644 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4646 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4647 iview
->planes
[0].isl
.base_level
);
4649 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4650 layer_count
= fb
->layers
;
4653 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4654 uint32_t array_layer
= base_layer
+ a
;
4655 if (image
->samples
== 1) {
4656 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4657 iview
->planes
[0].isl
.format
,
4658 VK_IMAGE_ASPECT_COLOR_BIT
,
4659 iview
->planes
[0].isl
.base_level
,
4661 ISL_AUX_OP_PARTIAL_RESOLVE
,
4662 ANV_FAST_CLEAR_NONE
);
4664 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4665 iview
->planes
[0].isl
.format
,
4666 VK_IMAGE_ASPECT_COLOR_BIT
,
4668 ISL_AUX_OP_PARTIAL_RESOLVE
,
4669 ANV_FAST_CLEAR_NONE
);
4675 /* Transition the image into the final layout for this render pass */
4676 VkImageLayout target_layout
=
4677 cmd_state
->pass
->attachments
[a
].final_layout
;
4679 uint32_t base_layer
, layer_count
;
4680 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4682 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4683 iview
->planes
[0].isl
.base_level
);
4685 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4686 layer_count
= fb
->layers
;
4689 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4690 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4691 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4692 iview
->planes
[0].isl
.base_level
, 1,
4693 base_layer
, layer_count
,
4694 att_state
->current_layout
, target_layout
);
4697 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4698 transition_depth_buffer(cmd_buffer
, image
,
4699 att_state
->current_layout
, target_layout
);
4702 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4703 transition_stencil_buffer(cmd_buffer
, image
,
4704 iview
->planes
[0].isl
.base_level
, 1,
4705 base_layer
, layer_count
,
4706 att_state
->current_layout
, target_layout
);
4710 /* Accumulate any subpass flushes that need to happen after the subpass.
4711 * Yes, they do get accumulated twice in the NextSubpass case but since
4712 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4713 * ORing the bits in twice so it's harmless.
4715 cmd_buffer
->state
.pending_pipe_bits
|=
4716 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4719 void genX(CmdBeginRenderPass
)(
4720 VkCommandBuffer commandBuffer
,
4721 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4722 VkSubpassContents contents
)
4724 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4725 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4726 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4728 cmd_buffer
->state
.framebuffer
= framebuffer
;
4729 cmd_buffer
->state
.pass
= pass
;
4730 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4732 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4734 /* If we failed to setup the attachments we should not try to go further */
4735 if (result
!= VK_SUCCESS
) {
4736 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4740 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4742 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4745 void genX(CmdBeginRenderPass2KHR
)(
4746 VkCommandBuffer commandBuffer
,
4747 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4748 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4750 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4751 pSubpassBeginInfo
->contents
);
4754 void genX(CmdNextSubpass
)(
4755 VkCommandBuffer commandBuffer
,
4756 VkSubpassContents contents
)
4758 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4760 if (anv_batch_has_error(&cmd_buffer
->batch
))
4763 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4765 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4766 cmd_buffer_end_subpass(cmd_buffer
);
4767 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4770 void genX(CmdNextSubpass2KHR
)(
4771 VkCommandBuffer commandBuffer
,
4772 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4773 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4775 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4778 void genX(CmdEndRenderPass
)(
4779 VkCommandBuffer commandBuffer
)
4781 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4783 if (anv_batch_has_error(&cmd_buffer
->batch
))
4786 cmd_buffer_end_subpass(cmd_buffer
);
4788 cmd_buffer
->state
.hiz_enabled
= false;
4791 anv_dump_add_attachments(cmd_buffer
);
4794 /* Remove references to render pass specific state. This enables us to
4795 * detect whether or not we're in a renderpass.
4797 cmd_buffer
->state
.framebuffer
= NULL
;
4798 cmd_buffer
->state
.pass
= NULL
;
4799 cmd_buffer
->state
.subpass
= NULL
;
4802 void genX(CmdEndRenderPass2KHR
)(
4803 VkCommandBuffer commandBuffer
,
4804 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4806 genX(CmdEndRenderPass
)(commandBuffer
);
4810 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
4812 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4813 struct gen_mi_builder b
;
4814 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4816 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
4817 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4818 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4820 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
4821 mip
.LoadOperation
= LOAD_LOADINV
;
4822 mip
.CombineOperation
= COMBINE_SET
;
4823 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4828 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4829 void genX(CmdBeginConditionalRenderingEXT
)(
4830 VkCommandBuffer commandBuffer
,
4831 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4833 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4834 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4835 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4836 struct anv_address value_address
=
4837 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
4839 const bool isInverted
= pConditionalRenderingBegin
->flags
&
4840 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
4842 cmd_state
->conditional_render_enabled
= true;
4844 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4846 struct gen_mi_builder b
;
4847 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4849 /* Section 19.4 of the Vulkan 1.1.85 spec says:
4851 * If the value of the predicate in buffer memory changes
4852 * while conditional rendering is active, the rendering commands
4853 * may be discarded in an implementation-dependent way.
4854 * Some implementations may latch the value of the predicate
4855 * upon beginning conditional rendering while others
4856 * may read it before every rendering command.
4858 * So it's perfectly fine to read a value from the buffer once.
4860 struct gen_mi_value value
= gen_mi_mem32(value_address
);
4862 /* Precompute predicate result, it is necessary to support secondary
4863 * command buffers since it is unknown if conditional rendering is
4864 * inverted when populating them.
4866 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
4867 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
4868 gen_mi_ult(&b
, gen_mi_imm(0), value
));
4871 void genX(CmdEndConditionalRenderingEXT
)(
4872 VkCommandBuffer commandBuffer
)
4874 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4875 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4877 cmd_state
->conditional_render_enabled
= false;
4881 /* Set of stage bits for which are pipelined, i.e. they get queued by the
4882 * command streamer for later execution.
4884 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
4885 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
4886 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
4887 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
4888 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
4889 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
4890 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
4891 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
4892 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
4893 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
4894 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
4895 VK_PIPELINE_STAGE_TRANSFER_BIT | \
4896 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
4897 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
4898 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
4900 void genX(CmdSetEvent
)(
4901 VkCommandBuffer commandBuffer
,
4903 VkPipelineStageFlags stageMask
)
4905 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4906 ANV_FROM_HANDLE(anv_event
, event
, _event
);
4908 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4909 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
4910 pc
.StallAtPixelScoreboard
= true;
4911 pc
.CommandStreamerStallEnable
= true;
4914 pc
.DestinationAddressType
= DAT_PPGTT
,
4915 pc
.PostSyncOperation
= WriteImmediateData
,
4916 pc
.Address
= (struct anv_address
) {
4917 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4920 pc
.ImmediateData
= VK_EVENT_SET
;
4924 void genX(CmdResetEvent
)(
4925 VkCommandBuffer commandBuffer
,
4927 VkPipelineStageFlags stageMask
)
4929 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4930 ANV_FROM_HANDLE(anv_event
, event
, _event
);
4932 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4933 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
4934 pc
.StallAtPixelScoreboard
= true;
4935 pc
.CommandStreamerStallEnable
= true;
4938 pc
.DestinationAddressType
= DAT_PPGTT
;
4939 pc
.PostSyncOperation
= WriteImmediateData
;
4940 pc
.Address
= (struct anv_address
) {
4941 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4944 pc
.ImmediateData
= VK_EVENT_RESET
;
4948 void genX(CmdWaitEvents
)(
4949 VkCommandBuffer commandBuffer
,
4950 uint32_t eventCount
,
4951 const VkEvent
* pEvents
,
4952 VkPipelineStageFlags srcStageMask
,
4953 VkPipelineStageFlags destStageMask
,
4954 uint32_t memoryBarrierCount
,
4955 const VkMemoryBarrier
* pMemoryBarriers
,
4956 uint32_t bufferMemoryBarrierCount
,
4957 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4958 uint32_t imageMemoryBarrierCount
,
4959 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4962 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4964 for (uint32_t i
= 0; i
< eventCount
; i
++) {
4965 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
4967 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
4968 sem
.WaitMode
= PollingMode
,
4969 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
4970 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
4971 sem
.SemaphoreAddress
= (struct anv_address
) {
4972 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4978 anv_finishme("Implement events on gen7");
4981 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
4982 false, /* byRegion */
4983 memoryBarrierCount
, pMemoryBarriers
,
4984 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4985 imageMemoryBarrierCount
, pImageMemoryBarriers
);