2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
,
37 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
39 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
40 lrm
.RegisterAddress
= reg
;
41 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
46 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
48 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
49 lri
.RegisterOffset
= reg
;
54 #if GEN_IS_HASWELL || GEN_GEN >= 8
56 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
58 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
59 lrr
.SourceRegisterAddress
= src
;
60 lrr
.DestinationRegisterAddress
= dst
;
66 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
68 struct anv_device
*device
= cmd_buffer
->device
;
70 /* Emit a render target cache flush.
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
77 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
78 pc
.DCFlushEnable
= true;
79 pc
.RenderTargetCacheFlushEnable
= true;
80 pc
.CommandStreamerStallEnable
= true;
83 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
84 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
85 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
86 sba
.GeneralStateBaseAddressModifyEnable
= true;
88 sba
.SurfaceStateBaseAddress
=
89 anv_cmd_buffer_surface_base_address(cmd_buffer
);
90 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
91 sba
.SurfaceStateBaseAddressModifyEnable
= true;
93 sba
.DynamicStateBaseAddress
=
94 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
95 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
96 sba
.DynamicStateBaseAddressModifyEnable
= true;
98 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
99 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
100 sba
.IndirectObjectBaseAddressModifyEnable
= true;
102 sba
.InstructionBaseAddress
=
103 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
104 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
105 sba
.InstructionBaseAddressModifyEnable
= true;
108 /* Broadwell requires that we specify a buffer size for a bunch of
109 * these fields. However, since we will be growing the BO's live, we
110 * just set them all to the maximum.
112 sba
.GeneralStateBufferSize
= 0xfffff;
113 sba
.GeneralStateBufferSizeModifyEnable
= true;
114 sba
.DynamicStateBufferSize
= 0xfffff;
115 sba
.DynamicStateBufferSizeModifyEnable
= true;
116 sba
.IndirectObjectBufferSize
= 0xfffff;
117 sba
.IndirectObjectBufferSizeModifyEnable
= true;
118 sba
.InstructionBufferSize
= 0xfffff;
119 sba
.InstructionBuffersizeModifyEnable
= true;
123 /* After re-setting the surface state base address, we have to do some
124 * cache flusing so that the sampler engine will pick up the new
125 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
126 * Shared Function > 3D Sampler > State > State Caching (page 96):
128 * Coherency with system memory in the state cache, like the texture
129 * cache is handled partially by software. It is expected that the
130 * command stream or shader will issue Cache Flush operation or
131 * Cache_Flush sampler message to ensure that the L1 cache remains
132 * coherent with system memory.
136 * Whenever the value of the Dynamic_State_Base_Addr,
137 * Surface_State_Base_Addr are altered, the L1 state cache must be
138 * invalidated to ensure the new surface or sampler state is fetched
139 * from system memory.
141 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
142 * which, according the PIPE_CONTROL instruction documentation in the
145 * Setting this bit is independent of any other bit in this packet.
146 * This bit controls the invalidation of the L1 and L2 state caches
147 * at the top of the pipe i.e. at the parsing time.
149 * Unfortunately, experimentation seems to indicate that state cache
150 * invalidation through a PIPE_CONTROL does nothing whatsoever in
151 * regards to surface state and binding tables. In stead, it seems that
152 * invalidating the texture cache is what is actually needed.
154 * XXX: As far as we have been able to determine through
155 * experimentation, shows that flush the texture cache appears to be
156 * sufficient. The theory here is that all of the sampling/rendering
157 * units cache the binding table in the texture cache. However, we have
158 * yet to be able to actually confirm this.
160 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
161 pc
.TextureCacheInvalidationEnable
= true;
162 pc
.ConstantCacheInvalidationEnable
= true;
163 pc
.StateCacheInvalidationEnable
= true;
168 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
169 struct anv_state state
,
170 struct anv_bo
*bo
, uint32_t offset
)
172 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
175 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
176 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
177 if (result
!= VK_SUCCESS
)
178 anv_batch_set_error(&cmd_buffer
->batch
, result
);
182 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
183 const struct anv_image_view
*image_view
,
184 const uint32_t plane
,
185 struct anv_surface_state state
)
187 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
188 const struct anv_image
*image
= image_view
->image
;
189 uint32_t image_plane
= image_view
->planes
[plane
].image_plane
;
191 add_surface_state_reloc(cmd_buffer
, state
.state
,
192 image
->planes
[image_plane
].bo
, state
.address
);
194 if (state
.aux_address
) {
196 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
197 &cmd_buffer
->pool
->alloc
,
198 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
199 image
->planes
[image_plane
].bo
, state
.aux_address
);
200 if (result
!= VK_SUCCESS
)
201 anv_batch_set_error(&cmd_buffer
->batch
, result
);
206 color_is_zero_one(VkClearColorValue value
, enum isl_format format
)
208 if (isl_format_has_int_channel(format
)) {
209 for (unsigned i
= 0; i
< 4; i
++) {
210 if (value
.int32
[i
] != 0 && value
.int32
[i
] != 1)
214 for (unsigned i
= 0; i
< 4; i
++) {
215 if (value
.float32
[i
] != 0.0f
&& value
.float32
[i
] != 1.0f
)
224 color_attachment_compute_aux_usage(struct anv_device
* device
,
225 struct anv_cmd_state
* cmd_state
,
226 uint32_t att
, VkRect2D render_area
,
227 union isl_color_value
*fast_clear_color
)
229 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
230 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
232 assert(iview
->n_planes
== 1);
234 if (iview
->planes
[0].isl
.base_array_layer
>=
235 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
236 iview
->planes
[0].isl
.base_level
)) {
237 /* There is no aux buffer which corresponds to the level and layer(s)
240 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
241 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
242 att_state
->fast_clear
= false;
244 } else if (iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_MCS
) {
245 att_state
->aux_usage
= ISL_AUX_USAGE_MCS
;
246 att_state
->input_aux_usage
= ISL_AUX_USAGE_MCS
;
247 att_state
->fast_clear
= false;
249 } else if (iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
250 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
251 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_E
;
253 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
254 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
256 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
257 * setting is only allowed if Surface Format supported for Fast
258 * Clear. In addition, if the surface is bound to the sampling
259 * engine, Surface Format must be supported for Render Target
260 * Compression for surfaces bound to the sampling engine."
262 * In other words, we can only sample from a fast-cleared image if it
263 * also supports color compression.
265 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
266 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
268 /* While fast-clear resolves and partial resolves are fairly cheap in the
269 * case where you render to most of the pixels, full resolves are not
270 * because they potentially involve reading and writing the entire
271 * framebuffer. If we can't texture with CCS_E, we should leave it off and
272 * limit ourselves to fast clears.
274 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
275 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
276 anv_perf_warn(device
->instance
, iview
->image
,
277 "Not temporarily enabling CCS_E.");
280 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
284 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
286 att_state
->clear_color_is_zero_one
=
287 color_is_zero_one(att_state
->clear_value
.color
, iview
->planes
[0].isl
.format
);
288 att_state
->clear_color_is_zero
=
289 att_state
->clear_value
.color
.uint32
[0] == 0 &&
290 att_state
->clear_value
.color
.uint32
[1] == 0 &&
291 att_state
->clear_value
.color
.uint32
[2] == 0 &&
292 att_state
->clear_value
.color
.uint32
[3] == 0;
294 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
295 /* Start off assuming fast clears are possible */
296 att_state
->fast_clear
= true;
298 /* Potentially, we could do partial fast-clears but doing so has crazy
299 * alignment restrictions. It's easier to just restrict to full size
300 * fast clears for now.
302 if (render_area
.offset
.x
!= 0 ||
303 render_area
.offset
.y
!= 0 ||
304 render_area
.extent
.width
!= iview
->extent
.width
||
305 render_area
.extent
.height
!= iview
->extent
.height
)
306 att_state
->fast_clear
= false;
308 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
309 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
310 att_state
->fast_clear
= false;
312 /* We allow fast clears when all aux layers of the miplevel are targeted.
313 * See add_fast_clear_state_buffer() for more information. Also, because
314 * we only either do a fast clear or a normal clear and not both, this
315 * complies with the gen7 restriction of not fast-clearing multiple
318 if (cmd_state
->framebuffer
->layers
!=
319 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
320 iview
->planes
[0].isl
.base_level
)) {
321 att_state
->fast_clear
= false;
323 anv_perf_warn(device
->instance
, iview
->image
,
324 "Not fast-clearing the first layer in "
325 "a multi-layer fast clear.");
329 /* We only allow fast clears in the GENERAL layout if the auxiliary
330 * buffer is always enabled and the fast-clear value is all 0's. See
331 * add_fast_clear_state_buffer() for more information.
333 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
334 VK_IMAGE_LAYOUT_GENERAL
&&
335 (!att_state
->clear_color_is_zero
||
336 iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_NONE
)) {
337 att_state
->fast_clear
= false;
340 if (att_state
->fast_clear
) {
341 memcpy(fast_clear_color
->u32
, att_state
->clear_value
.color
.uint32
,
342 sizeof(fast_clear_color
->u32
));
345 att_state
->fast_clear
= false;
350 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
352 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
355 /* We only allocate input attachment states for color surfaces. Compression
356 * is not yet enabled for depth textures and stencil doesn't allow
357 * compression so we can just use the texture surface state from the view.
359 return vk_format_is_color(att
->format
);
362 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
363 * the initial layout is undefined, the HiZ buffer and depth buffer will
364 * represent the same data at the end of this operation.
367 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
368 const struct anv_image
*image
,
369 VkImageLayout initial_layout
,
370 VkImageLayout final_layout
)
374 /* A transition is a no-op if HiZ is not enabled, or if the initial and
375 * final layouts are equal.
377 * The undefined layout indicates that the user doesn't care about the data
378 * that's currently in the buffer. Therefore, a data-preserving resolve
379 * operation is not needed.
381 if (image
->planes
[0].aux_usage
!= ISL_AUX_USAGE_HIZ
|| initial_layout
== final_layout
)
384 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
385 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
386 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
387 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
388 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
389 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
391 enum blorp_hiz_op hiz_op
;
392 if (hiz_enabled
&& !enable_hiz
) {
393 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
394 } else if (!hiz_enabled
&& enable_hiz
) {
395 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
397 assert(hiz_enabled
== enable_hiz
);
398 /* If the same buffer will be used, no resolves are necessary. */
399 hiz_op
= BLORP_HIZ_OP_NONE
;
402 if (hiz_op
!= BLORP_HIZ_OP_NONE
)
403 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, hiz_op
);
406 #define MI_PREDICATE_SRC0 0x2400
407 #define MI_PREDICATE_SRC1 0x2408
409 /* Manages the state of an color image subresource to ensure resolves are
410 * performed properly.
413 genX(set_image_needs_resolve
)(struct anv_cmd_buffer
*cmd_buffer
,
414 const struct anv_image
*image
,
415 VkImageAspectFlagBits aspect
,
416 unsigned level
, bool needs_resolve
)
418 assert(cmd_buffer
&& image
);
419 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
420 assert(level
< anv_image_aux_levels(image
, aspect
));
422 /* The HW docs say that there is no way to guarantee the completion of
423 * the following command. We use it nevertheless because it shows no
424 * issues in testing is currently being used in the GL driver.
426 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
427 sdi
.Address
= anv_image_get_needs_resolve_addr(cmd_buffer
->device
,
428 image
, aspect
, level
);
429 sdi
.ImmediateData
= needs_resolve
;
434 genX(load_needs_resolve_predicate
)(struct anv_cmd_buffer
*cmd_buffer
,
435 const struct anv_image
*image
,
436 VkImageAspectFlagBits aspect
,
439 assert(cmd_buffer
&& image
);
440 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
441 assert(level
< anv_image_aux_levels(image
, aspect
));
443 const struct anv_address resolve_flag_addr
=
444 anv_image_get_needs_resolve_addr(cmd_buffer
->device
,
445 image
, aspect
, level
);
447 /* Make the pending predicated resolve a no-op if one is not needed.
448 * predicate = do_resolve = resolve_flag != 0;
450 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
451 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
452 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, 0);
453 emit_lrm(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4,
454 resolve_flag_addr
.bo
, resolve_flag_addr
.offset
);
455 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
456 mip
.LoadOperation
= LOAD_LOADINV
;
457 mip
.CombineOperation
= COMBINE_SET
;
458 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
463 init_fast_clear_state_entry(struct anv_cmd_buffer
*cmd_buffer
,
464 const struct anv_image
*image
,
465 VkImageAspectFlagBits aspect
,
468 assert(cmd_buffer
&& image
);
469 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
470 assert(level
< anv_image_aux_levels(image
, aspect
));
472 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
473 enum isl_aux_usage aux_usage
= image
->planes
[plane
].aux_usage
;
475 /* The resolve flag should updated to signify that fast-clear/compression
476 * data needs to be removed when leaving the undefined layout. Such data
477 * may need to be removed if it would cause accesses to the color buffer
478 * to return incorrect data. The fast clear data in CCS_D buffers should
479 * be removed because CCS_D isn't enabled all the time.
481 genX(set_image_needs_resolve
)(cmd_buffer
, image
, aspect
, level
,
482 aux_usage
== ISL_AUX_USAGE_NONE
);
484 /* The fast clear value dword(s) will be copied into a surface state object.
485 * Ensure that the restrictions of the fields in the dword(s) are followed.
487 * CCS buffers on SKL+ can have any value set for the clear colors.
489 if (image
->samples
== 1 && GEN_GEN
>= 9)
492 /* Other combinations of auxiliary buffers and platforms require specific
493 * values in the clear value dword(s).
495 struct anv_address addr
=
496 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
, level
);
498 for (; i
< cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
; i
+= 4) {
499 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
503 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
504 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
505 sdi
.ImmediateData
= 0;
506 } else if (GEN_VERSIONx10
>= 75) {
507 /* Pre-SKL, the dword containing the clear values also contains
508 * other fields, so we need to initialize those fields to match the
509 * values that would be in a color attachment.
512 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
513 ISL_CHANNEL_SELECT_GREEN
<< 22 |
514 ISL_CHANNEL_SELECT_BLUE
<< 19 |
515 ISL_CHANNEL_SELECT_ALPHA
<< 16;
516 } else if (GEN_VERSIONx10
== 70) {
517 /* On IVB, the dword containing the clear values also contains
518 * other fields that must be zero or can be zero.
521 sdi
.ImmediateData
= 0;
529 /* Copy the fast-clear value dword(s) between a surface state object and an
530 * image's fast clear state buffer.
533 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
534 struct anv_state surface_state
,
535 const struct anv_image
*image
,
536 VkImageAspectFlagBits aspect
,
538 bool copy_from_surface_state
)
540 assert(cmd_buffer
&& image
);
541 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
542 assert(level
< anv_image_aux_levels(image
, aspect
));
544 struct anv_bo
*ss_bo
=
545 &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
;
546 uint32_t ss_clear_offset
= surface_state
.offset
+
547 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
;
548 const struct anv_address entry_addr
=
549 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
, level
);
550 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
552 if (copy_from_surface_state
) {
553 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
.bo
, entry_addr
.offset
,
554 ss_bo
, ss_clear_offset
, copy_size
);
556 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_bo
, ss_clear_offset
,
557 entry_addr
.bo
, entry_addr
.offset
, copy_size
);
559 /* Updating a surface state object may require that the state cache be
560 * invalidated. From the SKL PRM, Shared Functions -> State -> State
563 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
564 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
565 * modified [...], the L1 state cache must be invalidated to ensure
566 * the new surface or sampler state is fetched from system memory.
568 * In testing, SKL doesn't actually seem to need this, but HSW does.
570 cmd_buffer
->state
.pending_pipe_bits
|=
571 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
576 * @brief Transitions a color buffer from one layout to another.
578 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
581 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
582 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
583 * this represents the maximum layers to transition at each
584 * specified miplevel.
587 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
588 const struct anv_image
*image
,
589 VkImageAspectFlagBits aspect
,
590 const uint32_t base_level
, uint32_t level_count
,
591 uint32_t base_layer
, uint32_t layer_count
,
592 VkImageLayout initial_layout
,
593 VkImageLayout final_layout
)
595 /* Validate the inputs. */
597 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
598 /* These values aren't supported for simplicity's sake. */
599 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
600 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
601 /* Ensure the subresource range is valid. */
602 uint64_t last_level_num
= base_level
+ level_count
;
603 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
604 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
605 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
606 assert(last_level_num
<= image
->levels
);
607 /* The spec disallows these final layouts. */
608 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
609 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
611 /* No work is necessary if the layout stays the same or if this subresource
612 * range lacks auxiliary data.
614 if (initial_layout
== final_layout
)
617 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
619 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
620 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
621 /* This surface is a linear compressed image with a tiled shadow surface
622 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
623 * we need to ensure the shadow copy is up-to-date.
625 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
626 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
627 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
628 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
630 anv_image_copy_to_shadow(cmd_buffer
, image
,
631 base_level
, level_count
,
632 base_layer
, layer_count
);
635 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
638 /* A transition of a 3D subresource works on all slices at a time. */
639 if (image
->type
== VK_IMAGE_TYPE_3D
) {
641 layer_count
= anv_minify(image
->extent
.depth
, base_level
);
644 /* We're interested in the subresource range subset that has aux data. */
645 level_count
= MIN2(level_count
, anv_image_aux_levels(image
, aspect
) - base_level
);
646 layer_count
= MIN2(layer_count
,
647 anv_image_aux_layers(image
, aspect
, base_level
) - base_layer
);
648 last_level_num
= base_level
+ level_count
;
650 /* Record whether or not the layout is undefined. Pre-initialized images
651 * with auxiliary buffers have a non-linear layout and are thus undefined.
653 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
654 const bool undef_layout
= initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
655 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
;
657 /* Do preparatory work before the resolve operation or return early if no
658 * resolve is actually needed.
661 /* A subresource in the undefined layout may have been aliased and
662 * populated with any arrangement of bits. Therefore, we must initialize
663 * the related aux buffer and clear buffer entry with desirable values.
665 * Initialize the relevant clear buffer entries.
667 for (unsigned level
= base_level
; level
< last_level_num
; level
++)
668 init_fast_clear_state_entry(cmd_buffer
, image
, aspect
, level
);
670 /* Initialize the aux buffers to enable correct rendering. This operation
671 * requires up to two steps: one to rid the aux buffer of data that may
672 * cause GPU hangs, and another to ensure that writes done without aux
673 * will be visible to reads done with aux.
675 * Having an aux buffer with invalid data is possible for CCS buffers
676 * SKL+ and for MCS buffers with certain sample counts (2x and 8x). One
677 * easy way to get to a valid state is to fast-clear the specified range.
679 * Even for MCS buffers that have sample counts that don't require
680 * certain bits to be reserved (4x and 8x), we're unsure if the hardware
681 * will be okay with the sample mappings given by the undefined buffer.
682 * We don't have any data to show that this is a problem, but we want to
683 * avoid causing difficult-to-debug problems.
685 if ((GEN_GEN
>= 9 && image
->samples
== 1) || image
->samples
> 1) {
686 if (image
->samples
== 4 || image
->samples
== 16) {
687 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
688 "Doing a potentially unnecessary fast-clear to "
689 "define an MCS buffer.");
692 anv_image_fast_clear(cmd_buffer
, image
, aspect
,
693 base_level
, level_count
,
694 base_layer
, layer_count
);
696 /* At this point, some elements of the CCS buffer may have the fast-clear
697 * bit-arrangement. As the user writes to a subresource, we need to have
698 * the associated CCS elements enter the ambiguated state. This enables
699 * reads (implicit or explicit) to reflect the user-written data instead
700 * of the clear color. The only time such elements will not change their
701 * state as described above, is in a final layout that doesn't have CCS
702 * enabled. In this case, we must force the associated CCS buffers of the
703 * specified range to enter the ambiguated state in advance.
705 if (image
->samples
== 1 &&
706 image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
707 final_layout
!= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
708 /* The CCS_D buffer may not be enabled in the final layout. Continue
709 * executing this function to perform a resolve.
711 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
712 "Performing an additional resolve for CCS_D layout "
713 "transition. Consider always leaving it on or "
714 "performing an ambiguation pass.");
716 /* Writes in the final layout will be aware of the auxiliary buffer.
717 * In addition, the clear buffer entries and the auxiliary buffers
718 * have been populated with values that will result in correct
723 } else if (initial_layout
!= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
724 /* Resolves are only necessary if the subresource may contain blocks
725 * fast-cleared to values unsupported in other layouts. This only occurs
726 * if the initial layout is COLOR_ATTACHMENT_OPTIMAL.
729 } else if (image
->samples
> 1) {
730 /* MCS buffers don't need resolving. */
734 /* Perform a resolve to synchronize data between the main and aux buffer.
735 * Before we begin, we must satisfy the cache flushing requirement specified
736 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
738 * Any transition from any value in {Clear, Render, Resolve} to a
739 * different value in {Clear, Render, Resolve} requires end of pipe
742 * We perform a flush of the write cache before and after the clear and
743 * resolve operations to meet this requirement.
745 * Unlike other drawing, fast clear operations are not properly
746 * synchronized. The first PIPE_CONTROL here likely ensures that the
747 * contents of the previous render or clear hit the render target before we
748 * resolve and the second likely ensures that the resolve is complete before
749 * we do any more rendering or clearing.
751 cmd_buffer
->state
.pending_pipe_bits
|=
752 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
754 for (uint32_t level
= base_level
; level
< last_level_num
; level
++) {
756 /* The number of layers changes at each 3D miplevel. */
757 if (image
->type
== VK_IMAGE_TYPE_3D
) {
758 layer_count
= MIN2(layer_count
, anv_image_aux_layers(image
, aspect
, level
));
761 genX(load_needs_resolve_predicate
)(cmd_buffer
, image
, aspect
, level
);
763 anv_ccs_resolve(cmd_buffer
, image
, aspect
, level
, base_layer
, layer_count
,
764 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
?
765 BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
766 BLORP_FAST_CLEAR_OP_RESOLVE_FULL
);
768 genX(set_image_needs_resolve
)(cmd_buffer
, image
, aspect
, level
, false);
771 cmd_buffer
->state
.pending_pipe_bits
|=
772 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
776 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
779 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
780 struct anv_render_pass
*pass
,
781 const VkRenderPassBeginInfo
*begin
)
783 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
784 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
786 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
788 if (pass
->attachment_count
> 0) {
789 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
790 pass
->attachment_count
*
791 sizeof(state
->attachments
[0]),
792 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
793 if (state
->attachments
== NULL
) {
794 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
795 return anv_batch_set_error(&cmd_buffer
->batch
,
796 VK_ERROR_OUT_OF_HOST_MEMORY
);
799 state
->attachments
= NULL
;
802 /* Reserve one for the NULL state. */
803 unsigned num_states
= 1;
804 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
805 if (vk_format_is_color(pass
->attachments
[i
].format
))
808 if (need_input_attachment_state(&pass
->attachments
[i
]))
812 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
813 state
->render_pass_states
=
814 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
815 num_states
* ss_stride
, isl_dev
->ss
.align
);
817 struct anv_state next_state
= state
->render_pass_states
;
818 next_state
.alloc_size
= isl_dev
->ss
.size
;
820 state
->null_surface_state
= next_state
;
821 next_state
.offset
+= ss_stride
;
822 next_state
.map
+= ss_stride
;
824 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
825 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
826 state
->attachments
[i
].color
.state
= next_state
;
827 next_state
.offset
+= ss_stride
;
828 next_state
.map
+= ss_stride
;
831 if (need_input_attachment_state(&pass
->attachments
[i
])) {
832 state
->attachments
[i
].input
.state
= next_state
;
833 next_state
.offset
+= ss_stride
;
834 next_state
.map
+= ss_stride
;
837 assert(next_state
.offset
== state
->render_pass_states
.offset
+
838 state
->render_pass_states
.alloc_size
);
841 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
842 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
844 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
845 isl_extent3d(framebuffer
->width
,
847 framebuffer
->layers
));
849 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
850 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
851 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
852 VkImageAspectFlags clear_aspects
= 0;
854 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
855 /* color attachment */
856 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
857 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
860 /* depthstencil attachment */
861 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
862 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
863 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
865 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
866 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
867 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
871 state
->attachments
[i
].current_layout
= att
->initial_layout
;
872 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
874 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
876 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
877 anv_assert(iview
->vk_format
== att
->format
);
878 anv_assert(iview
->n_planes
== 1);
880 union isl_color_value clear_color
= { .u32
= { 0, } };
881 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
882 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
883 color_attachment_compute_aux_usage(cmd_buffer
->device
,
884 state
, i
, begin
->renderArea
,
887 anv_image_fill_surface_state(cmd_buffer
->device
,
889 VK_IMAGE_ASPECT_COLOR_BIT
,
890 &iview
->planes
[0].isl
,
891 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
892 state
->attachments
[i
].aux_usage
,
895 &state
->attachments
[i
].color
,
898 add_image_view_relocs(cmd_buffer
, iview
, 0,
899 state
->attachments
[i
].color
);
901 /* This field will be initialized after the first subpass
904 state
->attachments
[i
].aux_usage
= ISL_AUX_USAGE_NONE
;
906 state
->attachments
[i
].input_aux_usage
= ISL_AUX_USAGE_NONE
;
909 if (need_input_attachment_state(&pass
->attachments
[i
])) {
910 anv_image_fill_surface_state(cmd_buffer
->device
,
912 VK_IMAGE_ASPECT_COLOR_BIT
,
913 &iview
->planes
[0].isl
,
914 ISL_SURF_USAGE_TEXTURE_BIT
,
915 state
->attachments
[i
].input_aux_usage
,
918 &state
->attachments
[i
].input
,
921 add_image_view_relocs(cmd_buffer
, iview
, 0,
922 state
->attachments
[i
].input
);
931 genX(BeginCommandBuffer
)(
932 VkCommandBuffer commandBuffer
,
933 const VkCommandBufferBeginInfo
* pBeginInfo
)
935 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
937 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
938 * command buffer's state. Otherwise, we must *reset* its state. In both
941 * From the Vulkan 1.0 spec:
943 * If a command buffer is in the executable state and the command buffer
944 * was allocated from a command pool with the
945 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
946 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
947 * as if vkResetCommandBuffer had been called with
948 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
949 * the command buffer in the recording state.
951 anv_cmd_buffer_reset(cmd_buffer
);
953 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
955 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
956 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
958 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
960 /* We sometimes store vertex data in the dynamic state buffer for blorp
961 * operations and our dynamic state stream may re-use data from previous
962 * command buffers. In order to prevent stale cache data, we flush the VF
963 * cache. We could do this on every blorp call but that's not really
964 * needed as all of the data will get written by the CPU prior to the GPU
965 * executing anything. The chances are fairly high that they will use
966 * blorp at least once per primary command buffer so it shouldn't be
969 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
970 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
972 VkResult result
= VK_SUCCESS
;
973 if (cmd_buffer
->usage_flags
&
974 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
975 assert(pBeginInfo
->pInheritanceInfo
);
976 cmd_buffer
->state
.pass
=
977 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
978 cmd_buffer
->state
.subpass
=
979 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
981 /* This is optional in the inheritance info. */
982 cmd_buffer
->state
.framebuffer
=
983 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
985 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
986 cmd_buffer
->state
.pass
, NULL
);
988 /* Record that HiZ is enabled if we can. */
989 if (cmd_buffer
->state
.framebuffer
) {
990 const struct anv_image_view
* const iview
=
991 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
994 VkImageLayout layout
=
995 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.layout
;
997 enum isl_aux_usage aux_usage
=
998 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
999 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1001 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1005 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1012 genX(EndCommandBuffer
)(
1013 VkCommandBuffer commandBuffer
)
1015 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1017 if (anv_batch_has_error(&cmd_buffer
->batch
))
1018 return cmd_buffer
->batch
.status
;
1020 /* We want every command buffer to start with the PMA fix in a known state,
1021 * so we disable it at the end of the command buffer.
1023 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1025 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1027 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1033 genX(CmdExecuteCommands
)(
1034 VkCommandBuffer commandBuffer
,
1035 uint32_t commandBufferCount
,
1036 const VkCommandBuffer
* pCmdBuffers
)
1038 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1040 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1042 if (anv_batch_has_error(&primary
->batch
))
1045 /* The secondary command buffers will assume that the PMA fix is disabled
1046 * when they begin executing. Make sure this is true.
1048 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1050 /* The secondary command buffer doesn't know which textures etc. have been
1051 * flushed prior to their execution. Apply those flushes now.
1053 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1055 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1056 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1058 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1059 assert(!anv_batch_has_error(&secondary
->batch
));
1061 if (secondary
->usage_flags
&
1062 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1063 /* If we're continuing a render pass from the primary, we need to
1064 * copy the surface states for the current subpass into the storage
1065 * we allocated for them in BeginCommandBuffer.
1067 struct anv_bo
*ss_bo
=
1068 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1069 struct anv_state src_state
= primary
->state
.render_pass_states
;
1070 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1071 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1073 genX(cmd_buffer_so_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
1074 ss_bo
, src_state
.offset
,
1075 src_state
.alloc_size
);
1078 anv_cmd_buffer_add_secondary(primary
, secondary
);
1081 /* The secondary may have selected a different pipeline (3D or compute) and
1082 * may have changed the current L3$ configuration. Reset our tracking
1083 * variables to invalid values to ensure that we re-emit these in the case
1084 * where we do any draws or compute dispatches from the primary after the
1085 * secondary has returned.
1087 primary
->state
.current_pipeline
= UINT32_MAX
;
1088 primary
->state
.current_l3_config
= NULL
;
1090 /* Each of the secondary command buffers will use its own state base
1091 * address. We need to re-emit state base address for the primary after
1092 * all of the secondaries are done.
1094 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1097 genX(cmd_buffer_emit_state_base_address
)(primary
);
1100 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1101 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1102 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1105 * Program the hardware to use the specified L3 configuration.
1108 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1109 const struct gen_l3_config
*cfg
)
1112 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1115 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1116 intel_logd("L3 config transition: ");
1117 gen_dump_l3_config(cfg
, stderr
);
1120 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1122 /* According to the hardware docs, the L3 partitioning can only be changed
1123 * while the pipeline is completely drained and the caches are flushed,
1124 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1126 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1127 pc
.DCFlushEnable
= true;
1128 pc
.PostSyncOperation
= NoWrite
;
1129 pc
.CommandStreamerStallEnable
= true;
1132 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1133 * invalidation of the relevant caches. Note that because RO invalidation
1134 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1135 * command is processed by the CS) we cannot combine it with the previous
1136 * stalling flush as the hardware documentation suggests, because that
1137 * would cause the CS to stall on previous rendering *after* RO
1138 * invalidation and wouldn't prevent the RO caches from being polluted by
1139 * concurrent rendering before the stall completes. This intentionally
1140 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1141 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1142 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1143 * already guarantee that there is no concurrent GPGPU kernel execution
1144 * (see SKL HSD 2132585).
1146 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1147 pc
.TextureCacheInvalidationEnable
= true;
1148 pc
.ConstantCacheInvalidationEnable
= true;
1149 pc
.InstructionCacheInvalidateEnable
= true;
1150 pc
.StateCacheInvalidationEnable
= true;
1151 pc
.PostSyncOperation
= NoWrite
;
1154 /* Now send a third stalling flush to make sure that invalidation is
1155 * complete when the L3 configuration registers are modified.
1157 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1158 pc
.DCFlushEnable
= true;
1159 pc
.PostSyncOperation
= NoWrite
;
1160 pc
.CommandStreamerStallEnable
= true;
1165 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1168 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1169 .SLMEnable
= has_slm
,
1170 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1171 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1172 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1173 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1175 /* Set up the L3 partitioning. */
1176 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1180 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1181 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1182 cfg
->n
[GEN_L3P_ALL
];
1183 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1184 cfg
->n
[GEN_L3P_ALL
];
1185 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1186 cfg
->n
[GEN_L3P_ALL
];
1188 assert(!cfg
->n
[GEN_L3P_ALL
]);
1190 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1191 * the matching space on the remaining banks has to be allocated to a
1192 * client (URB for all validated configurations) set to the
1193 * lower-bandwidth 2-bank address hashing mode.
1195 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1196 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1197 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1199 /* Minimum number of ways that can be allocated to the URB. */
1200 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1201 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1203 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1204 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1205 .ConvertDC_UC
= !has_dc
,
1206 .ConvertIS_UC
= !has_is
,
1207 .ConvertC_UC
= !has_c
,
1208 .ConvertT_UC
= !has_t
);
1210 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1211 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1212 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1214 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1215 .SLMEnable
= has_slm
,
1216 .URBLowBandwidth
= urb_low_bw
,
1217 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1219 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1221 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1222 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1224 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1225 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1226 .ISLowBandwidth
= 0,
1227 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1229 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1230 .TLowBandwidth
= 0);
1232 /* Set up the L3 partitioning. */
1233 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1234 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1235 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1238 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1239 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1240 * them disabled to avoid crashing the system hard.
1242 uint32_t scratch1
, chicken3
;
1243 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1244 .L3AtomicDisable
= !has_dc
);
1245 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1246 .L3AtomicDisableMask
= true,
1247 .L3AtomicDisable
= !has_dc
);
1248 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1249 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1255 cmd_buffer
->state
.current_l3_config
= cfg
;
1259 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1261 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1263 /* Flushes are pipelined while invalidations are handled immediately.
1264 * Therefore, if we're flushing anything then we need to schedule a stall
1265 * before any invalidations can happen.
1267 if (bits
& ANV_PIPE_FLUSH_BITS
)
1268 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1270 /* If we're going to do an invalidate and we have a pending CS stall that
1271 * has yet to be resolved, we do the CS stall now.
1273 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1274 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1275 bits
|= ANV_PIPE_CS_STALL_BIT
;
1276 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1279 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1280 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1281 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1282 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1283 pipe
.RenderTargetCacheFlushEnable
=
1284 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1286 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1287 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1288 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1291 * According to the Broadwell documentation, any PIPE_CONTROL with the
1292 * "Command Streamer Stall" bit set must also have another bit set,
1293 * with five different options:
1295 * - Render Target Cache Flush
1296 * - Depth Cache Flush
1297 * - Stall at Pixel Scoreboard
1298 * - Post-Sync Operation
1302 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1303 * mesa and it seems to work fine. The choice is fairly arbitrary.
1305 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1306 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1307 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1308 pipe
.StallAtPixelScoreboard
= true;
1311 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1314 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1315 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1316 pipe
.StateCacheInvalidationEnable
=
1317 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1318 pipe
.ConstantCacheInvalidationEnable
=
1319 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1320 pipe
.VFCacheInvalidationEnable
=
1321 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1322 pipe
.TextureCacheInvalidationEnable
=
1323 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1324 pipe
.InstructionCacheInvalidateEnable
=
1325 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1328 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1331 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1334 void genX(CmdPipelineBarrier
)(
1335 VkCommandBuffer commandBuffer
,
1336 VkPipelineStageFlags srcStageMask
,
1337 VkPipelineStageFlags destStageMask
,
1339 uint32_t memoryBarrierCount
,
1340 const VkMemoryBarrier
* pMemoryBarriers
,
1341 uint32_t bufferMemoryBarrierCount
,
1342 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1343 uint32_t imageMemoryBarrierCount
,
1344 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1346 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1348 /* XXX: Right now, we're really dumb and just flush whatever categories
1349 * the app asks for. One of these days we may make this a bit better
1350 * but right now that's all the hardware allows for in most areas.
1352 VkAccessFlags src_flags
= 0;
1353 VkAccessFlags dst_flags
= 0;
1355 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1356 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1357 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1360 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1361 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1362 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1365 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1366 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1367 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1368 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1369 const VkImageSubresourceRange
*range
=
1370 &pImageMemoryBarriers
[i
].subresourceRange
;
1372 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1373 transition_depth_buffer(cmd_buffer
, image
,
1374 pImageMemoryBarriers
[i
].oldLayout
,
1375 pImageMemoryBarriers
[i
].newLayout
);
1376 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1377 VkImageAspectFlags color_aspects
=
1378 anv_image_expand_aspects(image
, range
->aspectMask
);
1379 uint32_t aspect_bit
;
1381 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1382 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1383 range
->baseMipLevel
,
1384 anv_get_levelCount(image
, range
),
1385 range
->baseArrayLayer
,
1386 anv_get_layerCount(image
, range
),
1387 pImageMemoryBarriers
[i
].oldLayout
,
1388 pImageMemoryBarriers
[i
].newLayout
);
1393 cmd_buffer
->state
.pending_pipe_bits
|=
1394 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1395 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1399 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1401 VkShaderStageFlags stages
=
1402 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1404 /* In order to avoid thrash, we assume that vertex and fragment stages
1405 * always exist. In the rare case where one is missing *and* the other
1406 * uses push concstants, this may be suboptimal. However, avoiding stalls
1407 * seems more important.
1409 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1411 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1415 const unsigned push_constant_kb
= 32;
1416 #elif GEN_IS_HASWELL
1417 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1419 const unsigned push_constant_kb
= 16;
1422 const unsigned num_stages
=
1423 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1424 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1426 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1427 * units of 2KB. Incidentally, these are the same platforms that have
1428 * 32KB worth of push constant space.
1430 if (push_constant_kb
== 32)
1431 size_per_stage
&= ~1u;
1433 uint32_t kb_used
= 0;
1434 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1435 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1436 anv_batch_emit(&cmd_buffer
->batch
,
1437 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1438 alloc
._3DCommandSubOpcode
= 18 + i
;
1439 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1440 alloc
.ConstantBufferSize
= push_size
;
1442 kb_used
+= push_size
;
1445 anv_batch_emit(&cmd_buffer
->batch
,
1446 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1447 alloc
.ConstantBufferOffset
= kb_used
;
1448 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1451 cmd_buffer
->state
.push_constant_stages
= stages
;
1453 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1455 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1456 * the next 3DPRIMITIVE command after programming the
1457 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1459 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1460 * pipeline setup, we need to dirty push constants.
1462 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1465 static const struct anv_descriptor
*
1466 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1467 const struct anv_pipeline_binding
*binding
)
1469 assert(binding
->set
< MAX_SETS
);
1470 const struct anv_descriptor_set
*set
=
1471 pipe_state
->descriptors
[binding
->set
];
1472 const uint32_t offset
=
1473 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1474 return &set
->descriptors
[offset
+ binding
->index
];
1478 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1479 const struct anv_pipeline
*pipeline
,
1480 const struct anv_pipeline_binding
*binding
)
1482 assert(binding
->set
< MAX_SETS
);
1483 const struct anv_descriptor_set
*set
=
1484 pipe_state
->descriptors
[binding
->set
];
1486 uint32_t dynamic_offset_idx
=
1487 pipeline
->layout
->set
[binding
->set
].dynamic_offset_start
+
1488 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1491 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1495 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1496 gl_shader_stage stage
,
1497 struct anv_state
*bt_state
)
1499 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1500 struct anv_cmd_pipeline_state
*pipe_state
;
1501 struct anv_pipeline
*pipeline
;
1502 uint32_t bias
, state_offset
;
1505 case MESA_SHADER_COMPUTE
:
1506 pipe_state
= &cmd_buffer
->state
.compute
.base
;
1510 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
1514 pipeline
= pipe_state
->pipeline
;
1516 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1517 *bt_state
= (struct anv_state
) { 0, };
1521 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1522 if (bias
+ map
->surface_count
== 0) {
1523 *bt_state
= (struct anv_state
) { 0, };
1527 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1528 bias
+ map
->surface_count
,
1530 uint32_t *bt_map
= bt_state
->map
;
1532 if (bt_state
->map
== NULL
)
1533 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1535 if (stage
== MESA_SHADER_COMPUTE
&&
1536 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
1537 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
1538 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
1540 struct anv_state surface_state
;
1542 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1544 const enum isl_format format
=
1545 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1546 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1547 format
, bo_offset
, 12, 1);
1549 bt_map
[0] = surface_state
.offset
+ state_offset
;
1550 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1553 if (map
->surface_count
== 0)
1556 if (map
->image_count
> 0) {
1558 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1559 if (result
!= VK_SUCCESS
)
1562 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1566 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1567 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1569 struct anv_state surface_state
;
1571 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1572 /* Color attachment binding */
1573 assert(stage
== MESA_SHADER_FRAGMENT
);
1574 assert(binding
->binding
== 0);
1575 if (binding
->index
< subpass
->color_count
) {
1576 const unsigned att
=
1577 subpass
->color_attachments
[binding
->index
].attachment
;
1579 /* From the Vulkan 1.0.46 spec:
1581 * "If any color or depth/stencil attachments are
1582 * VK_ATTACHMENT_UNUSED, then no writes occur for those
1585 if (att
== VK_ATTACHMENT_UNUSED
) {
1586 surface_state
= cmd_buffer
->state
.null_surface_state
;
1588 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
1591 surface_state
= cmd_buffer
->state
.null_surface_state
;
1594 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1598 const struct anv_descriptor
*desc
=
1599 anv_descriptor_for_binding(pipe_state
, binding
);
1601 switch (desc
->type
) {
1602 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1603 /* Nothing for us to do here */
1606 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1607 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
1608 struct anv_surface_state sstate
=
1609 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
1610 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
1611 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
1612 surface_state
= sstate
.state
;
1613 assert(surface_state
.alloc_size
);
1614 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1615 binding
->plane
, sstate
);
1618 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1619 assert(stage
== MESA_SHADER_FRAGMENT
);
1620 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
1621 /* For depth and stencil input attachments, we treat it like any
1622 * old texture that a user may have bound.
1624 struct anv_surface_state sstate
=
1625 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
1626 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
1627 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
1628 surface_state
= sstate
.state
;
1629 assert(surface_state
.alloc_size
);
1630 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1631 binding
->plane
, sstate
);
1633 /* For color input attachments, we create the surface state at
1634 * vkBeginRenderPass time so that we can include aux and clear
1635 * color information.
1637 assert(binding
->input_attachment_index
< subpass
->input_count
);
1638 const unsigned subpass_att
= binding
->input_attachment_index
;
1639 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
1640 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
1644 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1645 struct anv_surface_state sstate
= (binding
->write_only
)
1646 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
1647 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
1648 surface_state
= sstate
.state
;
1649 assert(surface_state
.alloc_size
);
1650 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1651 binding
->plane
, sstate
);
1653 struct brw_image_param
*image_param
=
1654 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1656 *image_param
= desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
1657 image_param
->surface_idx
= bias
+ s
;
1661 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
1662 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
1663 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
1664 surface_state
= desc
->buffer_view
->surface_state
;
1665 assert(surface_state
.alloc_size
);
1666 add_surface_state_reloc(cmd_buffer
, surface_state
,
1667 desc
->buffer_view
->bo
,
1668 desc
->buffer_view
->offset
);
1671 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
1672 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
1673 /* Compute the offset within the buffer */
1674 uint32_t dynamic_offset
=
1675 dynamic_offset_for_binding(pipe_state
, pipeline
, binding
);
1676 uint64_t offset
= desc
->offset
+ dynamic_offset
;
1677 /* Clamp to the buffer size */
1678 offset
= MIN2(offset
, desc
->buffer
->size
);
1679 /* Clamp the range to the buffer size */
1680 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
1683 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
1684 enum isl_format format
=
1685 anv_isl_format_for_descriptor_type(desc
->type
);
1687 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1688 format
, offset
, range
, 1);
1689 add_surface_state_reloc(cmd_buffer
, surface_state
,
1691 desc
->buffer
->offset
+ offset
);
1695 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
1696 surface_state
= (binding
->write_only
)
1697 ? desc
->buffer_view
->writeonly_storage_surface_state
1698 : desc
->buffer_view
->storage_surface_state
;
1699 assert(surface_state
.alloc_size
);
1700 add_surface_state_reloc(cmd_buffer
, surface_state
,
1701 desc
->buffer_view
->bo
,
1702 desc
->buffer_view
->offset
);
1704 struct brw_image_param
*image_param
=
1705 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1707 *image_param
= desc
->buffer_view
->storage_image_param
;
1708 image_param
->surface_idx
= bias
+ s
;
1712 assert(!"Invalid descriptor type");
1716 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1718 assert(image
== map
->image_count
);
1721 anv_state_flush(cmd_buffer
->device
, *bt_state
);
1727 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1728 gl_shader_stage stage
,
1729 struct anv_state
*state
)
1731 struct anv_cmd_pipeline_state
*pipe_state
=
1732 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
1733 &cmd_buffer
->state
.gfx
.base
;
1734 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
1736 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1737 *state
= (struct anv_state
) { 0, };
1741 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1742 if (map
->sampler_count
== 0) {
1743 *state
= (struct anv_state
) { 0, };
1747 uint32_t size
= map
->sampler_count
* 16;
1748 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1750 if (state
->map
== NULL
)
1751 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1753 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1754 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1755 const struct anv_descriptor
*desc
=
1756 anv_descriptor_for_binding(pipe_state
, binding
);
1758 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1759 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1762 struct anv_sampler
*sampler
= desc
->sampler
;
1764 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1765 * happens to be zero.
1767 if (sampler
== NULL
)
1770 memcpy(state
->map
+ (s
* 16),
1771 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
1774 anv_state_flush(cmd_buffer
->device
, *state
);
1780 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1782 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
1784 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1785 pipeline
->active_stages
;
1787 VkResult result
= VK_SUCCESS
;
1788 anv_foreach_stage(s
, dirty
) {
1789 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1790 if (result
!= VK_SUCCESS
)
1792 result
= emit_binding_table(cmd_buffer
, s
,
1793 &cmd_buffer
->state
.binding_tables
[s
]);
1794 if (result
!= VK_SUCCESS
)
1798 if (result
!= VK_SUCCESS
) {
1799 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1801 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1802 if (result
!= VK_SUCCESS
)
1805 /* Re-emit state base addresses so we get the new surface state base
1806 * address before we start emitting binding tables etc.
1808 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1810 /* Re-emit all active binding tables */
1811 dirty
|= pipeline
->active_stages
;
1812 anv_foreach_stage(s
, dirty
) {
1813 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1814 if (result
!= VK_SUCCESS
) {
1815 anv_batch_set_error(&cmd_buffer
->batch
, result
);
1818 result
= emit_binding_table(cmd_buffer
, s
,
1819 &cmd_buffer
->state
.binding_tables
[s
]);
1820 if (result
!= VK_SUCCESS
) {
1821 anv_batch_set_error(&cmd_buffer
->batch
, result
);
1827 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1833 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1836 static const uint32_t sampler_state_opcodes
[] = {
1837 [MESA_SHADER_VERTEX
] = 43,
1838 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1839 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1840 [MESA_SHADER_GEOMETRY
] = 46,
1841 [MESA_SHADER_FRAGMENT
] = 47,
1842 [MESA_SHADER_COMPUTE
] = 0,
1845 static const uint32_t binding_table_opcodes
[] = {
1846 [MESA_SHADER_VERTEX
] = 38,
1847 [MESA_SHADER_TESS_CTRL
] = 39,
1848 [MESA_SHADER_TESS_EVAL
] = 40,
1849 [MESA_SHADER_GEOMETRY
] = 41,
1850 [MESA_SHADER_FRAGMENT
] = 42,
1851 [MESA_SHADER_COMPUTE
] = 0,
1854 anv_foreach_stage(s
, stages
) {
1855 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
1856 assert(binding_table_opcodes
[s
] > 0);
1858 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1859 anv_batch_emit(&cmd_buffer
->batch
,
1860 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1861 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1862 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1866 /* Always emit binding table pointers if we're asked to, since on SKL
1867 * this is what flushes push constants. */
1868 anv_batch_emit(&cmd_buffer
->batch
,
1869 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1870 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1871 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1877 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1878 VkShaderStageFlags dirty_stages
)
1880 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
1881 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
1883 static const uint32_t push_constant_opcodes
[] = {
1884 [MESA_SHADER_VERTEX
] = 21,
1885 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1886 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1887 [MESA_SHADER_GEOMETRY
] = 22,
1888 [MESA_SHADER_FRAGMENT
] = 23,
1889 [MESA_SHADER_COMPUTE
] = 0,
1892 VkShaderStageFlags flushed
= 0;
1894 anv_foreach_stage(stage
, dirty_stages
) {
1895 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
1896 assert(push_constant_opcodes
[stage
] > 0);
1898 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1899 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1901 if (anv_pipeline_has_stage(pipeline
, stage
)) {
1902 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1903 const struct brw_stage_prog_data
*prog_data
=
1904 pipeline
->shaders
[stage
]->prog_data
;
1905 const struct anv_pipeline_bind_map
*bind_map
=
1906 &pipeline
->shaders
[stage
]->bind_map
;
1908 /* The Skylake PRM contains the following restriction:
1910 * "The driver must ensure The following case does not occur
1911 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
1912 * buffer 3 read length equal to zero committed followed by a
1913 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
1916 * To avoid this, we program the buffers in the highest slots.
1917 * This way, slot 0 is only used if slot 3 is also used.
1921 for (int i
= 3; i
>= 0; i
--) {
1922 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
1923 if (range
->length
== 0)
1926 const unsigned surface
=
1927 prog_data
->binding_table
.ubo_start
+ range
->block
;
1929 assert(surface
<= bind_map
->surface_count
);
1930 const struct anv_pipeline_binding
*binding
=
1931 &bind_map
->surface_to_descriptor
[surface
];
1933 const struct anv_descriptor
*desc
=
1934 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
1936 struct anv_address read_addr
;
1938 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
1939 read_len
= MIN2(range
->length
,
1940 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
1941 read_addr
= (struct anv_address
) {
1942 .bo
= desc
->buffer_view
->bo
,
1943 .offset
= desc
->buffer_view
->offset
+
1947 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
1949 uint32_t dynamic_offset
=
1950 dynamic_offset_for_binding(&gfx_state
->base
,
1952 uint32_t buf_offset
=
1953 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
1954 uint32_t buf_range
=
1955 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
1957 read_len
= MIN2(range
->length
,
1958 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
1959 read_addr
= (struct anv_address
) {
1960 .bo
= desc
->buffer
->bo
,
1961 .offset
= desc
->buffer
->offset
+ buf_offset
+
1967 c
.ConstantBody
.Buffer
[n
] = read_addr
;
1968 c
.ConstantBody
.ReadLength
[n
] = read_len
;
1973 struct anv_state state
=
1974 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1976 if (state
.alloc_size
> 0) {
1977 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
1978 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
1979 .offset
= state
.offset
,
1981 c
.ConstantBody
.ReadLength
[n
] =
1982 DIV_ROUND_UP(state
.alloc_size
, 32);
1985 /* For Ivy Bridge, the push constants packets have a different
1986 * rule that would require us to iterate in the other direction
1987 * and possibly mess around with dynamic state base address.
1988 * Don't bother; just emit regular push constants at n = 0.
1990 struct anv_state state
=
1991 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1993 if (state
.alloc_size
> 0) {
1994 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
1995 c
.ConstantBody
.ReadLength
[0] =
1996 DIV_ROUND_UP(state
.alloc_size
, 32);
2002 flushed
|= mesa_to_vk_shader_stage(stage
);
2005 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2009 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2011 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2014 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
2016 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2018 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2020 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2023 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2024 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2026 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2027 GENX(3DSTATE_VERTEX_BUFFERS
));
2029 for_each_bit(vb
, vb_emit
) {
2030 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2031 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2033 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2034 .VertexBufferIndex
= vb
,
2037 .MemoryObjectControlState
= GENX(MOCS
),
2039 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
2040 /* Our implementation of VK_KHR_multiview uses instancing to draw
2041 * the different views. If the client asks for instancing, we
2042 * need to use the Instance Data Step Rate to ensure that we
2043 * repeat the client's per-instance data once for each view.
2045 .InstanceDataStepRate
= anv_subpass_view_count(pipeline
->subpass
),
2046 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2049 .AddressModifyEnable
= true,
2050 .BufferPitch
= pipeline
->binding_stride
[vb
],
2051 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
2054 .BufferSize
= buffer
->size
- offset
2056 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
2060 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2065 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
2067 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2068 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2070 /* The exact descriptor layout is pulled from the pipeline, so we need
2071 * to re-emit binding tables on every pipeline change.
2073 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2075 /* If the pipeline changed, we may need to re-allocate push constant
2078 cmd_buffer_alloc_push_constants(cmd_buffer
);
2082 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2083 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2084 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2086 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2087 * stall needs to be sent just prior to any 3DSTATE_VS,
2088 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2089 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2090 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2091 * PIPE_CONTROL needs to be sent before any combination of VS
2092 * associated 3DSTATE."
2094 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2095 pc
.DepthStallEnable
= true;
2096 pc
.PostSyncOperation
= WriteImmediateData
;
2098 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2103 /* Render targets live in the same binding table as fragment descriptors */
2104 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2105 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2107 /* We emit the binding tables and sampler tables first, then emit push
2108 * constants and then finally emit binding table and sampler table
2109 * pointers. It has to happen in this order, since emitting the binding
2110 * tables may change the push constants (in case of storage images). After
2111 * emitting push constants, on SKL+ we have to emit the corresponding
2112 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2115 if (cmd_buffer
->state
.descriptors_dirty
)
2116 dirty
= flush_descriptor_sets(cmd_buffer
);
2118 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2119 /* Because we're pushing UBOs, we have to push whenever either
2120 * descriptors or push constants is dirty.
2122 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2123 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2124 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2128 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2130 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2131 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2133 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2134 ANV_CMD_DIRTY_PIPELINE
)) {
2135 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2136 pipeline
->depth_clamp_enable
);
2139 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
2140 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2142 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2144 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2148 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2149 struct anv_bo
*bo
, uint32_t offset
,
2150 uint32_t size
, uint32_t index
)
2152 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2153 GENX(3DSTATE_VERTEX_BUFFERS
));
2155 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2156 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2157 .VertexBufferIndex
= index
,
2158 .AddressModifyEnable
= true,
2161 .MemoryObjectControlState
= GENX(MOCS
),
2162 .BufferStartingAddress
= { bo
, offset
},
2165 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2166 .BufferStartingAddress
= { bo
, offset
},
2167 .EndAddress
= { bo
, offset
+ size
},
2173 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2174 struct anv_bo
*bo
, uint32_t offset
)
2176 emit_vertex_bo(cmd_buffer
, bo
, offset
, 8, ANV_SVGS_VB_INDEX
);
2180 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2181 uint32_t base_vertex
, uint32_t base_instance
)
2183 struct anv_state id_state
=
2184 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2186 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2187 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2189 anv_state_flush(cmd_buffer
->device
, id_state
);
2191 emit_base_vertex_instance_bo(cmd_buffer
,
2192 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
, id_state
.offset
);
2196 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2198 struct anv_state state
=
2199 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2201 ((uint32_t *)state
.map
)[0] = draw_index
;
2203 anv_state_flush(cmd_buffer
->device
, state
);
2205 emit_vertex_bo(cmd_buffer
,
2206 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2207 state
.offset
, 4, ANV_DRAWID_VB_INDEX
);
2211 VkCommandBuffer commandBuffer
,
2212 uint32_t vertexCount
,
2213 uint32_t instanceCount
,
2214 uint32_t firstVertex
,
2215 uint32_t firstInstance
)
2217 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2218 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2219 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2221 if (anv_batch_has_error(&cmd_buffer
->batch
))
2224 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2226 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2227 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2228 if (vs_prog_data
->uses_drawid
)
2229 emit_draw_index(cmd_buffer
, 0);
2231 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2232 * different views. We need to multiply instanceCount by the view count.
2234 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2236 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2237 prim
.VertexAccessType
= SEQUENTIAL
;
2238 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2239 prim
.VertexCountPerInstance
= vertexCount
;
2240 prim
.StartVertexLocation
= firstVertex
;
2241 prim
.InstanceCount
= instanceCount
;
2242 prim
.StartInstanceLocation
= firstInstance
;
2243 prim
.BaseVertexLocation
= 0;
2247 void genX(CmdDrawIndexed
)(
2248 VkCommandBuffer commandBuffer
,
2249 uint32_t indexCount
,
2250 uint32_t instanceCount
,
2251 uint32_t firstIndex
,
2252 int32_t vertexOffset
,
2253 uint32_t firstInstance
)
2255 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2256 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2257 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2259 if (anv_batch_has_error(&cmd_buffer
->batch
))
2262 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2264 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2265 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2266 if (vs_prog_data
->uses_drawid
)
2267 emit_draw_index(cmd_buffer
, 0);
2269 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2270 * different views. We need to multiply instanceCount by the view count.
2272 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2274 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2275 prim
.VertexAccessType
= RANDOM
;
2276 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2277 prim
.VertexCountPerInstance
= indexCount
;
2278 prim
.StartVertexLocation
= firstIndex
;
2279 prim
.InstanceCount
= instanceCount
;
2280 prim
.StartInstanceLocation
= firstInstance
;
2281 prim
.BaseVertexLocation
= vertexOffset
;
2285 /* Auto-Draw / Indirect Registers */
2286 #define GEN7_3DPRIM_END_OFFSET 0x2420
2287 #define GEN7_3DPRIM_START_VERTEX 0x2430
2288 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2289 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2290 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2291 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2293 /* MI_MATH only exists on Haswell+ */
2294 #if GEN_IS_HASWELL || GEN_GEN >= 8
2297 mi_alu(uint32_t opcode
, uint32_t op1
, uint32_t op2
)
2299 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
2300 .ALUOpcode
= opcode
,
2306 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
2311 #define CS_GPR(n) (0x2600 + (n) * 8)
2313 /* Emit dwords to multiply GPR0 by N */
2315 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2317 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2319 #define append_alu(opcode, operand1, operand2) \
2320 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2323 unsigned top_bit
= 31 - __builtin_clz(N
);
2324 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2325 /* We get our initial data in GPR0 and we write the final data out to
2326 * GPR0 but we use GPR1 as our scratch register.
2328 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2329 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2331 /* Shift the current value left by 1 */
2332 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2333 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2334 append_alu(MI_ALU_ADD
, 0, 0);
2337 /* Store ACCU to R1 and add R0 to R1 */
2338 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2339 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2340 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2341 append_alu(MI_ALU_ADD
, 0, 0);
2344 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2351 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2353 uint32_t num_dwords
;
2354 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2356 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2357 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2360 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2363 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2364 struct anv_buffer
*buffer
, uint64_t offset
,
2367 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2368 struct anv_bo
*bo
= buffer
->bo
;
2369 uint32_t bo_offset
= buffer
->offset
+ offset
;
2371 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
2373 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2374 if (view_count
> 1) {
2375 #if GEN_IS_HASWELL || GEN_GEN >= 8
2376 emit_lrm(batch
, CS_GPR(0), bo
, bo_offset
+ 4);
2377 emit_mul_gpr0(batch
, view_count
);
2378 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2380 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2381 "MI_MATH is not supported on Ivy Bridge");
2382 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2385 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2388 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
2391 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
2392 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
2394 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
2395 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2399 void genX(CmdDrawIndirect
)(
2400 VkCommandBuffer commandBuffer
,
2402 VkDeviceSize offset
,
2406 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2407 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2408 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2409 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2411 if (anv_batch_has_error(&cmd_buffer
->batch
))
2414 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2416 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2417 struct anv_bo
*bo
= buffer
->bo
;
2418 uint32_t bo_offset
= buffer
->offset
+ offset
;
2420 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2421 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
2422 if (vs_prog_data
->uses_drawid
)
2423 emit_draw_index(cmd_buffer
, i
);
2425 load_indirect_parameters(cmd_buffer
, buffer
, offset
, false);
2427 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2428 prim
.IndirectParameterEnable
= true;
2429 prim
.VertexAccessType
= SEQUENTIAL
;
2430 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2437 void genX(CmdDrawIndexedIndirect
)(
2438 VkCommandBuffer commandBuffer
,
2440 VkDeviceSize offset
,
2444 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2445 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2446 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2447 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2449 if (anv_batch_has_error(&cmd_buffer
->batch
))
2452 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2454 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2455 struct anv_bo
*bo
= buffer
->bo
;
2456 uint32_t bo_offset
= buffer
->offset
+ offset
;
2458 /* TODO: We need to stomp base vertex to 0 somehow */
2459 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2460 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
2461 if (vs_prog_data
->uses_drawid
)
2462 emit_draw_index(cmd_buffer
, i
);
2464 load_indirect_parameters(cmd_buffer
, buffer
, offset
, true);
2466 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2467 prim
.IndirectParameterEnable
= true;
2468 prim
.VertexAccessType
= RANDOM
;
2469 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2477 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2479 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2480 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2483 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2484 if (result
!= VK_SUCCESS
) {
2485 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2487 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2488 if (result
!= VK_SUCCESS
)
2491 /* Re-emit state base addresses so we get the new surface state base
2492 * address before we start emitting binding tables etc.
2494 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2496 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2497 if (result
!= VK_SUCCESS
) {
2498 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2503 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
2504 if (result
!= VK_SUCCESS
) {
2505 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2509 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
2510 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2511 .BindingTablePointer
= surfaces
.offset
,
2512 .SamplerStatePointer
= samplers
.offset
,
2514 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
2516 struct anv_state state
=
2517 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
2518 pipeline
->interface_descriptor_data
,
2519 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
2522 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
2523 anv_batch_emit(&cmd_buffer
->batch
,
2524 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
2525 mid
.InterfaceDescriptorTotalLength
= size
;
2526 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
2533 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2535 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2536 MAYBE_UNUSED VkResult result
;
2538 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
2540 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2542 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
2544 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
2545 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
2547 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
2548 * the only bits that are changed are scoreboard related: Scoreboard
2549 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
2550 * these scoreboard related states, a MEDIA_STATE_FLUSH is
2553 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2554 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2556 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2559 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
2560 cmd_buffer
->state
.compute
.pipeline_dirty
) {
2561 /* FIXME: figure out descriptors for gen7 */
2562 result
= flush_compute_descriptor_set(cmd_buffer
);
2563 if (result
!= VK_SUCCESS
)
2566 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
2569 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
2570 struct anv_state push_state
=
2571 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
2573 if (push_state
.alloc_size
) {
2574 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
2575 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
2576 curbe
.CURBEDataStartAddress
= push_state
.offset
;
2581 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
2583 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2589 verify_cmd_parser(const struct anv_device
*device
,
2590 int required_version
,
2591 const char *function
)
2593 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
2594 return vk_errorf(device
->instance
, device
->instance
,
2595 VK_ERROR_FEATURE_NOT_PRESENT
,
2596 "cmd parser version %d is required for %s",
2597 required_version
, function
);
2605 void genX(CmdDispatch
)(
2606 VkCommandBuffer commandBuffer
,
2611 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2612 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2613 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
2615 if (anv_batch_has_error(&cmd_buffer
->batch
))
2618 if (prog_data
->uses_num_work_groups
) {
2619 struct anv_state state
=
2620 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
2621 uint32_t *sizes
= state
.map
;
2625 anv_state_flush(cmd_buffer
->device
, state
);
2626 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
2627 cmd_buffer
->state
.num_workgroups_bo
=
2628 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
;
2631 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2633 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
2634 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2635 ggw
.ThreadDepthCounterMaximum
= 0;
2636 ggw
.ThreadHeightCounterMaximum
= 0;
2637 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2638 ggw
.ThreadGroupIDXDimension
= x
;
2639 ggw
.ThreadGroupIDYDimension
= y
;
2640 ggw
.ThreadGroupIDZDimension
= z
;
2641 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2642 ggw
.BottomExecutionMask
= 0xffffffff;
2645 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2648 #define GPGPU_DISPATCHDIMX 0x2500
2649 #define GPGPU_DISPATCHDIMY 0x2504
2650 #define GPGPU_DISPATCHDIMZ 0x2508
2652 void genX(CmdDispatchIndirect
)(
2653 VkCommandBuffer commandBuffer
,
2655 VkDeviceSize offset
)
2657 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2658 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2659 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2660 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
2661 struct anv_bo
*bo
= buffer
->bo
;
2662 uint32_t bo_offset
= buffer
->offset
+ offset
;
2663 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2666 /* Linux 4.4 added command parser version 5 which allows the GPGPU
2667 * indirect dispatch registers to be written.
2669 if (verify_cmd_parser(cmd_buffer
->device
, 5,
2670 "vkCmdDispatchIndirect") != VK_SUCCESS
)
2674 if (prog_data
->uses_num_work_groups
) {
2675 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
2676 cmd_buffer
->state
.num_workgroups_bo
= bo
;
2679 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2681 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
2682 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
2683 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
2686 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
2687 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
2688 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
2689 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
2691 /* Load compute_dispatch_indirect_x_size into SRC0 */
2692 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
2694 /* predicate = (compute_dispatch_indirect_x_size == 0); */
2695 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2696 mip
.LoadOperation
= LOAD_LOAD
;
2697 mip
.CombineOperation
= COMBINE_SET
;
2698 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2701 /* Load compute_dispatch_indirect_y_size into SRC0 */
2702 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
2704 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
2705 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2706 mip
.LoadOperation
= LOAD_LOAD
;
2707 mip
.CombineOperation
= COMBINE_OR
;
2708 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2711 /* Load compute_dispatch_indirect_z_size into SRC0 */
2712 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
2714 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
2715 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2716 mip
.LoadOperation
= LOAD_LOAD
;
2717 mip
.CombineOperation
= COMBINE_OR
;
2718 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2721 /* predicate = !predicate; */
2722 #define COMPARE_FALSE 1
2723 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2724 mip
.LoadOperation
= LOAD_LOADINV
;
2725 mip
.CombineOperation
= COMBINE_OR
;
2726 mip
.CompareOperation
= COMPARE_FALSE
;
2730 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
2731 ggw
.IndirectParameterEnable
= true;
2732 ggw
.PredicateEnable
= GEN_GEN
<= 7;
2733 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2734 ggw
.ThreadDepthCounterMaximum
= 0;
2735 ggw
.ThreadHeightCounterMaximum
= 0;
2736 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2737 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2738 ggw
.BottomExecutionMask
= 0xffffffff;
2741 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2745 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
2748 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
2750 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
2753 #if GEN_GEN >= 8 && GEN_GEN < 10
2754 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
2756 * Software must clear the COLOR_CALC_STATE Valid field in
2757 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
2758 * with Pipeline Select set to GPGPU.
2760 * The internal hardware docs recommend the same workaround for Gen9
2763 if (pipeline
== GPGPU
)
2764 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
2767 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
2768 * PIPELINE_SELECT [DevBWR+]":
2772 * Software must ensure all the write caches are flushed through a
2773 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
2774 * command to invalidate read only caches prior to programming
2775 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
2777 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2778 pc
.RenderTargetCacheFlushEnable
= true;
2779 pc
.DepthCacheFlushEnable
= true;
2780 pc
.DCFlushEnable
= true;
2781 pc
.PostSyncOperation
= NoWrite
;
2782 pc
.CommandStreamerStallEnable
= true;
2785 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2786 pc
.TextureCacheInvalidationEnable
= true;
2787 pc
.ConstantCacheInvalidationEnable
= true;
2788 pc
.StateCacheInvalidationEnable
= true;
2789 pc
.InstructionCacheInvalidateEnable
= true;
2790 pc
.PostSyncOperation
= NoWrite
;
2793 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2797 ps
.PipelineSelection
= pipeline
;
2801 if (devinfo
->is_geminilake
) {
2804 * "This chicken bit works around a hardware issue with barrier logic
2805 * encountered when switching between GPGPU and 3D pipelines. To
2806 * workaround the issue, this mode bit should be set after a pipeline
2810 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
2812 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
2813 : GLK_BARRIER_MODE_3D_HULL
,
2814 .GLKBarrierModeMask
= 1);
2815 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
2819 cmd_buffer
->state
.current_pipeline
= pipeline
;
2823 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
2825 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
2829 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
2831 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
2835 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
2840 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
2842 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
2843 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
2844 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
2845 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
2846 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
2847 * Depth Flush Bit set, followed by another pipelined depth stall
2848 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
2849 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
2850 * via a preceding MI_FLUSH)."
2852 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2853 pipe
.DepthStallEnable
= true;
2855 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2856 pipe
.DepthCacheFlushEnable
= true;
2858 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2859 pipe
.DepthStallEnable
= true;
2864 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
2866 struct anv_device
*device
= cmd_buffer
->device
;
2867 const struct anv_image_view
*iview
=
2868 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2869 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
2871 /* FIXME: Width and Height are wrong */
2873 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
2875 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
2876 device
->isl_dev
.ds
.size
/ 4);
2880 struct isl_depth_stencil_hiz_emit_info info
= {
2881 .mocs
= device
->default_mocs
,
2885 info
.view
= &iview
->planes
[0].isl
;
2887 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
2888 uint32_t depth_plane
=
2889 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
2890 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
2892 info
.depth_surf
= &surface
->isl
;
2894 info
.depth_address
=
2895 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2896 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
2897 image
->planes
[depth_plane
].bo
,
2898 image
->planes
[depth_plane
].bo_offset
+
2902 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.attachment
;
2903 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
2904 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
2905 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
2908 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2909 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
2910 image
->planes
[depth_plane
].bo
,
2911 image
->planes
[depth_plane
].bo_offset
+
2912 image
->planes
[depth_plane
].aux_surface
.offset
);
2914 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
2918 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
2919 uint32_t stencil_plane
=
2920 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
2921 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
2923 info
.stencil_surf
= &surface
->isl
;
2925 info
.stencil_address
=
2926 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2927 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
2928 image
->planes
[stencil_plane
].bo
,
2929 image
->planes
[stencil_plane
].bo_offset
+ surface
->offset
);
2932 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
2934 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
2939 * @brief Perform any layout transitions required at the beginning and/or end
2940 * of the current subpass for depth buffers.
2942 * TODO: Consider preprocessing the attachment reference array at render pass
2943 * create time to determine if no layout transition is needed at the
2944 * beginning and/or end of each subpass.
2946 * @param cmd_buffer The command buffer the transition is happening within.
2947 * @param subpass_end If true, marks that the transition is happening at the
2948 * end of the subpass.
2951 cmd_buffer_subpass_transition_layouts(struct anv_cmd_buffer
* const cmd_buffer
,
2952 const bool subpass_end
)
2954 /* We need a non-NULL command buffer. */
2957 const struct anv_cmd_state
* const cmd_state
= &cmd_buffer
->state
;
2958 const struct anv_subpass
* const subpass
= cmd_state
->subpass
;
2960 /* This function must be called within a subpass. */
2963 /* If there are attachment references, the array shouldn't be NULL.
2965 if (subpass
->attachment_count
> 0)
2966 assert(subpass
->attachments
);
2968 /* Iterate over the array of attachment references. */
2969 for (const VkAttachmentReference
*att_ref
= subpass
->attachments
;
2970 att_ref
< subpass
->attachments
+ subpass
->attachment_count
; att_ref
++) {
2972 /* If the attachment is unused, we can't perform a layout transition. */
2973 if (att_ref
->attachment
== VK_ATTACHMENT_UNUSED
)
2976 /* This attachment index shouldn't go out of bounds. */
2977 assert(att_ref
->attachment
< cmd_state
->pass
->attachment_count
);
2979 const struct anv_render_pass_attachment
* const att_desc
=
2980 &cmd_state
->pass
->attachments
[att_ref
->attachment
];
2981 struct anv_attachment_state
* const att_state
=
2982 &cmd_buffer
->state
.attachments
[att_ref
->attachment
];
2984 /* The attachment should not be used in a subpass after its last. */
2985 assert(att_desc
->last_subpass_idx
>= anv_get_subpass_id(cmd_state
));
2987 if (subpass_end
&& anv_get_subpass_id(cmd_state
) <
2988 att_desc
->last_subpass_idx
) {
2989 /* We're calling this function on a buffer twice in one subpass and
2990 * this is not the last use of the buffer. The layout should not have
2991 * changed from the first call and no transition is necessary.
2993 assert(att_state
->current_layout
== att_ref
->layout
||
2994 att_state
->current_layout
==
2995 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
2999 /* The attachment index must be less than the number of attachments
3000 * within the framebuffer.
3002 assert(att_ref
->attachment
< cmd_state
->framebuffer
->attachment_count
);
3004 const struct anv_image_view
* const iview
=
3005 cmd_state
->framebuffer
->attachments
[att_ref
->attachment
];
3006 const struct anv_image
* const image
= iview
->image
;
3008 /* Get the appropriate target layout for this attachment. */
3009 VkImageLayout target_layout
;
3011 /* A resolve is necessary before use as an input attachment if the clear
3012 * color or auxiliary buffer usage isn't supported by the sampler.
3014 const bool input_needs_resolve
=
3015 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3016 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3018 target_layout
= att_desc
->final_layout
;
3019 } else if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3020 !input_needs_resolve
) {
3021 /* Layout transitions before the final only help to enable sampling as
3022 * an input attachment. If the input attachment supports sampling
3023 * using the auxiliary surface, we can skip such transitions by making
3024 * the target layout one that is CCS-aware.
3026 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3028 target_layout
= att_ref
->layout
;
3031 /* Perform the layout transition. */
3032 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3033 transition_depth_buffer(cmd_buffer
, image
,
3034 att_state
->current_layout
, target_layout
);
3035 att_state
->aux_usage
=
3036 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3037 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3038 } else if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3039 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3040 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3041 iview
->planes
[0].isl
.base_level
, 1,
3042 iview
->planes
[0].isl
.base_array_layer
,
3043 iview
->planes
[0].isl
.array_len
,
3044 att_state
->current_layout
, target_layout
);
3047 att_state
->current_layout
= target_layout
;
3051 /* Update the clear value dword(s) in surface state objects or the fast clear
3052 * state buffer entry for the color attachments used in this subpass.
3055 cmd_buffer_subpass_sync_fast_clear_values(struct anv_cmd_buffer
*cmd_buffer
)
3057 assert(cmd_buffer
&& cmd_buffer
->state
.subpass
);
3059 const struct anv_cmd_state
*state
= &cmd_buffer
->state
;
3061 /* Iterate through every color attachment used in this subpass. */
3062 for (uint32_t i
= 0; i
< state
->subpass
->color_count
; ++i
) {
3064 /* The attachment should be one of the attachments described in the
3065 * render pass and used in the subpass.
3067 const uint32_t a
= state
->subpass
->color_attachments
[i
].attachment
;
3068 if (a
== VK_ATTACHMENT_UNUSED
)
3071 assert(a
< state
->pass
->attachment_count
);
3073 /* Store some information regarding this attachment. */
3074 const struct anv_attachment_state
*att_state
= &state
->attachments
[a
];
3075 const struct anv_image_view
*iview
= state
->framebuffer
->attachments
[a
];
3076 const struct anv_render_pass_attachment
*rp_att
=
3077 &state
->pass
->attachments
[a
];
3079 if (att_state
->aux_usage
== ISL_AUX_USAGE_NONE
)
3082 /* The fast clear state entry must be updated if a fast clear is going to
3083 * happen. The surface state must be updated if the clear value from a
3084 * prior fast clear may be needed.
3086 if (att_state
->pending_clear_aspects
&& att_state
->fast_clear
) {
3087 /* Update the fast clear state entry. */
3088 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3090 VK_IMAGE_ASPECT_COLOR_BIT
,
3091 iview
->planes
[0].isl
.base_level
,
3092 true /* copy from ss */);
3094 /* Fast-clears impact whether or not a resolve will be necessary. */
3095 if (iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_CCS_E
&&
3096 att_state
->clear_color_is_zero
) {
3097 /* This image always has the auxiliary buffer enabled. We can mark
3098 * the subresource as not needing a resolve because the clear color
3099 * will match what's in every RENDER_SURFACE_STATE object when it's
3100 * being used for sampling.
3102 genX(set_image_needs_resolve
)(cmd_buffer
, iview
->image
,
3103 VK_IMAGE_ASPECT_COLOR_BIT
,
3104 iview
->planes
[0].isl
.base_level
,
3107 genX(set_image_needs_resolve
)(cmd_buffer
, iview
->image
,
3108 VK_IMAGE_ASPECT_COLOR_BIT
,
3109 iview
->planes
[0].isl
.base_level
,
3112 } else if (rp_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
3113 /* The attachment may have been fast-cleared in a previous render
3114 * pass and the value is needed now. Update the surface state(s).
3116 * TODO: Do this only once per render pass instead of every subpass.
3118 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3120 VK_IMAGE_ASPECT_COLOR_BIT
,
3121 iview
->planes
[0].isl
.base_level
,
3122 false /* copy to ss */);
3124 if (need_input_attachment_state(rp_att
) &&
3125 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3126 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3128 VK_IMAGE_ASPECT_COLOR_BIT
,
3129 iview
->planes
[0].isl
.base_level
,
3130 false /* copy to ss */);
3138 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
3139 struct anv_subpass
*subpass
)
3141 cmd_buffer
->state
.subpass
= subpass
;
3143 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3145 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3146 * different views. If the client asks for instancing, we need to use the
3147 * Instance Data Step Rate to ensure that we repeat the client's
3148 * per-instance data once for each view. Since this bit is in
3149 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3153 cmd_buffer
->state
.vb_dirty
|= ~0;
3155 /* Perform transitions to the subpass layout before any writes have
3158 cmd_buffer_subpass_transition_layouts(cmd_buffer
, false);
3160 /* Update clear values *after* performing automatic layout transitions.
3161 * This ensures that transitions from the UNDEFINED layout have had a chance
3162 * to populate the clear value buffer with the correct values for the
3163 * LOAD_OP_LOAD loadOp and that the fast-clears will update the buffer
3164 * without the aforementioned layout transition overwriting the fast-clear
3167 cmd_buffer_subpass_sync_fast_clear_values(cmd_buffer
);
3169 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3171 anv_cmd_buffer_clear_subpass(cmd_buffer
);
3174 void genX(CmdBeginRenderPass
)(
3175 VkCommandBuffer commandBuffer
,
3176 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3177 VkSubpassContents contents
)
3179 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3180 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3181 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3183 cmd_buffer
->state
.framebuffer
= framebuffer
;
3184 cmd_buffer
->state
.pass
= pass
;
3185 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3187 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3189 /* If we failed to setup the attachments we should not try to go further */
3190 if (result
!= VK_SUCCESS
) {
3191 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3195 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3197 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
3199 cmd_buffer
->state
.pending_pipe_bits
|=
3200 cmd_buffer
->state
.pass
->subpass_flushes
[0];
3203 void genX(CmdNextSubpass
)(
3204 VkCommandBuffer commandBuffer
,
3205 VkSubpassContents contents
)
3207 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3209 if (anv_batch_has_error(&cmd_buffer
->batch
))
3212 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3214 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3216 /* Perform transitions to the final layout after all writes have occurred.
3218 cmd_buffer_subpass_transition_layouts(cmd_buffer
, true);
3220 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
3222 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3223 cmd_buffer
->state
.pending_pipe_bits
|=
3224 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3227 void genX(CmdEndRenderPass
)(
3228 VkCommandBuffer commandBuffer
)
3230 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3232 if (anv_batch_has_error(&cmd_buffer
->batch
))
3235 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3237 /* Perform transitions to the final layout after all writes have occurred.
3239 cmd_buffer_subpass_transition_layouts(cmd_buffer
, true);
3241 cmd_buffer
->state
.pending_pipe_bits
|=
3242 cmd_buffer
->state
.pass
->subpass_flushes
[cmd_buffer
->state
.pass
->subpass_count
];
3244 cmd_buffer
->state
.hiz_enabled
= false;
3247 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
3250 /* Remove references to render pass specific state. This enables us to
3251 * detect whether or not we're in a renderpass.
3253 cmd_buffer
->state
.framebuffer
= NULL
;
3254 cmd_buffer
->state
.pass
= NULL
;
3255 cmd_buffer
->state
.subpass
= NULL
;