2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "common/gen_l3_config.h"
31 #include "genxml/gen_macros.h"
32 #include "genxml/genX_pack.h"
35 emit_lrm(struct anv_batch
*batch
,
36 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
54 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
56 struct anv_device
*device
= cmd_buffer
->device
;
58 /* Emit a render target cache flush.
60 * This isn't documented anywhere in the PRM. However, it seems to be
61 * necessary prior to changing the surface state base adress. Without
62 * this, we get GPU hangs when using multi-level command buffers which
63 * clear depth, reset state base address, and then go render stuff.
65 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
66 pc
.RenderTargetCacheFlushEnable
= true;
69 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
70 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
71 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
72 sba
.GeneralStateBaseAddressModifyEnable
= true;
74 sba
.SurfaceStateBaseAddress
=
75 anv_cmd_buffer_surface_base_address(cmd_buffer
);
76 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
77 sba
.SurfaceStateBaseAddressModifyEnable
= true;
79 sba
.DynamicStateBaseAddress
=
80 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
81 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
82 sba
.DynamicStateBaseAddressModifyEnable
= true;
84 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
85 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
86 sba
.IndirectObjectBaseAddressModifyEnable
= true;
88 sba
.InstructionBaseAddress
=
89 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
90 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
91 sba
.InstructionBaseAddressModifyEnable
= true;
94 /* Broadwell requires that we specify a buffer size for a bunch of
95 * these fields. However, since we will be growing the BO's live, we
96 * just set them all to the maximum.
98 sba
.GeneralStateBufferSize
= 0xfffff;
99 sba
.GeneralStateBufferSizeModifyEnable
= true;
100 sba
.DynamicStateBufferSize
= 0xfffff;
101 sba
.DynamicStateBufferSizeModifyEnable
= true;
102 sba
.IndirectObjectBufferSize
= 0xfffff;
103 sba
.IndirectObjectBufferSizeModifyEnable
= true;
104 sba
.InstructionBufferSize
= 0xfffff;
105 sba
.InstructionBuffersizeModifyEnable
= true;
109 /* After re-setting the surface state base address, we have to do some
110 * cache flusing so that the sampler engine will pick up the new
111 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
112 * Shared Function > 3D Sampler > State > State Caching (page 96):
114 * Coherency with system memory in the state cache, like the texture
115 * cache is handled partially by software. It is expected that the
116 * command stream or shader will issue Cache Flush operation or
117 * Cache_Flush sampler message to ensure that the L1 cache remains
118 * coherent with system memory.
122 * Whenever the value of the Dynamic_State_Base_Addr,
123 * Surface_State_Base_Addr are altered, the L1 state cache must be
124 * invalidated to ensure the new surface or sampler state is fetched
125 * from system memory.
127 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
128 * which, according the PIPE_CONTROL instruction documentation in the
131 * Setting this bit is independent of any other bit in this packet.
132 * This bit controls the invalidation of the L1 and L2 state caches
133 * at the top of the pipe i.e. at the parsing time.
135 * Unfortunately, experimentation seems to indicate that state cache
136 * invalidation through a PIPE_CONTROL does nothing whatsoever in
137 * regards to surface state and binding tables. In stead, it seems that
138 * invalidating the texture cache is what is actually needed.
140 * XXX: As far as we have been able to determine through
141 * experimentation, shows that flush the texture cache appears to be
142 * sufficient. The theory here is that all of the sampling/rendering
143 * units cache the binding table in the texture cache. However, we have
144 * yet to be able to actually confirm this.
146 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
147 pc
.TextureCacheInvalidationEnable
= true;
152 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
153 struct anv_state state
,
154 struct anv_bo
*bo
, uint32_t offset
)
156 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
158 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
159 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
163 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
164 const struct anv_image_view
*iview
,
165 enum isl_aux_usage aux_usage
,
166 struct anv_state state
)
168 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
170 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
171 state
.offset
+ isl_dev
->ss
.addr_offset
,
172 iview
->bo
, iview
->offset
);
174 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
175 uint32_t aux_offset
= iview
->offset
+ iview
->image
->aux_surface
.offset
;
177 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
178 * used to store other information. This should be ok, however, because
179 * surface buffer addresses are always 4K page alinged.
181 assert((aux_offset
& 0xfff) == 0);
182 uint32_t *aux_addr_dw
= state
.map
+ isl_dev
->ss
.aux_addr_offset
;
183 aux_offset
+= *aux_addr_dw
& 0xfff;
185 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
186 state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
187 iview
->bo
, aux_offset
);
192 color_is_zero_one(VkClearColorValue value
, enum isl_format format
)
194 if (isl_format_has_int_channel(format
)) {
195 for (unsigned i
= 0; i
< 4; i
++) {
196 if (value
.int32
[i
] != 0 && value
.int32
[i
] != 1)
200 for (unsigned i
= 0; i
< 4; i
++) {
201 if (value
.float32
[i
] != 0.0f
&& value
.float32
[i
] != 1.0f
)
210 color_attachment_compute_aux_usage(struct anv_device
*device
,
211 struct anv_attachment_state
*att_state
,
212 struct anv_image_view
*iview
,
213 VkRect2D render_area
,
214 union isl_color_value
*fast_clear_color
)
216 if (iview
->image
->aux_surface
.isl
.size
== 0) {
217 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
218 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
219 att_state
->fast_clear
= false;
223 assert(iview
->image
->aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
225 att_state
->clear_color_is_zero_one
=
226 color_is_zero_one(att_state
->clear_value
.color
, iview
->isl
.format
);
228 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
229 /* Start off assuming fast clears are possible */
230 att_state
->fast_clear
= true;
232 /* Potentially, we could do partial fast-clears but doing so has crazy
233 * alignment restrictions. It's easier to just restrict to full size
234 * fast clears for now.
236 if (render_area
.offset
.x
!= 0 ||
237 render_area
.offset
.y
!= 0 ||
238 render_area
.extent
.width
!= iview
->extent
.width
||
239 render_area
.extent
.height
!= iview
->extent
.height
)
240 att_state
->fast_clear
= false;
243 /* On gen7, we can't do multi-LOD or multi-layer fast-clears. We
244 * technically can, but it comes with crazy restrictions that we
245 * don't want to deal with now.
247 if (iview
->isl
.base_level
> 0 ||
248 iview
->isl
.base_array_layer
> 0 ||
249 iview
->isl
.array_len
> 1)
250 att_state
->fast_clear
= false;
253 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
254 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
255 att_state
->fast_clear
= false;
257 if (att_state
->fast_clear
) {
258 memcpy(fast_clear_color
->u32
, att_state
->clear_value
.color
.uint32
,
259 sizeof(fast_clear_color
->u32
));
262 att_state
->fast_clear
= false;
265 if (isl_format_supports_lossless_compression(&device
->info
,
266 iview
->isl
.format
)) {
267 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
268 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_E
;
269 } else if (att_state
->fast_clear
) {
270 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
272 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
274 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
275 * setting is only allowed if Surface Format supported for Fast
276 * Clear. In addition, if the surface is bound to the sampling
277 * engine, Surface Format must be supported for Render Target
278 * Compression for surfaces bound to the sampling engine."
280 * In other words, we can't sample from a fast-cleared image if it
281 * doesn't also support color compression.
283 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
284 } else if (GEN_GEN
== 8) {
285 /* Broadwell can sample from fast-cleared images */
286 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
288 /* Ivy Bridge and Haswell cannot */
289 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
292 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
293 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
298 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
300 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
303 /* We only allocate input attachment states for color surfaces. Compression
304 * is not yet enabled for depth textures and stencil doesn't allow
305 * compression so we can just use the texture surface state from the view.
307 return vk_format_is_color(att
->format
);
310 static enum isl_aux_usage
311 layout_to_hiz_usage(VkImageLayout layout
, uint8_t samples
)
314 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
315 return ISL_AUX_USAGE_HIZ
;
316 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
317 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
318 if (anv_can_sample_with_hiz(GEN_GEN
, samples
))
319 return ISL_AUX_USAGE_HIZ
;
321 case VK_IMAGE_LAYOUT_GENERAL
:
322 /* This buffer could be used as a source or destination in a transfer
323 * operation. Transfer operations current don't perform HiZ-enabled reads
327 return ISL_AUX_USAGE_NONE
;
331 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
332 * the initial layout is undefined, the HiZ buffer and depth buffer will
333 * represent the same data at the end of this operation.
336 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
337 const struct anv_image
*image
,
338 VkImageLayout initial_layout
,
339 VkImageLayout final_layout
)
343 if (image
->aux_usage
!= ISL_AUX_USAGE_HIZ
|| final_layout
== initial_layout
)
346 const bool hiz_enabled
= layout_to_hiz_usage(initial_layout
, image
->samples
) ==
348 const bool enable_hiz
= layout_to_hiz_usage(final_layout
, image
->samples
) ==
351 enum blorp_hiz_op hiz_op
;
352 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
353 /* We've already initialized the aux HiZ buffer at BindImageMemory time,
354 * so there's no need to perform a HIZ resolve or clear to avoid GPU hangs.
355 * This initial layout indicates that the user doesn't care about the data
356 * that's currently in the buffer, so resolves are not necessary except
357 * for the special case noted below.
359 hiz_op
= BLORP_HIZ_OP_NONE
;
360 } else if (hiz_enabled
&& !enable_hiz
) {
361 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
362 } else if (!hiz_enabled
&& enable_hiz
) {
363 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
365 assert(hiz_enabled
== enable_hiz
);
366 /* If the same buffer will be used, no resolves are necessary except for
367 * the special case noted below.
369 hiz_op
= BLORP_HIZ_OP_NONE
;
372 if (hiz_op
!= BLORP_HIZ_OP_NONE
)
373 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, hiz_op
);
375 /* Images that have sampling with HiZ enabled cause all shader sampling to
376 * load data with the HiZ buffer. Therefore, in the case of transitioning to
377 * the general layout - which currently routes all writes to the depth
378 * buffer - we must ensure that the HiZ buffer remains consistent with the
379 * depth buffer by performing an additional HIZ resolve if the operation
380 * required by this transition was not already a HiZ resolve.
382 if (final_layout
== VK_IMAGE_LAYOUT_GENERAL
&&
383 anv_can_sample_with_hiz(GEN_GEN
, image
->samples
) &&
384 hiz_op
!= BLORP_HIZ_OP_HIZ_RESOLVE
) {
385 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, BLORP_HIZ_OP_HIZ_RESOLVE
);
391 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
394 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
395 struct anv_render_pass
*pass
,
396 const VkRenderPassBeginInfo
*begin
)
398 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
399 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
401 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
403 if (pass
->attachment_count
== 0) {
404 state
->attachments
= NULL
;
408 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
409 pass
->attachment_count
*
410 sizeof(state
->attachments
[0]),
411 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
412 if (state
->attachments
== NULL
) {
413 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
417 bool need_null_state
= false;
418 unsigned num_states
= 0;
419 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
420 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
423 /* We need a null state for any depth-stencil-only subpasses.
424 * Importantly, this includes depth/stencil clears so we create one
425 * whenever we have depth or stencil
427 need_null_state
= true;
430 if (need_input_attachment_state(&pass
->attachments
[i
]))
433 num_states
+= need_null_state
;
435 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
436 state
->render_pass_states
=
437 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
438 num_states
* ss_stride
, isl_dev
->ss
.align
);
440 struct anv_state next_state
= state
->render_pass_states
;
441 next_state
.alloc_size
= isl_dev
->ss
.size
;
443 if (need_null_state
) {
444 state
->null_surface_state
= next_state
;
445 next_state
.offset
+= ss_stride
;
446 next_state
.map
+= ss_stride
;
449 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
450 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
451 state
->attachments
[i
].color_rt_state
= next_state
;
452 next_state
.offset
+= ss_stride
;
453 next_state
.map
+= ss_stride
;
456 if (need_input_attachment_state(&pass
->attachments
[i
])) {
457 state
->attachments
[i
].input_att_state
= next_state
;
458 next_state
.offset
+= ss_stride
;
459 next_state
.map
+= ss_stride
;
462 assert(next_state
.offset
== state
->render_pass_states
.offset
+
463 state
->render_pass_states
.alloc_size
);
466 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
467 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
469 if (need_null_state
) {
470 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
471 .SurfaceType
= SURFTYPE_NULL
,
472 .SurfaceArray
= framebuffer
->layers
> 0,
473 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
477 .TiledSurface
= true,
479 .Width
= framebuffer
->width
- 1,
480 .Height
= framebuffer
->height
- 1,
481 .Depth
= framebuffer
->layers
- 1,
482 .RenderTargetViewExtent
= framebuffer
->layers
- 1,
484 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
->null_surface_state
.map
,
488 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
489 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
490 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
491 VkImageAspectFlags clear_aspects
= 0;
493 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
494 /* color attachment */
495 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
496 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
499 /* depthstencil attachment */
500 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
501 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
502 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
504 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
505 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
506 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
510 state
->attachments
[i
].current_layout
= att
->initial_layout
;
511 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
513 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
515 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
516 assert(iview
->vk_format
== att
->format
);
518 union isl_color_value clear_color
= { .u32
= { 0, } };
519 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
520 color_attachment_compute_aux_usage(cmd_buffer
->device
,
521 &state
->attachments
[i
],
522 iview
, begin
->renderArea
,
525 struct isl_view view
= iview
->isl
;
526 view
.usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
527 isl_surf_fill_state(isl_dev
,
528 state
->attachments
[i
].color_rt_state
.map
,
529 .surf
= &iview
->image
->color_surface
.isl
,
531 .aux_surf
= &iview
->image
->aux_surface
.isl
,
532 .aux_usage
= state
->attachments
[i
].aux_usage
,
533 .clear_color
= clear_color
,
534 .mocs
= cmd_buffer
->device
->default_mocs
);
536 add_image_view_relocs(cmd_buffer
, iview
,
537 state
->attachments
[i
].aux_usage
,
538 state
->attachments
[i
].color_rt_state
);
540 if (iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
541 state
->attachments
[i
].aux_usage
=
542 layout_to_hiz_usage(att
->initial_layout
, iview
->image
->samples
);
544 state
->attachments
[i
].aux_usage
= ISL_AUX_USAGE_NONE
;
546 state
->attachments
[i
].input_aux_usage
= ISL_AUX_USAGE_NONE
;
549 if (need_input_attachment_state(&pass
->attachments
[i
])) {
550 struct isl_view view
= iview
->isl
;
551 view
.usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
552 isl_surf_fill_state(isl_dev
,
553 state
->attachments
[i
].input_att_state
.map
,
554 .surf
= &iview
->image
->color_surface
.isl
,
556 .aux_surf
= &iview
->image
->aux_surface
.isl
,
557 .aux_usage
= state
->attachments
[i
].input_aux_usage
,
558 .clear_color
= clear_color
,
559 .mocs
= cmd_buffer
->device
->default_mocs
);
561 add_image_view_relocs(cmd_buffer
, iview
,
562 state
->attachments
[i
].input_aux_usage
,
563 state
->attachments
[i
].input_att_state
);
567 if (!cmd_buffer
->device
->info
.has_llc
)
568 anv_state_clflush(state
->render_pass_states
);
573 genX(BeginCommandBuffer
)(
574 VkCommandBuffer commandBuffer
,
575 const VkCommandBufferBeginInfo
* pBeginInfo
)
577 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
579 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
580 * command buffer's state. Otherwise, we must *reset* its state. In both
583 * From the Vulkan 1.0 spec:
585 * If a command buffer is in the executable state and the command buffer
586 * was allocated from a command pool with the
587 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
588 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
589 * as if vkResetCommandBuffer had been called with
590 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
591 * the command buffer in the recording state.
593 anv_cmd_buffer_reset(cmd_buffer
);
595 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
597 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
598 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
600 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
602 if (cmd_buffer
->usage_flags
&
603 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
604 cmd_buffer
->state
.pass
=
605 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
606 cmd_buffer
->state
.subpass
=
607 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
608 cmd_buffer
->state
.framebuffer
= NULL
;
610 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, cmd_buffer
->state
.pass
,
613 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
620 genX(EndCommandBuffer
)(
621 VkCommandBuffer commandBuffer
)
623 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
625 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
627 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
633 genX(CmdExecuteCommands
)(
634 VkCommandBuffer commandBuffer
,
635 uint32_t commandBufferCount
,
636 const VkCommandBuffer
* pCmdBuffers
)
638 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
640 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
642 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
643 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
645 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
647 if (secondary
->usage_flags
&
648 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
649 /* If we're continuing a render pass from the primary, we need to
650 * copy the surface states for the current subpass into the storage
651 * we allocated for them in BeginCommandBuffer.
653 struct anv_bo
*ss_bo
= &primary
->device
->surface_state_block_pool
.bo
;
654 struct anv_state src_state
= primary
->state
.render_pass_states
;
655 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
656 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
658 genX(cmd_buffer_gpu_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
659 ss_bo
, src_state
.offset
,
660 src_state
.alloc_size
);
663 anv_cmd_buffer_add_secondary(primary
, secondary
);
666 /* Each of the secondary command buffers will use its own state base
667 * address. We need to re-emit state base address for the primary after
668 * all of the secondaries are done.
670 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
673 genX(cmd_buffer_emit_state_base_address
)(primary
);
676 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
677 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
678 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
681 * Program the hardware to use the specified L3 configuration.
684 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
685 const struct gen_l3_config
*cfg
)
688 if (cfg
== cmd_buffer
->state
.current_l3_config
)
691 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
692 fprintf(stderr
, "L3 config transition: ");
693 gen_dump_l3_config(cfg
, stderr
);
696 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
698 /* According to the hardware docs, the L3 partitioning can only be changed
699 * while the pipeline is completely drained and the caches are flushed,
700 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
702 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
703 pc
.DCFlushEnable
= true;
704 pc
.PostSyncOperation
= NoWrite
;
705 pc
.CommandStreamerStallEnable
= true;
708 /* ...followed by a second pipelined PIPE_CONTROL that initiates
709 * invalidation of the relevant caches. Note that because RO invalidation
710 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
711 * command is processed by the CS) we cannot combine it with the previous
712 * stalling flush as the hardware documentation suggests, because that
713 * would cause the CS to stall on previous rendering *after* RO
714 * invalidation and wouldn't prevent the RO caches from being polluted by
715 * concurrent rendering before the stall completes. This intentionally
716 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
717 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
718 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
719 * already guarantee that there is no concurrent GPGPU kernel execution
720 * (see SKL HSD 2132585).
722 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
723 pc
.TextureCacheInvalidationEnable
= true;
724 pc
.ConstantCacheInvalidationEnable
= true;
725 pc
.InstructionCacheInvalidateEnable
= true;
726 pc
.StateCacheInvalidationEnable
= true;
727 pc
.PostSyncOperation
= NoWrite
;
730 /* Now send a third stalling flush to make sure that invalidation is
731 * complete when the L3 configuration registers are modified.
733 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
734 pc
.DCFlushEnable
= true;
735 pc
.PostSyncOperation
= NoWrite
;
736 pc
.CommandStreamerStallEnable
= true;
741 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
744 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
745 .SLMEnable
= has_slm
,
746 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
747 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
748 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
749 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
751 /* Set up the L3 partitioning. */
752 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
756 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
757 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
759 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
761 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
764 assert(!cfg
->n
[GEN_L3P_ALL
]);
766 /* When enabled SLM only uses a portion of the L3 on half of the banks,
767 * the matching space on the remaining banks has to be allocated to a
768 * client (URB for all validated configurations) set to the
769 * lower-bandwidth 2-bank address hashing mode.
771 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
772 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
773 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
775 /* Minimum number of ways that can be allocated to the URB. */
776 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
777 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
779 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
780 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
781 .ConvertDC_UC
= !has_dc
,
782 .ConvertIS_UC
= !has_is
,
783 .ConvertC_UC
= !has_c
,
784 .ConvertT_UC
= !has_t
);
786 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
787 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
788 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
790 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
791 .SLMEnable
= has_slm
,
792 .URBLowBandwidth
= urb_low_bw
,
793 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
795 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
797 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
798 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
800 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
801 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
803 .CAllocation
= cfg
->n
[GEN_L3P_C
],
805 .TAllocation
= cfg
->n
[GEN_L3P_T
],
808 /* Set up the L3 partitioning. */
809 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
810 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
811 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
814 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
815 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
816 * them disabled to avoid crashing the system hard.
818 uint32_t scratch1
, chicken3
;
819 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
820 .L3AtomicDisable
= !has_dc
);
821 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
822 .L3AtomicDisableMask
= true,
823 .L3AtomicDisable
= !has_dc
);
824 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
825 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
831 cmd_buffer
->state
.current_l3_config
= cfg
;
835 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
837 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
839 /* Flushes are pipelined while invalidations are handled immediately.
840 * Therefore, if we're flushing anything then we need to schedule a stall
841 * before any invalidations can happen.
843 if (bits
& ANV_PIPE_FLUSH_BITS
)
844 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
846 /* If we're going to do an invalidate and we have a pending CS stall that
847 * has yet to be resolved, we do the CS stall now.
849 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
850 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
851 bits
|= ANV_PIPE_CS_STALL_BIT
;
852 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
855 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
856 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
857 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
858 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
859 pipe
.RenderTargetCacheFlushEnable
=
860 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
862 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
863 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
864 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
867 * According to the Broadwell documentation, any PIPE_CONTROL with the
868 * "Command Streamer Stall" bit set must also have another bit set,
869 * with five different options:
871 * - Render Target Cache Flush
872 * - Depth Cache Flush
873 * - Stall at Pixel Scoreboard
874 * - Post-Sync Operation
878 * I chose "Stall at Pixel Scoreboard" since that's what we use in
879 * mesa and it seems to work fine. The choice is fairly arbitrary.
881 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
882 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
883 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
884 pipe
.StallAtPixelScoreboard
= true;
887 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
890 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
891 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
892 pipe
.StateCacheInvalidationEnable
=
893 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
894 pipe
.ConstantCacheInvalidationEnable
=
895 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
896 pipe
.VFCacheInvalidationEnable
=
897 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
898 pipe
.TextureCacheInvalidationEnable
=
899 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
900 pipe
.InstructionCacheInvalidateEnable
=
901 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
904 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
907 cmd_buffer
->state
.pending_pipe_bits
= bits
;
910 void genX(CmdPipelineBarrier
)(
911 VkCommandBuffer commandBuffer
,
912 VkPipelineStageFlags srcStageMask
,
913 VkPipelineStageFlags destStageMask
,
915 uint32_t memoryBarrierCount
,
916 const VkMemoryBarrier
* pMemoryBarriers
,
917 uint32_t bufferMemoryBarrierCount
,
918 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
919 uint32_t imageMemoryBarrierCount
,
920 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
922 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
925 /* XXX: Right now, we're really dumb and just flush whatever categories
926 * the app asks for. One of these days we may make this a bit better
927 * but right now that's all the hardware allows for in most areas.
929 VkAccessFlags src_flags
= 0;
930 VkAccessFlags dst_flags
= 0;
932 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
933 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
934 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
937 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
938 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
939 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
942 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
943 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
944 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
945 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
946 if (pImageMemoryBarriers
[i
].subresourceRange
.aspectMask
&
947 VK_IMAGE_ASPECT_DEPTH_BIT
) {
948 transition_depth_buffer(cmd_buffer
, image
,
949 pImageMemoryBarriers
[i
].oldLayout
,
950 pImageMemoryBarriers
[i
].newLayout
);
954 enum anv_pipe_bits pipe_bits
= 0;
956 for_each_bit(b
, src_flags
) {
957 switch ((VkAccessFlagBits
)(1 << b
)) {
958 case VK_ACCESS_SHADER_WRITE_BIT
:
959 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
961 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
962 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
964 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
965 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
967 case VK_ACCESS_TRANSFER_WRITE_BIT
:
968 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
969 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
972 break; /* Nothing to do */
976 for_each_bit(b
, dst_flags
) {
977 switch ((VkAccessFlagBits
)(1 << b
)) {
978 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
979 case VK_ACCESS_INDEX_READ_BIT
:
980 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
981 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
983 case VK_ACCESS_UNIFORM_READ_BIT
:
984 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
985 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
987 case VK_ACCESS_SHADER_READ_BIT
:
988 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
989 case VK_ACCESS_TRANSFER_READ_BIT
:
990 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
993 break; /* Nothing to do */
997 cmd_buffer
->state
.pending_pipe_bits
|= pipe_bits
;
1001 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1003 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
1005 /* In order to avoid thrash, we assume that vertex and fragment stages
1006 * always exist. In the rare case where one is missing *and* the other
1007 * uses push concstants, this may be suboptimal. However, avoiding stalls
1008 * seems more important.
1010 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1012 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1016 const unsigned push_constant_kb
= 32;
1017 #elif GEN_IS_HASWELL
1018 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1020 const unsigned push_constant_kb
= 16;
1023 const unsigned num_stages
=
1024 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1025 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1027 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1028 * units of 2KB. Incidentally, these are the same platforms that have
1029 * 32KB worth of push constant space.
1031 if (push_constant_kb
== 32)
1032 size_per_stage
&= ~1u;
1034 uint32_t kb_used
= 0;
1035 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1036 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1037 anv_batch_emit(&cmd_buffer
->batch
,
1038 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1039 alloc
._3DCommandSubOpcode
= 18 + i
;
1040 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1041 alloc
.ConstantBufferSize
= push_size
;
1043 kb_used
+= push_size
;
1046 anv_batch_emit(&cmd_buffer
->batch
,
1047 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1048 alloc
.ConstantBufferOffset
= kb_used
;
1049 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1052 cmd_buffer
->state
.push_constant_stages
= stages
;
1054 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1056 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1057 * the next 3DPRIMITIVE command after programming the
1058 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1060 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1061 * pipeline setup, we need to dirty push constants.
1063 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1067 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1068 gl_shader_stage stage
,
1069 struct anv_state
*bt_state
)
1071 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1072 struct anv_pipeline
*pipeline
;
1073 uint32_t bias
, state_offset
;
1076 case MESA_SHADER_COMPUTE
:
1077 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1081 pipeline
= cmd_buffer
->state
.pipeline
;
1086 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1087 *bt_state
= (struct anv_state
) { 0, };
1091 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1092 if (bias
+ map
->surface_count
== 0) {
1093 *bt_state
= (struct anv_state
) { 0, };
1097 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1098 bias
+ map
->surface_count
,
1100 uint32_t *bt_map
= bt_state
->map
;
1102 if (bt_state
->map
== NULL
)
1103 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1105 if (stage
== MESA_SHADER_COMPUTE
&&
1106 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
1107 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
1108 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
1110 struct anv_state surface_state
;
1112 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1114 const enum isl_format format
=
1115 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1116 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1117 format
, bo_offset
, 12, 1);
1119 bt_map
[0] = surface_state
.offset
+ state_offset
;
1120 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1123 if (map
->surface_count
== 0)
1126 if (map
->image_count
> 0) {
1128 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1129 if (result
!= VK_SUCCESS
)
1132 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1136 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1137 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1139 struct anv_state surface_state
;
1141 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1142 /* Color attachment binding */
1143 assert(stage
== MESA_SHADER_FRAGMENT
);
1144 assert(binding
->binding
== 0);
1145 if (binding
->index
< subpass
->color_count
) {
1146 const unsigned att
= subpass
->color_attachments
[binding
->index
];
1147 surface_state
= cmd_buffer
->state
.attachments
[att
].color_rt_state
;
1149 surface_state
= cmd_buffer
->state
.null_surface_state
;
1152 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1156 struct anv_descriptor_set
*set
=
1157 cmd_buffer
->state
.descriptors
[binding
->set
];
1158 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1159 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1161 switch (desc
->type
) {
1162 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1163 /* Nothing for us to do here */
1166 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1167 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
1168 surface_state
= desc
->image_view
->sampler_surface_state
;
1169 assert(surface_state
.alloc_size
);
1170 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1171 desc
->image_view
->image
->aux_usage
,
1175 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1176 assert(stage
== MESA_SHADER_FRAGMENT
);
1177 if (desc
->image_view
->aspect_mask
!= VK_IMAGE_ASPECT_COLOR_BIT
) {
1178 /* For depth and stencil input attachments, we treat it like any
1179 * old texture that a user may have bound.
1181 surface_state
= desc
->image_view
->sampler_surface_state
;
1182 assert(surface_state
.alloc_size
);
1183 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1184 desc
->image_view
->image
->aux_usage
,
1187 /* For color input attachments, we create the surface state at
1188 * vkBeginRenderPass time so that we can include aux and clear
1189 * color information.
1191 assert(binding
->input_attachment_index
< subpass
->input_count
);
1192 const unsigned subpass_att
= binding
->input_attachment_index
;
1193 const unsigned att
= subpass
->input_attachments
[subpass_att
];
1194 surface_state
= cmd_buffer
->state
.attachments
[att
].input_att_state
;
1198 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1199 surface_state
= desc
->image_view
->storage_surface_state
;
1200 assert(surface_state
.alloc_size
);
1201 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1202 desc
->image_view
->image
->aux_usage
,
1205 struct brw_image_param
*image_param
=
1206 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1208 *image_param
= desc
->image_view
->storage_image_param
;
1209 image_param
->surface_idx
= bias
+ s
;
1213 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
1214 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
1215 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
1216 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
1217 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
1218 surface_state
= desc
->buffer_view
->surface_state
;
1219 assert(surface_state
.alloc_size
);
1220 add_surface_state_reloc(cmd_buffer
, surface_state
,
1221 desc
->buffer_view
->bo
,
1222 desc
->buffer_view
->offset
);
1225 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
1226 surface_state
= desc
->buffer_view
->storage_surface_state
;
1227 assert(surface_state
.alloc_size
);
1228 add_surface_state_reloc(cmd_buffer
, surface_state
,
1229 desc
->buffer_view
->bo
,
1230 desc
->buffer_view
->offset
);
1232 struct brw_image_param
*image_param
=
1233 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1235 *image_param
= desc
->buffer_view
->storage_image_param
;
1236 image_param
->surface_idx
= bias
+ s
;
1240 assert(!"Invalid descriptor type");
1244 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1246 assert(image
== map
->image_count
);
1249 if (!cmd_buffer
->device
->info
.has_llc
)
1250 anv_state_clflush(*bt_state
);
1256 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1257 gl_shader_stage stage
,
1258 struct anv_state
*state
)
1260 struct anv_pipeline
*pipeline
;
1262 if (stage
== MESA_SHADER_COMPUTE
)
1263 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1265 pipeline
= cmd_buffer
->state
.pipeline
;
1267 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1268 *state
= (struct anv_state
) { 0, };
1272 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1273 if (map
->sampler_count
== 0) {
1274 *state
= (struct anv_state
) { 0, };
1278 uint32_t size
= map
->sampler_count
* 16;
1279 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1281 if (state
->map
== NULL
)
1282 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1284 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1285 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1286 struct anv_descriptor_set
*set
=
1287 cmd_buffer
->state
.descriptors
[binding
->set
];
1288 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1289 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1291 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1292 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1295 struct anv_sampler
*sampler
= desc
->sampler
;
1297 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1298 * happens to be zero.
1300 if (sampler
== NULL
)
1303 memcpy(state
->map
+ (s
* 16),
1304 sampler
->state
, sizeof(sampler
->state
));
1307 if (!cmd_buffer
->device
->info
.has_llc
)
1308 anv_state_clflush(*state
);
1314 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1316 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1317 cmd_buffer
->state
.pipeline
->active_stages
;
1319 VkResult result
= VK_SUCCESS
;
1320 anv_foreach_stage(s
, dirty
) {
1321 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1322 if (result
!= VK_SUCCESS
)
1324 result
= emit_binding_table(cmd_buffer
, s
,
1325 &cmd_buffer
->state
.binding_tables
[s
]);
1326 if (result
!= VK_SUCCESS
)
1330 if (result
!= VK_SUCCESS
) {
1331 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1333 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1334 assert(result
== VK_SUCCESS
);
1336 /* Re-emit state base addresses so we get the new surface state base
1337 * address before we start emitting binding tables etc.
1339 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1341 /* Re-emit all active binding tables */
1342 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
1343 anv_foreach_stage(s
, dirty
) {
1344 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1345 if (result
!= VK_SUCCESS
)
1347 result
= emit_binding_table(cmd_buffer
, s
,
1348 &cmd_buffer
->state
.binding_tables
[s
]);
1349 if (result
!= VK_SUCCESS
)
1354 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1360 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1363 static const uint32_t sampler_state_opcodes
[] = {
1364 [MESA_SHADER_VERTEX
] = 43,
1365 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1366 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1367 [MESA_SHADER_GEOMETRY
] = 46,
1368 [MESA_SHADER_FRAGMENT
] = 47,
1369 [MESA_SHADER_COMPUTE
] = 0,
1372 static const uint32_t binding_table_opcodes
[] = {
1373 [MESA_SHADER_VERTEX
] = 38,
1374 [MESA_SHADER_TESS_CTRL
] = 39,
1375 [MESA_SHADER_TESS_EVAL
] = 40,
1376 [MESA_SHADER_GEOMETRY
] = 41,
1377 [MESA_SHADER_FRAGMENT
] = 42,
1378 [MESA_SHADER_COMPUTE
] = 0,
1381 anv_foreach_stage(s
, stages
) {
1382 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1383 anv_batch_emit(&cmd_buffer
->batch
,
1384 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1385 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1386 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1390 /* Always emit binding table pointers if we're asked to, since on SKL
1391 * this is what flushes push constants. */
1392 anv_batch_emit(&cmd_buffer
->batch
,
1393 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1394 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1395 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1401 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1403 static const uint32_t push_constant_opcodes
[] = {
1404 [MESA_SHADER_VERTEX
] = 21,
1405 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1406 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1407 [MESA_SHADER_GEOMETRY
] = 22,
1408 [MESA_SHADER_FRAGMENT
] = 23,
1409 [MESA_SHADER_COMPUTE
] = 0,
1412 VkShaderStageFlags flushed
= 0;
1414 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
1415 if (stage
== MESA_SHADER_COMPUTE
)
1418 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1420 if (state
.offset
== 0) {
1421 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1422 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1424 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1425 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1426 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1428 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
1429 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1431 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
1432 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1438 flushed
|= mesa_to_vk_shader_stage(stage
);
1441 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1447 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1449 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1452 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1454 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1456 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1458 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1461 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1462 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1464 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1465 GENX(3DSTATE_VERTEX_BUFFERS
));
1467 for_each_bit(vb
, vb_emit
) {
1468 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1469 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1471 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1472 .VertexBufferIndex
= vb
,
1475 .MemoryObjectControlState
= GENX(MOCS
),
1477 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1478 .InstanceDataStepRate
= 1,
1479 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1482 .AddressModifyEnable
= true,
1483 .BufferPitch
= pipeline
->binding_stride
[vb
],
1484 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1487 .BufferSize
= buffer
->size
- offset
1489 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1493 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1498 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1500 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1501 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1503 /* The exact descriptor layout is pulled from the pipeline, so we need
1504 * to re-emit binding tables on every pipeline change.
1506 cmd_buffer
->state
.descriptors_dirty
|=
1507 cmd_buffer
->state
.pipeline
->active_stages
;
1509 /* If the pipeline changed, we may need to re-allocate push constant
1512 cmd_buffer_alloc_push_constants(cmd_buffer
);
1516 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1517 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1518 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1520 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1521 * stall needs to be sent just prior to any 3DSTATE_VS,
1522 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1523 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1524 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1525 * PIPE_CONTROL needs to be sent before any combination of VS
1526 * associated 3DSTATE."
1528 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1529 pc
.DepthStallEnable
= true;
1530 pc
.PostSyncOperation
= WriteImmediateData
;
1532 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1537 /* Render targets live in the same binding table as fragment descriptors */
1538 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1539 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1541 /* We emit the binding tables and sampler tables first, then emit push
1542 * constants and then finally emit binding table and sampler table
1543 * pointers. It has to happen in this order, since emitting the binding
1544 * tables may change the push constants (in case of storage images). After
1545 * emitting push constants, on SKL+ we have to emit the corresponding
1546 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1549 if (cmd_buffer
->state
.descriptors_dirty
)
1550 dirty
= flush_descriptor_sets(cmd_buffer
);
1552 if (cmd_buffer
->state
.push_constants_dirty
) {
1554 /* On Sky Lake and later, the binding table pointers commands are
1555 * what actually flush the changes to push constant state so we need
1556 * to dirty them so they get re-emitted below.
1558 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1560 cmd_buffer_flush_push_constants(cmd_buffer
);
1565 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1567 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1568 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1570 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1571 ANV_CMD_DIRTY_PIPELINE
)) {
1572 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1573 pipeline
->depth_clamp_enable
);
1576 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1577 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1579 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1581 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1585 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1586 struct anv_bo
*bo
, uint32_t offset
)
1588 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1589 GENX(3DSTATE_VERTEX_BUFFERS
));
1591 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1592 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1593 .VertexBufferIndex
= 32, /* Reserved for this */
1594 .AddressModifyEnable
= true,
1597 .MemoryObjectControlState
= GENX(MOCS
),
1598 .BufferStartingAddress
= { bo
, offset
},
1601 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1602 .BufferStartingAddress
= { bo
, offset
},
1603 .EndAddress
= { bo
, offset
+ 8 },
1609 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1610 uint32_t base_vertex
, uint32_t base_instance
)
1612 struct anv_state id_state
=
1613 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1615 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1616 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1618 if (!cmd_buffer
->device
->info
.has_llc
)
1619 anv_state_clflush(id_state
);
1621 emit_base_vertex_instance_bo(cmd_buffer
,
1622 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
1626 VkCommandBuffer commandBuffer
,
1627 uint32_t vertexCount
,
1628 uint32_t instanceCount
,
1629 uint32_t firstVertex
,
1630 uint32_t firstInstance
)
1632 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1633 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1634 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1636 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1638 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1639 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1641 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1642 prim
.VertexAccessType
= SEQUENTIAL
;
1643 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1644 prim
.VertexCountPerInstance
= vertexCount
;
1645 prim
.StartVertexLocation
= firstVertex
;
1646 prim
.InstanceCount
= instanceCount
;
1647 prim
.StartInstanceLocation
= firstInstance
;
1648 prim
.BaseVertexLocation
= 0;
1652 void genX(CmdDrawIndexed
)(
1653 VkCommandBuffer commandBuffer
,
1654 uint32_t indexCount
,
1655 uint32_t instanceCount
,
1656 uint32_t firstIndex
,
1657 int32_t vertexOffset
,
1658 uint32_t firstInstance
)
1660 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1661 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1662 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1664 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1666 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1667 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1669 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1670 prim
.VertexAccessType
= RANDOM
;
1671 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1672 prim
.VertexCountPerInstance
= indexCount
;
1673 prim
.StartVertexLocation
= firstIndex
;
1674 prim
.InstanceCount
= instanceCount
;
1675 prim
.StartInstanceLocation
= firstInstance
;
1676 prim
.BaseVertexLocation
= vertexOffset
;
1680 /* Auto-Draw / Indirect Registers */
1681 #define GEN7_3DPRIM_END_OFFSET 0x2420
1682 #define GEN7_3DPRIM_START_VERTEX 0x2430
1683 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1684 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1685 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1686 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1688 void genX(CmdDrawIndirect
)(
1689 VkCommandBuffer commandBuffer
,
1691 VkDeviceSize offset
,
1695 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1696 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1697 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1698 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1699 struct anv_bo
*bo
= buffer
->bo
;
1700 uint32_t bo_offset
= buffer
->offset
+ offset
;
1702 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1704 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1705 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
1707 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1708 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1709 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1710 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
1711 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
1713 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1714 prim
.IndirectParameterEnable
= true;
1715 prim
.VertexAccessType
= SEQUENTIAL
;
1716 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1720 void genX(CmdDrawIndexedIndirect
)(
1721 VkCommandBuffer commandBuffer
,
1723 VkDeviceSize offset
,
1727 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1728 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1729 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1730 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1731 struct anv_bo
*bo
= buffer
->bo
;
1732 uint32_t bo_offset
= buffer
->offset
+ offset
;
1734 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1736 /* TODO: We need to stomp base vertex to 0 somehow */
1737 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1738 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
1740 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1741 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1742 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1743 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
1744 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
1746 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1747 prim
.IndirectParameterEnable
= true;
1748 prim
.VertexAccessType
= RANDOM
;
1749 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1754 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
1756 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1757 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
1760 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1761 if (result
!= VK_SUCCESS
) {
1762 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1763 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1764 assert(result
== VK_SUCCESS
);
1766 /* Re-emit state base addresses so we get the new surface state base
1767 * address before we start emitting binding tables etc.
1769 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1771 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1772 assert(result
== VK_SUCCESS
);
1775 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
1776 assert(result
== VK_SUCCESS
);
1778 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
1779 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1780 .BindingTablePointer
= surfaces
.offset
,
1781 .SamplerStatePointer
= samplers
.offset
,
1783 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
1785 struct anv_state state
=
1786 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
1787 pipeline
->interface_descriptor_data
,
1788 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
1791 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
1792 anv_batch_emit(&cmd_buffer
->batch
,
1793 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
1794 mid
.InterfaceDescriptorTotalLength
= size
;
1795 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
1802 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1804 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1805 MAYBE_UNUSED VkResult result
;
1807 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
1809 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1811 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
1813 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1814 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
1816 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
1817 * the only bits that are changed are scoreboard related: Scoreboard
1818 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
1819 * these scoreboard related states, a MEDIA_STATE_FLUSH is
1822 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1823 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1825 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1828 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
1829 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
1830 /* FIXME: figure out descriptors for gen7 */
1831 result
= flush_compute_descriptor_set(cmd_buffer
);
1832 assert(result
== VK_SUCCESS
);
1833 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
1836 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
1837 struct anv_state push_state
=
1838 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
1840 if (push_state
.alloc_size
) {
1841 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
1842 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
1843 curbe
.CURBEDataStartAddress
= push_state
.offset
;
1848 cmd_buffer
->state
.compute_dirty
= 0;
1850 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1856 verify_cmd_parser(const struct anv_device
*device
,
1857 int required_version
,
1858 const char *function
)
1860 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
1861 vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
1862 "cmd parser version %d is required for %s",
1863 required_version
, function
);
1872 void genX(CmdDispatch
)(
1873 VkCommandBuffer commandBuffer
,
1878 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1879 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1880 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1882 if (prog_data
->uses_num_work_groups
) {
1883 struct anv_state state
=
1884 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
1885 uint32_t *sizes
= state
.map
;
1889 if (!cmd_buffer
->device
->info
.has_llc
)
1890 anv_state_clflush(state
);
1891 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
1892 cmd_buffer
->state
.num_workgroups_bo
=
1893 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
1896 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1898 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
1899 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1900 ggw
.ThreadDepthCounterMaximum
= 0;
1901 ggw
.ThreadHeightCounterMaximum
= 0;
1902 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1903 ggw
.ThreadGroupIDXDimension
= x
;
1904 ggw
.ThreadGroupIDYDimension
= y
;
1905 ggw
.ThreadGroupIDZDimension
= z
;
1906 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1907 ggw
.BottomExecutionMask
= 0xffffffff;
1910 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1913 #define GPGPU_DISPATCHDIMX 0x2500
1914 #define GPGPU_DISPATCHDIMY 0x2504
1915 #define GPGPU_DISPATCHDIMZ 0x2508
1917 #define MI_PREDICATE_SRC0 0x2400
1918 #define MI_PREDICATE_SRC1 0x2408
1920 void genX(CmdDispatchIndirect
)(
1921 VkCommandBuffer commandBuffer
,
1923 VkDeviceSize offset
)
1925 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1926 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1927 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1928 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1929 struct anv_bo
*bo
= buffer
->bo
;
1930 uint32_t bo_offset
= buffer
->offset
+ offset
;
1931 struct anv_batch
*batch
= &cmd_buffer
->batch
;
1934 /* Linux 4.4 added command parser version 5 which allows the GPGPU
1935 * indirect dispatch registers to be written.
1937 if (!verify_cmd_parser(cmd_buffer
->device
, 5, "vkCmdDispatchIndirect"))
1941 if (prog_data
->uses_num_work_groups
) {
1942 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
1943 cmd_buffer
->state
.num_workgroups_bo
= bo
;
1946 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1948 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
1949 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
1950 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
1953 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
1954 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
1955 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
1956 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
1958 /* Load compute_dispatch_indirect_x_size into SRC0 */
1959 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
1961 /* predicate = (compute_dispatch_indirect_x_size == 0); */
1962 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1963 mip
.LoadOperation
= LOAD_LOAD
;
1964 mip
.CombineOperation
= COMBINE_SET
;
1965 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1968 /* Load compute_dispatch_indirect_y_size into SRC0 */
1969 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
1971 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
1972 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1973 mip
.LoadOperation
= LOAD_LOAD
;
1974 mip
.CombineOperation
= COMBINE_OR
;
1975 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1978 /* Load compute_dispatch_indirect_z_size into SRC0 */
1979 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
1981 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
1982 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1983 mip
.LoadOperation
= LOAD_LOAD
;
1984 mip
.CombineOperation
= COMBINE_OR
;
1985 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1988 /* predicate = !predicate; */
1989 #define COMPARE_FALSE 1
1990 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1991 mip
.LoadOperation
= LOAD_LOADINV
;
1992 mip
.CombineOperation
= COMBINE_OR
;
1993 mip
.CompareOperation
= COMPARE_FALSE
;
1997 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
1998 ggw
.IndirectParameterEnable
= true;
1999 ggw
.PredicateEnable
= GEN_GEN
<= 7;
2000 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2001 ggw
.ThreadDepthCounterMaximum
= 0;
2002 ggw
.ThreadHeightCounterMaximum
= 0;
2003 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2004 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2005 ggw
.BottomExecutionMask
= 0xffffffff;
2008 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2012 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
2015 #if GEN_GEN >= 8 && GEN_GEN < 10
2016 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
2018 * Software must clear the COLOR_CALC_STATE Valid field in
2019 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
2020 * with Pipeline Select set to GPGPU.
2022 * The internal hardware docs recommend the same workaround for Gen9
2025 if (pipeline
== GPGPU
)
2026 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
2028 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
2029 * PIPELINE_SELECT [DevBWR+]":
2033 * Software must ensure all the write caches are flushed through a
2034 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
2035 * command to invalidate read only caches prior to programming
2036 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
2038 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2039 pc
.RenderTargetCacheFlushEnable
= true;
2040 pc
.DepthCacheFlushEnable
= true;
2041 pc
.DCFlushEnable
= true;
2042 pc
.PostSyncOperation
= NoWrite
;
2043 pc
.CommandStreamerStallEnable
= true;
2046 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2047 pc
.TextureCacheInvalidationEnable
= true;
2048 pc
.ConstantCacheInvalidationEnable
= true;
2049 pc
.StateCacheInvalidationEnable
= true;
2050 pc
.InstructionCacheInvalidateEnable
= true;
2051 pc
.PostSyncOperation
= NoWrite
;
2057 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
2059 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
2060 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
2062 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2066 ps
.PipelineSelection
= _3D
;
2069 cmd_buffer
->state
.current_pipeline
= _3D
;
2074 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
2076 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
2077 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
2079 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2083 ps
.PipelineSelection
= GPGPU
;
2086 cmd_buffer
->state
.current_pipeline
= GPGPU
;
2091 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
2096 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
2098 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
2099 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
2100 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
2101 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
2102 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
2103 * Depth Flush Bit set, followed by another pipelined depth stall
2104 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
2105 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
2106 * via a preceding MI_FLUSH)."
2108 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2109 pipe
.DepthStallEnable
= true;
2111 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2112 pipe
.DepthCacheFlushEnable
= true;
2114 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2115 pipe
.DepthStallEnable
= true;
2120 depth_stencil_surface_type(enum isl_surf_dim dim
)
2123 case ISL_SURF_DIM_1D
:
2125 /* From the Sky Lake PRM, 3DSTATAE_DEPTH_BUFFER::SurfaceType
2127 * Programming Notes:
2128 * The Surface Type of the depth buffer must be the same as the
2129 * Surface Type of the render target(s) (defined in
2130 * SURFACE_STATE), unless either the depth buffer or render
2131 * targets are SURFTYPE_NULL (see exception below for SKL). 1D
2132 * surface type not allowed for depth surface and stencil surface.
2135 * If depth/stencil is enabled with 1D render target,
2136 * depth/stencil surface type needs to be set to 2D surface type
2137 * and height set to 1. Depth will use (legacy) TileY and stencil
2138 * will use TileW. For this case only, the Surface Type of the
2139 * depth buffer can be 2D while the Surface Type of the render
2140 * target(s) are 1D, representing an exception to a programming
2147 case ISL_SURF_DIM_2D
:
2149 case ISL_SURF_DIM_3D
:
2151 /* The Sky Lake docs list the value for 3D as "Reserved". However,
2152 * they have the exact same layout as 2D arrays on gen9+, so we can
2160 unreachable("Invalid surface dimension");
2165 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
2167 struct anv_device
*device
= cmd_buffer
->device
;
2168 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
2169 const struct anv_image_view
*iview
=
2170 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2171 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
2172 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
2173 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2174 const bool has_hiz
= image
!= NULL
&&
2175 cmd_buffer
->state
.attachments
[ds
].aux_usage
== ISL_AUX_USAGE_HIZ
;
2176 const bool has_stencil
=
2177 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
2179 /* FIXME: Implement the PMA stall W/A */
2180 /* FIXME: Width and Height are wrong */
2182 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
2184 /* Emit 3DSTATE_DEPTH_BUFFER */
2186 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2188 depth_stencil_surface_type(image
->depth_surface
.isl
.dim
);
2189 db
.DepthWriteEnable
= true;
2190 db
.StencilWriteEnable
= has_stencil
;
2191 db
.HierarchicalDepthBufferEnable
= has_hiz
;
2193 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
2194 &image
->depth_surface
.isl
);
2196 db
.SurfaceBaseAddress
= (struct anv_address
) {
2198 .offset
= image
->offset
+ image
->depth_surface
.offset
,
2200 db
.DepthBufferObjectControlState
= GENX(MOCS
);
2202 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
2203 db
.Height
= image
->extent
.height
- 1;
2204 db
.Width
= image
->extent
.width
- 1;
2205 db
.LOD
= iview
->isl
.base_level
;
2206 db
.MinimumArrayElement
= iview
->isl
.base_array_layer
;
2208 assert(image
->depth_surface
.isl
.dim
!= ISL_SURF_DIM_3D
);
2210 db
.RenderTargetViewExtent
=
2211 iview
->isl
.array_len
- iview
->isl
.base_array_layer
- 1;
2215 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2;
2219 /* Even when no depth buffer is present, the hardware requires that
2220 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
2222 * If a null depth buffer is bound, the driver must instead bind depth as:
2223 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
2224 * 3DSTATE_DEPTH.Width = 1
2225 * 3DSTATE_DEPTH.Height = 1
2226 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
2227 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
2228 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
2229 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
2230 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
2232 * The PRM is wrong, though. The width and height must be programmed to
2233 * actual framebuffer's width and height, even when neither depth buffer
2234 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
2235 * be combined with a stencil buffer so we use D32_FLOAT instead.
2237 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2240 depth_stencil_surface_type(image
->stencil_surface
.isl
.dim
);
2242 db
.SurfaceType
= SURFTYPE_2D
;
2244 db
.SurfaceFormat
= D32_FLOAT
;
2245 db
.Width
= MAX2(fb
->width
, 1) - 1;
2246 db
.Height
= MAX2(fb
->height
, 1) - 1;
2247 db
.StencilWriteEnable
= has_stencil
;
2252 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
) {
2253 hdb
.HierarchicalDepthBufferObjectControlState
= GENX(MOCS
);
2254 hdb
.SurfacePitch
= image
->aux_surface
.isl
.row_pitch
- 1;
2255 hdb
.SurfaceBaseAddress
= (struct anv_address
) {
2257 .offset
= image
->offset
+ image
->aux_surface
.offset
,
2260 /* From the SKL PRM Vol2a:
2262 * The interpretation of this field is dependent on Surface Type
2264 * - SURFTYPE_1D: distance in pixels between array slices
2265 * - SURFTYPE_2D/CUBE: distance in rows between array slices
2266 * - SURFTYPE_3D: distance in rows between R - slices
2268 * Unfortunately, the docs aren't 100% accurate here. They fail to
2269 * mention that the 1-D rule only applies to linear 1-D images.
2270 * Since depth and HiZ buffers are always tiled, they are treated as
2271 * 2-D images. Prior to Sky Lake, this field is always in rows.
2274 isl_surf_get_array_pitch_sa_rows(&image
->aux_surface
.isl
) >> 2;
2278 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
);
2281 /* Emit 3DSTATE_STENCIL_BUFFER */
2283 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
2284 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2285 sb
.StencilBufferEnable
= true;
2287 sb
.StencilBufferObjectControlState
= GENX(MOCS
);
2289 sb
.SurfacePitch
= image
->stencil_surface
.isl
.row_pitch
- 1;
2292 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2;
2294 sb
.SurfaceBaseAddress
= (struct anv_address
) {
2296 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
2300 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
2303 /* From the IVB PRM Vol2P1, 11.5.5.4 3DSTATE_CLEAR_PARAMS:
2305 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along with
2306 * the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
2307 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)
2309 * Testing also shows that some variant of this restriction may exist HSW+.
2310 * On BDW+, it is not possible to emit 2 of these packets consecutively when
2311 * both have DepthClearValueValid set. An analysis of such state programming
2312 * on SKL showed that the GPU doesn't register the latter packet's clear
2315 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
) {
2317 cp
.DepthClearValueValid
= true;
2318 cp
.DepthClearValue
= ANV_HZ_FC_VAL
;
2324 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
2325 struct anv_subpass
*subpass
)
2327 cmd_buffer
->state
.subpass
= subpass
;
2329 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
2331 const struct anv_image_view
*iview
=
2332 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2334 if (iview
&& iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
2335 const uint32_t ds
= subpass
->depth_stencil_attachment
;
2336 transition_depth_buffer(cmd_buffer
, iview
->image
,
2337 cmd_buffer
->state
.attachments
[ds
].current_layout
,
2338 cmd_buffer
->state
.subpass
->depth_stencil_layout
);
2339 cmd_buffer
->state
.attachments
[ds
].current_layout
=
2340 cmd_buffer
->state
.subpass
->depth_stencil_layout
;
2341 cmd_buffer
->state
.attachments
[ds
].aux_usage
=
2342 layout_to_hiz_usage(cmd_buffer
->state
.subpass
->depth_stencil_layout
,
2343 iview
->image
->samples
);
2346 cmd_buffer_emit_depth_stencil(cmd_buffer
);
2348 anv_cmd_buffer_clear_subpass(cmd_buffer
);
2351 void genX(CmdBeginRenderPass
)(
2352 VkCommandBuffer commandBuffer
,
2353 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2354 VkSubpassContents contents
)
2356 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2357 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2358 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2360 cmd_buffer
->state
.framebuffer
= framebuffer
;
2361 cmd_buffer
->state
.pass
= pass
;
2362 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2363 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
2365 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2367 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
2370 void genX(CmdNextSubpass
)(
2371 VkCommandBuffer commandBuffer
,
2372 VkSubpassContents contents
)
2374 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2376 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2378 const struct anv_image_view
*iview
=
2379 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2381 if (iview
&& iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
2382 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2384 if (cmd_buffer
->state
.subpass
- cmd_buffer
->state
.pass
->subpasses
==
2385 cmd_buffer
->state
.pass
->attachments
[ds
].last_subpass_idx
) {
2386 transition_depth_buffer(cmd_buffer
, iview
->image
,
2387 cmd_buffer
->state
.attachments
[ds
].current_layout
,
2388 cmd_buffer
->state
.pass
->attachments
[ds
].final_layout
);
2392 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2393 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
2396 void genX(CmdEndRenderPass
)(
2397 VkCommandBuffer commandBuffer
)
2399 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2401 const struct anv_image_view
*iview
=
2402 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2404 if (iview
&& iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
2405 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2407 if (cmd_buffer
->state
.subpass
- cmd_buffer
->state
.pass
->subpasses
==
2408 cmd_buffer
->state
.pass
->attachments
[ds
].last_subpass_idx
) {
2409 transition_depth_buffer(cmd_buffer
, iview
->image
,
2410 cmd_buffer
->state
.attachments
[ds
].current_layout
,
2411 cmd_buffer
->state
.pass
->attachments
[ds
].final_layout
);
2415 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2418 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
2423 emit_ps_depth_count(struct anv_cmd_buffer
*cmd_buffer
,
2424 struct anv_bo
*bo
, uint32_t offset
)
2426 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2427 pc
.DestinationAddressType
= DAT_PPGTT
;
2428 pc
.PostSyncOperation
= WritePSDepthCount
;
2429 pc
.DepthStallEnable
= true;
2430 pc
.Address
= (struct anv_address
) { bo
, offset
};
2432 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2433 pc
.CommandStreamerStallEnable
= true;
2438 emit_query_availability(struct anv_cmd_buffer
*cmd_buffer
,
2439 struct anv_bo
*bo
, uint32_t offset
)
2441 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2442 pc
.DestinationAddressType
= DAT_PPGTT
;
2443 pc
.PostSyncOperation
= WriteImmediateData
;
2444 pc
.Address
= (struct anv_address
) { bo
, offset
};
2445 pc
.ImmediateData
= 1;
2449 void genX(CmdBeginQuery
)(
2450 VkCommandBuffer commandBuffer
,
2451 VkQueryPool queryPool
,
2453 VkQueryControlFlags flags
)
2455 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2456 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2458 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
2459 * that the pipelining of the depth write breaks. What we see is that
2460 * samples from the render pass clear leaks into the first query
2461 * immediately after the clear. Doing a pipecontrol with a post-sync
2462 * operation and DepthStallEnable seems to work around the issue.
2464 if (cmd_buffer
->state
.need_query_wa
) {
2465 cmd_buffer
->state
.need_query_wa
= false;
2466 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2467 pc
.DepthCacheFlushEnable
= true;
2468 pc
.DepthStallEnable
= true;
2472 switch (pool
->type
) {
2473 case VK_QUERY_TYPE_OCCLUSION
:
2474 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2475 query
* sizeof(struct anv_query_pool_slot
));
2478 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2484 void genX(CmdEndQuery
)(
2485 VkCommandBuffer commandBuffer
,
2486 VkQueryPool queryPool
,
2489 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2490 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2492 switch (pool
->type
) {
2493 case VK_QUERY_TYPE_OCCLUSION
:
2494 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2495 query
* sizeof(struct anv_query_pool_slot
) + 8);
2497 emit_query_availability(cmd_buffer
, &pool
->bo
,
2498 query
* sizeof(struct anv_query_pool_slot
) + 16);
2501 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2507 #define TIMESTAMP 0x2358
2509 void genX(CmdWriteTimestamp
)(
2510 VkCommandBuffer commandBuffer
,
2511 VkPipelineStageFlagBits pipelineStage
,
2512 VkQueryPool queryPool
,
2515 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2516 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2517 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
2519 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
2521 switch (pipelineStage
) {
2522 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
2523 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2524 srm
.RegisterAddress
= TIMESTAMP
;
2525 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
};
2527 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2528 srm
.RegisterAddress
= TIMESTAMP
+ 4;
2529 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
+ 4 };
2534 /* Everything else is bottom-of-pipe */
2535 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2536 pc
.DestinationAddressType
= DAT_PPGTT
;
2537 pc
.PostSyncOperation
= WriteTimestamp
;
2538 pc
.Address
= (struct anv_address
) { &pool
->bo
, offset
};
2540 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2541 pc
.CommandStreamerStallEnable
= true;
2546 emit_query_availability(cmd_buffer
, &pool
->bo
, query
+ 16);
2549 #if GEN_GEN > 7 || GEN_IS_HASWELL
2551 #define alu_opcode(v) __gen_uint((v), 20, 31)
2552 #define alu_operand1(v) __gen_uint((v), 10, 19)
2553 #define alu_operand2(v) __gen_uint((v), 0, 9)
2554 #define alu(opcode, operand1, operand2) \
2555 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
2557 #define OPCODE_NOOP 0x000
2558 #define OPCODE_LOAD 0x080
2559 #define OPCODE_LOADINV 0x480
2560 #define OPCODE_LOAD0 0x081
2561 #define OPCODE_LOAD1 0x481
2562 #define OPCODE_ADD 0x100
2563 #define OPCODE_SUB 0x101
2564 #define OPCODE_AND 0x102
2565 #define OPCODE_OR 0x103
2566 #define OPCODE_XOR 0x104
2567 #define OPCODE_STORE 0x180
2568 #define OPCODE_STOREINV 0x580
2570 #define OPERAND_R0 0x00
2571 #define OPERAND_R1 0x01
2572 #define OPERAND_R2 0x02
2573 #define OPERAND_R3 0x03
2574 #define OPERAND_R4 0x04
2575 #define OPERAND_SRCA 0x20
2576 #define OPERAND_SRCB 0x21
2577 #define OPERAND_ACCU 0x31
2578 #define OPERAND_ZF 0x32
2579 #define OPERAND_CF 0x33
2581 #define CS_GPR(n) (0x2600 + (n) * 8)
2584 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
2585 struct anv_bo
*bo
, uint32_t offset
)
2587 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2588 lrm
.RegisterAddress
= reg
,
2589 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2591 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2592 lrm
.RegisterAddress
= reg
+ 4;
2593 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2598 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
2599 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
2601 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2602 srm
.RegisterAddress
= reg
;
2603 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2606 if (flags
& VK_QUERY_RESULT_64_BIT
) {
2607 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2608 srm
.RegisterAddress
= reg
+ 4;
2609 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2614 void genX(CmdCopyQueryPoolResults
)(
2615 VkCommandBuffer commandBuffer
,
2616 VkQueryPool queryPool
,
2617 uint32_t firstQuery
,
2618 uint32_t queryCount
,
2619 VkBuffer destBuffer
,
2620 VkDeviceSize destOffset
,
2621 VkDeviceSize destStride
,
2622 VkQueryResultFlags flags
)
2624 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2625 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2626 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
2627 uint32_t slot_offset
, dst_offset
;
2629 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
2630 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2631 pc
.CommandStreamerStallEnable
= true;
2632 pc
.StallAtPixelScoreboard
= true;
2636 dst_offset
= buffer
->offset
+ destOffset
;
2637 for (uint32_t i
= 0; i
< queryCount
; i
++) {
2639 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
2640 switch (pool
->type
) {
2641 case VK_QUERY_TYPE_OCCLUSION
:
2642 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2643 CS_GPR(0), &pool
->bo
, slot_offset
);
2644 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2645 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
2647 /* FIXME: We need to clamp the result for 32 bit. */
2649 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
2650 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
2651 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
2652 dw
[3] = alu(OPCODE_SUB
, 0, 0);
2653 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
2656 case VK_QUERY_TYPE_TIMESTAMP
:
2657 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2658 CS_GPR(2), &pool
->bo
, slot_offset
);
2662 unreachable("unhandled query type");
2665 store_query_result(&cmd_buffer
->batch
,
2666 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
2668 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
2669 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
2670 &pool
->bo
, slot_offset
+ 16);
2671 if (flags
& VK_QUERY_RESULT_64_BIT
)
2672 store_query_result(&cmd_buffer
->batch
,
2673 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
2675 store_query_result(&cmd_buffer
->batch
,
2676 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
2679 dst_offset
+= destStride
;
2684 void genX(CmdCopyQueryPoolResults
)(
2685 VkCommandBuffer commandBuffer
,
2686 VkQueryPool queryPool
,
2687 uint32_t firstQuery
,
2688 uint32_t queryCount
,
2689 VkBuffer destBuffer
,
2690 VkDeviceSize destOffset
,
2691 VkDeviceSize destStride
,
2692 VkQueryResultFlags flags
)
2694 anv_finishme("Queries not yet supported on Ivy Bridge");