2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_l3_config.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
36 /* We reserve GPR 14 and 15 for conditional rendering */
37 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
38 #define __gen_get_batch_dwords anv_batch_emit_dwords
39 #define __gen_address_offset anv_address_add
40 #include "common/gen_mi_builder.h"
43 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
45 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
46 lri
.RegisterOffset
= reg
;
52 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
54 struct anv_device
*device
= cmd_buffer
->device
;
56 /* If we are emitting a new state base address we probably need to re-emit
59 cmd_buffer
->state
.descriptors_dirty
|= ~0;
61 /* Emit a render target cache flush.
63 * This isn't documented anywhere in the PRM. However, it seems to be
64 * necessary prior to changing the surface state base adress. Without
65 * this, we get GPU hangs when using multi-level command buffers which
66 * clear depth, reset state base address, and then go render stuff.
68 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
69 pc
.DCFlushEnable
= true;
70 pc
.RenderTargetCacheFlushEnable
= true;
71 pc
.CommandStreamerStallEnable
= true;
74 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
75 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
76 sba
.GeneralStateMOCS
= GENX(MOCS
);
77 sba
.GeneralStateBaseAddressModifyEnable
= true;
79 sba
.SurfaceStateBaseAddress
=
80 anv_cmd_buffer_surface_base_address(cmd_buffer
);
81 sba
.SurfaceStateMOCS
= GENX(MOCS
);
82 sba
.SurfaceStateBaseAddressModifyEnable
= true;
84 sba
.DynamicStateBaseAddress
=
85 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
86 sba
.DynamicStateMOCS
= GENX(MOCS
);
87 sba
.DynamicStateBaseAddressModifyEnable
= true;
89 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
90 sba
.IndirectObjectMOCS
= GENX(MOCS
);
91 sba
.IndirectObjectBaseAddressModifyEnable
= true;
93 sba
.InstructionBaseAddress
=
94 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
95 sba
.InstructionMOCS
= GENX(MOCS
);
96 sba
.InstructionBaseAddressModifyEnable
= true;
99 /* Broadwell requires that we specify a buffer size for a bunch of
100 * these fields. However, since we will be growing the BO's live, we
101 * just set them all to the maximum.
103 sba
.GeneralStateBufferSize
= 0xfffff;
104 sba
.GeneralStateBufferSizeModifyEnable
= true;
105 sba
.DynamicStateBufferSize
= 0xfffff;
106 sba
.DynamicStateBufferSizeModifyEnable
= true;
107 sba
.IndirectObjectBufferSize
= 0xfffff;
108 sba
.IndirectObjectBufferSizeModifyEnable
= true;
109 sba
.InstructionBufferSize
= 0xfffff;
110 sba
.InstructionBuffersizeModifyEnable
= true;
113 if (cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
) {
114 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
115 .bo
= device
->surface_state_pool
.block_pool
.bo
,
118 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
120 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
121 sba
.BindlessSurfaceStateSize
= 0;
123 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
124 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
127 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
128 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
129 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
130 sba
.BindlessSamplerStateBufferSize
= 0;
134 /* After re-setting the surface state base address, we have to do some
135 * cache flusing so that the sampler engine will pick up the new
136 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
137 * Shared Function > 3D Sampler > State > State Caching (page 96):
139 * Coherency with system memory in the state cache, like the texture
140 * cache is handled partially by software. It is expected that the
141 * command stream or shader will issue Cache Flush operation or
142 * Cache_Flush sampler message to ensure that the L1 cache remains
143 * coherent with system memory.
147 * Whenever the value of the Dynamic_State_Base_Addr,
148 * Surface_State_Base_Addr are altered, the L1 state cache must be
149 * invalidated to ensure the new surface or sampler state is fetched
150 * from system memory.
152 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
153 * which, according the PIPE_CONTROL instruction documentation in the
156 * Setting this bit is independent of any other bit in this packet.
157 * This bit controls the invalidation of the L1 and L2 state caches
158 * at the top of the pipe i.e. at the parsing time.
160 * Unfortunately, experimentation seems to indicate that state cache
161 * invalidation through a PIPE_CONTROL does nothing whatsoever in
162 * regards to surface state and binding tables. In stead, it seems that
163 * invalidating the texture cache is what is actually needed.
165 * XXX: As far as we have been able to determine through
166 * experimentation, shows that flush the texture cache appears to be
167 * sufficient. The theory here is that all of the sampling/rendering
168 * units cache the binding table in the texture cache. However, we have
169 * yet to be able to actually confirm this.
171 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
172 pc
.TextureCacheInvalidationEnable
= true;
173 pc
.ConstantCacheInvalidationEnable
= true;
174 pc
.StateCacheInvalidationEnable
= true;
179 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
180 struct anv_state state
, struct anv_address addr
)
182 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
185 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
186 state
.offset
+ isl_dev
->ss
.addr_offset
,
187 addr
.bo
, addr
.offset
);
188 if (result
!= VK_SUCCESS
)
189 anv_batch_set_error(&cmd_buffer
->batch
, result
);
193 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
194 struct anv_surface_state state
)
196 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
198 assert(!anv_address_is_null(state
.address
));
199 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
201 if (!anv_address_is_null(state
.aux_address
)) {
203 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
204 &cmd_buffer
->pool
->alloc
,
205 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
206 state
.aux_address
.bo
, state
.aux_address
.offset
);
207 if (result
!= VK_SUCCESS
)
208 anv_batch_set_error(&cmd_buffer
->batch
, result
);
211 if (!anv_address_is_null(state
.clear_address
)) {
213 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
214 &cmd_buffer
->pool
->alloc
,
216 isl_dev
->ss
.clear_color_state_offset
,
217 state
.clear_address
.bo
, state
.clear_address
.offset
);
218 if (result
!= VK_SUCCESS
)
219 anv_batch_set_error(&cmd_buffer
->batch
, result
);
224 color_attachment_compute_aux_usage(struct anv_device
* device
,
225 struct anv_cmd_state
* cmd_state
,
226 uint32_t att
, VkRect2D render_area
,
227 union isl_color_value
*fast_clear_color
)
229 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
230 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
232 assert(iview
->n_planes
== 1);
234 if (iview
->planes
[0].isl
.base_array_layer
>=
235 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
236 iview
->planes
[0].isl
.base_level
)) {
237 /* There is no aux buffer which corresponds to the level and layer(s)
240 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
241 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
242 att_state
->fast_clear
= false;
246 att_state
->aux_usage
=
247 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
248 VK_IMAGE_ASPECT_COLOR_BIT
,
249 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
251 /* If we don't have aux, then we should have returned early in the layer
252 * check above. If we got here, we must have something.
254 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
256 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
257 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
258 att_state
->input_aux_usage
= att_state
->aux_usage
;
260 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
262 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
263 * setting is only allowed if Surface Format supported for Fast
264 * Clear. In addition, if the surface is bound to the sampling
265 * engine, Surface Format must be supported for Render Target
266 * Compression for surfaces bound to the sampling engine."
268 * In other words, we can only sample from a fast-cleared image if it
269 * also supports color compression.
271 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
272 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
274 /* While fast-clear resolves and partial resolves are fairly cheap in the
275 * case where you render to most of the pixels, full resolves are not
276 * because they potentially involve reading and writing the entire
277 * framebuffer. If we can't texture with CCS_E, we should leave it off and
278 * limit ourselves to fast clears.
280 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
281 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
282 anv_perf_warn(device
->instance
, iview
->image
,
283 "Not temporarily enabling CCS_E.");
286 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
290 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
291 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
293 union isl_color_value clear_color
= {};
294 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
296 att_state
->clear_color_is_zero_one
=
297 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
298 att_state
->clear_color_is_zero
=
299 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
301 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
302 /* Start by getting the fast clear type. We use the first subpass
303 * layout here because we don't want to fast-clear if the first subpass
304 * to use the attachment can't handle fast-clears.
306 enum anv_fast_clear_type fast_clear_type
=
307 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
308 VK_IMAGE_ASPECT_COLOR_BIT
,
309 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
310 switch (fast_clear_type
) {
311 case ANV_FAST_CLEAR_NONE
:
312 att_state
->fast_clear
= false;
314 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
315 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
317 case ANV_FAST_CLEAR_ANY
:
318 att_state
->fast_clear
= true;
322 /* Potentially, we could do partial fast-clears but doing so has crazy
323 * alignment restrictions. It's easier to just restrict to full size
324 * fast clears for now.
326 if (render_area
.offset
.x
!= 0 ||
327 render_area
.offset
.y
!= 0 ||
328 render_area
.extent
.width
!= iview
->extent
.width
||
329 render_area
.extent
.height
!= iview
->extent
.height
)
330 att_state
->fast_clear
= false;
332 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
333 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
334 att_state
->fast_clear
= false;
336 /* We only allow fast clears to the first slice of an image (level 0,
337 * layer 0) and only for the entire slice. This guarantees us that, at
338 * any given time, there is only one clear color on any given image at
339 * any given time. At the time of our testing (Jan 17, 2018), there
340 * were no known applications which would benefit from fast-clearing
341 * more than just the first slice.
343 if (att_state
->fast_clear
&&
344 (iview
->planes
[0].isl
.base_level
> 0 ||
345 iview
->planes
[0].isl
.base_array_layer
> 0)) {
346 anv_perf_warn(device
->instance
, iview
->image
,
347 "Rendering with multi-lod or multi-layer framebuffer "
348 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
349 "baseArrayLayer > 0. Not fast clearing.");
350 att_state
->fast_clear
= false;
351 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
352 anv_perf_warn(device
->instance
, iview
->image
,
353 "Rendering to a multi-layer framebuffer with "
354 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
357 if (att_state
->fast_clear
)
358 *fast_clear_color
= clear_color
;
360 att_state
->fast_clear
= false;
365 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
366 struct anv_cmd_state
*cmd_state
,
367 uint32_t att
, VkRect2D render_area
)
369 struct anv_render_pass_attachment
*pass_att
=
370 &cmd_state
->pass
->attachments
[att
];
371 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
372 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
374 /* These will be initialized after the first subpass transition. */
375 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
376 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
379 /* We don't do any HiZ or depth fast-clears on gen7 yet */
380 att_state
->fast_clear
= false;
384 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
385 /* If we're just clearing stencil, we can always HiZ clear */
386 att_state
->fast_clear
= true;
390 /* Default to false for now */
391 att_state
->fast_clear
= false;
393 /* We must have depth in order to have HiZ */
394 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
397 const enum isl_aux_usage first_subpass_aux_usage
=
398 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
399 VK_IMAGE_ASPECT_DEPTH_BIT
,
400 pass_att
->first_subpass_layout
);
401 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
404 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
405 iview
->planes
[0].isl
.format
,
406 iview
->image
->samples
,
407 render_area
.offset
.x
,
408 render_area
.offset
.y
,
409 render_area
.offset
.x
+
410 render_area
.extent
.width
,
411 render_area
.offset
.y
+
412 render_area
.extent
.height
))
415 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
418 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
419 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
420 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
421 * only supports returning 0.0f. Gens prior to gen8 do not support this
427 /* If we got here, then we can fast clear */
428 att_state
->fast_clear
= true;
432 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
434 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
437 /* We only allocate input attachment states for color surfaces. Compression
438 * is not yet enabled for depth textures and stencil doesn't allow
439 * compression so we can just use the texture surface state from the view.
441 return vk_format_is_color(att
->format
);
444 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
445 * the initial layout is undefined, the HiZ buffer and depth buffer will
446 * represent the same data at the end of this operation.
449 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
450 const struct anv_image
*image
,
451 VkImageLayout initial_layout
,
452 VkImageLayout final_layout
)
454 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
455 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
456 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
457 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
458 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
459 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
461 enum isl_aux_op hiz_op
;
462 if (hiz_enabled
&& !enable_hiz
) {
463 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
464 } else if (!hiz_enabled
&& enable_hiz
) {
465 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
467 assert(hiz_enabled
== enable_hiz
);
468 /* If the same buffer will be used, no resolves are necessary. */
469 hiz_op
= ISL_AUX_OP_NONE
;
472 if (hiz_op
!= ISL_AUX_OP_NONE
)
473 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
477 #define MI_PREDICATE_SRC0 0x2400
478 #define MI_PREDICATE_SRC1 0x2408
479 #define MI_PREDICATE_RESULT 0x2418
482 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
483 const struct anv_image
*image
,
484 VkImageAspectFlagBits aspect
,
486 uint32_t base_layer
, uint32_t layer_count
,
489 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
491 /* We only have compression tracking for CCS_E */
492 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
495 for (uint32_t a
= 0; a
< layer_count
; a
++) {
496 uint32_t layer
= base_layer
+ a
;
497 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
498 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
501 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
507 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
508 const struct anv_image
*image
,
509 VkImageAspectFlagBits aspect
,
510 enum anv_fast_clear_type fast_clear
)
512 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
513 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
515 sdi
.ImmediateData
= fast_clear
;
518 /* Whenever we have fast-clear, we consider that slice to be compressed.
519 * This makes building predicates much easier.
521 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
522 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
525 #if GEN_IS_HASWELL || GEN_GEN >= 8
526 static inline uint32_t
527 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
529 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
531 .Operand1
= operand1
,
532 .Operand2
= operand2
,
536 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
542 /* This is only really practical on haswell and above because it requires
543 * MI math in order to get it correct.
545 #if GEN_GEN >= 8 || GEN_IS_HASWELL
547 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
548 const struct anv_image
*image
,
549 VkImageAspectFlagBits aspect
,
550 uint32_t level
, uint32_t array_layer
,
551 enum isl_aux_op resolve_op
,
552 enum anv_fast_clear_type fast_clear_supported
)
554 struct gen_mi_builder b
;
555 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
557 const struct gen_mi_value fast_clear_type
=
558 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
561 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
562 /* In this case, we're doing a full resolve which means we want the
563 * resolve to happen if any compression (including fast-clears) is
566 * In order to simplify the logic a bit, we make the assumption that,
567 * if the first slice has been fast-cleared, it is also marked as
568 * compressed. See also set_image_fast_clear_state.
570 const struct gen_mi_value compression_state
=
571 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
573 level
, array_layer
));
574 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
576 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
578 if (level
== 0 && array_layer
== 0) {
579 /* If the predicate is true, we want to write 0 to the fast clear type
580 * and, if it's false, leave it alone. We can do this by writing
582 * clear_type = clear_type & ~predicate;
584 struct gen_mi_value new_fast_clear_type
=
585 gen_mi_iand(&b
, fast_clear_type
,
586 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
587 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
589 } else if (level
== 0 && array_layer
== 0) {
590 /* In this case, we are doing a partial resolve to get rid of fast-clear
591 * colors. We don't care about the compression state but we do care
592 * about how much fast clear is allowed by the final layout.
594 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
595 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
597 /* We need to compute (fast_clear_supported < image->fast_clear) */
598 struct gen_mi_value pred
=
599 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
600 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
601 gen_mi_value_ref(&b
, pred
));
603 /* If the predicate is true, we want to write 0 to the fast clear type
604 * and, if it's false, leave it alone. We can do this by writing
606 * clear_type = clear_type & ~predicate;
608 struct gen_mi_value new_fast_clear_type
=
609 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
610 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
612 /* In this case, we're trying to do a partial resolve on a slice that
613 * doesn't have clear color. There's nothing to do.
615 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
619 /* Set src1 to 0 and use a != condition */
620 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
622 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
623 mip
.LoadOperation
= LOAD_LOADINV
;
624 mip
.CombineOperation
= COMBINE_SET
;
625 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
628 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
632 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
633 const struct anv_image
*image
,
634 VkImageAspectFlagBits aspect
,
635 uint32_t level
, uint32_t array_layer
,
636 enum isl_aux_op resolve_op
,
637 enum anv_fast_clear_type fast_clear_supported
)
639 struct gen_mi_builder b
;
640 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
642 struct gen_mi_value fast_clear_type_mem
=
643 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
646 /* This only works for partial resolves and only when the clear color is
647 * all or nothing. On the upside, this emits less command streamer code
648 * and works on Ivybridge and Bay Trail.
650 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
651 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
653 /* We don't support fast clears on anything other than the first slice. */
654 if (level
> 0 || array_layer
> 0)
657 /* On gen8, we don't have a concept of default clear colors because we
658 * can't sample from CCS surfaces. It's enough to just load the fast clear
659 * state into the predicate register.
661 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
662 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
663 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
665 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
666 mip
.LoadOperation
= LOAD_LOADINV
;
667 mip
.CombineOperation
= COMBINE_SET
;
668 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
671 #endif /* GEN_GEN <= 8 */
674 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
675 const struct anv_image
*image
,
676 enum isl_format format
,
677 VkImageAspectFlagBits aspect
,
678 uint32_t level
, uint32_t array_layer
,
679 enum isl_aux_op resolve_op
,
680 enum anv_fast_clear_type fast_clear_supported
)
682 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
685 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
686 aspect
, level
, array_layer
,
687 resolve_op
, fast_clear_supported
);
688 #else /* GEN_GEN <= 8 */
689 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
690 aspect
, level
, array_layer
,
691 resolve_op
, fast_clear_supported
);
694 /* CCS_D only supports full resolves and BLORP will assert on us if we try
695 * to do a partial resolve on a CCS_D surface.
697 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
698 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
699 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
701 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
702 array_layer
, 1, resolve_op
, NULL
, true);
706 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
707 const struct anv_image
*image
,
708 enum isl_format format
,
709 VkImageAspectFlagBits aspect
,
710 uint32_t array_layer
,
711 enum isl_aux_op resolve_op
,
712 enum anv_fast_clear_type fast_clear_supported
)
714 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
715 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
717 #if GEN_GEN >= 8 || GEN_IS_HASWELL
718 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
719 aspect
, 0, array_layer
,
720 resolve_op
, fast_clear_supported
);
722 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
723 array_layer
, 1, resolve_op
, NULL
, true);
725 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
730 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
731 const struct anv_image
*image
,
732 VkImageAspectFlagBits aspect
,
733 enum isl_aux_usage aux_usage
,
736 uint32_t layer_count
)
738 /* The aspect must be exactly one of the image aspects. */
739 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
741 /* The only compression types with more than just fast-clears are MCS,
742 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
743 * track the current fast-clear and compression state. This leaves us
744 * with just MCS and CCS_E.
746 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
747 aux_usage
!= ISL_AUX_USAGE_MCS
)
750 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
751 level
, base_layer
, layer_count
, true);
755 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
756 const struct anv_image
*image
,
757 VkImageAspectFlagBits aspect
)
759 assert(cmd_buffer
&& image
);
760 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
762 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
763 ANV_FAST_CLEAR_NONE
);
765 /* The fast clear value dword(s) will be copied into a surface state object.
766 * Ensure that the restrictions of the fields in the dword(s) are followed.
768 * CCS buffers on SKL+ can have any value set for the clear colors.
770 if (image
->samples
== 1 && GEN_GEN
>= 9)
773 /* Other combinations of auxiliary buffers and platforms require specific
774 * values in the clear value dword(s).
776 struct anv_address addr
=
777 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
780 for (unsigned i
= 0; i
< 4; i
++) {
781 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
783 sdi
.Address
.offset
+= i
* 4;
784 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
785 assert(image
->samples
> 1);
786 sdi
.ImmediateData
= 0;
790 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
792 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
793 /* Pre-SKL, the dword containing the clear values also contains
794 * other fields, so we need to initialize those fields to match the
795 * values that would be in a color attachment.
797 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
798 ISL_CHANNEL_SELECT_GREEN
<< 22 |
799 ISL_CHANNEL_SELECT_BLUE
<< 19 |
800 ISL_CHANNEL_SELECT_ALPHA
<< 16;
801 } else if (GEN_GEN
== 7) {
802 /* On IVB, the dword containing the clear values also contains
803 * other fields that must be zero or can be zero.
805 sdi
.ImmediateData
= 0;
811 /* Copy the fast-clear value dword(s) between a surface state object and an
812 * image's fast clear state buffer.
815 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
816 struct anv_state surface_state
,
817 const struct anv_image
*image
,
818 VkImageAspectFlagBits aspect
,
819 bool copy_from_surface_state
)
821 assert(cmd_buffer
&& image
);
822 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
824 struct anv_address ss_clear_addr
= {
825 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
826 .offset
= surface_state
.offset
+
827 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
829 const struct anv_address entry_addr
=
830 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
831 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
834 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
835 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
836 * in-flight when they are issued even if the memory touched is not
837 * currently active for rendering. The weird bit is that it is not the
838 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
839 * rendering hangs such that the next stalling command after the
840 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
842 * It is unclear exactly why this hang occurs. Both MI commands come with
843 * warnings about the 3D pipeline but that doesn't seem to fully explain
844 * it. My (Jason's) best theory is that it has something to do with the
845 * fact that we're using a GPU state register as our temporary and that
846 * something with reading/writing it is causing problems.
848 * In order to work around this issue, we emit a PIPE_CONTROL with the
849 * command streamer stall bit set.
851 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
852 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
855 struct gen_mi_builder b
;
856 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
858 if (copy_from_surface_state
) {
859 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
861 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
863 /* Updating a surface state object may require that the state cache be
864 * invalidated. From the SKL PRM, Shared Functions -> State -> State
867 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
868 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
869 * modified [...], the L1 state cache must be invalidated to ensure
870 * the new surface or sampler state is fetched from system memory.
872 * In testing, SKL doesn't actually seem to need this, but HSW does.
874 cmd_buffer
->state
.pending_pipe_bits
|=
875 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
880 * @brief Transitions a color buffer from one layout to another.
882 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
885 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
886 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
887 * this represents the maximum layers to transition at each
888 * specified miplevel.
891 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
892 const struct anv_image
*image
,
893 VkImageAspectFlagBits aspect
,
894 const uint32_t base_level
, uint32_t level_count
,
895 uint32_t base_layer
, uint32_t layer_count
,
896 VkImageLayout initial_layout
,
897 VkImageLayout final_layout
)
899 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
900 /* Validate the inputs. */
902 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
903 /* These values aren't supported for simplicity's sake. */
904 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
905 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
906 /* Ensure the subresource range is valid. */
907 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
908 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
909 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
910 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
911 assert(last_level_num
<= image
->levels
);
912 /* The spec disallows these final layouts. */
913 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
914 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
916 /* No work is necessary if the layout stays the same or if this subresource
917 * range lacks auxiliary data.
919 if (initial_layout
== final_layout
)
922 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
924 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
925 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
926 /* This surface is a linear compressed image with a tiled shadow surface
927 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
928 * we need to ensure the shadow copy is up-to-date.
930 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
931 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
932 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
933 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
935 anv_image_copy_to_shadow(cmd_buffer
, image
,
936 base_level
, level_count
,
937 base_layer
, layer_count
);
940 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
943 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
945 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
946 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
947 /* A subresource in the undefined layout may have been aliased and
948 * populated with any arrangement of bits. Therefore, we must initialize
949 * the related aux buffer and clear buffer entry with desirable values.
950 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
951 * images with VK_IMAGE_TILING_OPTIMAL.
953 * Initialize the relevant clear buffer entries.
955 if (base_level
== 0 && base_layer
== 0)
956 init_fast_clear_color(cmd_buffer
, image
, aspect
);
958 /* Initialize the aux buffers to enable correct rendering. In order to
959 * ensure that things such as storage images work correctly, aux buffers
960 * need to be initialized to valid data.
962 * Having an aux buffer with invalid data is a problem for two reasons:
964 * 1) Having an invalid value in the buffer can confuse the hardware.
965 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
966 * invalid and leads to the hardware doing strange things. It
967 * doesn't hang as far as we can tell but rendering corruption can
970 * 2) If this transition is into the GENERAL layout and we then use the
971 * image as a storage image, then we must have the aux buffer in the
972 * pass-through state so that, if we then go to texture from the
973 * image, we get the results of our storage image writes and not the
974 * fast clear color or other random data.
976 * For CCS both of the problems above are real demonstrable issues. In
977 * that case, the only thing we can do is to perform an ambiguate to
978 * transition the aux surface into the pass-through state.
980 * For MCS, (2) is never an issue because we don't support multisampled
981 * storage images. In theory, issue (1) is a problem with MCS but we've
982 * never seen it in the wild. For 4x and 16x, all bit patters could, in
983 * theory, be interpreted as something but we don't know that all bit
984 * patterns are actually valid. For 2x and 8x, you could easily end up
985 * with the MCS referring to an invalid plane because not all bits of
986 * the MCS value are actually used. Even though we've never seen issues
987 * in the wild, it's best to play it safe and initialize the MCS. We
988 * can use a fast-clear for MCS because we only ever touch from render
989 * and texture (no image load store).
991 if (image
->samples
== 1) {
992 for (uint32_t l
= 0; l
< level_count
; l
++) {
993 const uint32_t level
= base_level
+ l
;
995 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
996 if (base_layer
>= aux_layers
)
997 break; /* We will only get fewer layers as level increases */
998 uint32_t level_layer_count
=
999 MIN2(layer_count
, aux_layers
- base_layer
);
1001 anv_image_ccs_op(cmd_buffer
, image
,
1002 image
->planes
[plane
].surface
.isl
.format
,
1003 aspect
, level
, base_layer
, level_layer_count
,
1004 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1006 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1007 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1008 level
, base_layer
, level_layer_count
,
1013 if (image
->samples
== 4 || image
->samples
== 16) {
1014 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1015 "Doing a potentially unnecessary fast-clear to "
1016 "define an MCS buffer.");
1019 assert(base_level
== 0 && level_count
== 1);
1020 anv_image_mcs_op(cmd_buffer
, image
,
1021 image
->planes
[plane
].surface
.isl
.format
,
1022 aspect
, base_layer
, layer_count
,
1023 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1028 const enum isl_aux_usage initial_aux_usage
=
1029 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1030 const enum isl_aux_usage final_aux_usage
=
1031 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1033 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1034 * We can handle transitions between CCS_D/E to and from NONE. What we
1035 * don't yet handle is switching between CCS_E and CCS_D within a given
1036 * image. Doing so in a performant way requires more detailed aux state
1037 * tracking such as what is done in i965. For now, just assume that we
1038 * only have one type of compression.
1040 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1041 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1042 initial_aux_usage
== final_aux_usage
);
1044 /* If initial aux usage is NONE, there is nothing to resolve */
1045 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1048 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1050 /* If the initial layout supports more fast clear than the final layout
1051 * then we need at least a partial resolve.
1053 const enum anv_fast_clear_type initial_fast_clear
=
1054 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1055 const enum anv_fast_clear_type final_fast_clear
=
1056 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1057 if (final_fast_clear
< initial_fast_clear
)
1058 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1060 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1061 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1062 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1064 if (resolve_op
== ISL_AUX_OP_NONE
)
1067 /* Perform a resolve to synchronize data between the main and aux buffer.
1068 * Before we begin, we must satisfy the cache flushing requirement specified
1069 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1071 * Any transition from any value in {Clear, Render, Resolve} to a
1072 * different value in {Clear, Render, Resolve} requires end of pipe
1075 * We perform a flush of the write cache before and after the clear and
1076 * resolve operations to meet this requirement.
1078 * Unlike other drawing, fast clear operations are not properly
1079 * synchronized. The first PIPE_CONTROL here likely ensures that the
1080 * contents of the previous render or clear hit the render target before we
1081 * resolve and the second likely ensures that the resolve is complete before
1082 * we do any more rendering or clearing.
1084 cmd_buffer
->state
.pending_pipe_bits
|=
1085 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1087 for (uint32_t l
= 0; l
< level_count
; l
++) {
1088 uint32_t level
= base_level
+ l
;
1090 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1091 if (base_layer
>= aux_layers
)
1092 break; /* We will only get fewer layers as level increases */
1093 uint32_t level_layer_count
=
1094 MIN2(layer_count
, aux_layers
- base_layer
);
1096 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1097 uint32_t array_layer
= base_layer
+ a
;
1098 if (image
->samples
== 1) {
1099 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1100 image
->planes
[plane
].surface
.isl
.format
,
1101 aspect
, level
, array_layer
, resolve_op
,
1104 /* We only support fast-clear on the first layer so partial
1105 * resolves should not be used on other layers as they will use
1106 * the clear color stored in memory that is only valid for layer0.
1108 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1112 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1113 image
->planes
[plane
].surface
.isl
.format
,
1114 aspect
, array_layer
, resolve_op
,
1120 cmd_buffer
->state
.pending_pipe_bits
|=
1121 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1125 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1128 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1129 struct anv_render_pass
*pass
,
1130 const VkRenderPassBeginInfo
*begin
)
1132 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1133 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1135 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1137 if (pass
->attachment_count
> 0) {
1138 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1139 pass
->attachment_count
*
1140 sizeof(state
->attachments
[0]),
1141 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1142 if (state
->attachments
== NULL
) {
1143 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1144 return anv_batch_set_error(&cmd_buffer
->batch
,
1145 VK_ERROR_OUT_OF_HOST_MEMORY
);
1148 state
->attachments
= NULL
;
1151 /* Reserve one for the NULL state. */
1152 unsigned num_states
= 1;
1153 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1154 if (vk_format_is_color(pass
->attachments
[i
].format
))
1157 if (need_input_attachment_state(&pass
->attachments
[i
]))
1161 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1162 state
->render_pass_states
=
1163 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1164 num_states
* ss_stride
, isl_dev
->ss
.align
);
1166 struct anv_state next_state
= state
->render_pass_states
;
1167 next_state
.alloc_size
= isl_dev
->ss
.size
;
1169 state
->null_surface_state
= next_state
;
1170 next_state
.offset
+= ss_stride
;
1171 next_state
.map
+= ss_stride
;
1173 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1174 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1175 state
->attachments
[i
].color
.state
= next_state
;
1176 next_state
.offset
+= ss_stride
;
1177 next_state
.map
+= ss_stride
;
1180 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1181 state
->attachments
[i
].input
.state
= next_state
;
1182 next_state
.offset
+= ss_stride
;
1183 next_state
.map
+= ss_stride
;
1186 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1187 state
->render_pass_states
.alloc_size
);
1190 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1191 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1193 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1194 isl_extent3d(framebuffer
->width
,
1195 framebuffer
->height
,
1196 framebuffer
->layers
));
1198 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1199 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1200 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1201 VkImageAspectFlags clear_aspects
= 0;
1202 VkImageAspectFlags load_aspects
= 0;
1204 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1205 /* color attachment */
1206 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1207 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1208 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1209 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1212 /* depthstencil attachment */
1213 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1214 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1215 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1216 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1217 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1220 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1221 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1222 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1223 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1224 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1229 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1230 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1231 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1233 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1235 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1236 anv_assert(iview
->vk_format
== att
->format
);
1238 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1239 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1241 union isl_color_value clear_color
= { .u32
= { 0, } };
1242 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1243 anv_assert(iview
->n_planes
== 1);
1244 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1245 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1246 state
, i
, begin
->renderArea
,
1249 anv_image_fill_surface_state(cmd_buffer
->device
,
1251 VK_IMAGE_ASPECT_COLOR_BIT
,
1252 &iview
->planes
[0].isl
,
1253 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1254 state
->attachments
[i
].aux_usage
,
1257 &state
->attachments
[i
].color
,
1260 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1262 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1267 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1268 anv_image_fill_surface_state(cmd_buffer
->device
,
1270 VK_IMAGE_ASPECT_COLOR_BIT
,
1271 &iview
->planes
[0].isl
,
1272 ISL_SURF_USAGE_TEXTURE_BIT
,
1273 state
->attachments
[i
].input_aux_usage
,
1276 &state
->attachments
[i
].input
,
1279 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1288 genX(BeginCommandBuffer
)(
1289 VkCommandBuffer commandBuffer
,
1290 const VkCommandBufferBeginInfo
* pBeginInfo
)
1292 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1294 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1295 * command buffer's state. Otherwise, we must *reset* its state. In both
1296 * cases we reset it.
1298 * From the Vulkan 1.0 spec:
1300 * If a command buffer is in the executable state and the command buffer
1301 * was allocated from a command pool with the
1302 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1303 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1304 * as if vkResetCommandBuffer had been called with
1305 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1306 * the command buffer in the recording state.
1308 anv_cmd_buffer_reset(cmd_buffer
);
1310 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1312 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1313 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1315 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1317 /* We sometimes store vertex data in the dynamic state buffer for blorp
1318 * operations and our dynamic state stream may re-use data from previous
1319 * command buffers. In order to prevent stale cache data, we flush the VF
1320 * cache. We could do this on every blorp call but that's not really
1321 * needed as all of the data will get written by the CPU prior to the GPU
1322 * executing anything. The chances are fairly high that they will use
1323 * blorp at least once per primary command buffer so it shouldn't be
1326 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1327 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1329 /* We send an "Indirect State Pointers Disable" packet at
1330 * EndCommandBuffer, so all push contant packets are ignored during a
1331 * context restore. Documentation says after that command, we need to
1332 * emit push constants again before any rendering operation. So we
1333 * flag them dirty here to make sure they get emitted.
1335 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1337 VkResult result
= VK_SUCCESS
;
1338 if (cmd_buffer
->usage_flags
&
1339 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1340 assert(pBeginInfo
->pInheritanceInfo
);
1341 cmd_buffer
->state
.pass
=
1342 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1343 cmd_buffer
->state
.subpass
=
1344 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1346 /* This is optional in the inheritance info. */
1347 cmd_buffer
->state
.framebuffer
=
1348 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1350 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1351 cmd_buffer
->state
.pass
, NULL
);
1353 /* Record that HiZ is enabled if we can. */
1354 if (cmd_buffer
->state
.framebuffer
) {
1355 const struct anv_image_view
* const iview
=
1356 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1359 VkImageLayout layout
=
1360 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1362 enum isl_aux_usage aux_usage
=
1363 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1364 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1366 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1370 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1373 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1374 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1375 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1376 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1378 /* If secondary buffer supports conditional rendering
1379 * we should emit commands as if conditional rendering is enabled.
1381 cmd_buffer
->state
.conditional_render_enabled
=
1382 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1389 /* From the PRM, Volume 2a:
1391 * "Indirect State Pointers Disable
1393 * At the completion of the post-sync operation associated with this pipe
1394 * control packet, the indirect state pointers in the hardware are
1395 * considered invalid; the indirect pointers are not saved in the context.
1396 * If any new indirect state commands are executed in the command stream
1397 * while the pipe control is pending, the new indirect state commands are
1400 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1401 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1402 * commands are only considered as Indirect State Pointers. Once ISP is
1403 * issued in a context, SW must initialize by programming push constant
1404 * commands for all the shaders (at least to zero length) before attempting
1405 * any rendering operation for the same context."
1407 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1408 * even though they point to a BO that has been already unreferenced at
1409 * the end of the previous batch buffer. This has been fine so far since
1410 * we are protected by these scratch page (every address not covered by
1411 * a BO should be pointing to the scratch page). But on CNL, it is
1412 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1415 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1416 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1417 * context restore, so the mentioned hang doesn't happen. However,
1418 * software must program push constant commands for all stages prior to
1419 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1421 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1422 * constants have been loaded into the EUs prior to disable the push constants
1423 * so that it doesn't hang a previous 3DPRIMITIVE.
1426 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1428 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1429 pc
.StallAtPixelScoreboard
= true;
1430 pc
.CommandStreamerStallEnable
= true;
1432 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1433 pc
.IndirectStatePointersDisable
= true;
1434 pc
.CommandStreamerStallEnable
= true;
1439 genX(EndCommandBuffer
)(
1440 VkCommandBuffer commandBuffer
)
1442 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1444 if (anv_batch_has_error(&cmd_buffer
->batch
))
1445 return cmd_buffer
->batch
.status
;
1447 /* We want every command buffer to start with the PMA fix in a known state,
1448 * so we disable it at the end of the command buffer.
1450 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1452 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1454 emit_isp_disable(cmd_buffer
);
1456 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1462 genX(CmdExecuteCommands
)(
1463 VkCommandBuffer commandBuffer
,
1464 uint32_t commandBufferCount
,
1465 const VkCommandBuffer
* pCmdBuffers
)
1467 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1469 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1471 if (anv_batch_has_error(&primary
->batch
))
1474 /* The secondary command buffers will assume that the PMA fix is disabled
1475 * when they begin executing. Make sure this is true.
1477 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1479 /* The secondary command buffer doesn't know which textures etc. have been
1480 * flushed prior to their execution. Apply those flushes now.
1482 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1484 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1485 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1487 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1488 assert(!anv_batch_has_error(&secondary
->batch
));
1490 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1491 if (secondary
->state
.conditional_render_enabled
) {
1492 if (!primary
->state
.conditional_render_enabled
) {
1493 /* Secondary buffer is constructed as if it will be executed
1494 * with conditional rendering, we should satisfy this dependency
1495 * regardless of conditional rendering being enabled in primary.
1497 struct gen_mi_builder b
;
1498 gen_mi_builder_init(&b
, &primary
->batch
);
1499 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1500 gen_mi_imm(UINT64_MAX
));
1505 if (secondary
->usage_flags
&
1506 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1507 /* If we're continuing a render pass from the primary, we need to
1508 * copy the surface states for the current subpass into the storage
1509 * we allocated for them in BeginCommandBuffer.
1511 struct anv_bo
*ss_bo
=
1512 primary
->device
->surface_state_pool
.block_pool
.bo
;
1513 struct anv_state src_state
= primary
->state
.render_pass_states
;
1514 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1515 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1517 genX(cmd_buffer_so_memcpy
)(primary
,
1518 (struct anv_address
) {
1520 .offset
= dst_state
.offset
,
1522 (struct anv_address
) {
1524 .offset
= src_state
.offset
,
1526 src_state
.alloc_size
);
1529 anv_cmd_buffer_add_secondary(primary
, secondary
);
1532 /* The secondary may have selected a different pipeline (3D or compute) and
1533 * may have changed the current L3$ configuration. Reset our tracking
1534 * variables to invalid values to ensure that we re-emit these in the case
1535 * where we do any draws or compute dispatches from the primary after the
1536 * secondary has returned.
1538 primary
->state
.current_pipeline
= UINT32_MAX
;
1539 primary
->state
.current_l3_config
= NULL
;
1541 /* Each of the secondary command buffers will use its own state base
1542 * address. We need to re-emit state base address for the primary after
1543 * all of the secondaries are done.
1545 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1548 genX(cmd_buffer_emit_state_base_address
)(primary
);
1551 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1552 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1553 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1556 * Program the hardware to use the specified L3 configuration.
1559 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1560 const struct gen_l3_config
*cfg
)
1563 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1566 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1567 intel_logd("L3 config transition: ");
1568 gen_dump_l3_config(cfg
, stderr
);
1571 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1573 /* According to the hardware docs, the L3 partitioning can only be changed
1574 * while the pipeline is completely drained and the caches are flushed,
1575 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1577 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1578 pc
.DCFlushEnable
= true;
1579 pc
.PostSyncOperation
= NoWrite
;
1580 pc
.CommandStreamerStallEnable
= true;
1583 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1584 * invalidation of the relevant caches. Note that because RO invalidation
1585 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1586 * command is processed by the CS) we cannot combine it with the previous
1587 * stalling flush as the hardware documentation suggests, because that
1588 * would cause the CS to stall on previous rendering *after* RO
1589 * invalidation and wouldn't prevent the RO caches from being polluted by
1590 * concurrent rendering before the stall completes. This intentionally
1591 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1592 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1593 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1594 * already guarantee that there is no concurrent GPGPU kernel execution
1595 * (see SKL HSD 2132585).
1597 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1598 pc
.TextureCacheInvalidationEnable
= true;
1599 pc
.ConstantCacheInvalidationEnable
= true;
1600 pc
.InstructionCacheInvalidateEnable
= true;
1601 pc
.StateCacheInvalidationEnable
= true;
1602 pc
.PostSyncOperation
= NoWrite
;
1605 /* Now send a third stalling flush to make sure that invalidation is
1606 * complete when the L3 configuration registers are modified.
1608 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1609 pc
.DCFlushEnable
= true;
1610 pc
.PostSyncOperation
= NoWrite
;
1611 pc
.CommandStreamerStallEnable
= true;
1616 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1619 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1620 .SLMEnable
= has_slm
,
1622 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1623 * in L3CNTLREG register. The default setting of the bit is not the
1624 * desirable behavior.
1626 .ErrorDetectionBehaviorControl
= true,
1627 .UseFullWays
= true,
1629 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1630 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1631 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1632 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1634 /* Set up the L3 partitioning. */
1635 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1639 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1640 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1641 cfg
->n
[GEN_L3P_ALL
];
1642 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1643 cfg
->n
[GEN_L3P_ALL
];
1644 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1645 cfg
->n
[GEN_L3P_ALL
];
1647 assert(!cfg
->n
[GEN_L3P_ALL
]);
1649 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1650 * the matching space on the remaining banks has to be allocated to a
1651 * client (URB for all validated configurations) set to the
1652 * lower-bandwidth 2-bank address hashing mode.
1654 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1655 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1656 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1658 /* Minimum number of ways that can be allocated to the URB. */
1659 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1660 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1662 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1663 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1664 .ConvertDC_UC
= !has_dc
,
1665 .ConvertIS_UC
= !has_is
,
1666 .ConvertC_UC
= !has_c
,
1667 .ConvertT_UC
= !has_t
);
1669 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1670 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1671 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1673 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1674 .SLMEnable
= has_slm
,
1675 .URBLowBandwidth
= urb_low_bw
,
1676 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1678 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1680 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1681 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1683 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1684 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1685 .ISLowBandwidth
= 0,
1686 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1688 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1689 .TLowBandwidth
= 0);
1691 /* Set up the L3 partitioning. */
1692 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1693 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1694 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1697 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1698 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1699 * them disabled to avoid crashing the system hard.
1701 uint32_t scratch1
, chicken3
;
1702 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1703 .L3AtomicDisable
= !has_dc
);
1704 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1705 .L3AtomicDisableMask
= true,
1706 .L3AtomicDisable
= !has_dc
);
1707 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1708 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1714 cmd_buffer
->state
.current_l3_config
= cfg
;
1718 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1720 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1722 /* Flushes are pipelined while invalidations are handled immediately.
1723 * Therefore, if we're flushing anything then we need to schedule a stall
1724 * before any invalidations can happen.
1726 if (bits
& ANV_PIPE_FLUSH_BITS
)
1727 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1729 /* If we're going to do an invalidate and we have a pending CS stall that
1730 * has yet to be resolved, we do the CS stall now.
1732 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1733 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1734 bits
|= ANV_PIPE_CS_STALL_BIT
;
1735 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1738 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1739 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1740 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1741 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1742 pipe
.RenderTargetCacheFlushEnable
=
1743 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1745 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1746 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1747 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1750 * According to the Broadwell documentation, any PIPE_CONTROL with the
1751 * "Command Streamer Stall" bit set must also have another bit set,
1752 * with five different options:
1754 * - Render Target Cache Flush
1755 * - Depth Cache Flush
1756 * - Stall at Pixel Scoreboard
1757 * - Post-Sync Operation
1761 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1762 * mesa and it seems to work fine. The choice is fairly arbitrary.
1764 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1765 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1766 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1767 pipe
.StallAtPixelScoreboard
= true;
1770 /* If a render target flush was emitted, then we can toggle off the bit
1771 * saying that render target writes are ongoing.
1773 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1774 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1776 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1779 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1780 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1782 * "If the VF Cache Invalidation Enable is set to a 1 in a
1783 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1784 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1785 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1788 * This appears to hang Broadwell, so we restrict it to just gen9.
1790 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1791 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1793 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1794 pipe
.StateCacheInvalidationEnable
=
1795 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1796 pipe
.ConstantCacheInvalidationEnable
=
1797 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1798 pipe
.VFCacheInvalidationEnable
=
1799 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1800 pipe
.TextureCacheInvalidationEnable
=
1801 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1802 pipe
.InstructionCacheInvalidateEnable
=
1803 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1805 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1807 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1808 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1809 * “Write Timestamp”.
1811 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1812 pipe
.PostSyncOperation
= WriteImmediateData
;
1814 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1818 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1821 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1824 void genX(CmdPipelineBarrier
)(
1825 VkCommandBuffer commandBuffer
,
1826 VkPipelineStageFlags srcStageMask
,
1827 VkPipelineStageFlags destStageMask
,
1829 uint32_t memoryBarrierCount
,
1830 const VkMemoryBarrier
* pMemoryBarriers
,
1831 uint32_t bufferMemoryBarrierCount
,
1832 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1833 uint32_t imageMemoryBarrierCount
,
1834 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1836 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1838 /* XXX: Right now, we're really dumb and just flush whatever categories
1839 * the app asks for. One of these days we may make this a bit better
1840 * but right now that's all the hardware allows for in most areas.
1842 VkAccessFlags src_flags
= 0;
1843 VkAccessFlags dst_flags
= 0;
1845 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1846 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1847 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1850 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1851 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1852 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1855 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1856 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1857 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1858 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1859 const VkImageSubresourceRange
*range
=
1860 &pImageMemoryBarriers
[i
].subresourceRange
;
1862 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1863 transition_depth_buffer(cmd_buffer
, image
,
1864 pImageMemoryBarriers
[i
].oldLayout
,
1865 pImageMemoryBarriers
[i
].newLayout
);
1866 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1867 VkImageAspectFlags color_aspects
=
1868 anv_image_expand_aspects(image
, range
->aspectMask
);
1869 uint32_t aspect_bit
;
1871 uint32_t base_layer
, layer_count
;
1872 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1874 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1876 base_layer
= range
->baseArrayLayer
;
1877 layer_count
= anv_get_layerCount(image
, range
);
1880 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1881 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1882 range
->baseMipLevel
,
1883 anv_get_levelCount(image
, range
),
1884 base_layer
, layer_count
,
1885 pImageMemoryBarriers
[i
].oldLayout
,
1886 pImageMemoryBarriers
[i
].newLayout
);
1891 cmd_buffer
->state
.pending_pipe_bits
|=
1892 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1893 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1897 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1899 VkShaderStageFlags stages
=
1900 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1902 /* In order to avoid thrash, we assume that vertex and fragment stages
1903 * always exist. In the rare case where one is missing *and* the other
1904 * uses push concstants, this may be suboptimal. However, avoiding stalls
1905 * seems more important.
1907 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1909 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1913 const unsigned push_constant_kb
= 32;
1914 #elif GEN_IS_HASWELL
1915 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1917 const unsigned push_constant_kb
= 16;
1920 const unsigned num_stages
=
1921 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1922 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1924 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1925 * units of 2KB. Incidentally, these are the same platforms that have
1926 * 32KB worth of push constant space.
1928 if (push_constant_kb
== 32)
1929 size_per_stage
&= ~1u;
1931 uint32_t kb_used
= 0;
1932 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1933 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1934 anv_batch_emit(&cmd_buffer
->batch
,
1935 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1936 alloc
._3DCommandSubOpcode
= 18 + i
;
1937 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1938 alloc
.ConstantBufferSize
= push_size
;
1940 kb_used
+= push_size
;
1943 anv_batch_emit(&cmd_buffer
->batch
,
1944 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1945 alloc
.ConstantBufferOffset
= kb_used
;
1946 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1949 cmd_buffer
->state
.push_constant_stages
= stages
;
1951 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1953 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1954 * the next 3DPRIMITIVE command after programming the
1955 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1957 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1958 * pipeline setup, we need to dirty push constants.
1960 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1963 static const struct anv_descriptor
*
1964 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1965 const struct anv_pipeline_binding
*binding
)
1967 assert(binding
->set
< MAX_SETS
);
1968 const struct anv_descriptor_set
*set
=
1969 pipe_state
->descriptors
[binding
->set
];
1970 const uint32_t offset
=
1971 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1972 return &set
->descriptors
[offset
+ binding
->index
];
1976 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1977 const struct anv_pipeline_binding
*binding
)
1979 assert(binding
->set
< MAX_SETS
);
1980 const struct anv_descriptor_set
*set
=
1981 pipe_state
->descriptors
[binding
->set
];
1983 uint32_t dynamic_offset_idx
=
1984 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1985 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1988 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1991 static struct anv_address
1992 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
1993 struct anv_descriptor_set
*set
)
1996 /* This is a normal descriptor set */
1997 return (struct anv_address
) {
1998 .bo
= &set
->pool
->bo
,
1999 .offset
= set
->desc_mem
.offset
,
2002 /* This is a push descriptor set. We have to flag it as used on the GPU
2003 * so that the next time we push descriptors, we grab a new memory.
2005 struct anv_push_descriptor_set
*push_set
=
2006 (struct anv_push_descriptor_set
*)set
;
2007 push_set
->set_used_on_gpu
= true;
2009 return (struct anv_address
) {
2010 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2011 .offset
= set
->desc_mem
.offset
,
2017 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2018 gl_shader_stage stage
,
2019 struct anv_state
*bt_state
)
2021 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2022 struct anv_cmd_pipeline_state
*pipe_state
;
2023 struct anv_pipeline
*pipeline
;
2024 uint32_t state_offset
;
2027 case MESA_SHADER_COMPUTE
:
2028 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2031 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2034 pipeline
= pipe_state
->pipeline
;
2036 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2037 *bt_state
= (struct anv_state
) { 0, };
2041 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2042 if (map
->surface_count
== 0) {
2043 *bt_state
= (struct anv_state
) { 0, };
2047 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2050 uint32_t *bt_map
= bt_state
->map
;
2052 if (bt_state
->map
== NULL
)
2053 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2055 /* We only need to emit relocs if we're not using softpin. If we are using
2056 * softpin then we always keep all user-allocated memory objects resident.
2058 const bool need_client_mem_relocs
=
2059 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
;
2061 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2062 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2064 struct anv_state surface_state
;
2066 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2067 /* Color attachment binding */
2068 assert(stage
== MESA_SHADER_FRAGMENT
);
2069 assert(binding
->binding
== 0);
2070 if (binding
->index
< subpass
->color_count
) {
2071 const unsigned att
=
2072 subpass
->color_attachments
[binding
->index
].attachment
;
2074 /* From the Vulkan 1.0.46 spec:
2076 * "If any color or depth/stencil attachments are
2077 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2080 if (att
== VK_ATTACHMENT_UNUSED
) {
2081 surface_state
= cmd_buffer
->state
.null_surface_state
;
2083 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2086 surface_state
= cmd_buffer
->state
.null_surface_state
;
2089 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2091 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2092 struct anv_state surface_state
=
2093 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2095 struct anv_address constant_data
= {
2096 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2097 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2099 unsigned constant_data_size
=
2100 pipeline
->shaders
[stage
]->constant_data_size
;
2102 const enum isl_format format
=
2103 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2104 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2105 surface_state
, format
,
2106 constant_data
, constant_data_size
, 1);
2108 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2109 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2111 } else if (binding
->set
== ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
) {
2112 /* This is always the first binding for compute shaders */
2113 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2114 if (!get_cs_prog_data(pipeline
)->uses_num_work_groups
)
2117 struct anv_state surface_state
=
2118 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2120 const enum isl_format format
=
2121 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2122 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2124 cmd_buffer
->state
.compute
.num_workgroups
,
2126 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2127 if (need_client_mem_relocs
) {
2128 add_surface_reloc(cmd_buffer
, surface_state
,
2129 cmd_buffer
->state
.compute
.num_workgroups
);
2132 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2133 /* This is a descriptor set buffer so the set index is actually
2134 * given by binding->binding. (Yes, that's confusing.)
2136 struct anv_descriptor_set
*set
=
2137 pipe_state
->descriptors
[binding
->binding
];
2138 assert(set
->desc_mem
.alloc_size
);
2139 assert(set
->desc_surface_state
.alloc_size
);
2140 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2141 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2142 anv_descriptor_set_address(cmd_buffer
, set
));
2146 const struct anv_descriptor
*desc
=
2147 anv_descriptor_for_binding(pipe_state
, binding
);
2149 switch (desc
->type
) {
2150 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2151 /* Nothing for us to do here */
2154 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2155 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2156 struct anv_surface_state sstate
=
2157 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2158 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2159 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2160 surface_state
= sstate
.state
;
2161 assert(surface_state
.alloc_size
);
2162 if (need_client_mem_relocs
)
2163 add_surface_state_relocs(cmd_buffer
, sstate
);
2166 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2167 assert(stage
== MESA_SHADER_FRAGMENT
);
2168 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2169 /* For depth and stencil input attachments, we treat it like any
2170 * old texture that a user may have bound.
2172 struct anv_surface_state sstate
=
2173 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2174 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2175 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2176 surface_state
= sstate
.state
;
2177 assert(surface_state
.alloc_size
);
2178 if (need_client_mem_relocs
)
2179 add_surface_state_relocs(cmd_buffer
, sstate
);
2181 /* For color input attachments, we create the surface state at
2182 * vkBeginRenderPass time so that we can include aux and clear
2183 * color information.
2185 assert(binding
->input_attachment_index
< subpass
->input_count
);
2186 const unsigned subpass_att
= binding
->input_attachment_index
;
2187 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2188 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2192 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2193 struct anv_surface_state sstate
= (binding
->write_only
)
2194 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2195 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2196 surface_state
= sstate
.state
;
2197 assert(surface_state
.alloc_size
);
2198 if (need_client_mem_relocs
)
2199 add_surface_state_relocs(cmd_buffer
, sstate
);
2203 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2204 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2205 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2206 surface_state
= desc
->buffer_view
->surface_state
;
2207 assert(surface_state
.alloc_size
);
2208 if (need_client_mem_relocs
) {
2209 add_surface_reloc(cmd_buffer
, surface_state
,
2210 desc
->buffer_view
->address
);
2214 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2215 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2216 /* Compute the offset within the buffer */
2217 uint32_t dynamic_offset
=
2218 dynamic_offset_for_binding(pipe_state
, binding
);
2219 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2220 /* Clamp to the buffer size */
2221 offset
= MIN2(offset
, desc
->buffer
->size
);
2222 /* Clamp the range to the buffer size */
2223 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2225 struct anv_address address
=
2226 anv_address_add(desc
->buffer
->address
, offset
);
2229 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2230 enum isl_format format
=
2231 anv_isl_format_for_descriptor_type(desc
->type
);
2233 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2234 format
, address
, range
, 1);
2235 if (need_client_mem_relocs
)
2236 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2240 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2241 surface_state
= (binding
->write_only
)
2242 ? desc
->buffer_view
->writeonly_storage_surface_state
2243 : desc
->buffer_view
->storage_surface_state
;
2244 assert(surface_state
.alloc_size
);
2245 if (need_client_mem_relocs
) {
2246 add_surface_reloc(cmd_buffer
, surface_state
,
2247 desc
->buffer_view
->address
);
2252 assert(!"Invalid descriptor type");
2256 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2260 /* The PIPE_CONTROL command description says:
2262 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2263 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2264 * Target Cache Flush by enabling this bit. When render target flush
2265 * is set due to new association of BTI, PS Scoreboard Stall bit must
2266 * be set in this packet."
2268 * FINISHME: Currently we shuffle around the surface states in the binding
2269 * table based on if they are getting used or not. So, we've to do below
2270 * pipe control flush for every binding table upload. Make changes so
2271 * that we do it only when we modify render target surface states.
2273 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2274 pc
.RenderTargetCacheFlushEnable
= true;
2275 pc
.StallAtPixelScoreboard
= true;
2283 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2284 gl_shader_stage stage
,
2285 struct anv_state
*state
)
2287 struct anv_cmd_pipeline_state
*pipe_state
=
2288 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2289 &cmd_buffer
->state
.gfx
.base
;
2290 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2292 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2293 *state
= (struct anv_state
) { 0, };
2297 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2298 if (map
->sampler_count
== 0) {
2299 *state
= (struct anv_state
) { 0, };
2303 uint32_t size
= map
->sampler_count
* 16;
2304 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2306 if (state
->map
== NULL
)
2307 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2309 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2310 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2311 const struct anv_descriptor
*desc
=
2312 anv_descriptor_for_binding(pipe_state
, binding
);
2314 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2315 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2318 struct anv_sampler
*sampler
= desc
->sampler
;
2320 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2321 * happens to be zero.
2323 if (sampler
== NULL
)
2326 memcpy(state
->map
+ (s
* 16),
2327 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2334 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2336 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2338 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2339 pipeline
->active_stages
;
2341 VkResult result
= VK_SUCCESS
;
2342 anv_foreach_stage(s
, dirty
) {
2343 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2344 if (result
!= VK_SUCCESS
)
2346 result
= emit_binding_table(cmd_buffer
, s
,
2347 &cmd_buffer
->state
.binding_tables
[s
]);
2348 if (result
!= VK_SUCCESS
)
2352 if (result
!= VK_SUCCESS
) {
2353 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2355 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2356 if (result
!= VK_SUCCESS
)
2359 /* Re-emit state base addresses so we get the new surface state base
2360 * address before we start emitting binding tables etc.
2362 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2364 /* Re-emit all active binding tables */
2365 dirty
|= pipeline
->active_stages
;
2366 anv_foreach_stage(s
, dirty
) {
2367 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2368 if (result
!= VK_SUCCESS
) {
2369 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2372 result
= emit_binding_table(cmd_buffer
, s
,
2373 &cmd_buffer
->state
.binding_tables
[s
]);
2374 if (result
!= VK_SUCCESS
) {
2375 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2381 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2387 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2390 static const uint32_t sampler_state_opcodes
[] = {
2391 [MESA_SHADER_VERTEX
] = 43,
2392 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2393 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2394 [MESA_SHADER_GEOMETRY
] = 46,
2395 [MESA_SHADER_FRAGMENT
] = 47,
2396 [MESA_SHADER_COMPUTE
] = 0,
2399 static const uint32_t binding_table_opcodes
[] = {
2400 [MESA_SHADER_VERTEX
] = 38,
2401 [MESA_SHADER_TESS_CTRL
] = 39,
2402 [MESA_SHADER_TESS_EVAL
] = 40,
2403 [MESA_SHADER_GEOMETRY
] = 41,
2404 [MESA_SHADER_FRAGMENT
] = 42,
2405 [MESA_SHADER_COMPUTE
] = 0,
2408 anv_foreach_stage(s
, stages
) {
2409 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2410 assert(binding_table_opcodes
[s
] > 0);
2412 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2413 anv_batch_emit(&cmd_buffer
->batch
,
2414 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2415 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2416 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2420 /* Always emit binding table pointers if we're asked to, since on SKL
2421 * this is what flushes push constants. */
2422 anv_batch_emit(&cmd_buffer
->batch
,
2423 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2424 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2425 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2431 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2432 VkShaderStageFlags dirty_stages
)
2434 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2435 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2437 static const uint32_t push_constant_opcodes
[] = {
2438 [MESA_SHADER_VERTEX
] = 21,
2439 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2440 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2441 [MESA_SHADER_GEOMETRY
] = 22,
2442 [MESA_SHADER_FRAGMENT
] = 23,
2443 [MESA_SHADER_COMPUTE
] = 0,
2446 VkShaderStageFlags flushed
= 0;
2448 anv_foreach_stage(stage
, dirty_stages
) {
2449 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2450 assert(push_constant_opcodes
[stage
] > 0);
2452 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2453 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2455 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2456 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2457 const struct brw_stage_prog_data
*prog_data
=
2458 pipeline
->shaders
[stage
]->prog_data
;
2459 const struct anv_pipeline_bind_map
*bind_map
=
2460 &pipeline
->shaders
[stage
]->bind_map
;
2462 /* The Skylake PRM contains the following restriction:
2464 * "The driver must ensure The following case does not occur
2465 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2466 * buffer 3 read length equal to zero committed followed by a
2467 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2470 * To avoid this, we program the buffers in the highest slots.
2471 * This way, slot 0 is only used if slot 3 is also used.
2475 for (int i
= 3; i
>= 0; i
--) {
2476 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2477 if (range
->length
== 0)
2480 const unsigned surface
=
2481 prog_data
->binding_table
.ubo_start
+ range
->block
;
2483 assert(surface
<= bind_map
->surface_count
);
2484 const struct anv_pipeline_binding
*binding
=
2485 &bind_map
->surface_to_descriptor
[surface
];
2487 struct anv_address read_addr
;
2489 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2490 struct anv_address constant_data
= {
2491 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2492 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2494 unsigned constant_data_size
=
2495 pipeline
->shaders
[stage
]->constant_data_size
;
2497 read_len
= MIN2(range
->length
,
2498 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2499 read_addr
= anv_address_add(constant_data
,
2501 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2502 /* This is a descriptor set buffer so the set index is
2503 * actually given by binding->binding. (Yes, that's
2506 struct anv_descriptor_set
*set
=
2507 gfx_state
->base
.descriptors
[binding
->binding
];
2508 struct anv_address desc_buffer_addr
=
2509 anv_descriptor_set_address(cmd_buffer
, set
);
2510 const unsigned desc_buffer_size
= set
->desc_mem
.alloc_size
;
2512 read_len
= MIN2(range
->length
,
2513 DIV_ROUND_UP(desc_buffer_size
, 32) - range
->start
);
2514 read_addr
= anv_address_add(desc_buffer_addr
,
2517 const struct anv_descriptor
*desc
=
2518 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2520 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2521 read_len
= MIN2(range
->length
,
2522 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2523 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2526 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2528 uint32_t dynamic_offset
=
2529 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2530 uint32_t buf_offset
=
2531 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2532 uint32_t buf_range
=
2533 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2535 read_len
= MIN2(range
->length
,
2536 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2537 read_addr
= anv_address_add(desc
->buffer
->address
,
2538 buf_offset
+ range
->start
* 32);
2543 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2544 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2549 struct anv_state state
=
2550 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2552 if (state
.alloc_size
> 0) {
2553 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2554 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2555 .offset
= state
.offset
,
2557 c
.ConstantBody
.ReadLength
[n
] =
2558 DIV_ROUND_UP(state
.alloc_size
, 32);
2561 /* For Ivy Bridge, the push constants packets have a different
2562 * rule that would require us to iterate in the other direction
2563 * and possibly mess around with dynamic state base address.
2564 * Don't bother; just emit regular push constants at n = 0.
2566 struct anv_state state
=
2567 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2569 if (state
.alloc_size
> 0) {
2570 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2571 c
.ConstantBody
.ReadLength
[0] =
2572 DIV_ROUND_UP(state
.alloc_size
, 32);
2578 flushed
|= mesa_to_vk_shader_stage(stage
);
2581 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2585 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2587 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2590 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2591 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2592 vb_emit
|= pipeline
->vb_used
;
2594 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2596 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2598 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2601 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2602 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2604 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2605 GENX(3DSTATE_VERTEX_BUFFERS
));
2607 for_each_bit(vb
, vb_emit
) {
2608 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2609 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2611 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2612 .VertexBufferIndex
= vb
,
2614 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2616 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2617 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2620 .AddressModifyEnable
= true,
2621 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2622 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2625 .BufferSize
= buffer
->size
- offset
2627 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2631 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2636 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2639 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2640 /* We don't need any per-buffer dirty tracking because you're not
2641 * allowed to bind different XFB buffers while XFB is enabled.
2643 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2644 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2645 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2646 sob
.SOBufferIndex
= idx
;
2648 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2649 sob
.SOBufferEnable
= true;
2650 sob
.MOCS
= cmd_buffer
->device
->default_mocs
,
2651 sob
.StreamOffsetWriteEnable
= false;
2652 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2654 /* Size is in DWords - 1 */
2655 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2660 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2662 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2666 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2667 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2669 /* The exact descriptor layout is pulled from the pipeline, so we need
2670 * to re-emit binding tables on every pipeline change.
2672 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2674 /* If the pipeline changed, we may need to re-allocate push constant
2677 cmd_buffer_alloc_push_constants(cmd_buffer
);
2681 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2682 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2683 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2685 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2686 * stall needs to be sent just prior to any 3DSTATE_VS,
2687 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2688 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2689 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2690 * PIPE_CONTROL needs to be sent before any combination of VS
2691 * associated 3DSTATE."
2693 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2694 pc
.DepthStallEnable
= true;
2695 pc
.PostSyncOperation
= WriteImmediateData
;
2697 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2702 /* Render targets live in the same binding table as fragment descriptors */
2703 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2704 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2706 /* We emit the binding tables and sampler tables first, then emit push
2707 * constants and then finally emit binding table and sampler table
2708 * pointers. It has to happen in this order, since emitting the binding
2709 * tables may change the push constants (in case of storage images). After
2710 * emitting push constants, on SKL+ we have to emit the corresponding
2711 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2714 if (cmd_buffer
->state
.descriptors_dirty
)
2715 dirty
= flush_descriptor_sets(cmd_buffer
);
2717 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2718 /* Because we're pushing UBOs, we have to push whenever either
2719 * descriptors or push constants is dirty.
2721 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2722 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2723 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2727 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2729 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2730 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2732 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2733 ANV_CMD_DIRTY_PIPELINE
)) {
2734 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2735 pipeline
->depth_clamp_enable
);
2738 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2739 ANV_CMD_DIRTY_RENDER_TARGETS
))
2740 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2742 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2744 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2748 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2749 struct anv_address addr
,
2750 uint32_t size
, uint32_t index
)
2752 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2753 GENX(3DSTATE_VERTEX_BUFFERS
));
2755 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2756 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2757 .VertexBufferIndex
= index
,
2758 .AddressModifyEnable
= true,
2760 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2762 .BufferStartingAddress
= addr
,
2765 .BufferStartingAddress
= addr
,
2766 .EndAddress
= anv_address_add(addr
, size
),
2772 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2773 struct anv_address addr
)
2775 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2779 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2780 uint32_t base_vertex
, uint32_t base_instance
)
2782 struct anv_state id_state
=
2783 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2785 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2786 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2788 struct anv_address addr
= {
2789 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2790 .offset
= id_state
.offset
,
2793 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2797 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2799 struct anv_state state
=
2800 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2802 ((uint32_t *)state
.map
)[0] = draw_index
;
2804 struct anv_address addr
= {
2805 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2806 .offset
= state
.offset
,
2809 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2813 VkCommandBuffer commandBuffer
,
2814 uint32_t vertexCount
,
2815 uint32_t instanceCount
,
2816 uint32_t firstVertex
,
2817 uint32_t firstInstance
)
2819 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2820 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2821 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2823 if (anv_batch_has_error(&cmd_buffer
->batch
))
2826 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2828 if (cmd_buffer
->state
.conditional_render_enabled
)
2829 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2831 if (vs_prog_data
->uses_firstvertex
||
2832 vs_prog_data
->uses_baseinstance
)
2833 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2834 if (vs_prog_data
->uses_drawid
)
2835 emit_draw_index(cmd_buffer
, 0);
2837 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2838 * different views. We need to multiply instanceCount by the view count.
2840 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2842 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2843 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2844 prim
.VertexAccessType
= SEQUENTIAL
;
2845 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2846 prim
.VertexCountPerInstance
= vertexCount
;
2847 prim
.StartVertexLocation
= firstVertex
;
2848 prim
.InstanceCount
= instanceCount
;
2849 prim
.StartInstanceLocation
= firstInstance
;
2850 prim
.BaseVertexLocation
= 0;
2854 void genX(CmdDrawIndexed
)(
2855 VkCommandBuffer commandBuffer
,
2856 uint32_t indexCount
,
2857 uint32_t instanceCount
,
2858 uint32_t firstIndex
,
2859 int32_t vertexOffset
,
2860 uint32_t firstInstance
)
2862 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2863 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2864 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2866 if (anv_batch_has_error(&cmd_buffer
->batch
))
2869 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2871 if (cmd_buffer
->state
.conditional_render_enabled
)
2872 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2874 if (vs_prog_data
->uses_firstvertex
||
2875 vs_prog_data
->uses_baseinstance
)
2876 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2877 if (vs_prog_data
->uses_drawid
)
2878 emit_draw_index(cmd_buffer
, 0);
2880 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2881 * different views. We need to multiply instanceCount by the view count.
2883 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2885 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2886 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2887 prim
.VertexAccessType
= RANDOM
;
2888 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2889 prim
.VertexCountPerInstance
= indexCount
;
2890 prim
.StartVertexLocation
= firstIndex
;
2891 prim
.InstanceCount
= instanceCount
;
2892 prim
.StartInstanceLocation
= firstInstance
;
2893 prim
.BaseVertexLocation
= vertexOffset
;
2897 /* Auto-Draw / Indirect Registers */
2898 #define GEN7_3DPRIM_END_OFFSET 0x2420
2899 #define GEN7_3DPRIM_START_VERTEX 0x2430
2900 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2901 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2902 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2903 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2905 void genX(CmdDrawIndirectByteCountEXT
)(
2906 VkCommandBuffer commandBuffer
,
2907 uint32_t instanceCount
,
2908 uint32_t firstInstance
,
2909 VkBuffer counterBuffer
,
2910 VkDeviceSize counterBufferOffset
,
2911 uint32_t counterOffset
,
2912 uint32_t vertexStride
)
2914 #if GEN_IS_HASWELL || GEN_GEN >= 8
2915 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2916 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
2917 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2918 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2920 /* firstVertex is always zero for this draw function */
2921 const uint32_t firstVertex
= 0;
2923 if (anv_batch_has_error(&cmd_buffer
->batch
))
2926 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2928 if (vs_prog_data
->uses_firstvertex
||
2929 vs_prog_data
->uses_baseinstance
)
2930 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2931 if (vs_prog_data
->uses_drawid
)
2932 emit_draw_index(cmd_buffer
, 0);
2934 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2935 * different views. We need to multiply instanceCount by the view count.
2937 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2939 struct gen_mi_builder b
;
2940 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
2941 struct gen_mi_value count
=
2942 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
2943 counterBufferOffset
));
2945 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
2946 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
2947 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
2949 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
2950 gen_mi_imm(firstVertex
));
2951 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
2952 gen_mi_imm(instanceCount
));
2953 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
2954 gen_mi_imm(firstInstance
));
2955 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
2957 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2958 prim
.IndirectParameterEnable
= true;
2959 prim
.VertexAccessType
= SEQUENTIAL
;
2960 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2962 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2966 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2967 struct anv_address addr
,
2970 struct gen_mi_builder b
;
2971 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
2973 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
2974 gen_mi_mem32(anv_address_add(addr
, 0)));
2976 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
2977 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2978 if (view_count
> 1) {
2979 #if GEN_IS_HASWELL || GEN_GEN >= 8
2980 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
2982 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2983 "MI_MATH is not supported on Ivy Bridge");
2986 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
2988 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
2989 gen_mi_mem32(anv_address_add(addr
, 8)));
2992 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
2993 gen_mi_mem32(anv_address_add(addr
, 12)));
2994 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
2995 gen_mi_mem32(anv_address_add(addr
, 16)));
2997 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
2998 gen_mi_mem32(anv_address_add(addr
, 12)));
2999 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3003 void genX(CmdDrawIndirect
)(
3004 VkCommandBuffer commandBuffer
,
3006 VkDeviceSize offset
,
3010 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3011 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3012 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3013 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3015 if (anv_batch_has_error(&cmd_buffer
->batch
))
3018 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3020 if (cmd_buffer
->state
.conditional_render_enabled
)
3021 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3023 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3024 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3026 if (vs_prog_data
->uses_firstvertex
||
3027 vs_prog_data
->uses_baseinstance
)
3028 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3029 if (vs_prog_data
->uses_drawid
)
3030 emit_draw_index(cmd_buffer
, i
);
3032 load_indirect_parameters(cmd_buffer
, draw
, false);
3034 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3035 prim
.IndirectParameterEnable
= true;
3036 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3037 prim
.VertexAccessType
= SEQUENTIAL
;
3038 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3045 void genX(CmdDrawIndexedIndirect
)(
3046 VkCommandBuffer commandBuffer
,
3048 VkDeviceSize offset
,
3052 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3053 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3054 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3055 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3057 if (anv_batch_has_error(&cmd_buffer
->batch
))
3060 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3062 if (cmd_buffer
->state
.conditional_render_enabled
)
3063 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3065 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3066 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3068 /* TODO: We need to stomp base vertex to 0 somehow */
3069 if (vs_prog_data
->uses_firstvertex
||
3070 vs_prog_data
->uses_baseinstance
)
3071 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3072 if (vs_prog_data
->uses_drawid
)
3073 emit_draw_index(cmd_buffer
, i
);
3075 load_indirect_parameters(cmd_buffer
, draw
, true);
3077 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3078 prim
.IndirectParameterEnable
= true;
3079 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3080 prim
.VertexAccessType
= RANDOM
;
3081 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3088 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3091 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3092 struct anv_address count_address
,
3093 const bool conditional_render_enabled
)
3095 struct gen_mi_builder b
;
3096 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3098 if (conditional_render_enabled
) {
3099 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3100 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3101 gen_mi_mem32(count_address
));
3104 /* Upload the current draw count from the draw parameters buffer to
3105 * MI_PREDICATE_SRC0.
3107 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3108 gen_mi_mem32(count_address
));
3110 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3115 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3116 uint32_t draw_index
)
3118 struct gen_mi_builder b
;
3119 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3121 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3122 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3124 if (draw_index
== 0) {
3125 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3126 mip
.LoadOperation
= LOAD_LOADINV
;
3127 mip
.CombineOperation
= COMBINE_SET
;
3128 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3131 /* While draw_index < draw_count the predicate's result will be
3132 * (draw_index == draw_count) ^ TRUE = TRUE
3133 * When draw_index == draw_count the result is
3134 * (TRUE) ^ TRUE = FALSE
3135 * After this all results will be:
3136 * (FALSE) ^ FALSE = FALSE
3138 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3139 mip
.LoadOperation
= LOAD_LOAD
;
3140 mip
.CombineOperation
= COMBINE_XOR
;
3141 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3146 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3148 emit_draw_count_predicate_with_conditional_render(
3149 struct anv_cmd_buffer
*cmd_buffer
,
3150 uint32_t draw_index
)
3152 struct gen_mi_builder b
;
3153 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3155 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3156 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3157 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3160 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3162 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3163 * so we emit MI_PREDICATE to set it.
3166 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3167 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3169 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3170 mip
.LoadOperation
= LOAD_LOADINV
;
3171 mip
.CombineOperation
= COMBINE_SET
;
3172 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3178 void genX(CmdDrawIndirectCountKHR
)(
3179 VkCommandBuffer commandBuffer
,
3181 VkDeviceSize offset
,
3182 VkBuffer _countBuffer
,
3183 VkDeviceSize countBufferOffset
,
3184 uint32_t maxDrawCount
,
3187 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3188 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3189 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3190 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3191 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3192 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3194 if (anv_batch_has_error(&cmd_buffer
->batch
))
3197 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3199 struct anv_address count_address
=
3200 anv_address_add(count_buffer
->address
, countBufferOffset
);
3202 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3203 cmd_state
->conditional_render_enabled
);
3205 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3206 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3208 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3209 if (cmd_state
->conditional_render_enabled
) {
3210 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3212 emit_draw_count_predicate(cmd_buffer
, i
);
3215 emit_draw_count_predicate(cmd_buffer
, i
);
3218 if (vs_prog_data
->uses_firstvertex
||
3219 vs_prog_data
->uses_baseinstance
)
3220 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3221 if (vs_prog_data
->uses_drawid
)
3222 emit_draw_index(cmd_buffer
, i
);
3224 load_indirect_parameters(cmd_buffer
, draw
, false);
3226 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3227 prim
.IndirectParameterEnable
= true;
3228 prim
.PredicateEnable
= true;
3229 prim
.VertexAccessType
= SEQUENTIAL
;
3230 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3237 void genX(CmdDrawIndexedIndirectCountKHR
)(
3238 VkCommandBuffer commandBuffer
,
3240 VkDeviceSize offset
,
3241 VkBuffer _countBuffer
,
3242 VkDeviceSize countBufferOffset
,
3243 uint32_t maxDrawCount
,
3246 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3247 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3248 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3249 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3250 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3251 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3253 if (anv_batch_has_error(&cmd_buffer
->batch
))
3256 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3258 struct anv_address count_address
=
3259 anv_address_add(count_buffer
->address
, countBufferOffset
);
3261 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3262 cmd_state
->conditional_render_enabled
);
3264 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3265 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3267 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3268 if (cmd_state
->conditional_render_enabled
) {
3269 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3271 emit_draw_count_predicate(cmd_buffer
, i
);
3274 emit_draw_count_predicate(cmd_buffer
, i
);
3277 /* TODO: We need to stomp base vertex to 0 somehow */
3278 if (vs_prog_data
->uses_firstvertex
||
3279 vs_prog_data
->uses_baseinstance
)
3280 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3281 if (vs_prog_data
->uses_drawid
)
3282 emit_draw_index(cmd_buffer
, i
);
3284 load_indirect_parameters(cmd_buffer
, draw
, true);
3286 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3287 prim
.IndirectParameterEnable
= true;
3288 prim
.PredicateEnable
= true;
3289 prim
.VertexAccessType
= RANDOM
;
3290 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3297 void genX(CmdBeginTransformFeedbackEXT
)(
3298 VkCommandBuffer commandBuffer
,
3299 uint32_t firstCounterBuffer
,
3300 uint32_t counterBufferCount
,
3301 const VkBuffer
* pCounterBuffers
,
3302 const VkDeviceSize
* pCounterBufferOffsets
)
3304 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3306 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3307 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3308 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3310 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3312 * "Ssoftware must ensure that no HW stream output operations can be in
3313 * process or otherwise pending at the point that the MI_LOAD/STORE
3314 * commands are processed. This will likely require a pipeline flush."
3316 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3317 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3319 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3320 /* If we have a counter buffer, this is a resume so we need to load the
3321 * value into the streamout offset register. Otherwise, this is a begin
3322 * and we need to reset it to zero.
3324 if (pCounterBuffers
&&
3325 idx
>= firstCounterBuffer
&&
3326 idx
- firstCounterBuffer
< counterBufferCount
&&
3327 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3328 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3329 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3330 uint64_t offset
= pCounterBufferOffsets
?
3331 pCounterBufferOffsets
[cb_idx
] : 0;
3333 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3334 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3335 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3339 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3340 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3346 cmd_buffer
->state
.xfb_enabled
= true;
3347 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3350 void genX(CmdEndTransformFeedbackEXT
)(
3351 VkCommandBuffer commandBuffer
,
3352 uint32_t firstCounterBuffer
,
3353 uint32_t counterBufferCount
,
3354 const VkBuffer
* pCounterBuffers
,
3355 const VkDeviceSize
* pCounterBufferOffsets
)
3357 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3359 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3360 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3361 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3363 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3365 * "Ssoftware must ensure that no HW stream output operations can be in
3366 * process or otherwise pending at the point that the MI_LOAD/STORE
3367 * commands are processed. This will likely require a pipeline flush."
3369 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3370 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3372 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3373 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3375 /* If we have a counter buffer, this is a resume so we need to load the
3376 * value into the streamout offset register. Otherwise, this is a begin
3377 * and we need to reset it to zero.
3379 if (pCounterBuffers
&&
3380 cb_idx
< counterBufferCount
&&
3381 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3382 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3383 uint64_t offset
= pCounterBufferOffsets
?
3384 pCounterBufferOffsets
[cb_idx
] : 0;
3386 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3387 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3389 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3394 cmd_buffer
->state
.xfb_enabled
= false;
3395 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3399 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3401 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3402 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3405 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3406 if (result
!= VK_SUCCESS
) {
3407 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3409 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3410 if (result
!= VK_SUCCESS
)
3413 /* Re-emit state base addresses so we get the new surface state base
3414 * address before we start emitting binding tables etc.
3416 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3418 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3419 if (result
!= VK_SUCCESS
) {
3420 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3425 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3426 if (result
!= VK_SUCCESS
) {
3427 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3431 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3432 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3433 .BindingTablePointer
= surfaces
.offset
,
3434 .SamplerStatePointer
= samplers
.offset
,
3436 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3438 struct anv_state state
=
3439 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3440 pipeline
->interface_descriptor_data
,
3441 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3444 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3445 anv_batch_emit(&cmd_buffer
->batch
,
3446 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3447 mid
.InterfaceDescriptorTotalLength
= size
;
3448 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3455 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3457 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3458 MAYBE_UNUSED VkResult result
;
3460 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3462 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3464 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3466 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3467 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3469 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3470 * the only bits that are changed are scoreboard related: Scoreboard
3471 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3472 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3475 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3476 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3478 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3481 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3482 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3483 /* FIXME: figure out descriptors for gen7 */
3484 result
= flush_compute_descriptor_set(cmd_buffer
);
3485 if (result
!= VK_SUCCESS
)
3488 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3491 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3492 struct anv_state push_state
=
3493 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3495 if (push_state
.alloc_size
) {
3496 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3497 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3498 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3502 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3505 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3507 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3513 verify_cmd_parser(const struct anv_device
*device
,
3514 int required_version
,
3515 const char *function
)
3517 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3518 return vk_errorf(device
->instance
, device
->instance
,
3519 VK_ERROR_FEATURE_NOT_PRESENT
,
3520 "cmd parser version %d is required for %s",
3521 required_version
, function
);
3530 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3531 uint32_t baseGroupX
,
3532 uint32_t baseGroupY
,
3533 uint32_t baseGroupZ
)
3535 if (anv_batch_has_error(&cmd_buffer
->batch
))
3538 struct anv_push_constants
*push
=
3539 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3540 if (push
->base_work_group_id
[0] != baseGroupX
||
3541 push
->base_work_group_id
[1] != baseGroupY
||
3542 push
->base_work_group_id
[2] != baseGroupZ
) {
3543 push
->base_work_group_id
[0] = baseGroupX
;
3544 push
->base_work_group_id
[1] = baseGroupY
;
3545 push
->base_work_group_id
[2] = baseGroupZ
;
3547 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3551 void genX(CmdDispatch
)(
3552 VkCommandBuffer commandBuffer
,
3557 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3560 void genX(CmdDispatchBase
)(
3561 VkCommandBuffer commandBuffer
,
3562 uint32_t baseGroupX
,
3563 uint32_t baseGroupY
,
3564 uint32_t baseGroupZ
,
3565 uint32_t groupCountX
,
3566 uint32_t groupCountY
,
3567 uint32_t groupCountZ
)
3569 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3570 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3571 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3573 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3574 baseGroupY
, baseGroupZ
);
3576 if (anv_batch_has_error(&cmd_buffer
->batch
))
3579 if (prog_data
->uses_num_work_groups
) {
3580 struct anv_state state
=
3581 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3582 uint32_t *sizes
= state
.map
;
3583 sizes
[0] = groupCountX
;
3584 sizes
[1] = groupCountY
;
3585 sizes
[2] = groupCountZ
;
3586 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3587 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3588 .offset
= state
.offset
,
3592 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3594 if (cmd_buffer
->state
.conditional_render_enabled
)
3595 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3597 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3598 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3599 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3600 ggw
.ThreadDepthCounterMaximum
= 0;
3601 ggw
.ThreadHeightCounterMaximum
= 0;
3602 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3603 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3604 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3605 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3606 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3607 ggw
.BottomExecutionMask
= 0xffffffff;
3610 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3613 #define GPGPU_DISPATCHDIMX 0x2500
3614 #define GPGPU_DISPATCHDIMY 0x2504
3615 #define GPGPU_DISPATCHDIMZ 0x2508
3617 void genX(CmdDispatchIndirect
)(
3618 VkCommandBuffer commandBuffer
,
3620 VkDeviceSize offset
)
3622 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3623 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3624 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3625 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3626 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3627 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3629 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3632 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3633 * indirect dispatch registers to be written.
3635 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3636 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3640 if (prog_data
->uses_num_work_groups
)
3641 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3643 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3645 struct gen_mi_builder b
;
3646 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3648 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
3649 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
3650 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
3652 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
3653 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
3654 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
3657 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3658 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
3659 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3660 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3661 mip
.LoadOperation
= LOAD_LOAD
;
3662 mip
.CombineOperation
= COMBINE_SET
;
3663 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3666 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3667 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
3668 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3669 mip
.LoadOperation
= LOAD_LOAD
;
3670 mip
.CombineOperation
= COMBINE_OR
;
3671 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3674 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3675 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
3676 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3677 mip
.LoadOperation
= LOAD_LOAD
;
3678 mip
.CombineOperation
= COMBINE_OR
;
3679 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3682 /* predicate = !predicate; */
3683 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3684 mip
.LoadOperation
= LOAD_LOADINV
;
3685 mip
.CombineOperation
= COMBINE_OR
;
3686 mip
.CompareOperation
= COMPARE_FALSE
;
3690 if (cmd_buffer
->state
.conditional_render_enabled
) {
3691 /* predicate &= !(conditional_rendering_predicate == 0); */
3692 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
3693 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
3694 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3695 mip
.LoadOperation
= LOAD_LOADINV
;
3696 mip
.CombineOperation
= COMBINE_AND
;
3697 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3702 #else /* GEN_GEN > 7 */
3703 if (cmd_buffer
->state
.conditional_render_enabled
)
3704 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3707 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3708 ggw
.IndirectParameterEnable
= true;
3709 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3710 cmd_buffer
->state
.conditional_render_enabled
;
3711 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3712 ggw
.ThreadDepthCounterMaximum
= 0;
3713 ggw
.ThreadHeightCounterMaximum
= 0;
3714 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3715 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3716 ggw
.BottomExecutionMask
= 0xffffffff;
3719 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3723 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3726 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3728 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3731 #if GEN_GEN >= 8 && GEN_GEN < 10
3732 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3734 * Software must clear the COLOR_CALC_STATE Valid field in
3735 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3736 * with Pipeline Select set to GPGPU.
3738 * The internal hardware docs recommend the same workaround for Gen9
3741 if (pipeline
== GPGPU
)
3742 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3745 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3746 * PIPELINE_SELECT [DevBWR+]":
3750 * Software must ensure all the write caches are flushed through a
3751 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3752 * command to invalidate read only caches prior to programming
3753 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3755 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3756 pc
.RenderTargetCacheFlushEnable
= true;
3757 pc
.DepthCacheFlushEnable
= true;
3758 pc
.DCFlushEnable
= true;
3759 pc
.PostSyncOperation
= NoWrite
;
3760 pc
.CommandStreamerStallEnable
= true;
3763 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3764 pc
.TextureCacheInvalidationEnable
= true;
3765 pc
.ConstantCacheInvalidationEnable
= true;
3766 pc
.StateCacheInvalidationEnable
= true;
3767 pc
.InstructionCacheInvalidateEnable
= true;
3768 pc
.PostSyncOperation
= NoWrite
;
3771 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3775 ps
.PipelineSelection
= pipeline
;
3779 if (devinfo
->is_geminilake
) {
3782 * "This chicken bit works around a hardware issue with barrier logic
3783 * encountered when switching between GPGPU and 3D pipelines. To
3784 * workaround the issue, this mode bit should be set after a pipeline
3788 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3790 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3791 : GLK_BARRIER_MODE_3D_HULL
,
3792 .GLKBarrierModeMask
= 1);
3793 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3797 cmd_buffer
->state
.current_pipeline
= pipeline
;
3801 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3803 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3807 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3809 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3813 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3818 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3820 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3821 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3822 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3823 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3824 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3825 * Depth Flush Bit set, followed by another pipelined depth stall
3826 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3827 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3828 * via a preceding MI_FLUSH)."
3830 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3831 pipe
.DepthStallEnable
= true;
3833 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3834 pipe
.DepthCacheFlushEnable
= true;
3836 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3837 pipe
.DepthStallEnable
= true;
3842 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3844 struct anv_device
*device
= cmd_buffer
->device
;
3845 const struct anv_image_view
*iview
=
3846 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3847 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3849 /* FIXME: Width and Height are wrong */
3851 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3853 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3854 device
->isl_dev
.ds
.size
/ 4);
3858 struct isl_depth_stencil_hiz_emit_info info
= { };
3861 info
.view
= &iview
->planes
[0].isl
;
3863 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3864 uint32_t depth_plane
=
3865 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3866 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3868 info
.depth_surf
= &surface
->isl
;
3870 info
.depth_address
=
3871 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3872 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3873 image
->planes
[depth_plane
].address
.bo
,
3874 image
->planes
[depth_plane
].address
.offset
+
3877 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
3880 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3881 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3882 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3883 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3886 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3887 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3888 image
->planes
[depth_plane
].address
.bo
,
3889 image
->planes
[depth_plane
].address
.offset
+
3890 image
->planes
[depth_plane
].aux_surface
.offset
);
3892 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3896 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3897 uint32_t stencil_plane
=
3898 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3899 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3901 info
.stencil_surf
= &surface
->isl
;
3903 info
.stencil_address
=
3904 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3905 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3906 image
->planes
[stencil_plane
].address
.bo
,
3907 image
->planes
[stencil_plane
].address
.offset
+
3910 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
3913 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3915 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3919 * This ANDs the view mask of the current subpass with the pending clear
3920 * views in the attachment to get the mask of views active in the subpass
3921 * that still need to be cleared.
3923 static inline uint32_t
3924 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3925 const struct anv_attachment_state
*att_state
)
3927 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3931 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3932 const struct anv_attachment_state
*att_state
)
3934 if (!cmd_state
->subpass
->view_mask
)
3937 uint32_t pending_clear_mask
=
3938 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3940 return pending_clear_mask
& 1;
3944 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3947 const uint32_t last_subpass_idx
=
3948 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3949 const struct anv_subpass
*last_subpass
=
3950 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3951 return last_subpass
== cmd_state
->subpass
;
3955 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3956 uint32_t subpass_id
)
3958 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3959 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3960 cmd_state
->subpass
= subpass
;
3962 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3964 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3965 * different views. If the client asks for instancing, we need to use the
3966 * Instance Data Step Rate to ensure that we repeat the client's
3967 * per-instance data once for each view. Since this bit is in
3968 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3972 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3974 /* It is possible to start a render pass with an old pipeline. Because the
3975 * render pass and subpass index are both baked into the pipeline, this is
3976 * highly unlikely. In order to do so, it requires that you have a render
3977 * pass with a single subpass and that you use that render pass twice
3978 * back-to-back and use the same pipeline at the start of the second render
3979 * pass as at the end of the first. In order to avoid unpredictable issues
3980 * with this edge case, we just dirty the pipeline at the start of every
3983 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3985 /* Accumulate any subpass flushes that need to happen before the subpass */
3986 cmd_buffer
->state
.pending_pipe_bits
|=
3987 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3989 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3990 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3992 bool is_multiview
= subpass
->view_mask
!= 0;
3994 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3995 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3996 if (a
== VK_ATTACHMENT_UNUSED
)
3999 assert(a
< cmd_state
->pass
->attachment_count
);
4000 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4002 struct anv_image_view
*iview
= fb
->attachments
[a
];
4003 const struct anv_image
*image
= iview
->image
;
4005 /* A resolve is necessary before use as an input attachment if the clear
4006 * color or auxiliary buffer usage isn't supported by the sampler.
4008 const bool input_needs_resolve
=
4009 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4010 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4012 VkImageLayout target_layout
;
4013 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4014 !input_needs_resolve
) {
4015 /* Layout transitions before the final only help to enable sampling
4016 * as an input attachment. If the input attachment supports sampling
4017 * using the auxiliary surface, we can skip such transitions by
4018 * making the target layout one that is CCS-aware.
4020 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4022 target_layout
= subpass
->attachments
[i
].layout
;
4025 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4026 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4028 uint32_t base_layer
, layer_count
;
4029 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4031 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4032 iview
->planes
[0].isl
.base_level
);
4034 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4035 layer_count
= fb
->layers
;
4038 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4039 iview
->planes
[0].isl
.base_level
, 1,
4040 base_layer
, layer_count
,
4041 att_state
->current_layout
, target_layout
);
4042 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4043 transition_depth_buffer(cmd_buffer
, image
,
4044 att_state
->current_layout
, target_layout
);
4045 att_state
->aux_usage
=
4046 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4047 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4049 att_state
->current_layout
= target_layout
;
4051 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4052 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4054 /* Multi-planar images are not supported as attachments */
4055 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4056 assert(image
->n_planes
== 1);
4058 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4059 uint32_t clear_layer_count
= fb
->layers
;
4061 if (att_state
->fast_clear
&&
4062 do_first_layer_clear(cmd_state
, att_state
)) {
4063 /* We only support fast-clears on the first layer */
4064 assert(iview
->planes
[0].isl
.base_level
== 0);
4065 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4067 union isl_color_value clear_color
= {};
4068 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4069 if (iview
->image
->samples
== 1) {
4070 anv_image_ccs_op(cmd_buffer
, image
,
4071 iview
->planes
[0].isl
.format
,
4072 VK_IMAGE_ASPECT_COLOR_BIT
,
4073 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4077 anv_image_mcs_op(cmd_buffer
, image
,
4078 iview
->planes
[0].isl
.format
,
4079 VK_IMAGE_ASPECT_COLOR_BIT
,
4080 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4085 clear_layer_count
--;
4087 att_state
->pending_clear_views
&= ~1;
4089 if (att_state
->clear_color_is_zero
) {
4090 /* This image has the auxiliary buffer enabled. We can mark the
4091 * subresource as not needing a resolve because the clear color
4092 * will match what's in every RENDER_SURFACE_STATE object when
4093 * it's being used for sampling.
4095 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4096 VK_IMAGE_ASPECT_COLOR_BIT
,
4097 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4099 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4100 VK_IMAGE_ASPECT_COLOR_BIT
,
4101 ANV_FAST_CLEAR_ANY
);
4105 /* From the VkFramebufferCreateInfo spec:
4107 * "If the render pass uses multiview, then layers must be one and each
4108 * attachment requires a number of layers that is greater than the
4109 * maximum bit index set in the view mask in the subpasses in which it
4112 * So if multiview is active we ignore the number of layers in the
4113 * framebuffer and instead we honor the view mask from the subpass.
4116 assert(image
->n_planes
== 1);
4117 uint32_t pending_clear_mask
=
4118 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4121 for_each_bit(layer_idx
, pending_clear_mask
) {
4123 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4125 anv_image_clear_color(cmd_buffer
, image
,
4126 VK_IMAGE_ASPECT_COLOR_BIT
,
4127 att_state
->aux_usage
,
4128 iview
->planes
[0].isl
.format
,
4129 iview
->planes
[0].isl
.swizzle
,
4130 iview
->planes
[0].isl
.base_level
,
4133 vk_to_isl_color(att_state
->clear_value
.color
));
4136 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4137 } else if (clear_layer_count
> 0) {
4138 assert(image
->n_planes
== 1);
4139 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4140 att_state
->aux_usage
,
4141 iview
->planes
[0].isl
.format
,
4142 iview
->planes
[0].isl
.swizzle
,
4143 iview
->planes
[0].isl
.base_level
,
4144 base_clear_layer
, clear_layer_count
,
4146 vk_to_isl_color(att_state
->clear_value
.color
));
4148 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4149 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4150 if (att_state
->fast_clear
&& !is_multiview
) {
4151 /* We currently only support HiZ for single-layer images */
4152 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4153 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4154 assert(iview
->planes
[0].isl
.base_level
== 0);
4155 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4156 assert(fb
->layers
== 1);
4159 anv_image_hiz_clear(cmd_buffer
, image
,
4160 att_state
->pending_clear_aspects
,
4161 iview
->planes
[0].isl
.base_level
,
4162 iview
->planes
[0].isl
.base_array_layer
,
4163 fb
->layers
, render_area
,
4164 att_state
->clear_value
.depthStencil
.stencil
);
4165 } else if (is_multiview
) {
4166 uint32_t pending_clear_mask
=
4167 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4170 for_each_bit(layer_idx
, pending_clear_mask
) {
4172 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4174 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4175 att_state
->pending_clear_aspects
,
4176 att_state
->aux_usage
,
4177 iview
->planes
[0].isl
.base_level
,
4180 att_state
->clear_value
.depthStencil
.depth
,
4181 att_state
->clear_value
.depthStencil
.stencil
);
4184 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4186 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4187 att_state
->pending_clear_aspects
,
4188 att_state
->aux_usage
,
4189 iview
->planes
[0].isl
.base_level
,
4190 iview
->planes
[0].isl
.base_array_layer
,
4191 fb
->layers
, render_area
,
4192 att_state
->clear_value
.depthStencil
.depth
,
4193 att_state
->clear_value
.depthStencil
.stencil
);
4196 assert(att_state
->pending_clear_aspects
== 0);
4200 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4201 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4202 iview
->planes
[0].isl
.base_level
== 0 &&
4203 iview
->planes
[0].isl
.base_array_layer
== 0) {
4204 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4205 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4206 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4207 false /* copy to ss */);
4210 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4211 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4212 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4213 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4214 false /* copy to ss */);
4218 if (subpass
->attachments
[i
].usage
==
4219 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4220 /* We assume that if we're starting a subpass, we're going to do some
4221 * rendering so we may end up with compressed data.
4223 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4224 VK_IMAGE_ASPECT_COLOR_BIT
,
4225 att_state
->aux_usage
,
4226 iview
->planes
[0].isl
.base_level
,
4227 iview
->planes
[0].isl
.base_array_layer
,
4229 } else if (subpass
->attachments
[i
].usage
==
4230 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4231 /* We may be writing depth or stencil so we need to mark the surface.
4232 * Unfortunately, there's no way to know at this point whether the
4233 * depth or stencil tests used will actually write to the surface.
4235 * Even though stencil may be plane 1, it always shares a base_level
4238 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4239 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4240 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4241 VK_IMAGE_ASPECT_DEPTH_BIT
,
4242 att_state
->aux_usage
,
4243 ds_view
->base_level
,
4244 ds_view
->base_array_layer
,
4247 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4248 /* Even though stencil may be plane 1, it always shares a
4249 * base_level with depth.
4251 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4252 VK_IMAGE_ASPECT_STENCIL_BIT
,
4254 ds_view
->base_level
,
4255 ds_view
->base_array_layer
,
4260 /* If multiview is enabled, then we are only done clearing when we no
4261 * longer have pending layers to clear, or when we have processed the
4262 * last subpass that uses this attachment.
4264 if (!is_multiview
||
4265 att_state
->pending_clear_views
== 0 ||
4266 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4267 att_state
->pending_clear_aspects
= 0;
4270 att_state
->pending_load_aspects
= 0;
4273 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4276 static enum blorp_filter
4277 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4280 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4281 return BLORP_FILTER_SAMPLE_0
;
4282 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4283 return BLORP_FILTER_AVERAGE
;
4284 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4285 return BLORP_FILTER_MIN_SAMPLE
;
4286 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4287 return BLORP_FILTER_MAX_SAMPLE
;
4289 return BLORP_FILTER_NONE
;
4294 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4296 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4297 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4298 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4299 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4301 if (subpass
->has_color_resolve
) {
4302 /* We are about to do some MSAA resolves. We need to flush so that the
4303 * result of writes to the MSAA color attachments show up in the sampler
4304 * when we blit to the single-sampled resolve target.
4306 cmd_buffer
->state
.pending_pipe_bits
|=
4307 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4308 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4310 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4311 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4312 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4314 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4317 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4318 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4320 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4321 /* From the Vulkan 1.0 spec:
4323 * If the first use of an attachment in a render pass is as a
4324 * resolve attachment, then the loadOp is effectively ignored
4325 * as the resolve is guaranteed to overwrite all pixels in the
4328 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4331 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4332 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4334 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4336 enum isl_aux_usage src_aux_usage
=
4337 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4338 enum isl_aux_usage dst_aux_usage
=
4339 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4341 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4342 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4344 anv_image_msaa_resolve(cmd_buffer
,
4345 src_iview
->image
, src_aux_usage
,
4346 src_iview
->planes
[0].isl
.base_level
,
4347 src_iview
->planes
[0].isl
.base_array_layer
,
4348 dst_iview
->image
, dst_aux_usage
,
4349 dst_iview
->planes
[0].isl
.base_level
,
4350 dst_iview
->planes
[0].isl
.base_array_layer
,
4351 VK_IMAGE_ASPECT_COLOR_BIT
,
4352 render_area
.offset
.x
, render_area
.offset
.y
,
4353 render_area
.offset
.x
, render_area
.offset
.y
,
4354 render_area
.extent
.width
,
4355 render_area
.extent
.height
,
4356 fb
->layers
, BLORP_FILTER_NONE
);
4360 if (subpass
->ds_resolve_attachment
) {
4361 /* We are about to do some MSAA resolves. We need to flush so that the
4362 * result of writes to the MSAA depth attachments show up in the sampler
4363 * when we blit to the single-sampled resolve target.
4365 cmd_buffer
->state
.pending_pipe_bits
|=
4366 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4367 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4369 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4370 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4372 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4373 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4375 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4376 /* From the Vulkan 1.0 spec:
4378 * If the first use of an attachment in a render pass is as a
4379 * resolve attachment, then the loadOp is effectively ignored
4380 * as the resolve is guaranteed to overwrite all pixels in the
4383 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4386 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4387 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4389 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4391 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4392 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4394 struct anv_attachment_state
*src_state
=
4395 &cmd_state
->attachments
[src_att
];
4396 struct anv_attachment_state
*dst_state
=
4397 &cmd_state
->attachments
[dst_att
];
4399 /* MSAA resolves sample from the source attachment. Transition the
4400 * depth attachment first to get rid of any HiZ that we may not be
4403 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4404 src_state
->current_layout
,
4405 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4406 src_state
->aux_usage
=
4407 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4408 VK_IMAGE_ASPECT_DEPTH_BIT
,
4409 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4410 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4412 /* MSAA resolves write to the resolve attachment as if it were any
4413 * other transfer op. Transition the resolve attachment accordingly.
4415 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4417 /* If our render area is the entire size of the image, we're going to
4418 * blow it all away so we can claim the initial layout is UNDEFINED
4419 * and we'll get a HiZ ambiguate instead of a resolve.
4421 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4422 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4423 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4424 render_area
.extent
.height
== dst_iview
->extent
.height
)
4425 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4427 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4429 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4430 dst_state
->aux_usage
=
4431 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4432 VK_IMAGE_ASPECT_DEPTH_BIT
,
4433 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4434 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4436 enum blorp_filter filter
=
4437 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4439 anv_image_msaa_resolve(cmd_buffer
,
4440 src_iview
->image
, src_state
->aux_usage
,
4441 src_iview
->planes
[0].isl
.base_level
,
4442 src_iview
->planes
[0].isl
.base_array_layer
,
4443 dst_iview
->image
, dst_state
->aux_usage
,
4444 dst_iview
->planes
[0].isl
.base_level
,
4445 dst_iview
->planes
[0].isl
.base_array_layer
,
4446 VK_IMAGE_ASPECT_DEPTH_BIT
,
4447 render_area
.offset
.x
, render_area
.offset
.y
,
4448 render_area
.offset
.x
, render_area
.offset
.y
,
4449 render_area
.extent
.width
,
4450 render_area
.extent
.height
,
4451 fb
->layers
, filter
);
4454 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4455 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4457 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4458 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4460 enum blorp_filter filter
=
4461 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4463 anv_image_msaa_resolve(cmd_buffer
,
4464 src_iview
->image
, src_aux_usage
,
4465 src_iview
->planes
[0].isl
.base_level
,
4466 src_iview
->planes
[0].isl
.base_array_layer
,
4467 dst_iview
->image
, dst_aux_usage
,
4468 dst_iview
->planes
[0].isl
.base_level
,
4469 dst_iview
->planes
[0].isl
.base_array_layer
,
4470 VK_IMAGE_ASPECT_STENCIL_BIT
,
4471 render_area
.offset
.x
, render_area
.offset
.y
,
4472 render_area
.offset
.x
, render_area
.offset
.y
,
4473 render_area
.extent
.width
,
4474 render_area
.extent
.height
,
4475 fb
->layers
, filter
);
4479 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4480 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4481 if (a
== VK_ATTACHMENT_UNUSED
)
4484 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4487 assert(a
< cmd_state
->pass
->attachment_count
);
4488 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4489 struct anv_image_view
*iview
= fb
->attachments
[a
];
4490 const struct anv_image
*image
= iview
->image
;
4492 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4493 image
->vk_format
!= iview
->vk_format
) {
4494 enum anv_fast_clear_type fast_clear_type
=
4495 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4496 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4497 att_state
->current_layout
);
4499 /* If any clear color was used, flush it down the aux surfaces. If we
4500 * don't do it now using the view's format we might use the clear
4501 * color incorrectly in the following resolves (for example with an
4502 * SRGB view & a UNORM image).
4504 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4505 anv_perf_warn(cmd_buffer
->device
->instance
, fb
,
4506 "Doing a partial resolve to get rid of clear color at the "
4507 "end of a renderpass due to an image/view format mismatch");
4509 uint32_t base_layer
, layer_count
;
4510 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4512 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4513 iview
->planes
[0].isl
.base_level
);
4515 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4516 layer_count
= fb
->layers
;
4519 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4520 uint32_t array_layer
= base_layer
+ a
;
4521 if (image
->samples
== 1) {
4522 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4523 iview
->planes
[0].isl
.format
,
4524 VK_IMAGE_ASPECT_COLOR_BIT
,
4525 iview
->planes
[0].isl
.base_level
,
4527 ISL_AUX_OP_PARTIAL_RESOLVE
,
4528 ANV_FAST_CLEAR_NONE
);
4530 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4531 iview
->planes
[0].isl
.format
,
4532 VK_IMAGE_ASPECT_COLOR_BIT
,
4534 ISL_AUX_OP_PARTIAL_RESOLVE
,
4535 ANV_FAST_CLEAR_NONE
);
4541 /* Transition the image into the final layout for this render pass */
4542 VkImageLayout target_layout
=
4543 cmd_state
->pass
->attachments
[a
].final_layout
;
4545 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4546 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4548 uint32_t base_layer
, layer_count
;
4549 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4551 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4552 iview
->planes
[0].isl
.base_level
);
4554 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4555 layer_count
= fb
->layers
;
4558 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4559 iview
->planes
[0].isl
.base_level
, 1,
4560 base_layer
, layer_count
,
4561 att_state
->current_layout
, target_layout
);
4562 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4563 transition_depth_buffer(cmd_buffer
, image
,
4564 att_state
->current_layout
, target_layout
);
4568 /* Accumulate any subpass flushes that need to happen after the subpass.
4569 * Yes, they do get accumulated twice in the NextSubpass case but since
4570 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4571 * ORing the bits in twice so it's harmless.
4573 cmd_buffer
->state
.pending_pipe_bits
|=
4574 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4577 void genX(CmdBeginRenderPass
)(
4578 VkCommandBuffer commandBuffer
,
4579 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4580 VkSubpassContents contents
)
4582 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4583 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4584 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4586 cmd_buffer
->state
.framebuffer
= framebuffer
;
4587 cmd_buffer
->state
.pass
= pass
;
4588 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4590 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4592 /* If we failed to setup the attachments we should not try to go further */
4593 if (result
!= VK_SUCCESS
) {
4594 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4598 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4600 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4603 void genX(CmdBeginRenderPass2KHR
)(
4604 VkCommandBuffer commandBuffer
,
4605 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4606 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4608 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4609 pSubpassBeginInfo
->contents
);
4612 void genX(CmdNextSubpass
)(
4613 VkCommandBuffer commandBuffer
,
4614 VkSubpassContents contents
)
4616 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4618 if (anv_batch_has_error(&cmd_buffer
->batch
))
4621 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4623 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4624 cmd_buffer_end_subpass(cmd_buffer
);
4625 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4628 void genX(CmdNextSubpass2KHR
)(
4629 VkCommandBuffer commandBuffer
,
4630 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4631 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4633 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4636 void genX(CmdEndRenderPass
)(
4637 VkCommandBuffer commandBuffer
)
4639 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4641 if (anv_batch_has_error(&cmd_buffer
->batch
))
4644 cmd_buffer_end_subpass(cmd_buffer
);
4646 cmd_buffer
->state
.hiz_enabled
= false;
4649 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
4652 /* Remove references to render pass specific state. This enables us to
4653 * detect whether or not we're in a renderpass.
4655 cmd_buffer
->state
.framebuffer
= NULL
;
4656 cmd_buffer
->state
.pass
= NULL
;
4657 cmd_buffer
->state
.subpass
= NULL
;
4660 void genX(CmdEndRenderPass2KHR
)(
4661 VkCommandBuffer commandBuffer
,
4662 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4664 genX(CmdEndRenderPass
)(commandBuffer
);
4668 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
4670 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4671 struct gen_mi_builder b
;
4672 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4674 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
4675 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4676 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4678 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
4679 mip
.LoadOperation
= LOAD_LOADINV
;
4680 mip
.CombineOperation
= COMBINE_SET
;
4681 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4686 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4687 void genX(CmdBeginConditionalRenderingEXT
)(
4688 VkCommandBuffer commandBuffer
,
4689 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4691 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4692 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4693 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4694 struct anv_address value_address
=
4695 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
4697 const bool isInverted
= pConditionalRenderingBegin
->flags
&
4698 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
4700 cmd_state
->conditional_render_enabled
= true;
4702 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4704 struct gen_mi_builder b
;
4705 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4707 /* Section 19.4 of the Vulkan 1.1.85 spec says:
4709 * If the value of the predicate in buffer memory changes
4710 * while conditional rendering is active, the rendering commands
4711 * may be discarded in an implementation-dependent way.
4712 * Some implementations may latch the value of the predicate
4713 * upon beginning conditional rendering while others
4714 * may read it before every rendering command.
4716 * So it's perfectly fine to read a value from the buffer once.
4718 struct gen_mi_value value
= gen_mi_mem32(value_address
);
4720 /* Precompute predicate result, it is necessary to support secondary
4721 * command buffers since it is unknown if conditional rendering is
4722 * inverted when populating them.
4724 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
4725 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
4726 gen_mi_ult(&b
, gen_mi_imm(0), value
));
4729 void genX(CmdEndConditionalRenderingEXT
)(
4730 VkCommandBuffer commandBuffer
)
4732 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4733 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4735 cmd_state
->conditional_render_enabled
= false;