2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "anv_private.h"
26 #include "genxml/gen_macros.h"
27 #include "genxml/genX_pack.h"
29 #include "common/gen_l3_config.h"
32 * This file implements some lightweight memcpy/memset operations on the GPU
33 * using a vertex buffer and streamout.
37 * Returns the greatest common divisor of a and b that is a power of two.
40 gcd_pow2_u64(uint64_t a
, uint64_t b
)
42 assert(a
> 0 || b
> 0);
44 unsigned a_log2
= ffsll(a
) - 1;
45 unsigned b_log2
= ffsll(b
) - 1;
47 /* If either a or b is 0, then a_log2 or b_log2 will be UINT_MAX in which
48 * case, the MIN2() will take the other one. If both are 0 then we will
49 * hit the assert above.
51 return 1 << MIN2(a_log2
, b_log2
);
55 genX(cmd_buffer_mi_memcpy
)(struct anv_cmd_buffer
*cmd_buffer
,
56 struct anv_bo
*dst
, uint32_t dst_offset
,
57 struct anv_bo
*src
, uint32_t src_offset
,
60 /* This memcpy operates in units of dwords. */
61 assert(size
% 4 == 0);
62 assert(dst_offset
% 4 == 0);
63 assert(src_offset
% 4 == 0);
66 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
67 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
68 * in-flight when they are issued even if the memory touched is not
69 * currently active for rendering. The weird bit is that it is not the
70 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
71 * rendering hangs such that the next stalling command after the
72 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
74 * It is unclear exactly why this hang occurs. Both MI commands come with
75 * warnings about the 3D pipeline but that doesn't seem to fully explain
76 * it. My (Jason's) best theory is that it has something to do with the
77 * fact that we're using a GPU state register as our temporary and that
78 * something with reading/writing it is causing problems.
80 * In order to work around this issue, we emit a PIPE_CONTROL with the
81 * command streamer stall bit set.
83 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
84 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
87 for (uint32_t i
= 0; i
< size
; i
+= 4) {
88 const struct anv_address src_addr
=
89 (struct anv_address
) { src
, src_offset
+ i
};
90 const struct anv_address dst_addr
=
91 (struct anv_address
) { dst
, dst_offset
+ i
};
93 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
94 cp
.DestinationMemoryAddress
= dst_addr
;
95 cp
.SourceMemoryAddress
= src_addr
;
98 /* IVB does not have a general purpose register for command streamer
99 * commands. Therefore, we use an alternate temporary register.
101 #define TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */
102 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), load
) {
103 load
.RegisterAddress
= TEMP_REG
;
104 load
.MemoryAddress
= src_addr
;
106 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), store
) {
107 store
.RegisterAddress
= TEMP_REG
;
108 store
.MemoryAddress
= dst_addr
;
117 genX(cmd_buffer_so_memcpy
)(struct anv_cmd_buffer
*cmd_buffer
,
118 struct anv_bo
*dst
, uint32_t dst_offset
,
119 struct anv_bo
*src
, uint32_t src_offset
,
125 assert(dst_offset
+ size
<= dst
->size
);
126 assert(src_offset
+ size
<= src
->size
);
128 /* The maximum copy block size is 4 32-bit components at a time. */
130 bs
= gcd_pow2_u64(bs
, src_offset
);
131 bs
= gcd_pow2_u64(bs
, dst_offset
);
132 bs
= gcd_pow2_u64(bs
, size
);
134 enum isl_format format
;
136 case 4: format
= ISL_FORMAT_R32_UINT
; break;
137 case 8: format
= ISL_FORMAT_R32G32_UINT
; break;
138 case 16: format
= ISL_FORMAT_R32G32B32A32_UINT
; break;
140 unreachable("Invalid size");
143 if (!cmd_buffer
->state
.current_l3_config
) {
144 const struct gen_l3_config
*cfg
=
145 gen_get_default_l3_config(&cmd_buffer
->device
->info
);
146 genX(cmd_buffer_config_l3
)(cmd_buffer
, cfg
);
149 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
151 genX(flush_pipeline_select_3d
)(cmd_buffer
);
154 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(3DSTATE_VERTEX_BUFFERS
));
155 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, dw
+ 1,
156 &(struct GENX(VERTEX_BUFFER_STATE
)) {
157 .VertexBufferIndex
= 32, /* Reserved for this */
158 .AddressModifyEnable
= true,
159 .BufferStartingAddress
= { src
, src_offset
},
162 .MemoryObjectControlState
= GENX(MOCS
),
165 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
166 .EndAddress
= { src
, src_offset
+ size
- 1 },
170 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 3, GENX(3DSTATE_VERTEX_ELEMENTS
));
171 GENX(VERTEX_ELEMENT_STATE_pack
)(&cmd_buffer
->batch
, dw
+ 1,
172 &(struct GENX(VERTEX_ELEMENT_STATE
)) {
173 .VertexBufferIndex
= 32,
175 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) format
,
176 .SourceElementOffset
= 0,
177 .Component0Control
= (bs
>= 4) ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
178 .Component1Control
= (bs
>= 8) ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
179 .Component2Control
= (bs
>= 12) ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
180 .Component3Control
= (bs
>= 16) ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
184 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
187 /* Disable all shader stages */
188 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_VS
), vs
);
189 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HS
), hs
);
190 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_TE
), te
);
191 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DS
), DS
);
192 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_GS
), gs
);
193 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_PS
), gs
);
195 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SBE
), sbe
) {
196 sbe
.VertexURBEntryReadOffset
= 1;
197 sbe
.NumberofSFOutputAttributes
= 1;
198 sbe
.VertexURBEntryReadLength
= 1;
200 sbe
.ForceVertexURBEntryReadLength
= true;
201 sbe
.ForceVertexURBEntryReadOffset
= true;
205 for (unsigned i
= 0; i
< 32; i
++)
206 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
210 /* Emit URB setup. We tell it that the VS is active because we want it to
211 * allocate space for the VS. Even though one isn't run, we need VUEs to
212 * store the data that VF is going to pass to SOL.
214 const unsigned entry_size
[4] = { DIV_ROUND_UP(32, 64), 1, 1, 1 };
216 genX(emit_urb_setup
)(cmd_buffer
->device
, &cmd_buffer
->batch
,
217 cmd_buffer
->state
.current_l3_config
,
218 VK_SHADER_STAGE_VERTEX_BIT
, entry_size
);
220 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
221 sob
.SOBufferIndex
= 0;
222 sob
.SOBufferObjectControlState
= GENX(MOCS
);
223 sob
.SurfaceBaseAddress
= (struct anv_address
) { dst
, dst_offset
};
226 sob
.SOBufferEnable
= true;
227 sob
.SurfaceSize
= size
- 1;
229 sob
.SurfacePitch
= bs
;
230 sob
.SurfaceEndAddress
= sob
.SurfaceBaseAddress
;
231 sob
.SurfaceEndAddress
.offset
+= size
;
235 /* As SOL writes out data, it updates the SO_WRITE_OFFSET registers with
236 * the end position of the stream. We need to reset this value to 0 at
237 * the beginning of the run or else SOL will start at the offset from
240 sob
.StreamOffsetWriteEnable
= true;
241 sob
.StreamOffset
= 0;
246 /* The hardware can do this for us on BDW+ (see above) */
247 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), load
) {
248 load
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
);
253 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(3DSTATE_SO_DECL_LIST
),
254 .StreamtoBufferSelects0
= (1 << 0),
256 GENX(SO_DECL_ENTRY_pack
)(&cmd_buffer
->batch
, dw
+ 3,
257 &(struct GENX(SO_DECL_ENTRY
)) {
259 .OutputBufferSlot
= 0,
261 .ComponentMask
= (1 << (bs
/ 4)) - 1,
265 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STREAMOUT
), so
) {
266 so
.SOFunctionEnable
= true;
267 so
.RenderingDisable
= true;
268 so
.Stream0VertexReadOffset
= 0;
269 so
.Stream0VertexReadLength
= DIV_ROUND_UP(32, 64);
271 so
.Buffer0SurfacePitch
= bs
;
273 so
.SOBufferEnable0
= true;
278 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
279 topo
.PrimitiveTopologyType
= _3DPRIM_POINTLIST
;
283 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
284 vf
.StatisticsEnable
= false;
287 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
288 prim
.VertexAccessType
= SEQUENTIAL
;
289 prim
.PrimitiveTopologyType
= _3DPRIM_POINTLIST
;
290 prim
.VertexCountPerInstance
= size
/ bs
;
291 prim
.StartVertexLocation
= 0;
292 prim
.InstanceCount
= 1;
293 prim
.StartInstanceLocation
= 0;
294 prim
.BaseVertexLocation
= 0;
297 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;