src/intel/vulkan/genX_gpu_memcpy.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "anv_private.h"
  25
  26 #include "genxml/gen_macros.h"
  27 #include "genxml/genX_pack.h"
  28
  29 #include "common/gen_l3_config.h"
  30
  31 /**
  32  * This file implements some lightweight memcpy/memset operations on the GPU
  33  * using a vertex buffer and streamout.
  34  */
  35
  36 /**
  37  * Returns the greatest common divisor of a and b that is a power of two.
  38  */
  39 static uint64_t
  40 gcd_pow2_u64(uint64_t a, uint64_t b)
  41 {
  42    assert(a > 0 || b > 0);
  43
  44    unsigned a_log2 = ffsll(a) - 1;
  45    unsigned b_log2 = ffsll(b) - 1;
  46
  47    /* If either a or b is 0, then a_log2 or b_log2 will be UINT_MAX in which
  48     * case, the MIN2() will take the other one.  If both are 0 then we will
  49     * hit the assert above.
  50     */
  51    return 1 << MIN2(a_log2, b_log2);
  52 }
  53
  54 void
  55 genX(cmd_buffer_mi_memcpy)(struct anv_cmd_buffer *cmd_buffer,
  56                            struct anv_address dst, struct anv_address src,
  57                            uint32_t size)
  58 {
  59    /* This memcpy operates in units of dwords. */
  60    assert(size % 4 == 0);
  61    assert(dst.offset % 4 == 0);
  62    assert(src.offset % 4 == 0);
  63
  64 #if GEN_GEN == 7
  65    /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
  66     * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
  67     * in-flight when they are issued even if the memory touched is not
  68     * currently active for rendering.  The weird bit is that it is not the
  69     * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
  70     * rendering hangs such that the next stalling command after the
  71     * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
  72     *
  73     * It is unclear exactly why this hang occurs.  Both MI commands come with
  74     * warnings about the 3D pipeline but that doesn't seem to fully explain
  75     * it.  My (Jason's) best theory is that it has something to do with the
  76     * fact that we're using a GPU state register as our temporary and that
  77     * something with reading/writing it is causing problems.
  78     *
  79     * In order to work around this issue, we emit a PIPE_CONTROL with the
  80     * command streamer stall bit set.
  81     */
  82    cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
  83    genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
  84 #endif
  85
  86    for (uint32_t i = 0; i < size; i += 4) {
  87 #if GEN_GEN >= 8
  88       anv_batch_emit(&cmd_buffer->batch, GENX(MI_COPY_MEM_MEM), cp) {
  89          cp.DestinationMemoryAddress = anv_address_add(dst, i);
  90          cp.SourceMemoryAddress = anv_address_add(src, i);
  91       }
  92 #else
  93       /* IVB does not have a general purpose register for command streamer
  94        * commands. Therefore, we use an alternate temporary register.
  95        */
  96 #define TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */
  97       anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_MEM), load) {
  98          load.RegisterAddress = TEMP_REG;
  99          load.MemoryAddress = anv_address_add(src, i);
 100       }
 101       anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), store) {
 102          store.RegisterAddress = TEMP_REG;
 103          store.MemoryAddress = anv_address_add(dst, i);
 104       }
 105 #undef TEMP_REG
 106 #endif
 107    }
 108    return;
 109 }
 110
 111 void
 112 genX(cmd_buffer_mi_memset)(struct anv_cmd_buffer *cmd_buffer,
 113                            struct anv_address dst, uint32_t value,
 114                            uint32_t size)
 115 {
 116    /* This memset operates in units of dwords. */
 117    assert(size % 4 == 0);
 118    assert(dst.offset % 4 == 0);
 119
 120    for (uint32_t i = 0; i < size; i += 4) {
 121       anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
 122          sdi.Address = anv_address_add(dst, i);
 123          sdi.ImmediateData = value;
 124       }
 125    }
 126 }
 127
 128 void
 129 genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
 130                            struct anv_address dst, struct anv_address src,
 131                            uint32_t size)
 132 {
 133    if (size == 0)
 134       return;
 135
 136    /* The maximum copy block size is 4 32-bit components at a time. */
 137    assert(size % 4 == 0);
 138    unsigned bs = gcd_pow2_u64(16, size);
 139
 140    enum isl_format format;
 141    switch (bs) {
 142    case 4:  format = ISL_FORMAT_R32_UINT;          break;
 143    case 8:  format = ISL_FORMAT_R32G32_UINT;       break;
 144    case 16: format = ISL_FORMAT_R32G32B32A32_UINT; break;
 145    default:
 146       unreachable("Invalid size");
 147    }
 148
 149    if (!cmd_buffer->state.current_l3_config) {
 150       const struct gen_l3_config *cfg =
 151          gen_get_default_l3_config(&cmd_buffer->device->info);
 152       genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
 153    }
 154
 155    genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
 156
 157    genX(flush_pipeline_select_3d)(cmd_buffer);
 158
 159    uint32_t *dw;
 160    dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_VERTEX_BUFFERS));
 161    GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, dw + 1,
 162       &(struct GENX(VERTEX_BUFFER_STATE)) {
 163          .VertexBufferIndex = 32, /* Reserved for this */
 164          .AddressModifyEnable = true,
 165          .BufferStartingAddress = src,
 166          .BufferPitch = bs,
 167          .MOCS = anv_mocs_for_bo(cmd_buffer->device, src.bo),
 168 #if (GEN_GEN >= 8)
 169          .BufferSize = size,
 170 #else
 171          .EndAddress = anv_address_add(src, size - 1),
 172 #endif
 173       });
 174
 175    dw = anv_batch_emitn(&cmd_buffer->batch, 3, GENX(3DSTATE_VERTEX_ELEMENTS));
 176    GENX(VERTEX_ELEMENT_STATE_pack)(&cmd_buffer->batch, dw + 1,
 177       &(struct GENX(VERTEX_ELEMENT_STATE)) {
 178          .VertexBufferIndex = 32,
 179          .Valid = true,
 180          .SourceElementFormat = format,
 181          .SourceElementOffset = 0,
 182          .Component0Control = (bs >= 4) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
 183          .Component1Control = (bs >= 8) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
 184          .Component2Control = (bs >= 12) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
 185          .Component3Control = (bs >= 16) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
 186       });
 187
 188 #if GEN_GEN >= 8
 189    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_SGVS), sgvs);
 190 #endif
 191
 192    /* Disable all shader stages */
 193    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VS), vs);
 194    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HS), hs);
 195    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_TE), te);
 196    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DS), DS);
 197    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_GS), gs);
 198    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_PS), gs);
 199
 200    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SBE), sbe) {
 201       sbe.VertexURBEntryReadOffset = 1;
 202       sbe.NumberofSFOutputAttributes = 1;
 203       sbe.VertexURBEntryReadLength = 1;
 204 #if GEN_GEN >= 8
 205       sbe.ForceVertexURBEntryReadLength = true;
 206       sbe.ForceVertexURBEntryReadOffset = true;
 207 #endif
 208
 209 #if GEN_GEN >= 9
 210       for (unsigned i = 0; i < 32; i++)
 211          sbe.AttributeActiveComponentFormat[i] = ACF_XYZW;
 212 #endif
 213    }
 214
 215    /* Emit URB setup.  We tell it that the VS is active because we want it to
 216     * allocate space for the VS.  Even though one isn't run, we need VUEs to
 217     * store the data that VF is going to pass to SOL.
 218     */
 219    const unsigned entry_size[4] = { DIV_ROUND_UP(32, 64), 1, 1, 1 };
 220
 221    genX(emit_urb_setup)(cmd_buffer->device, &cmd_buffer->batch,
 222                         cmd_buffer->state.current_l3_config,
 223                         VK_SHADER_STAGE_VERTEX_BIT, entry_size);
 224
 225    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) {
 226       sob.SOBufferIndex = 0;
 227       sob.MOCS = anv_mocs_for_bo(cmd_buffer->device, dst.bo),
 228       sob.SurfaceBaseAddress = dst;
 229
 230 #if GEN_GEN >= 8
 231       sob.SOBufferEnable = true;
 232       sob.SurfaceSize = size / 4 - 1;
 233 #else
 234       sob.SurfacePitch = bs;
 235       sob.SurfaceEndAddress = anv_address_add(dst, size);
 236 #endif
 237
 238 #if GEN_GEN >= 8
 239       /* As SOL writes out data, it updates the SO_WRITE_OFFSET registers with
 240        * the end position of the stream.  We need to reset this value to 0 at
 241        * the beginning of the run or else SOL will start at the offset from
 242        * the previous draw.
 243        */
 244       sob.StreamOffsetWriteEnable = true;
 245       sob.StreamOffset = 0;
 246 #endif
 247    }
 248
 249 #if GEN_GEN <= 7
 250    /* The hardware can do this for us on BDW+ (see above) */
 251    anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), load) {
 252       load.RegisterOffset = GENX(SO_WRITE_OFFSET0_num);
 253       load.DataDWord = 0;
 254    }
 255 #endif
 256
 257    dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_SO_DECL_LIST),
 258                         .StreamtoBufferSelects0 = (1 << 0),
 259                         .NumEntries0 = 1);
 260    GENX(SO_DECL_ENTRY_pack)(&cmd_buffer->batch, dw + 3,
 261       &(struct GENX(SO_DECL_ENTRY)) {
 262          .Stream0Decl = {
 263             .OutputBufferSlot = 0,
 264             .RegisterIndex = 0,
 265             .ComponentMask = (1 << (bs / 4)) - 1,
 266          },
 267       });
 268
 269    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STREAMOUT), so) {
 270       so.SOFunctionEnable = true;
 271       so.RenderingDisable = true;
 272       so.Stream0VertexReadOffset = 0;
 273       so.Stream0VertexReadLength = DIV_ROUND_UP(32, 64);
 274 #if GEN_GEN >= 8
 275       so.Buffer0SurfacePitch = bs;
 276 #else
 277       so.SOBufferEnable0 = true;
 278 #endif
 279    }
 280
 281 #if GEN_GEN >= 8
 282    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
 283       topo.PrimitiveTopologyType = _3DPRIM_POINTLIST;
 284    }
 285 #endif
 286
 287    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_STATISTICS), vf) {
 288       vf.StatisticsEnable = false;
 289    }
 290
 291    anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
 292       prim.VertexAccessType         = SEQUENTIAL;
 293       prim.PrimitiveTopologyType    = _3DPRIM_POINTLIST;
 294       prim.VertexCountPerInstance   = size / bs;
 295       prim.StartVertexLocation      = 0;
 296       prim.InstanceCount            = 1;
 297       prim.StartInstanceLocation    = 0;
 298       prim.BaseVertexLocation       = 0;
 299    }
 300
 301    cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
 302    cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
 303 }