2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "anv_private.h"
26 #include "genxml/gen_macros.h"
27 #include "genxml/genX_pack.h"
29 #include "common/gen_l3_config.h"
30 #include "common/gen_sample_positions.h"
31 #include "vk_format_info.h"
34 vertex_element_comp_control(enum isl_format format
, unsigned comp
)
38 case 0: bits
= isl_format_layouts
[format
].channels
.r
.bits
; break;
39 case 1: bits
= isl_format_layouts
[format
].channels
.g
.bits
; break;
40 case 2: bits
= isl_format_layouts
[format
].channels
.b
.bits
; break;
41 case 3: bits
= isl_format_layouts
[format
].channels
.a
.bits
; break;
42 default: unreachable("Invalid component");
46 * Take in account hardware restrictions when dealing with 64-bit floats.
48 * From Broadwell spec, command reference structures, page 586:
49 * "When SourceElementFormat is set to one of the *64*_PASSTHRU formats,
50 * 64-bit components are stored * in the URB without any conversion. In
51 * this case, vertex elements must be written as 128 or 256 bits, with
52 * VFCOMP_STORE_0 being used to pad the output as required. E.g., if
53 * R64_PASSTHRU is used to copy a 64-bit Red component into the URB,
54 * Component 1 must be specified as VFCOMP_STORE_0 (with Components 2,3
55 * set to VFCOMP_NOSTORE) in order to output a 128-bit vertex element, or
56 * Components 1-3 must be specified as VFCOMP_STORE_0 in order to output
57 * a 256-bit vertex element. Likewise, use of R64G64B64_PASSTHRU requires
58 * Component 3 to be specified as VFCOMP_STORE_0 in order to output a
59 * 256-bit vertex element."
62 return VFCOMP_STORE_SRC
;
63 } else if (comp
>= 2 &&
64 !isl_format_layouts
[format
].channels
.b
.bits
&&
65 isl_format_layouts
[format
].channels
.r
.type
== ISL_RAW
) {
66 /* When emitting 64-bit attributes, we need to write either 128 or 256
67 * bit chunks, using VFCOMP_NOSTORE when not writing the chunk, and
68 * VFCOMP_STORE_0 to pad the written chunk */
69 return VFCOMP_NOSTORE
;
70 } else if (comp
< 3 ||
71 isl_format_layouts
[format
].channels
.r
.type
== ISL_RAW
) {
72 /* Note we need to pad with value 0, not 1, due hardware restrictions
73 * (see comment above) */
74 return VFCOMP_STORE_0
;
75 } else if (isl_format_layouts
[format
].channels
.r
.type
== ISL_UINT
||
76 isl_format_layouts
[format
].channels
.r
.type
== ISL_SINT
) {
78 return VFCOMP_STORE_1_INT
;
81 return VFCOMP_STORE_1_FP
;
86 emit_vertex_input(struct anv_pipeline
*pipeline
,
87 const VkPipelineVertexInputStateCreateInfo
*info
)
89 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
91 /* Pull inputs_read out of the VS prog data */
92 const uint64_t inputs_read
= vs_prog_data
->inputs_read
;
93 const uint64_t double_inputs_read
= vs_prog_data
->double_inputs_read
;
94 assert((inputs_read
& ((1 << VERT_ATTRIB_GENERIC0
) - 1)) == 0);
95 const uint32_t elements
= inputs_read
>> VERT_ATTRIB_GENERIC0
;
96 const uint32_t elements_double
= double_inputs_read
>> VERT_ATTRIB_GENERIC0
;
97 const bool needs_svgs_elem
= vs_prog_data
->uses_vertexid
||
98 vs_prog_data
->uses_instanceid
||
99 vs_prog_data
->uses_basevertex
||
100 vs_prog_data
->uses_baseinstance
;
102 uint32_t elem_count
= __builtin_popcount(elements
) -
103 __builtin_popcount(elements_double
) / 2;
105 const uint32_t total_elems
=
106 elem_count
+ needs_svgs_elem
+ vs_prog_data
->uses_drawid
;
107 if (total_elems
== 0)
112 const uint32_t num_dwords
= 1 + total_elems
* 2;
113 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
114 GENX(3DSTATE_VERTEX_ELEMENTS
));
115 memset(p
+ 1, 0, (num_dwords
- 1) * 4);
117 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
118 const VkVertexInputAttributeDescription
*desc
=
119 &info
->pVertexAttributeDescriptions
[i
];
120 enum isl_format format
= anv_get_isl_format(&pipeline
->device
->info
,
122 VK_IMAGE_ASPECT_COLOR_BIT
,
123 VK_IMAGE_TILING_LINEAR
);
125 assert(desc
->binding
< MAX_VBS
);
127 if ((elements
& (1 << desc
->location
)) == 0)
128 continue; /* Binding unused */
131 __builtin_popcount(elements
& ((1 << desc
->location
) - 1)) -
132 DIV_ROUND_UP(__builtin_popcount(elements_double
&
133 ((1 << desc
->location
) -1)), 2);
135 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
136 .VertexBufferIndex
= desc
->binding
,
138 .SourceElementFormat
= format
,
139 .EdgeFlagEnable
= false,
140 .SourceElementOffset
= desc
->offset
,
141 .Component0Control
= vertex_element_comp_control(format
, 0),
142 .Component1Control
= vertex_element_comp_control(format
, 1),
143 .Component2Control
= vertex_element_comp_control(format
, 2),
144 .Component3Control
= vertex_element_comp_control(format
, 3),
146 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + slot
* 2], &element
);
149 /* On Broadwell and later, we have a separate VF_INSTANCING packet
150 * that controls instancing. On Haswell and prior, that's part of
151 * VERTEX_BUFFER_STATE which we emit later.
153 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
154 vfi
.InstancingEnable
= pipeline
->instancing_enable
[desc
->binding
];
155 vfi
.VertexElementIndex
= slot
;
156 /* Vulkan so far doesn't have an instance divisor, so
157 * this is always 1 (ignored if not instancing). */
158 vfi
.InstanceDataStepRate
= 1;
163 const uint32_t id_slot
= elem_count
;
164 if (needs_svgs_elem
) {
165 /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
166 * "Within a VERTEX_ELEMENT_STATE structure, if a Component
167 * Control field is set to something other than VFCOMP_STORE_SRC,
168 * no higher-numbered Component Control fields may be set to
171 * This means, that if we have BaseInstance, we need BaseVertex as
172 * well. Just do all or nothing.
174 uint32_t base_ctrl
= (vs_prog_data
->uses_basevertex
||
175 vs_prog_data
->uses_baseinstance
) ?
176 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
178 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
179 .VertexBufferIndex
= ANV_SVGS_VB_INDEX
,
181 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
182 .Component0Control
= base_ctrl
,
183 .Component1Control
= base_ctrl
,
185 .Component2Control
= VFCOMP_STORE_0
,
186 .Component3Control
= VFCOMP_STORE_0
,
188 .Component2Control
= VFCOMP_STORE_VID
,
189 .Component3Control
= VFCOMP_STORE_IID
,
192 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + id_slot
* 2], &element
);
196 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
197 sgvs
.VertexIDEnable
= vs_prog_data
->uses_vertexid
;
198 sgvs
.VertexIDComponentNumber
= 2;
199 sgvs
.VertexIDElementOffset
= id_slot
;
200 sgvs
.InstanceIDEnable
= vs_prog_data
->uses_instanceid
;
201 sgvs
.InstanceIDComponentNumber
= 3;
202 sgvs
.InstanceIDElementOffset
= id_slot
;
206 const uint32_t drawid_slot
= elem_count
+ needs_svgs_elem
;
207 if (vs_prog_data
->uses_drawid
) {
208 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
209 .VertexBufferIndex
= ANV_DRAWID_VB_INDEX
,
211 .SourceElementFormat
= ISL_FORMAT_R32_UINT
,
212 .Component0Control
= VFCOMP_STORE_SRC
,
213 .Component1Control
= VFCOMP_STORE_0
,
214 .Component2Control
= VFCOMP_STORE_0
,
215 .Component3Control
= VFCOMP_STORE_0
,
217 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
,
218 &p
[1 + drawid_slot
* 2],
222 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
223 vfi
.VertexElementIndex
= drawid_slot
;
230 genX(emit_urb_setup
)(struct anv_device
*device
, struct anv_batch
*batch
,
231 const struct gen_l3_config
*l3_config
,
232 VkShaderStageFlags active_stages
,
233 const unsigned entry_size
[4])
235 const struct gen_device_info
*devinfo
= &device
->info
;
237 const unsigned push_constant_kb
= devinfo
->gt
== 3 ? 32 : 16;
239 const unsigned push_constant_kb
= GEN_GEN
>= 8 ? 32 : 16;
242 const unsigned urb_size_kb
= gen_get_l3_config_urb_size(devinfo
, l3_config
);
246 gen_get_urb_config(devinfo
,
247 1024 * push_constant_kb
, 1024 * urb_size_kb
,
249 VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
,
250 active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
,
251 entry_size
, entries
, start
);
253 #if GEN_GEN == 7 && !GEN_IS_HASWELL
254 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
256 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
257 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
258 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
259 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
260 * needs to be sent before any combination of VS associated 3DSTATE."
262 anv_batch_emit(batch
, GEN7_PIPE_CONTROL
, pc
) {
263 pc
.DepthStallEnable
= true;
264 pc
.PostSyncOperation
= WriteImmediateData
;
265 pc
.Address
= (struct anv_address
) { &device
->workaround_bo
, 0 };
269 for (int i
= 0; i
<= MESA_SHADER_GEOMETRY
; i
++) {
270 anv_batch_emit(batch
, GENX(3DSTATE_URB_VS
), urb
) {
271 urb
._3DCommandSubOpcode
+= i
;
272 urb
.VSURBStartingAddress
= start
[i
];
273 urb
.VSURBEntryAllocationSize
= entry_size
[i
] - 1;
274 urb
.VSNumberofURBEntries
= entries
[i
];
280 emit_urb_setup(struct anv_pipeline
*pipeline
)
282 unsigned entry_size
[4];
283 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
284 const struct brw_vue_prog_data
*prog_data
=
285 !anv_pipeline_has_stage(pipeline
, i
) ? NULL
:
286 (const struct brw_vue_prog_data
*) pipeline
->shaders
[i
]->prog_data
;
288 entry_size
[i
] = prog_data
? prog_data
->urb_entry_size
: 1;
291 genX(emit_urb_setup
)(pipeline
->device
, &pipeline
->batch
,
292 pipeline
->urb
.l3_config
,
293 pipeline
->active_stages
, entry_size
);
297 emit_3dstate_sbe(struct anv_pipeline
*pipeline
)
299 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
301 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
302 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SBE
), sbe
);
304 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SBE_SWIZ
), sbe
);
309 const struct brw_vue_map
*fs_input_map
=
310 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
312 struct GENX(3DSTATE_SBE
) sbe
= {
313 GENX(3DSTATE_SBE_header
),
314 .AttributeSwizzleEnable
= true,
315 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
,
316 .NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
,
317 .ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
,
321 for (unsigned i
= 0; i
< 32; i
++)
322 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
326 /* On Broadwell, they broke 3DSTATE_SBE into two packets */
327 struct GENX(3DSTATE_SBE_SWIZ
) swiz
= {
328 GENX(3DSTATE_SBE_SWIZ_header
),
334 /* Skip the VUE header and position slots by default */
335 unsigned urb_entry_read_offset
= 1;
336 int max_source_attr
= 0;
337 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
338 int input_index
= wm_prog_data
->urb_setup
[attr
];
343 /* gl_Layer is stored in the VUE header */
344 if (attr
== VARYING_SLOT_LAYER
) {
345 urb_entry_read_offset
= 0;
349 if (attr
== VARYING_SLOT_PNTC
) {
350 sbe
.PointSpriteTextureCoordinateEnable
= 1 << input_index
;
354 const int slot
= fs_input_map
->varying_to_slot
[attr
];
356 if (input_index
>= 16)
360 /* This attribute does not exist in the VUE--that means that the
361 * vertex shader did not write to it. It could be that it's a
362 * regular varying read by the fragment shader but not written by
363 * the vertex shader or it's gl_PrimitiveID. In the first case the
364 * value is undefined, in the second it needs to be
367 swiz
.Attribute
[input_index
].ConstantSource
= PRIM_ID
;
368 swiz
.Attribute
[input_index
].ComponentOverrideX
= true;
369 swiz
.Attribute
[input_index
].ComponentOverrideY
= true;
370 swiz
.Attribute
[input_index
].ComponentOverrideZ
= true;
371 swiz
.Attribute
[input_index
].ComponentOverrideW
= true;
373 /* We have to subtract two slots to accout for the URB entry output
374 * read offset in the VS and GS stages.
377 const int source_attr
= slot
- 2 * urb_entry_read_offset
;
378 max_source_attr
= MAX2(max_source_attr
, source_attr
);
379 swiz
.Attribute
[input_index
].SourceAttribute
= source_attr
;
383 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
384 sbe
.VertexURBEntryReadLength
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
386 sbe
.ForceVertexURBEntryReadOffset
= true;
387 sbe
.ForceVertexURBEntryReadLength
= true;
390 uint32_t *dw
= anv_batch_emit_dwords(&pipeline
->batch
,
391 GENX(3DSTATE_SBE_length
));
392 GENX(3DSTATE_SBE_pack
)(&pipeline
->batch
, dw
, &sbe
);
395 dw
= anv_batch_emit_dwords(&pipeline
->batch
, GENX(3DSTATE_SBE_SWIZ_length
));
396 GENX(3DSTATE_SBE_SWIZ_pack
)(&pipeline
->batch
, dw
, &swiz
);
400 static const uint32_t vk_to_gen_cullmode
[] = {
401 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
402 [VK_CULL_MODE_FRONT_BIT
] = CULLMODE_FRONT
,
403 [VK_CULL_MODE_BACK_BIT
] = CULLMODE_BACK
,
404 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
407 static const uint32_t vk_to_gen_fillmode
[] = {
408 [VK_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
409 [VK_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
410 [VK_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
413 static const uint32_t vk_to_gen_front_face
[] = {
414 [VK_FRONT_FACE_COUNTER_CLOCKWISE
] = 1,
415 [VK_FRONT_FACE_CLOCKWISE
] = 0
419 emit_rs_state(struct anv_pipeline
*pipeline
,
420 const VkPipelineRasterizationStateCreateInfo
*rs_info
,
421 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
422 const struct anv_render_pass
*pass
,
423 const struct anv_subpass
*subpass
)
425 struct GENX(3DSTATE_SF
) sf
= {
426 GENX(3DSTATE_SF_header
),
429 sf
.ViewportTransformEnable
= true;
430 sf
.StatisticsEnable
= true;
431 sf
.TriangleStripListProvokingVertexSelect
= 0;
432 sf
.LineStripListProvokingVertexSelect
= 0;
433 sf
.TriangleFanProvokingVertexSelect
= 1;
435 const struct brw_vue_prog_data
*last_vue_prog_data
=
436 anv_pipeline_get_last_vue_prog_data(pipeline
);
438 if (last_vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
439 sf
.PointWidthSource
= Vertex
;
441 sf
.PointWidthSource
= State
;
446 struct GENX(3DSTATE_RASTER
) raster
= {
447 GENX(3DSTATE_RASTER_header
),
453 /* For details on 3DSTATE_RASTER multisample state, see the BSpec table
454 * "Multisample Modes State".
457 raster
.DXMultisampleRasterizationEnable
= true;
458 raster
.ForcedSampleCount
= FSC_NUMRASTSAMPLES_0
;
459 raster
.ForceMultisampling
= false;
461 raster
.MultisampleRasterizationMode
=
462 (ms_info
&& ms_info
->rasterizationSamples
> 1) ?
463 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
466 raster
.FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
];
467 raster
.CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
];
468 raster
.FrontFaceFillMode
= vk_to_gen_fillmode
[rs_info
->polygonMode
];
469 raster
.BackFaceFillMode
= vk_to_gen_fillmode
[rs_info
->polygonMode
];
470 raster
.ScissorRectangleEnable
= true;
473 /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
474 raster
.ViewportZFarClipTestEnable
= !pipeline
->depth_clamp_enable
;
475 raster
.ViewportZNearClipTestEnable
= !pipeline
->depth_clamp_enable
;
477 raster
.ViewportZClipTestEnable
= !pipeline
->depth_clamp_enable
;
480 raster
.GlobalDepthOffsetEnableSolid
= rs_info
->depthBiasEnable
;
481 raster
.GlobalDepthOffsetEnableWireframe
= rs_info
->depthBiasEnable
;
482 raster
.GlobalDepthOffsetEnablePoint
= rs_info
->depthBiasEnable
;
485 /* Gen7 requires that we provide the depth format in 3DSTATE_SF so that it
486 * can get the depth offsets correct.
488 if (subpass
->depth_stencil_attachment
< pass
->attachment_count
) {
490 pass
->attachments
[subpass
->depth_stencil_attachment
].format
;
491 assert(vk_format_is_depth_or_stencil(vk_format
));
492 if (vk_format_aspects(vk_format
) & VK_IMAGE_ASPECT_DEPTH_BIT
) {
493 enum isl_format isl_format
=
494 anv_get_isl_format(&pipeline
->device
->info
, vk_format
,
495 VK_IMAGE_ASPECT_DEPTH_BIT
,
496 VK_IMAGE_TILING_OPTIMAL
);
497 sf
.DepthBufferSurfaceFormat
=
498 isl_format_get_depth_format(isl_format
, false);
504 GENX(3DSTATE_SF_pack
)(NULL
, pipeline
->gen8
.sf
, &sf
);
505 GENX(3DSTATE_RASTER_pack
)(NULL
, pipeline
->gen8
.raster
, &raster
);
508 GENX(3DSTATE_SF_pack
)(NULL
, &pipeline
->gen7
.sf
, &sf
);
513 emit_ms_state(struct anv_pipeline
*pipeline
,
514 const VkPipelineMultisampleStateCreateInfo
*info
)
516 uint32_t samples
= 1;
517 uint32_t log2_samples
= 0;
519 /* From the Vulkan 1.0 spec:
520 * If pSampleMask is NULL, it is treated as if the mask has all bits
521 * enabled, i.e. no coverage is removed from fragments.
523 * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
526 uint32_t sample_mask
= 0xffff;
528 uint32_t sample_mask
= 0xff;
532 samples
= info
->rasterizationSamples
;
533 log2_samples
= __builtin_ffs(samples
) - 1;
536 if (info
&& info
->pSampleMask
)
537 sample_mask
&= info
->pSampleMask
[0];
539 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
540 ms
.NumberofMultisamples
= log2_samples
;
543 /* The PRM says that this bit is valid only for DX9:
545 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
546 * should not have any effect by setting or not setting this bit.
548 ms
.PixelPositionOffsetEnable
= false;
549 ms
.PixelLocation
= CENTER
;
551 ms
.PixelLocation
= PIXLOC_CENTER
;
555 GEN_SAMPLE_POS_1X(ms
.Sample
);
558 GEN_SAMPLE_POS_2X(ms
.Sample
);
561 GEN_SAMPLE_POS_4X(ms
.Sample
);
564 GEN_SAMPLE_POS_8X(ms
.Sample
);
572 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
573 sm
.SampleMask
= sample_mask
;
577 static const uint32_t vk_to_gen_logic_op
[] = {
578 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
579 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
580 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
581 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
582 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
583 [VK_LOGIC_OP_NO_OP
] = LOGICOP_NOOP
,
584 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
585 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
586 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
587 [VK_LOGIC_OP_EQUIVALENT
] = LOGICOP_EQUIV
,
588 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
589 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
590 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
591 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
592 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
593 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
596 static const uint32_t vk_to_gen_blend
[] = {
597 [VK_BLEND_FACTOR_ZERO
] = BLENDFACTOR_ZERO
,
598 [VK_BLEND_FACTOR_ONE
] = BLENDFACTOR_ONE
,
599 [VK_BLEND_FACTOR_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
600 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
601 [VK_BLEND_FACTOR_DST_COLOR
] = BLENDFACTOR_DST_COLOR
,
602 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
603 [VK_BLEND_FACTOR_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
604 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
605 [VK_BLEND_FACTOR_DST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
606 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
607 [VK_BLEND_FACTOR_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
608 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
]= BLENDFACTOR_INV_CONST_COLOR
,
609 [VK_BLEND_FACTOR_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
610 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
]= BLENDFACTOR_INV_CONST_ALPHA
,
611 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
612 [VK_BLEND_FACTOR_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
613 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
614 [VK_BLEND_FACTOR_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
615 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
618 static const uint32_t vk_to_gen_blend_op
[] = {
619 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
620 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
621 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
622 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
623 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
626 static const uint32_t vk_to_gen_compare_op
[] = {
627 [VK_COMPARE_OP_NEVER
] = PREFILTEROPNEVER
,
628 [VK_COMPARE_OP_LESS
] = PREFILTEROPLESS
,
629 [VK_COMPARE_OP_EQUAL
] = PREFILTEROPEQUAL
,
630 [VK_COMPARE_OP_LESS_OR_EQUAL
] = PREFILTEROPLEQUAL
,
631 [VK_COMPARE_OP_GREATER
] = PREFILTEROPGREATER
,
632 [VK_COMPARE_OP_NOT_EQUAL
] = PREFILTEROPNOTEQUAL
,
633 [VK_COMPARE_OP_GREATER_OR_EQUAL
] = PREFILTEROPGEQUAL
,
634 [VK_COMPARE_OP_ALWAYS
] = PREFILTEROPALWAYS
,
637 static const uint32_t vk_to_gen_stencil_op
[] = {
638 [VK_STENCIL_OP_KEEP
] = STENCILOP_KEEP
,
639 [VK_STENCIL_OP_ZERO
] = STENCILOP_ZERO
,
640 [VK_STENCIL_OP_REPLACE
] = STENCILOP_REPLACE
,
641 [VK_STENCIL_OP_INCREMENT_AND_CLAMP
] = STENCILOP_INCRSAT
,
642 [VK_STENCIL_OP_DECREMENT_AND_CLAMP
] = STENCILOP_DECRSAT
,
643 [VK_STENCIL_OP_INVERT
] = STENCILOP_INVERT
,
644 [VK_STENCIL_OP_INCREMENT_AND_WRAP
] = STENCILOP_INCR
,
645 [VK_STENCIL_OP_DECREMENT_AND_WRAP
] = STENCILOP_DECR
,
649 emit_ds_state(struct anv_pipeline
*pipeline
,
650 const VkPipelineDepthStencilStateCreateInfo
*info
,
651 const struct anv_render_pass
*pass
,
652 const struct anv_subpass
*subpass
)
655 # define depth_stencil_dw pipeline->gen7.depth_stencil_state
657 # define depth_stencil_dw pipeline->gen8.wm_depth_stencil
659 # define depth_stencil_dw pipeline->gen9.wm_depth_stencil
663 /* We're going to OR this together with the dynamic state. We need
664 * to make sure it's initialized to something useful.
666 memset(depth_stencil_dw
, 0, sizeof(depth_stencil_dw
));
670 /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
673 struct GENX(DEPTH_STENCIL_STATE
) depth_stencil
= {
675 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) depth_stencil
= {
677 .DepthTestEnable
= info
->depthTestEnable
,
678 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
679 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
680 .DoubleSidedStencilEnable
= true,
682 .StencilTestEnable
= info
->stencilTestEnable
,
683 .StencilBufferWriteEnable
= info
->stencilTestEnable
,
684 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.failOp
],
685 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.passOp
],
686 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.depthFailOp
],
687 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.compareOp
],
688 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.failOp
],
689 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.passOp
],
690 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
->back
.depthFailOp
],
691 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.compareOp
],
694 VkImageAspectFlags aspects
= 0;
695 if (subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
) {
696 VkFormat depth_stencil_format
=
697 pass
->attachments
[subpass
->depth_stencil_attachment
].format
;
698 aspects
= vk_format_aspects(depth_stencil_format
);
701 /* The Vulkan spec requires that if either depth or stencil is not present,
702 * the pipeline is to act as if the test silently passes.
704 if (!(aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
705 depth_stencil
.DepthBufferWriteEnable
= false;
706 depth_stencil
.DepthTestFunction
= PREFILTEROPALWAYS
;
709 if (!(aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
710 depth_stencil
.StencilBufferWriteEnable
= false;
711 depth_stencil
.StencilTestFunction
= PREFILTEROPALWAYS
;
712 depth_stencil
.BackfaceStencilTestFunction
= PREFILTEROPALWAYS
;
715 /* From the Broadwell PRM:
717 * "If Depth_Test_Enable = 1 AND Depth_Test_func = EQUAL, the
718 * Depth_Write_Enable must be set to 0."
720 if (info
->depthTestEnable
&& info
->depthCompareOp
== VK_COMPARE_OP_EQUAL
)
721 depth_stencil
.DepthBufferWriteEnable
= false;
724 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
726 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
731 emit_cb_state(struct anv_pipeline
*pipeline
,
732 const VkPipelineColorBlendStateCreateInfo
*info
,
733 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
735 struct anv_device
*device
= pipeline
->device
;
737 const uint32_t num_dwords
= GENX(BLEND_STATE_length
);
738 pipeline
->blend_state
=
739 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
741 struct GENX(BLEND_STATE
) blend_state
= {
743 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
744 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
746 /* Make sure it gets zeroed */
747 .Entry
= { { 0, }, },
751 /* Default everything to disabled */
752 for (uint32_t i
= 0; i
< 8; i
++) {
753 blend_state
.Entry
[i
].WriteDisableAlpha
= true;
754 blend_state
.Entry
[i
].WriteDisableRed
= true;
755 blend_state
.Entry
[i
].WriteDisableGreen
= true;
756 blend_state
.Entry
[i
].WriteDisableBlue
= true;
759 uint32_t surface_count
= 0;
760 struct anv_pipeline_bind_map
*map
;
761 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
762 map
= &pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->bind_map
;
763 surface_count
= map
->surface_count
;
766 bool has_writeable_rt
= false;
767 for (unsigned i
= 0; i
< surface_count
; i
++) {
768 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[i
];
770 /* All color attachments are at the beginning of the binding table */
771 if (binding
->set
!= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
)
774 /* We can have at most 8 attachments */
777 if (binding
->index
>= info
->attachmentCount
)
780 assert(binding
->binding
== 0);
781 const VkPipelineColorBlendAttachmentState
*a
=
782 &info
->pAttachments
[binding
->index
];
784 blend_state
.Entry
[i
] = (struct GENX(BLEND_STATE_ENTRY
)) {
786 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
787 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
789 .LogicOpEnable
= info
->logicOpEnable
,
790 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
791 .ColorBufferBlendEnable
= a
->blendEnable
,
792 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
793 .PreBlendColorClampEnable
= true,
794 .PostBlendColorClampEnable
= true,
795 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcColorBlendFactor
],
796 .DestinationBlendFactor
= vk_to_gen_blend
[a
->dstColorBlendFactor
],
797 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->colorBlendOp
],
798 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcAlphaBlendFactor
],
799 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->dstAlphaBlendFactor
],
800 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->alphaBlendOp
],
801 .WriteDisableAlpha
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_A_BIT
),
802 .WriteDisableRed
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_R_BIT
),
803 .WriteDisableGreen
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_G_BIT
),
804 .WriteDisableBlue
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_B_BIT
),
807 if (a
->srcColorBlendFactor
!= a
->srcAlphaBlendFactor
||
808 a
->dstColorBlendFactor
!= a
->dstAlphaBlendFactor
||
809 a
->colorBlendOp
!= a
->alphaBlendOp
) {
811 blend_state
.IndependentAlphaBlendEnable
= true;
813 blend_state
.Entry
[i
].IndependentAlphaBlendEnable
= true;
817 if (a
->colorWriteMask
!= 0)
818 has_writeable_rt
= true;
820 /* Our hardware applies the blend factor prior to the blend function
821 * regardless of what function is used. Technically, this means the
822 * hardware can do MORE than GL or Vulkan specify. However, it also
823 * means that, for MIN and MAX, we have to stomp the blend factor to
824 * ONE to make it a no-op.
826 if (a
->colorBlendOp
== VK_BLEND_OP_MIN
||
827 a
->colorBlendOp
== VK_BLEND_OP_MAX
) {
828 blend_state
.Entry
[i
].SourceBlendFactor
= BLENDFACTOR_ONE
;
829 blend_state
.Entry
[i
].DestinationBlendFactor
= BLENDFACTOR_ONE
;
831 if (a
->alphaBlendOp
== VK_BLEND_OP_MIN
||
832 a
->alphaBlendOp
== VK_BLEND_OP_MAX
) {
833 blend_state
.Entry
[i
].SourceAlphaBlendFactor
= BLENDFACTOR_ONE
;
834 blend_state
.Entry
[i
].DestinationAlphaBlendFactor
= BLENDFACTOR_ONE
;
839 struct GENX(BLEND_STATE_ENTRY
) *bs0
= &blend_state
.Entry
[0];
840 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_BLEND
), blend
) {
841 blend
.AlphaToCoverageEnable
= blend_state
.AlphaToCoverageEnable
;
842 blend
.HasWriteableRT
= has_writeable_rt
;
843 blend
.ColorBufferBlendEnable
= bs0
->ColorBufferBlendEnable
;
844 blend
.SourceAlphaBlendFactor
= bs0
->SourceAlphaBlendFactor
;
845 blend
.DestinationAlphaBlendFactor
= bs0
->DestinationAlphaBlendFactor
;
846 blend
.SourceBlendFactor
= bs0
->SourceBlendFactor
;
847 blend
.DestinationBlendFactor
= bs0
->DestinationBlendFactor
;
848 blend
.AlphaTestEnable
= false;
849 blend
.IndependentAlphaBlendEnable
=
850 blend_state
.IndependentAlphaBlendEnable
;
853 (void)has_writeable_rt
;
856 GENX(BLEND_STATE_pack
)(NULL
, pipeline
->blend_state
.map
, &blend_state
);
857 if (!device
->info
.has_llc
)
858 anv_state_clflush(pipeline
->blend_state
);
860 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), bsp
) {
861 bsp
.BlendStatePointer
= pipeline
->blend_state
.offset
;
863 bsp
.BlendStatePointerValid
= true;
869 emit_3dstate_clip(struct anv_pipeline
*pipeline
,
870 const VkPipelineViewportStateCreateInfo
*vp_info
,
871 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
873 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
875 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_CLIP
), clip
) {
876 clip
.ClipEnable
= true;
877 clip
.EarlyCullEnable
= true;
878 clip
.APIMode
= APIMODE_D3D
,
879 clip
.ViewportXYClipTestEnable
= true;
881 clip
.ClipMode
= CLIPMODE_NORMAL
;
883 clip
.TriangleStripListProvokingVertexSelect
= 0;
884 clip
.LineStripListProvokingVertexSelect
= 0;
885 clip
.TriangleFanProvokingVertexSelect
= 1;
887 clip
.MinimumPointWidth
= 0.125;
888 clip
.MaximumPointWidth
= 255.875;
889 clip
.MaximumVPIndex
= (vp_info
? vp_info
->viewportCount
: 1) - 1;
892 clip
.FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
];
893 clip
.CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
];
894 clip
.ViewportZClipTestEnable
= !pipeline
->depth_clamp_enable
;
895 const struct brw_vue_prog_data
*last
=
896 anv_pipeline_get_last_vue_prog_data(pipeline
);
898 clip
.UserClipDistanceClipTestEnableBitmask
= last
->clip_distance_mask
;
899 clip
.UserClipDistanceCullTestEnableBitmask
= last
->cull_distance_mask
;
902 clip
.NonPerspectiveBarycentricEnable
= wm_prog_data
?
903 (wm_prog_data
->barycentric_interp_modes
& 0x38) != 0 : 0;
909 emit_3dstate_streamout(struct anv_pipeline
*pipeline
,
910 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
912 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_STREAMOUT
), so
) {
913 so
.RenderingDisable
= rs_info
->rasterizerDiscardEnable
;
917 static inline uint32_t
918 get_sampler_count(const struct anv_shader_bin
*bin
)
920 return DIV_ROUND_UP(bin
->bind_map
.sampler_count
, 4);
923 static inline uint32_t
924 get_binding_table_entry_count(const struct anv_shader_bin
*bin
)
926 return DIV_ROUND_UP(bin
->bind_map
.surface_count
, 32);
929 static inline struct anv_address
930 get_scratch_address(struct anv_pipeline
*pipeline
,
931 gl_shader_stage stage
,
932 const struct anv_shader_bin
*bin
)
934 return (struct anv_address
) {
935 .bo
= anv_scratch_pool_alloc(pipeline
->device
,
936 &pipeline
->device
->scratch_pool
,
937 stage
, bin
->prog_data
->total_scratch
),
942 static inline uint32_t
943 get_scratch_space(const struct anv_shader_bin
*bin
)
945 return ffs(bin
->prog_data
->total_scratch
/ 2048);
948 static inline uint32_t
949 get_urb_output_offset()
951 /* Skip the VUE header and position slots */
955 static inline uint32_t
956 get_urb_output_length(const struct anv_shader_bin
*bin
)
958 const struct brw_vue_prog_data
*prog_data
=
959 (const struct brw_vue_prog_data
*)bin
->prog_data
;
961 return (prog_data
->vue_map
.num_slots
+ 1) / 2 - get_urb_output_offset();
965 emit_3dstate_vs(struct anv_pipeline
*pipeline
)
967 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
968 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
969 const struct anv_shader_bin
*vs_bin
=
970 pipeline
->shaders
[MESA_SHADER_VERTEX
];
972 assert(anv_pipeline_has_stage(pipeline
, MESA_SHADER_VERTEX
));
974 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
), vs
) {
975 vs
.FunctionEnable
= true;
976 vs
.StatisticsEnable
= true;
977 vs
.KernelStartPointer
= vs_bin
->kernel
.offset
;
979 vs
.SIMD8DispatchEnable
=
980 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
983 assert(!vs_prog_data
->base
.base
.use_alt_mode
);
984 vs
.SingleVertexDispatch
= false;
985 vs
.VectorMaskEnable
= false;
986 vs
.SamplerCount
= get_sampler_count(vs_bin
);
987 vs
.BindingTableEntryCount
= get_binding_table_entry_count(vs_bin
);
988 vs
.FloatingPointMode
= IEEE754
;
989 vs
.IllegalOpcodeExceptionEnable
= false;
990 vs
.SoftwareExceptionEnable
= false;
991 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
992 vs
.VertexCacheDisable
= false;
994 vs
.VertexURBEntryReadLength
= vs_prog_data
->base
.urb_read_length
;
995 vs
.VertexURBEntryReadOffset
= 0;
996 vs
.DispatchGRFStartRegisterForURBData
=
997 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1000 vs
.VertexURBEntryOutputReadOffset
= get_urb_output_offset();
1001 vs
.VertexURBEntryOutputLength
= get_urb_output_length(vs_bin
);
1003 vs
.UserClipDistanceClipTestEnableBitmask
=
1004 vs_prog_data
->base
.clip_distance_mask
;
1005 vs
.UserClipDistanceCullTestEnableBitmask
=
1006 vs_prog_data
->base
.cull_distance_mask
;
1009 vs
.PerThreadScratchSpace
= get_scratch_space(vs_bin
);
1010 vs
.ScratchSpaceBasePointer
=
1011 get_scratch_address(pipeline
, MESA_SHADER_VERTEX
, vs_bin
);
1016 emit_3dstate_hs_te_ds(struct anv_pipeline
*pipeline
)
1018 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
)) {
1019 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_HS
), hs
);
1020 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_TE
), te
);
1021 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_DS
), ds
);
1025 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1026 const struct anv_shader_bin
*tcs_bin
=
1027 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1028 const struct anv_shader_bin
*tes_bin
=
1029 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1031 const struct brw_tcs_prog_data
*tcs_prog_data
= get_tcs_prog_data(pipeline
);
1032 const struct brw_tes_prog_data
*tes_prog_data
= get_tes_prog_data(pipeline
);
1034 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_HS
), hs
) {
1035 hs
.FunctionEnable
= true;
1036 hs
.StatisticsEnable
= true;
1037 hs
.KernelStartPointer
= tcs_bin
->kernel
.offset
;
1039 hs
.SamplerCount
= get_sampler_count(tcs_bin
);
1040 hs
.BindingTableEntryCount
= get_binding_table_entry_count(tcs_bin
);
1041 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
1042 hs
.IncludeVertexHandles
= true;
1043 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
1045 hs
.VertexURBEntryReadLength
= 0;
1046 hs
.VertexURBEntryReadOffset
= 0;
1047 hs
.DispatchGRFStartRegisterForURBData
=
1048 tcs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1050 hs
.PerThreadScratchSpace
= get_scratch_space(tcs_bin
);
1051 hs
.ScratchSpaceBasePointer
=
1052 get_scratch_address(pipeline
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
1055 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_TE
), te
) {
1056 te
.Partitioning
= tes_prog_data
->partitioning
;
1057 te
.OutputTopology
= tes_prog_data
->output_topology
;
1058 te
.TEDomain
= tes_prog_data
->domain
;
1060 te
.MaximumTessellationFactorOdd
= 63.0;
1061 te
.MaximumTessellationFactorNotOdd
= 64.0;
1064 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_DS
), ds
) {
1065 ds
.FunctionEnable
= true;
1066 ds
.StatisticsEnable
= true;
1067 ds
.KernelStartPointer
= tes_bin
->kernel
.offset
;
1069 ds
.SamplerCount
= get_sampler_count(tes_bin
);
1070 ds
.BindingTableEntryCount
= get_binding_table_entry_count(tes_bin
);
1071 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
1073 ds
.ComputeWCoordinateEnable
=
1074 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
1076 ds
.PatchURBEntryReadLength
= tes_prog_data
->base
.urb_read_length
;
1077 ds
.PatchURBEntryReadOffset
= 0;
1078 ds
.DispatchGRFStartRegisterForURBData
=
1079 tes_prog_data
->base
.base
.dispatch_grf_start_reg
;
1082 ds
.VertexURBEntryOutputReadOffset
= 1;
1083 ds
.VertexURBEntryOutputLength
=
1084 (tes_prog_data
->base
.vue_map
.num_slots
+ 1) / 2 - 1;
1087 tes_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
?
1088 DISPATCH_MODE_SIMD8_SINGLE_PATCH
:
1089 DISPATCH_MODE_SIMD4X2
;
1091 ds
.UserClipDistanceClipTestEnableBitmask
=
1092 tes_prog_data
->base
.clip_distance_mask
;
1093 ds
.UserClipDistanceCullTestEnableBitmask
=
1094 tes_prog_data
->base
.cull_distance_mask
;
1097 ds
.PerThreadScratchSpace
= get_scratch_space(tes_bin
);
1098 ds
.ScratchSpaceBasePointer
=
1099 get_scratch_address(pipeline
, MESA_SHADER_TESS_EVAL
, tes_bin
);
1104 emit_3dstate_gs(struct anv_pipeline
*pipeline
)
1106 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1107 const struct anv_shader_bin
*gs_bin
=
1108 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1110 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
)) {
1111 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), gs
);
1115 const struct brw_gs_prog_data
*gs_prog_data
= get_gs_prog_data(pipeline
);
1117 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), gs
) {
1118 gs
.FunctionEnable
= true;
1119 gs
.StatisticsEnable
= true;
1120 gs
.KernelStartPointer
= gs_bin
->kernel
.offset
;
1121 gs
.DispatchMode
= gs_prog_data
->base
.dispatch_mode
;
1123 gs
.SingleProgramFlow
= false;
1124 gs
.VectorMaskEnable
= false;
1125 gs
.SamplerCount
= get_sampler_count(gs_bin
);
1126 gs
.BindingTableEntryCount
= get_binding_table_entry_count(gs_bin
);
1127 gs
.IncludeVertexHandles
= gs_prog_data
->base
.include_vue_handles
;
1128 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
1131 /* Broadwell is weird. It needs us to divide by 2. */
1132 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
/ 2 - 1;
1134 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
1137 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
1138 gs
.OutputTopology
= gs_prog_data
->output_topology
;
1139 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
1140 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
1141 gs
.ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
;
1142 gs
.InstanceControl
= MAX2(gs_prog_data
->invocations
, 1) - 1;
1143 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1144 gs
.ReorderMode
= TRAILING
;
1146 gs
.ReorderEnable
= true;
1150 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
1151 gs
.StaticOutput
= gs_prog_data
->static_vertex_count
>= 0;
1152 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
>= 0 ?
1153 gs_prog_data
->static_vertex_count
: 0;
1156 gs
.VertexURBEntryReadOffset
= 0;
1157 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
1158 gs
.DispatchGRFStartRegisterForURBData
=
1159 gs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1162 gs
.VertexURBEntryOutputReadOffset
= get_urb_output_offset();
1163 gs
.VertexURBEntryOutputLength
= get_urb_output_length(gs_bin
);
1165 gs
.UserClipDistanceClipTestEnableBitmask
=
1166 gs_prog_data
->base
.clip_distance_mask
;
1167 gs
.UserClipDistanceCullTestEnableBitmask
=
1168 gs_prog_data
->base
.cull_distance_mask
;
1171 gs
.PerThreadScratchSpace
= get_scratch_space(gs_bin
);
1172 gs
.ScratchSpaceBasePointer
=
1173 get_scratch_address(pipeline
, MESA_SHADER_GEOMETRY
, gs_bin
);
1178 has_color_buffer_write_enabled(const struct anv_pipeline
*pipeline
)
1180 const struct anv_shader_bin
*shader_bin
=
1181 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1185 const struct anv_pipeline_bind_map
*bind_map
= &shader_bin
->bind_map
;
1186 for (int i
= 0; i
< bind_map
->surface_count
; i
++) {
1187 if (bind_map
->surface_to_descriptor
[i
].set
!=
1188 ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
)
1190 if (bind_map
->surface_to_descriptor
[i
].index
!= UINT8_MAX
)
1198 emit_3dstate_wm(struct anv_pipeline
*pipeline
, struct anv_subpass
*subpass
,
1199 const VkPipelineMultisampleStateCreateInfo
*multisample
)
1201 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1203 MAYBE_UNUSED
uint32_t samples
=
1204 multisample
? multisample
->rasterizationSamples
: 1;
1206 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_WM
), wm
) {
1207 wm
.StatisticsEnable
= true;
1208 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1209 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1210 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1212 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1213 if (wm_prog_data
->early_fragment_tests
) {
1214 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1215 } else if (wm_prog_data
->has_side_effects
) {
1216 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1218 wm
.EarlyDepthStencilControl
= EDSC_NORMAL
;
1221 wm
.BarycentricInterpolationMode
=
1222 wm_prog_data
->barycentric_interp_modes
;
1225 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1226 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1227 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1228 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1230 /* If the subpass has a depth or stencil self-dependency, then we
1231 * need to force the hardware to do the depth/stencil write *after*
1232 * fragment shader execution. Otherwise, the writes may hit memory
1233 * before we get around to fetching from the input attachment and we
1234 * may get the depth or stencil value from the current draw rather
1235 * than the previous one.
1237 wm
.PixelShaderKillsPixel
= subpass
->has_ds_self_dep
||
1238 wm_prog_data
->uses_kill
;
1240 if (wm
.PixelShaderComputedDepthMode
!= PSCDEPTH_OFF
||
1241 wm_prog_data
->has_side_effects
||
1242 wm
.PixelShaderKillsPixel
||
1243 has_color_buffer_write_enabled(pipeline
))
1244 wm
.ThreadDispatchEnable
= true;
1247 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1248 if (wm_prog_data
->persample_dispatch
) {
1249 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1251 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1254 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1255 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1263 is_dual_src_blend_factor(VkBlendFactor factor
)
1265 return factor
== VK_BLEND_FACTOR_SRC1_COLOR
||
1266 factor
== VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
||
1267 factor
== VK_BLEND_FACTOR_SRC1_ALPHA
||
1268 factor
== VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
;
1272 emit_3dstate_ps(struct anv_pipeline
*pipeline
,
1273 const VkPipelineColorBlendStateCreateInfo
*blend
)
1275 MAYBE_UNUSED
const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1276 const struct anv_shader_bin
*fs_bin
=
1277 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1279 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1280 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
), ps
) {
1282 /* Even if no fragments are ever dispatched, gen7 hardware hangs if
1283 * we don't at least set the maximum number of threads.
1285 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1291 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1294 /* The hardware wedges if you have this bit set but don't turn on any dual
1295 * source blend factors.
1297 bool dual_src_blend
= false;
1298 if (wm_prog_data
->dual_src_blend
) {
1299 for (uint32_t i
= 0; i
< blend
->attachmentCount
; i
++) {
1300 const VkPipelineColorBlendAttachmentState
*bstate
=
1301 &blend
->pAttachments
[i
];
1303 if (bstate
->blendEnable
&&
1304 (is_dual_src_blend_factor(bstate
->srcColorBlendFactor
) ||
1305 is_dual_src_blend_factor(bstate
->dstColorBlendFactor
) ||
1306 is_dual_src_blend_factor(bstate
->srcAlphaBlendFactor
) ||
1307 is_dual_src_blend_factor(bstate
->dstAlphaBlendFactor
))) {
1308 dual_src_blend
= true;
1315 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
), ps
) {
1316 ps
.KernelStartPointer0
= fs_bin
->kernel
.offset
;
1317 ps
.KernelStartPointer1
= 0;
1318 ps
.KernelStartPointer2
= fs_bin
->kernel
.offset
+
1319 wm_prog_data
->prog_offset_2
;
1320 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1321 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1322 ps
._32PixelDispatchEnable
= false;
1324 ps
.SingleProgramFlow
= false;
1325 ps
.VectorMaskEnable
= true;
1326 ps
.SamplerCount
= get_sampler_count(fs_bin
);
1327 ps
.BindingTableEntryCount
= get_binding_table_entry_count(fs_bin
);
1328 ps
.PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0;
1329 ps
.PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
1330 POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
1332 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
1333 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1334 ps
.DualSourceBlendEnable
= dual_src_blend
;
1338 /* Haswell requires the sample mask to be set in this packet as well
1339 * as in 3DSTATE_SAMPLE_MASK; the values should match.
1341 ps
.SampleMask
= 0xff;
1345 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
1347 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
1349 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1352 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
1353 wm_prog_data
->base
.dispatch_grf_start_reg
;
1354 ps
.DispatchGRFStartRegisterForConstantSetupData1
= 0;
1355 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
1356 wm_prog_data
->dispatch_grf_start_reg_2
;
1358 ps
.PerThreadScratchSpace
= get_scratch_space(fs_bin
);
1359 ps
.ScratchSpaceBasePointer
=
1360 get_scratch_address(pipeline
, MESA_SHADER_FRAGMENT
, fs_bin
);
1366 emit_3dstate_ps_extra(struct anv_pipeline
*pipeline
,
1367 struct anv_subpass
*subpass
)
1369 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1371 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1372 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_EXTRA
), ps
);
1376 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_EXTRA
), ps
) {
1377 ps
.PixelShaderValid
= true;
1378 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
1379 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1380 ps
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
1381 ps
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1382 ps
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1383 ps
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1385 /* If the subpass has a depth or stencil self-dependency, then we need
1386 * to force the hardware to do the depth/stencil write *after* fragment
1387 * shader execution. Otherwise, the writes may hit memory before we get
1388 * around to fetching from the input attachment and we may get the depth
1389 * or stencil value from the current draw rather than the previous one.
1391 ps
.PixelShaderKillsPixel
= subpass
->has_ds_self_dep
||
1392 wm_prog_data
->uses_kill
;
1394 /* The stricter cross-primitive coherency guarantees that the hardware
1395 * gives us with the "Accesses UAV" bit set for at least one shader stage
1396 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command are
1397 * redundant within the current image, atomic counter and SSBO GL APIs,
1398 * which all have very loose ordering and coherency requirements and
1399 * generally rely on the application to insert explicit barriers when a
1400 * shader invocation is expected to see the memory writes performed by the
1401 * invocations of some previous primitive. Regardless of the value of
1402 * "UAV coherency required", the "Accesses UAV" bits will implicitly cause
1403 * an in most cases useless DC flush when the lowermost stage with the bit
1404 * set finishes execution.
1406 * It would be nice to disable it, but in some cases we can't because on
1407 * Gen8+ it also has an influence on rasterization via the PS UAV-only
1408 * signal (which could be set independently from the coherency mechanism
1409 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
1410 * determine whether the hardware skips execution of the fragment shader
1411 * or not via the ThreadDispatchEnable signal. However if we know that
1412 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
1413 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
1414 * difference so we may just disable it here.
1416 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
1417 * take into account KillPixels when no depth or stencil writes are
1418 * enabled. In order for occlusion queries to work correctly with no
1419 * attachments, we need to force-enable here.
1421 if ((wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
) &&
1422 !has_color_buffer_write_enabled(pipeline
))
1423 ps
.PixelShaderHasUAV
= true;
1426 ps
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
1427 ps
.InputCoverageMaskState
= wm_prog_data
->uses_sample_mask
?
1428 ICMS_INNER_CONSERVATIVE
: ICMS_NONE
;
1430 ps
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1436 emit_3dstate_vf_topology(struct anv_pipeline
*pipeline
)
1438 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_TOPOLOGY
), vft
) {
1439 vft
.PrimitiveTopologyType
= pipeline
->topology
;
1445 genX(graphics_pipeline_create
)(
1447 struct anv_pipeline_cache
* cache
,
1448 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
1449 const VkAllocationCallbacks
* pAllocator
,
1450 VkPipeline
* pPipeline
)
1452 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1453 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
1454 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1455 struct anv_pipeline
*pipeline
;
1458 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1460 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1461 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1462 if (pipeline
== NULL
)
1463 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1465 result
= anv_pipeline_init(pipeline
, device
, cache
,
1466 pCreateInfo
, pAllocator
);
1467 if (result
!= VK_SUCCESS
) {
1468 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
1472 assert(pCreateInfo
->pVertexInputState
);
1473 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
);
1474 assert(pCreateInfo
->pRasterizationState
);
1475 emit_rs_state(pipeline
, pCreateInfo
->pRasterizationState
,
1476 pCreateInfo
->pMultisampleState
, pass
, subpass
);
1477 emit_ms_state(pipeline
, pCreateInfo
->pMultisampleState
);
1478 emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
, pass
, subpass
);
1479 emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
,
1480 pCreateInfo
->pMultisampleState
);
1482 emit_urb_setup(pipeline
);
1484 emit_3dstate_clip(pipeline
, pCreateInfo
->pViewportState
,
1485 pCreateInfo
->pRasterizationState
);
1486 emit_3dstate_streamout(pipeline
, pCreateInfo
->pRasterizationState
);
1489 /* From gen7_vs_state.c */
1492 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
1493 * Geometry > Geometry Shader > State:
1495 * "Note: Because of corruption in IVB:GT2, software needs to flush the
1496 * whole fixed function pipeline when the GS enable changes value in
1499 * The hardware architects have clarified that in this context "flush the
1500 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
1503 if (!brw
->is_haswell
&& !brw
->is_baytrail
)
1504 gen7_emit_vs_workaround_flush(brw
);
1507 emit_3dstate_vs(pipeline
);
1508 emit_3dstate_hs_te_ds(pipeline
);
1509 emit_3dstate_gs(pipeline
);
1510 emit_3dstate_sbe(pipeline
);
1511 emit_3dstate_wm(pipeline
, subpass
, pCreateInfo
->pMultisampleState
);
1512 emit_3dstate_ps(pipeline
, pCreateInfo
->pColorBlendState
);
1514 emit_3dstate_ps_extra(pipeline
, subpass
);
1515 emit_3dstate_vf_topology(pipeline
);
1518 *pPipeline
= anv_pipeline_to_handle(pipeline
);
1524 compute_pipeline_create(
1526 struct anv_pipeline_cache
* cache
,
1527 const VkComputePipelineCreateInfo
* pCreateInfo
,
1528 const VkAllocationCallbacks
* pAllocator
,
1529 VkPipeline
* pPipeline
)
1531 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1532 const struct anv_physical_device
*physical_device
=
1533 &device
->instance
->physicalDevice
;
1534 const struct gen_device_info
*devinfo
= &physical_device
->info
;
1535 struct anv_pipeline
*pipeline
;
1538 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
);
1540 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1541 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1542 if (pipeline
== NULL
)
1543 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1545 pipeline
->device
= device
;
1546 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1548 pipeline
->blend_state
.map
= NULL
;
1550 result
= anv_reloc_list_init(&pipeline
->batch_relocs
,
1551 pAllocator
? pAllocator
: &device
->alloc
);
1552 if (result
!= VK_SUCCESS
) {
1553 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
1556 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1557 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1558 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1560 /* When we free the pipeline, we detect stages based on the NULL status
1561 * of various prog_data pointers. Make them NULL by default.
1563 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1565 pipeline
->active_stages
= 0;
1567 pipeline
->needs_data_cache
= false;
1569 assert(pCreateInfo
->stage
.stage
== VK_SHADER_STAGE_COMPUTE_BIT
);
1570 ANV_FROM_HANDLE(anv_shader_module
, module
, pCreateInfo
->stage
.module
);
1571 result
= anv_pipeline_compile_cs(pipeline
, cache
, pCreateInfo
, module
,
1572 pCreateInfo
->stage
.pName
,
1573 pCreateInfo
->stage
.pSpecializationInfo
);
1574 if (result
!= VK_SUCCESS
) {
1575 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
1579 const struct brw_cs_prog_data
*cs_prog_data
= get_cs_prog_data(pipeline
);
1581 anv_pipeline_setup_l3_config(pipeline
, cs_prog_data
->base
.total_shared
> 0);
1583 uint32_t group_size
= cs_prog_data
->local_size
[0] *
1584 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
1585 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
1588 pipeline
->cs_right_mask
= ~0u >> (32 - remainder
);
1590 pipeline
->cs_right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
1592 const uint32_t vfe_curbe_allocation
=
1593 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
1594 cs_prog_data
->push
.cross_thread
.regs
, 2);
1596 const uint32_t subslices
= MAX2(physical_device
->subslice_total
, 1);
1598 const struct anv_shader_bin
*cs_bin
=
1599 pipeline
->shaders
[MESA_SHADER_COMPUTE
];
1601 anv_batch_emit(&pipeline
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
1605 vfe
.GPGPUMode
= true;
1607 vfe
.MaximumNumberofThreads
=
1608 devinfo
->max_cs_threads
* subslices
- 1;
1609 vfe
.NumberofURBEntries
= GEN_GEN
<= 7 ? 0 : 2;
1610 vfe
.ResetGatewayTimer
= true;
1612 vfe
.BypassGatewayControl
= true;
1614 vfe
.URBEntryAllocationSize
= GEN_GEN
<= 7 ? 0 : 2;
1615 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
1617 vfe
.PerThreadScratchSpace
= get_scratch_space(cs_bin
);
1618 vfe
.ScratchSpaceBasePointer
=
1619 get_scratch_address(pipeline
, MESA_SHADER_COMPUTE
, cs_bin
);
1622 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1623 .KernelStartPointer
= cs_bin
->kernel
.offset
,
1625 .SamplerCount
= get_sampler_count(cs_bin
),
1626 .BindingTableEntryCount
= get_binding_table_entry_count(cs_bin
),
1627 .BarrierEnable
= cs_prog_data
->uses_barrier
,
1628 .SharedLocalMemorySize
=
1629 encode_slm_size(GEN_GEN
, cs_prog_data
->base
.total_shared
),
1632 .ConstantURBEntryReadOffset
= 0,
1634 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
1635 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1636 .CrossThreadConstantDataReadLength
=
1637 cs_prog_data
->push
.cross_thread
.regs
,
1640 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
1642 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
,
1643 pipeline
->interface_descriptor_data
,
1646 *pPipeline
= anv_pipeline_to_handle(pipeline
);
1651 VkResult
genX(CreateGraphicsPipelines
)(
1653 VkPipelineCache pipelineCache
,
1655 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
1656 const VkAllocationCallbacks
* pAllocator
,
1657 VkPipeline
* pPipelines
)
1659 ANV_FROM_HANDLE(anv_pipeline_cache
, pipeline_cache
, pipelineCache
);
1661 VkResult result
= VK_SUCCESS
;
1664 for (i
= 0; i
< count
; i
++) {
1665 result
= genX(graphics_pipeline_create
)(_device
,
1668 pAllocator
, &pPipelines
[i
]);
1670 /* Bail out on the first error as it is not obvious what error should be
1671 * report upon 2 different failures. */
1672 if (result
!= VK_SUCCESS
)
1676 for (; i
< count
; i
++)
1677 pPipelines
[i
] = VK_NULL_HANDLE
;
1682 VkResult
genX(CreateComputePipelines
)(
1684 VkPipelineCache pipelineCache
,
1686 const VkComputePipelineCreateInfo
* pCreateInfos
,
1687 const VkAllocationCallbacks
* pAllocator
,
1688 VkPipeline
* pPipelines
)
1690 ANV_FROM_HANDLE(anv_pipeline_cache
, pipeline_cache
, pipelineCache
);
1692 VkResult result
= VK_SUCCESS
;
1695 for (i
= 0; i
< count
; i
++) {
1696 result
= compute_pipeline_create(_device
, pipeline_cache
,
1698 pAllocator
, &pPipelines
[i
]);
1700 /* Bail out on the first error as it is not obvious what error should be
1701 * report upon 2 different failures. */
1702 if (result
!= VK_SUCCESS
)
1706 for (; i
< count
; i
++)
1707 pPipelines
[i
] = VK_NULL_HANDLE
;