2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "anv_private.h"
26 #include "genxml/gen_macros.h"
27 #include "genxml/genX_pack.h"
29 #include "common/gen_l3_config.h"
30 #include "common/gen_sample_positions.h"
31 #include "vk_format_info.h"
34 vertex_element_comp_control(enum isl_format format
, unsigned comp
)
38 case 0: bits
= isl_format_layouts
[format
].channels
.r
.bits
; break;
39 case 1: bits
= isl_format_layouts
[format
].channels
.g
.bits
; break;
40 case 2: bits
= isl_format_layouts
[format
].channels
.b
.bits
; break;
41 case 3: bits
= isl_format_layouts
[format
].channels
.a
.bits
; break;
42 default: unreachable("Invalid component");
46 return VFCOMP_STORE_SRC
;
47 } else if (comp
< 3) {
48 return VFCOMP_STORE_0
;
49 } else if (isl_format_layouts
[format
].channels
.r
.type
== ISL_UINT
||
50 isl_format_layouts
[format
].channels
.r
.type
== ISL_SINT
) {
52 return VFCOMP_STORE_1_INT
;
55 return VFCOMP_STORE_1_FP
;
60 emit_vertex_input(struct anv_pipeline
*pipeline
,
61 const VkPipelineVertexInputStateCreateInfo
*info
)
63 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
65 /* Pull inputs_read out of the VS prog data */
66 const uint64_t inputs_read
= vs_prog_data
->inputs_read
;
67 assert((inputs_read
& ((1 << VERT_ATTRIB_GENERIC0
) - 1)) == 0);
68 const uint32_t elements
= inputs_read
>> VERT_ATTRIB_GENERIC0
;
71 /* On BDW+, we only need to allocate space for base ids. Setting up
72 * the actual vertex and instance id is a separate packet.
74 const bool needs_svgs_elem
= vs_prog_data
->uses_basevertex
||
75 vs_prog_data
->uses_baseinstance
;
77 /* On Haswell and prior, vertex and instance id are created by using the
78 * ComponentControl fields, so we need an element for any of them.
80 const bool needs_svgs_elem
= vs_prog_data
->uses_vertexid
||
81 vs_prog_data
->uses_instanceid
||
82 vs_prog_data
->uses_basevertex
||
83 vs_prog_data
->uses_baseinstance
;
86 uint32_t elem_count
= __builtin_popcount(elements
) + needs_svgs_elem
;
92 const uint32_t num_dwords
= 1 + elem_count
* 2;
93 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
94 GENX(3DSTATE_VERTEX_ELEMENTS
));
95 memset(p
+ 1, 0, (num_dwords
- 1) * 4);
97 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
98 const VkVertexInputAttributeDescription
*desc
=
99 &info
->pVertexAttributeDescriptions
[i
];
100 enum isl_format format
= anv_get_isl_format(&pipeline
->device
->info
,
102 VK_IMAGE_ASPECT_COLOR_BIT
,
103 VK_IMAGE_TILING_LINEAR
);
105 assert(desc
->binding
< 32);
107 if ((elements
& (1 << desc
->location
)) == 0)
108 continue; /* Binding unused */
110 uint32_t slot
= __builtin_popcount(elements
& ((1 << desc
->location
) - 1));
112 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
113 .VertexBufferIndex
= desc
->binding
,
115 .SourceElementFormat
= format
,
116 .EdgeFlagEnable
= false,
117 .SourceElementOffset
= desc
->offset
,
118 .Component0Control
= vertex_element_comp_control(format
, 0),
119 .Component1Control
= vertex_element_comp_control(format
, 1),
120 .Component2Control
= vertex_element_comp_control(format
, 2),
121 .Component3Control
= vertex_element_comp_control(format
, 3),
123 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + slot
* 2], &element
);
126 /* On Broadwell and later, we have a separate VF_INSTANCING packet
127 * that controls instancing. On Haswell and prior, that's part of
128 * VERTEX_BUFFER_STATE which we emit later.
130 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
131 vfi
.InstancingEnable
= pipeline
->instancing_enable
[desc
->binding
];
132 vfi
.VertexElementIndex
= slot
;
133 /* Vulkan so far doesn't have an instance divisor, so
134 * this is always 1 (ignored if not instancing). */
135 vfi
.InstanceDataStepRate
= 1;
140 const uint32_t id_slot
= __builtin_popcount(elements
);
141 if (needs_svgs_elem
) {
142 /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
143 * "Within a VERTEX_ELEMENT_STATE structure, if a Component
144 * Control field is set to something other than VFCOMP_STORE_SRC,
145 * no higher-numbered Component Control fields may be set to
148 * This means, that if we have BaseInstance, we need BaseVertex as
149 * well. Just do all or nothing.
151 uint32_t base_ctrl
= (vs_prog_data
->uses_basevertex
||
152 vs_prog_data
->uses_baseinstance
) ?
153 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
155 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
156 .VertexBufferIndex
= 32, /* Reserved for this */
158 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
159 .Component0Control
= base_ctrl
,
160 .Component1Control
= base_ctrl
,
162 .Component2Control
= VFCOMP_STORE_0
,
163 .Component3Control
= VFCOMP_STORE_0
,
165 .Component2Control
= VFCOMP_STORE_VID
,
166 .Component3Control
= VFCOMP_STORE_IID
,
169 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + id_slot
* 2], &element
);
173 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
174 sgvs
.VertexIDEnable
= vs_prog_data
->uses_vertexid
;
175 sgvs
.VertexIDComponentNumber
= 2;
176 sgvs
.VertexIDElementOffset
= id_slot
;
177 sgvs
.InstanceIDEnable
= vs_prog_data
->uses_instanceid
;
178 sgvs
.InstanceIDComponentNumber
= 3;
179 sgvs
.InstanceIDElementOffset
= id_slot
;
185 genX(emit_urb_setup
)(struct anv_device
*device
, struct anv_batch
*batch
,
186 const struct gen_l3_config
*l3_config
,
187 VkShaderStageFlags active_stages
,
188 const unsigned entry_size
[4])
190 const struct gen_device_info
*devinfo
= &device
->info
;
192 const unsigned push_constant_kb
= devinfo
->gt
== 3 ? 32 : 16;
194 const unsigned push_constant_kb
= GEN_GEN
>= 8 ? 32 : 16;
197 const unsigned urb_size_kb
= gen_get_l3_config_urb_size(devinfo
, l3_config
);
201 gen_get_urb_config(devinfo
,
202 1024 * push_constant_kb
, 1024 * urb_size_kb
,
204 VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
,
205 active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
,
206 entry_size
, entries
, start
);
208 #if GEN_GEN == 7 && !GEN_IS_HASWELL
209 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
211 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
212 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
213 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
214 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
215 * needs to be sent before any combination of VS associated 3DSTATE."
217 anv_batch_emit(batch
, GEN7_PIPE_CONTROL
, pc
) {
218 pc
.DepthStallEnable
= true;
219 pc
.PostSyncOperation
= WriteImmediateData
;
220 pc
.Address
= (struct anv_address
) { &device
->workaround_bo
, 0 };
224 for (int i
= 0; i
<= MESA_SHADER_GEOMETRY
; i
++) {
225 anv_batch_emit(batch
, GENX(3DSTATE_URB_VS
), urb
) {
226 urb
._3DCommandSubOpcode
+= i
;
227 urb
.VSURBStartingAddress
= start
[i
];
228 urb
.VSURBEntryAllocationSize
= entry_size
[i
] - 1;
229 urb
.VSNumberofURBEntries
= entries
[i
];
235 emit_urb_setup(struct anv_pipeline
*pipeline
)
237 unsigned entry_size
[4];
238 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
239 const struct brw_vue_prog_data
*prog_data
=
240 !anv_pipeline_has_stage(pipeline
, i
) ? NULL
:
241 (const struct brw_vue_prog_data
*) pipeline
->shaders
[i
]->prog_data
;
243 entry_size
[i
] = prog_data
? prog_data
->urb_entry_size
: 1;
246 genX(emit_urb_setup
)(pipeline
->device
, &pipeline
->batch
,
247 pipeline
->urb
.l3_config
,
248 pipeline
->active_stages
, entry_size
);
252 emit_3dstate_sbe(struct anv_pipeline
*pipeline
)
254 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
255 const struct brw_gs_prog_data
*gs_prog_data
= get_gs_prog_data(pipeline
);
256 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
257 const struct brw_vue_map
*fs_input_map
;
259 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
260 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SBE
), sbe
);
262 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SBE_SWIZ
), sbe
);
268 fs_input_map
= &gs_prog_data
->base
.vue_map
;
270 fs_input_map
= &vs_prog_data
->base
.vue_map
;
272 struct GENX(3DSTATE_SBE
) sbe
= {
273 GENX(3DSTATE_SBE_header
),
274 .AttributeSwizzleEnable
= true,
275 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
,
276 .NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
,
277 .ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
,
281 for (unsigned i
= 0; i
< 32; i
++)
282 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
286 /* On Broadwell, they broke 3DSTATE_SBE into two packets */
287 struct GENX(3DSTATE_SBE_SWIZ
) swiz
= {
288 GENX(3DSTATE_SBE_SWIZ_header
),
294 int max_source_attr
= 0;
295 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
296 int input_index
= wm_prog_data
->urb_setup
[attr
];
301 if (attr
== VARYING_SLOT_PNTC
) {
302 sbe
.PointSpriteTextureCoordinateEnable
= 1 << input_index
;
306 const int slot
= fs_input_map
->varying_to_slot
[attr
];
308 if (input_index
>= 16)
312 /* This attribute does not exist in the VUE--that means that the
313 * vertex shader did not write to it. It could be that it's a
314 * regular varying read by the fragment shader but not written by
315 * the vertex shader or it's gl_PrimitiveID. In the first case the
316 * value is undefined, in the second it needs to be
319 swiz
.Attribute
[input_index
].ConstantSource
= PRIM_ID
;
320 swiz
.Attribute
[input_index
].ComponentOverrideX
= true;
321 swiz
.Attribute
[input_index
].ComponentOverrideY
= true;
322 swiz
.Attribute
[input_index
].ComponentOverrideZ
= true;
323 swiz
.Attribute
[input_index
].ComponentOverrideW
= true;
326 const int source_attr
= slot
- 2;
327 max_source_attr
= MAX2(max_source_attr
, source_attr
);
328 /* We have to subtract two slots to accout for the URB entry output
329 * read offset in the VS and GS stages.
331 swiz
.Attribute
[input_index
].SourceAttribute
= source_attr
;
335 sbe
.VertexURBEntryReadOffset
= 1; /* Skip the VUE header and position slots */
336 sbe
.VertexURBEntryReadLength
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
338 uint32_t *dw
= anv_batch_emit_dwords(&pipeline
->batch
,
339 GENX(3DSTATE_SBE_length
));
340 GENX(3DSTATE_SBE_pack
)(&pipeline
->batch
, dw
, &sbe
);
343 dw
= anv_batch_emit_dwords(&pipeline
->batch
, GENX(3DSTATE_SBE_SWIZ_length
));
344 GENX(3DSTATE_SBE_SWIZ_pack
)(&pipeline
->batch
, dw
, &swiz
);
348 static const uint32_t vk_to_gen_cullmode
[] = {
349 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
350 [VK_CULL_MODE_FRONT_BIT
] = CULLMODE_FRONT
,
351 [VK_CULL_MODE_BACK_BIT
] = CULLMODE_BACK
,
352 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
355 static const uint32_t vk_to_gen_fillmode
[] = {
356 [VK_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
357 [VK_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
358 [VK_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
361 static const uint32_t vk_to_gen_front_face
[] = {
362 [VK_FRONT_FACE_COUNTER_CLOCKWISE
] = 1,
363 [VK_FRONT_FACE_CLOCKWISE
] = 0
367 emit_rs_state(struct anv_pipeline
*pipeline
,
368 const VkPipelineRasterizationStateCreateInfo
*rs_info
,
369 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
370 const struct anv_render_pass
*pass
,
371 const struct anv_subpass
*subpass
)
373 struct GENX(3DSTATE_SF
) sf
= {
374 GENX(3DSTATE_SF_header
),
377 sf
.ViewportTransformEnable
= true;
378 sf
.StatisticsEnable
= true;
379 sf
.TriangleStripListProvokingVertexSelect
= 0;
380 sf
.LineStripListProvokingVertexSelect
= 0;
381 sf
.TriangleFanProvokingVertexSelect
= 1;
382 sf
.PointWidthSource
= Vertex
;
386 struct GENX(3DSTATE_RASTER
) raster
= {
387 GENX(3DSTATE_RASTER_header
),
393 /* For details on 3DSTATE_RASTER multisample state, see the BSpec table
394 * "Multisample Modes State".
397 raster
.DXMultisampleRasterizationEnable
= true;
398 raster
.ForcedSampleCount
= FSC_NUMRASTSAMPLES_0
;
399 raster
.ForceMultisampling
= false;
401 raster
.MultisampleRasterizationMode
=
402 (ms_info
&& ms_info
->rasterizationSamples
> 1) ?
403 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
406 raster
.FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
];
407 raster
.CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
];
408 raster
.FrontFaceFillMode
= vk_to_gen_fillmode
[rs_info
->polygonMode
];
409 raster
.BackFaceFillMode
= vk_to_gen_fillmode
[rs_info
->polygonMode
];
410 raster
.ScissorRectangleEnable
= true;
413 /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
414 raster
.ViewportZFarClipTestEnable
= !pipeline
->depth_clamp_enable
;
415 raster
.ViewportZNearClipTestEnable
= !pipeline
->depth_clamp_enable
;
417 raster
.ViewportZClipTestEnable
= !pipeline
->depth_clamp_enable
;
420 raster
.GlobalDepthOffsetEnableSolid
= rs_info
->depthBiasEnable
;
421 raster
.GlobalDepthOffsetEnableWireframe
= rs_info
->depthBiasEnable
;
422 raster
.GlobalDepthOffsetEnablePoint
= rs_info
->depthBiasEnable
;
425 /* Gen7 requires that we provide the depth format in 3DSTATE_SF so that it
426 * can get the depth offsets correct.
428 if (subpass
->depth_stencil_attachment
< pass
->attachment_count
) {
430 pass
->attachments
[subpass
->depth_stencil_attachment
].format
;
431 assert(vk_format_is_depth_or_stencil(vk_format
));
432 if (vk_format_aspects(vk_format
) & VK_IMAGE_ASPECT_DEPTH_BIT
) {
433 enum isl_format isl_format
=
434 anv_get_isl_format(&pipeline
->device
->info
, vk_format
,
435 VK_IMAGE_ASPECT_DEPTH_BIT
,
436 VK_IMAGE_TILING_OPTIMAL
);
437 sf
.DepthBufferSurfaceFormat
=
438 isl_format_get_depth_format(isl_format
, false);
444 GENX(3DSTATE_SF_pack
)(NULL
, pipeline
->gen8
.sf
, &sf
);
445 GENX(3DSTATE_RASTER_pack
)(NULL
, pipeline
->gen8
.raster
, &raster
);
448 GENX(3DSTATE_SF_pack
)(NULL
, &pipeline
->gen7
.sf
, &sf
);
453 emit_ms_state(struct anv_pipeline
*pipeline
,
454 const VkPipelineMultisampleStateCreateInfo
*info
)
456 uint32_t samples
= 1;
457 uint32_t log2_samples
= 0;
459 /* From the Vulkan 1.0 spec:
460 * If pSampleMask is NULL, it is treated as if the mask has all bits
461 * enabled, i.e. no coverage is removed from fragments.
463 * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
466 uint32_t sample_mask
= 0xffff;
468 uint32_t sample_mask
= 0xff;
472 samples
= info
->rasterizationSamples
;
473 log2_samples
= __builtin_ffs(samples
) - 1;
476 if (info
&& info
->pSampleMask
)
477 sample_mask
&= info
->pSampleMask
[0];
479 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
480 ms
.NumberofMultisamples
= log2_samples
;
483 /* The PRM says that this bit is valid only for DX9:
485 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
486 * should not have any effect by setting or not setting this bit.
488 ms
.PixelPositionOffsetEnable
= false;
489 ms
.PixelLocation
= CENTER
;
491 ms
.PixelLocation
= PIXLOC_CENTER
;
495 GEN_SAMPLE_POS_1X(ms
.Sample
);
498 GEN_SAMPLE_POS_2X(ms
.Sample
);
501 GEN_SAMPLE_POS_4X(ms
.Sample
);
504 GEN_SAMPLE_POS_8X(ms
.Sample
);
512 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
513 sm
.SampleMask
= sample_mask
;
517 static const uint32_t vk_to_gen_logic_op
[] = {
518 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
519 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
520 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
521 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
522 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
523 [VK_LOGIC_OP_NO_OP
] = LOGICOP_NOOP
,
524 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
525 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
526 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
527 [VK_LOGIC_OP_EQUIVALENT
] = LOGICOP_EQUIV
,
528 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
529 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
530 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
531 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
532 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
533 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
536 static const uint32_t vk_to_gen_blend
[] = {
537 [VK_BLEND_FACTOR_ZERO
] = BLENDFACTOR_ZERO
,
538 [VK_BLEND_FACTOR_ONE
] = BLENDFACTOR_ONE
,
539 [VK_BLEND_FACTOR_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
540 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
541 [VK_BLEND_FACTOR_DST_COLOR
] = BLENDFACTOR_DST_COLOR
,
542 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
543 [VK_BLEND_FACTOR_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
544 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
545 [VK_BLEND_FACTOR_DST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
546 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
547 [VK_BLEND_FACTOR_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
548 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
]= BLENDFACTOR_INV_CONST_COLOR
,
549 [VK_BLEND_FACTOR_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
550 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
]= BLENDFACTOR_INV_CONST_ALPHA
,
551 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
552 [VK_BLEND_FACTOR_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
553 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
554 [VK_BLEND_FACTOR_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
555 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
558 static const uint32_t vk_to_gen_blend_op
[] = {
559 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
560 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
561 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
562 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
563 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
566 static const uint32_t vk_to_gen_compare_op
[] = {
567 [VK_COMPARE_OP_NEVER
] = PREFILTEROPNEVER
,
568 [VK_COMPARE_OP_LESS
] = PREFILTEROPLESS
,
569 [VK_COMPARE_OP_EQUAL
] = PREFILTEROPEQUAL
,
570 [VK_COMPARE_OP_LESS_OR_EQUAL
] = PREFILTEROPLEQUAL
,
571 [VK_COMPARE_OP_GREATER
] = PREFILTEROPGREATER
,
572 [VK_COMPARE_OP_NOT_EQUAL
] = PREFILTEROPNOTEQUAL
,
573 [VK_COMPARE_OP_GREATER_OR_EQUAL
] = PREFILTEROPGEQUAL
,
574 [VK_COMPARE_OP_ALWAYS
] = PREFILTEROPALWAYS
,
577 static const uint32_t vk_to_gen_stencil_op
[] = {
578 [VK_STENCIL_OP_KEEP
] = STENCILOP_KEEP
,
579 [VK_STENCIL_OP_ZERO
] = STENCILOP_ZERO
,
580 [VK_STENCIL_OP_REPLACE
] = STENCILOP_REPLACE
,
581 [VK_STENCIL_OP_INCREMENT_AND_CLAMP
] = STENCILOP_INCRSAT
,
582 [VK_STENCIL_OP_DECREMENT_AND_CLAMP
] = STENCILOP_DECRSAT
,
583 [VK_STENCIL_OP_INVERT
] = STENCILOP_INVERT
,
584 [VK_STENCIL_OP_INCREMENT_AND_WRAP
] = STENCILOP_INCR
,
585 [VK_STENCIL_OP_DECREMENT_AND_WRAP
] = STENCILOP_DECR
,
589 emit_ds_state(struct anv_pipeline
*pipeline
,
590 const VkPipelineDepthStencilStateCreateInfo
*info
,
591 const struct anv_render_pass
*pass
,
592 const struct anv_subpass
*subpass
)
595 # define depth_stencil_dw pipeline->gen7.depth_stencil_state
597 # define depth_stencil_dw pipeline->gen8.wm_depth_stencil
599 # define depth_stencil_dw pipeline->gen9.wm_depth_stencil
603 /* We're going to OR this together with the dynamic state. We need
604 * to make sure it's initialized to something useful.
606 memset(depth_stencil_dw
, 0, sizeof(depth_stencil_dw
));
610 /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
613 struct GENX(DEPTH_STENCIL_STATE
) depth_stencil
= {
615 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) depth_stencil
= {
617 .DepthTestEnable
= info
->depthTestEnable
,
618 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
619 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
620 .DoubleSidedStencilEnable
= true,
622 .StencilTestEnable
= info
->stencilTestEnable
,
623 .StencilBufferWriteEnable
= info
->stencilTestEnable
,
624 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.failOp
],
625 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.passOp
],
626 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.depthFailOp
],
627 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.compareOp
],
628 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.failOp
],
629 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.passOp
],
630 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
->back
.depthFailOp
],
631 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.compareOp
],
634 VkImageAspectFlags aspects
= 0;
635 if (subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
) {
636 VkFormat depth_stencil_format
=
637 pass
->attachments
[subpass
->depth_stencil_attachment
].format
;
638 aspects
= vk_format_aspects(depth_stencil_format
);
641 /* The Vulkan spec requires that if either depth or stencil is not present,
642 * the pipeline is to act as if the test silently passes.
644 if (!(aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
645 depth_stencil
.DepthBufferWriteEnable
= false;
646 depth_stencil
.DepthTestFunction
= PREFILTEROPALWAYS
;
649 if (!(aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
650 depth_stencil
.StencilBufferWriteEnable
= false;
651 depth_stencil
.StencilTestFunction
= PREFILTEROPALWAYS
;
652 depth_stencil
.BackfaceStencilTestFunction
= PREFILTEROPALWAYS
;
655 /* From the Broadwell PRM:
657 * "If Depth_Test_Enable = 1 AND Depth_Test_func = EQUAL, the
658 * Depth_Write_Enable must be set to 0."
660 if (info
->depthTestEnable
&& info
->depthCompareOp
== VK_COMPARE_OP_EQUAL
)
661 depth_stencil
.DepthBufferWriteEnable
= false;
664 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
666 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
671 emit_cb_state(struct anv_pipeline
*pipeline
,
672 const VkPipelineColorBlendStateCreateInfo
*info
,
673 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
675 struct anv_device
*device
= pipeline
->device
;
677 const uint32_t num_dwords
= GENX(BLEND_STATE_length
);
678 pipeline
->blend_state
=
679 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
681 struct GENX(BLEND_STATE
) blend_state
= {
683 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
684 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
686 /* Make sure it gets zeroed */
687 .Entry
= { { 0, }, },
691 /* Default everything to disabled */
692 for (uint32_t i
= 0; i
< 8; i
++) {
693 blend_state
.Entry
[i
].WriteDisableAlpha
= true;
694 blend_state
.Entry
[i
].WriteDisableRed
= true;
695 blend_state
.Entry
[i
].WriteDisableGreen
= true;
696 blend_state
.Entry
[i
].WriteDisableBlue
= true;
699 uint32_t surface_count
= 0;
700 struct anv_pipeline_bind_map
*map
;
701 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
702 map
= &pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->bind_map
;
703 surface_count
= map
->surface_count
;
706 bool has_writeable_rt
= false;
707 for (unsigned i
= 0; i
< surface_count
; i
++) {
708 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[i
];
710 /* All color attachments are at the beginning of the binding table */
711 if (binding
->set
!= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
)
714 /* We can have at most 8 attachments */
717 if (binding
->index
>= info
->attachmentCount
)
720 assert(binding
->binding
== 0);
721 const VkPipelineColorBlendAttachmentState
*a
=
722 &info
->pAttachments
[binding
->index
];
724 blend_state
.Entry
[i
] = (struct GENX(BLEND_STATE_ENTRY
)) {
726 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
727 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
729 .LogicOpEnable
= info
->logicOpEnable
,
730 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
731 .ColorBufferBlendEnable
= a
->blendEnable
,
732 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
733 .PreBlendColorClampEnable
= true,
734 .PostBlendColorClampEnable
= true,
735 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcColorBlendFactor
],
736 .DestinationBlendFactor
= vk_to_gen_blend
[a
->dstColorBlendFactor
],
737 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->colorBlendOp
],
738 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcAlphaBlendFactor
],
739 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->dstAlphaBlendFactor
],
740 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->alphaBlendOp
],
741 .WriteDisableAlpha
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_A_BIT
),
742 .WriteDisableRed
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_R_BIT
),
743 .WriteDisableGreen
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_G_BIT
),
744 .WriteDisableBlue
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_B_BIT
),
747 if (a
->srcColorBlendFactor
!= a
->srcAlphaBlendFactor
||
748 a
->dstColorBlendFactor
!= a
->dstAlphaBlendFactor
||
749 a
->colorBlendOp
!= a
->alphaBlendOp
) {
751 blend_state
.IndependentAlphaBlendEnable
= true;
753 blend_state
.Entry
[i
].IndependentAlphaBlendEnable
= true;
757 if (a
->colorWriteMask
!= 0)
758 has_writeable_rt
= true;
760 /* Our hardware applies the blend factor prior to the blend function
761 * regardless of what function is used. Technically, this means the
762 * hardware can do MORE than GL or Vulkan specify. However, it also
763 * means that, for MIN and MAX, we have to stomp the blend factor to
764 * ONE to make it a no-op.
766 if (a
->colorBlendOp
== VK_BLEND_OP_MIN
||
767 a
->colorBlendOp
== VK_BLEND_OP_MAX
) {
768 blend_state
.Entry
[i
].SourceBlendFactor
= BLENDFACTOR_ONE
;
769 blend_state
.Entry
[i
].DestinationBlendFactor
= BLENDFACTOR_ONE
;
771 if (a
->alphaBlendOp
== VK_BLEND_OP_MIN
||
772 a
->alphaBlendOp
== VK_BLEND_OP_MAX
) {
773 blend_state
.Entry
[i
].SourceAlphaBlendFactor
= BLENDFACTOR_ONE
;
774 blend_state
.Entry
[i
].DestinationAlphaBlendFactor
= BLENDFACTOR_ONE
;
779 struct GENX(BLEND_STATE_ENTRY
) *bs0
= &blend_state
.Entry
[0];
780 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_BLEND
), blend
) {
781 blend
.AlphaToCoverageEnable
= blend_state
.AlphaToCoverageEnable
;
782 blend
.HasWriteableRT
= has_writeable_rt
;
783 blend
.ColorBufferBlendEnable
= bs0
->ColorBufferBlendEnable
;
784 blend
.SourceAlphaBlendFactor
= bs0
->SourceAlphaBlendFactor
;
785 blend
.DestinationAlphaBlendFactor
= bs0
->DestinationAlphaBlendFactor
;
786 blend
.SourceBlendFactor
= bs0
->SourceBlendFactor
;
787 blend
.DestinationBlendFactor
= bs0
->DestinationBlendFactor
;
788 blend
.AlphaTestEnable
= false;
789 blend
.IndependentAlphaBlendEnable
=
790 blend_state
.IndependentAlphaBlendEnable
;
793 (void)has_writeable_rt
;
796 GENX(BLEND_STATE_pack
)(NULL
, pipeline
->blend_state
.map
, &blend_state
);
797 if (!device
->info
.has_llc
)
798 anv_state_clflush(pipeline
->blend_state
);
800 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), bsp
) {
801 bsp
.BlendStatePointer
= pipeline
->blend_state
.offset
;
803 bsp
.BlendStatePointerValid
= true;
809 * Get the brw_vue_prog_data for the last stage which outputs VUEs.
811 static inline struct brw_vue_prog_data
*
812 get_last_vue_prog_data(struct anv_pipeline
*pipeline
)
814 for (int s
= MESA_SHADER_GEOMETRY
; s
>= 0; s
--) {
815 if (pipeline
->shaders
[s
])
816 return (struct brw_vue_prog_data
*) pipeline
->shaders
[s
]->prog_data
;
822 emit_3dstate_clip(struct anv_pipeline
*pipeline
,
823 const VkPipelineViewportStateCreateInfo
*vp_info
,
824 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
826 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
828 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_CLIP
), clip
) {
829 clip
.ClipEnable
= true;
830 clip
.EarlyCullEnable
= true;
831 clip
.APIMode
= APIMODE_D3D
,
832 clip
.ViewportXYClipTestEnable
= true;
834 clip
.ClipMode
= CLIPMODE_NORMAL
;
836 clip
.TriangleStripListProvokingVertexSelect
= 0;
837 clip
.LineStripListProvokingVertexSelect
= 0;
838 clip
.TriangleFanProvokingVertexSelect
= 1;
840 clip
.MinimumPointWidth
= 0.125;
841 clip
.MaximumPointWidth
= 255.875;
842 clip
.MaximumVPIndex
= (vp_info
? vp_info
->viewportCount
: 1) - 1;
845 clip
.FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
];
846 clip
.CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
];
847 clip
.ViewportZClipTestEnable
= !pipeline
->depth_clamp_enable
;
848 const struct brw_vue_prog_data
*last
= get_last_vue_prog_data(pipeline
);
850 clip
.UserClipDistanceClipTestEnableBitmask
= last
->clip_distance_mask
;
851 clip
.UserClipDistanceCullTestEnableBitmask
= last
->cull_distance_mask
;
854 clip
.NonPerspectiveBarycentricEnable
= wm_prog_data
?
855 (wm_prog_data
->barycentric_interp_modes
& 0x38) != 0 : 0;
861 emit_3dstate_streamout(struct anv_pipeline
*pipeline
,
862 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
864 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_STREAMOUT
), so
) {
865 so
.RenderingDisable
= rs_info
->rasterizerDiscardEnable
;
869 static inline uint32_t
870 get_sampler_count(const struct anv_shader_bin
*bin
)
872 return DIV_ROUND_UP(bin
->bind_map
.sampler_count
, 4);
875 static inline uint32_t
876 get_binding_table_entry_count(const struct anv_shader_bin
*bin
)
878 return DIV_ROUND_UP(bin
->bind_map
.surface_count
, 32);
881 static inline struct anv_address
882 get_scratch_address(struct anv_pipeline
*pipeline
,
883 gl_shader_stage stage
,
884 const struct anv_shader_bin
*bin
)
886 return (struct anv_address
) {
887 .bo
= anv_scratch_pool_alloc(pipeline
->device
,
888 &pipeline
->device
->scratch_pool
,
889 stage
, bin
->prog_data
->total_scratch
),
894 static inline uint32_t
895 get_scratch_space(const struct anv_shader_bin
*bin
)
897 return ffs(bin
->prog_data
->total_scratch
/ 2048);
900 static inline uint32_t
901 get_urb_output_offset()
903 /* Skip the VUE header and position slots */
907 static inline uint32_t
908 get_urb_output_length(const struct anv_shader_bin
*bin
)
910 const struct brw_vue_prog_data
*prog_data
=
911 (const struct brw_vue_prog_data
*)bin
->prog_data
;
913 return (prog_data
->vue_map
.num_slots
+ 1) / 2 - get_urb_output_offset();
917 emit_3dstate_vs(struct anv_pipeline
*pipeline
)
919 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
920 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
921 const struct anv_shader_bin
*vs_bin
=
922 pipeline
->shaders
[MESA_SHADER_VERTEX
];
924 assert(anv_pipeline_has_stage(pipeline
, MESA_SHADER_VERTEX
));
926 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
), vs
) {
927 vs
.FunctionEnable
= true;
928 vs
.StatisticsEnable
= true;
929 vs
.KernelStartPointer
= vs_bin
->kernel
.offset
;
931 vs
.SIMD8DispatchEnable
=
932 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
935 assert(!vs_prog_data
->base
.base
.use_alt_mode
);
936 vs
.SingleVertexDispatch
= false;
937 vs
.VectorMaskEnable
= false;
938 vs
.SamplerCount
= get_sampler_count(vs_bin
);
939 vs
.BindingTableEntryCount
= get_binding_table_entry_count(vs_bin
);
940 vs
.FloatingPointMode
= IEEE754
;
941 vs
.IllegalOpcodeExceptionEnable
= false;
942 vs
.SoftwareExceptionEnable
= false;
943 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
944 vs
.VertexCacheDisable
= false;
946 vs
.VertexURBEntryReadLength
= vs_prog_data
->base
.urb_read_length
;
947 vs
.VertexURBEntryReadOffset
= 0;
948 vs
.DispatchGRFStartRegisterForURBData
=
949 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
952 vs
.VertexURBEntryOutputReadOffset
= get_urb_output_offset();
953 vs
.VertexURBEntryOutputLength
= get_urb_output_length(vs_bin
);
955 vs
.UserClipDistanceClipTestEnableBitmask
=
956 vs_prog_data
->base
.clip_distance_mask
;
957 vs
.UserClipDistanceCullTestEnableBitmask
=
958 vs_prog_data
->base
.cull_distance_mask
;
961 vs
.PerThreadScratchSpace
= get_scratch_space(vs_bin
);
962 vs
.ScratchSpaceBasePointer
=
963 get_scratch_address(pipeline
, MESA_SHADER_VERTEX
, vs_bin
);
968 emit_3dstate_gs(struct anv_pipeline
*pipeline
)
970 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
971 const struct anv_shader_bin
*gs_bin
=
972 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
974 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
)) {
975 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), gs
);
979 const struct brw_gs_prog_data
*gs_prog_data
= get_gs_prog_data(pipeline
);
981 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), gs
) {
982 gs
.FunctionEnable
= true;
983 gs
.StatisticsEnable
= true;
984 gs
.KernelStartPointer
= gs_bin
->kernel
.offset
;
985 gs
.DispatchMode
= gs_prog_data
->base
.dispatch_mode
;
987 gs
.SingleProgramFlow
= false;
988 gs
.VectorMaskEnable
= false;
989 gs
.SamplerCount
= get_sampler_count(gs_bin
);
990 gs
.BindingTableEntryCount
= get_binding_table_entry_count(gs_bin
);
991 gs
.IncludeVertexHandles
= gs_prog_data
->base
.include_vue_handles
;
992 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
995 /* Broadwell is weird. It needs us to divide by 2. */
996 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
/ 2 - 1;
998 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
1001 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
1002 gs
.OutputTopology
= gs_prog_data
->output_topology
;
1003 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
1004 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
1005 gs
.ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
;
1006 gs
.InstanceControl
= MAX2(gs_prog_data
->invocations
, 1) - 1;
1007 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1008 gs
.ReorderMode
= TRAILING
;
1010 gs
.ReorderEnable
= true;
1014 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
1015 gs
.StaticOutput
= gs_prog_data
->static_vertex_count
>= 0;
1016 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
>= 0 ?
1017 gs_prog_data
->static_vertex_count
: 0;
1020 gs
.VertexURBEntryReadOffset
= 0;
1021 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
1022 gs
.DispatchGRFStartRegisterForURBData
=
1023 gs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1026 gs
.VertexURBEntryOutputReadOffset
= get_urb_output_offset();
1027 gs
.VertexURBEntryOutputLength
= get_urb_output_length(gs_bin
);
1029 gs
.UserClipDistanceClipTestEnableBitmask
=
1030 gs_prog_data
->base
.clip_distance_mask
;
1031 gs
.UserClipDistanceCullTestEnableBitmask
=
1032 gs_prog_data
->base
.cull_distance_mask
;
1035 gs
.PerThreadScratchSpace
= get_scratch_space(gs_bin
);
1036 gs
.ScratchSpaceBasePointer
=
1037 get_scratch_address(pipeline
, MESA_SHADER_GEOMETRY
, gs_bin
);
1042 emit_3dstate_wm(struct anv_pipeline
*pipeline
, struct anv_subpass
*subpass
,
1043 const VkPipelineMultisampleStateCreateInfo
*multisample
)
1045 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1047 MAYBE_UNUSED
uint32_t samples
=
1048 multisample
? multisample
->rasterizationSamples
: 1;
1050 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_WM
), wm
) {
1051 wm
.StatisticsEnable
= true;
1052 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1053 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1054 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1056 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1057 if (wm_prog_data
->early_fragment_tests
) {
1058 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1059 } else if (wm_prog_data
->has_side_effects
) {
1060 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1062 wm
.EarlyDepthStencilControl
= EDSC_NORMAL
;
1065 wm
.BarycentricInterpolationMode
=
1066 wm_prog_data
->barycentric_interp_modes
;
1069 /* FIXME: This needs a lot more work, cf gen7 upload_wm_state(). */
1070 wm
.ThreadDispatchEnable
= true;
1072 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1073 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1074 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1075 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1077 /* If the subpass has a depth or stencil self-dependency, then we
1078 * need to force the hardware to do the depth/stencil write *after*
1079 * fragment shader execution. Otherwise, the writes may hit memory
1080 * before we get around to fetching from the input attachment and we
1081 * may get the depth or stencil value from the current draw rather
1082 * than the previous one.
1084 wm
.PixelShaderKillsPixel
= subpass
->has_ds_self_dep
||
1085 wm_prog_data
->uses_kill
;
1088 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1089 if (wm_prog_data
->persample_dispatch
) {
1090 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1092 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1095 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1096 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1104 is_dual_src_blend_factor(VkBlendFactor factor
)
1106 return factor
== VK_BLEND_FACTOR_SRC1_COLOR
||
1107 factor
== VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
||
1108 factor
== VK_BLEND_FACTOR_SRC1_ALPHA
||
1109 factor
== VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
;
1113 emit_3dstate_ps(struct anv_pipeline
*pipeline
,
1114 const VkPipelineColorBlendStateCreateInfo
*blend
)
1116 MAYBE_UNUSED
const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1117 const struct anv_shader_bin
*fs_bin
=
1118 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1120 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1121 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
), ps
) {
1123 /* Even if no fragments are ever dispatched, gen7 hardware hangs if
1124 * we don't at least set the maximum number of threads.
1126 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1132 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1135 /* The hardware wedges if you have this bit set but don't turn on any dual
1136 * source blend factors.
1138 bool dual_src_blend
= false;
1139 if (wm_prog_data
->dual_src_blend
) {
1140 for (uint32_t i
= 0; i
< blend
->attachmentCount
; i
++) {
1141 const VkPipelineColorBlendAttachmentState
*bstate
=
1142 &blend
->pAttachments
[i
];
1144 if (bstate
->blendEnable
&&
1145 (is_dual_src_blend_factor(bstate
->srcColorBlendFactor
) ||
1146 is_dual_src_blend_factor(bstate
->dstColorBlendFactor
) ||
1147 is_dual_src_blend_factor(bstate
->srcAlphaBlendFactor
) ||
1148 is_dual_src_blend_factor(bstate
->dstAlphaBlendFactor
))) {
1149 dual_src_blend
= true;
1156 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
), ps
) {
1157 ps
.KernelStartPointer0
= fs_bin
->kernel
.offset
;
1158 ps
.KernelStartPointer1
= 0;
1159 ps
.KernelStartPointer2
= fs_bin
->kernel
.offset
+
1160 wm_prog_data
->prog_offset_2
;
1161 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1162 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1163 ps
._32PixelDispatchEnable
= false;
1165 ps
.SingleProgramFlow
= false;
1166 ps
.VectorMaskEnable
= true;
1167 ps
.SamplerCount
= get_sampler_count(fs_bin
);
1168 ps
.BindingTableEntryCount
= get_binding_table_entry_count(fs_bin
);
1169 ps
.PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0;
1170 ps
.PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
1171 POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
1173 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
1174 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1175 ps
.DualSourceBlendEnable
= dual_src_blend
;
1179 /* Haswell requires the sample mask to be set in this packet as well
1180 * as in 3DSTATE_SAMPLE_MASK; the values should match.
1182 ps
.SampleMask
= 0xff;
1186 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
1188 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
1190 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1193 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
1194 wm_prog_data
->base
.dispatch_grf_start_reg
;
1195 ps
.DispatchGRFStartRegisterForConstantSetupData1
= 0;
1196 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
1197 wm_prog_data
->dispatch_grf_start_reg_2
;
1199 ps
.PerThreadScratchSpace
= get_scratch_space(fs_bin
);
1200 ps
.ScratchSpaceBasePointer
=
1201 get_scratch_address(pipeline
, MESA_SHADER_FRAGMENT
, fs_bin
);
1207 emit_3dstate_ps_extra(struct anv_pipeline
*pipeline
,
1208 struct anv_subpass
*subpass
)
1210 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1212 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1213 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_EXTRA
), ps
);
1217 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_EXTRA
), ps
) {
1218 ps
.PixelShaderValid
= true;
1219 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
1220 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1221 ps
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
1222 ps
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1223 ps
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1224 ps
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1226 /* If the subpass has a depth or stencil self-dependency, then we need
1227 * to force the hardware to do the depth/stencil write *after* fragment
1228 * shader execution. Otherwise, the writes may hit memory before we get
1229 * around to fetching from the input attachment and we may get the depth
1230 * or stencil value from the current draw rather than the previous one.
1232 ps
.PixelShaderKillsPixel
= subpass
->has_ds_self_dep
||
1233 wm_prog_data
->uses_kill
;
1236 ps
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
1237 ps
.InputCoverageMaskState
= wm_prog_data
->uses_sample_mask
?
1238 ICMS_INNER_CONSERVATIVE
: ICMS_NONE
;
1240 ps
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1246 emit_3dstate_vf_topology(struct anv_pipeline
*pipeline
)
1248 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_TOPOLOGY
), vft
) {
1249 vft
.PrimitiveTopologyType
= pipeline
->topology
;
1255 genX(graphics_pipeline_create
)(
1257 struct anv_pipeline_cache
* cache
,
1258 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
1259 const VkAllocationCallbacks
* pAllocator
,
1260 VkPipeline
* pPipeline
)
1262 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1263 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
1264 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1265 struct anv_pipeline
*pipeline
;
1268 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1270 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1271 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1272 if (pipeline
== NULL
)
1273 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1275 result
= anv_pipeline_init(pipeline
, device
, cache
,
1276 pCreateInfo
, pAllocator
);
1277 if (result
!= VK_SUCCESS
) {
1278 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
1282 assert(pCreateInfo
->pVertexInputState
);
1283 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
);
1284 assert(pCreateInfo
->pRasterizationState
);
1285 emit_rs_state(pipeline
, pCreateInfo
->pRasterizationState
,
1286 pCreateInfo
->pMultisampleState
, pass
, subpass
);
1287 emit_ms_state(pipeline
, pCreateInfo
->pMultisampleState
);
1288 emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
, pass
, subpass
);
1289 emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
,
1290 pCreateInfo
->pMultisampleState
);
1292 emit_urb_setup(pipeline
);
1294 emit_3dstate_clip(pipeline
, pCreateInfo
->pViewportState
,
1295 pCreateInfo
->pRasterizationState
);
1296 emit_3dstate_streamout(pipeline
, pCreateInfo
->pRasterizationState
);
1299 /* From gen7_vs_state.c */
1302 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
1303 * Geometry > Geometry Shader > State:
1305 * "Note: Because of corruption in IVB:GT2, software needs to flush the
1306 * whole fixed function pipeline when the GS enable changes value in
1309 * The hardware architects have clarified that in this context "flush the
1310 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
1313 if (!brw
->is_haswell
&& !brw
->is_baytrail
)
1314 gen7_emit_vs_workaround_flush(brw
);
1317 emit_3dstate_vs(pipeline
);
1318 emit_3dstate_gs(pipeline
);
1319 emit_3dstate_sbe(pipeline
);
1320 emit_3dstate_wm(pipeline
, subpass
, pCreateInfo
->pMultisampleState
);
1321 emit_3dstate_ps(pipeline
, pCreateInfo
->pColorBlendState
);
1323 emit_3dstate_ps_extra(pipeline
, subpass
);
1324 emit_3dstate_vf_topology(pipeline
);
1327 *pPipeline
= anv_pipeline_to_handle(pipeline
);
1333 compute_pipeline_create(
1335 struct anv_pipeline_cache
* cache
,
1336 const VkComputePipelineCreateInfo
* pCreateInfo
,
1337 const VkAllocationCallbacks
* pAllocator
,
1338 VkPipeline
* pPipeline
)
1340 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1341 const struct anv_physical_device
*physical_device
=
1342 &device
->instance
->physicalDevice
;
1343 const struct gen_device_info
*devinfo
= &physical_device
->info
;
1344 struct anv_pipeline
*pipeline
;
1347 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
);
1349 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1350 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1351 if (pipeline
== NULL
)
1352 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1354 pipeline
->device
= device
;
1355 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1357 pipeline
->blend_state
.map
= NULL
;
1359 result
= anv_reloc_list_init(&pipeline
->batch_relocs
,
1360 pAllocator
? pAllocator
: &device
->alloc
);
1361 if (result
!= VK_SUCCESS
) {
1362 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
1365 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1366 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1367 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1369 /* When we free the pipeline, we detect stages based on the NULL status
1370 * of various prog_data pointers. Make them NULL by default.
1372 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1374 pipeline
->active_stages
= 0;
1376 pipeline
->needs_data_cache
= false;
1378 assert(pCreateInfo
->stage
.stage
== VK_SHADER_STAGE_COMPUTE_BIT
);
1379 ANV_FROM_HANDLE(anv_shader_module
, module
, pCreateInfo
->stage
.module
);
1380 result
= anv_pipeline_compile_cs(pipeline
, cache
, pCreateInfo
, module
,
1381 pCreateInfo
->stage
.pName
,
1382 pCreateInfo
->stage
.pSpecializationInfo
);
1383 if (result
!= VK_SUCCESS
) {
1384 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
1388 const struct brw_cs_prog_data
*cs_prog_data
= get_cs_prog_data(pipeline
);
1390 anv_pipeline_setup_l3_config(pipeline
, cs_prog_data
->base
.total_shared
> 0);
1392 uint32_t group_size
= cs_prog_data
->local_size
[0] *
1393 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
1394 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
1397 pipeline
->cs_right_mask
= ~0u >> (32 - remainder
);
1399 pipeline
->cs_right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
1401 const uint32_t vfe_curbe_allocation
=
1402 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
1403 cs_prog_data
->push
.cross_thread
.regs
, 2);
1405 const uint32_t subslices
= MAX2(physical_device
->subslice_total
, 1);
1407 const struct anv_shader_bin
*cs_bin
=
1408 pipeline
->shaders
[MESA_SHADER_COMPUTE
];
1410 anv_batch_emit(&pipeline
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
1414 vfe
.GPGPUMode
= true;
1416 vfe
.MaximumNumberofThreads
=
1417 devinfo
->max_cs_threads
* subslices
- 1;
1418 vfe
.NumberofURBEntries
= GEN_GEN
<= 7 ? 0 : 2;
1419 vfe
.ResetGatewayTimer
= true;
1421 vfe
.BypassGatewayControl
= true;
1423 vfe
.URBEntryAllocationSize
= GEN_GEN
<= 7 ? 0 : 2;
1424 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
1426 vfe
.PerThreadScratchSpace
= get_scratch_space(cs_bin
);
1427 vfe
.ScratchSpaceBasePointer
=
1428 get_scratch_address(pipeline
, MESA_SHADER_COMPUTE
, cs_bin
);
1431 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1432 .KernelStartPointer
= cs_bin
->kernel
.offset
,
1434 .SamplerCount
= get_sampler_count(cs_bin
),
1435 .BindingTableEntryCount
= get_binding_table_entry_count(cs_bin
),
1436 .BarrierEnable
= cs_prog_data
->uses_barrier
,
1437 .SharedLocalMemorySize
=
1438 encode_slm_size(GEN_GEN
, cs_prog_data
->base
.total_shared
),
1441 .ConstantURBEntryReadOffset
= 0,
1443 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
1444 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1445 .CrossThreadConstantDataReadLength
=
1446 cs_prog_data
->push
.cross_thread
.regs
,
1449 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
1451 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
,
1452 pipeline
->interface_descriptor_data
,
1455 *pPipeline
= anv_pipeline_to_handle(pipeline
);
1460 VkResult
genX(CreateGraphicsPipelines
)(
1462 VkPipelineCache pipelineCache
,
1464 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
1465 const VkAllocationCallbacks
* pAllocator
,
1466 VkPipeline
* pPipelines
)
1468 ANV_FROM_HANDLE(anv_pipeline_cache
, pipeline_cache
, pipelineCache
);
1470 VkResult result
= VK_SUCCESS
;
1473 for (; i
< count
; i
++) {
1474 result
= genX(graphics_pipeline_create
)(_device
,
1477 pAllocator
, &pPipelines
[i
]);
1478 if (result
!= VK_SUCCESS
) {
1479 for (unsigned j
= 0; j
< i
; j
++) {
1480 anv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);
1490 VkResult
genX(CreateComputePipelines
)(
1492 VkPipelineCache pipelineCache
,
1494 const VkComputePipelineCreateInfo
* pCreateInfos
,
1495 const VkAllocationCallbacks
* pAllocator
,
1496 VkPipeline
* pPipelines
)
1498 ANV_FROM_HANDLE(anv_pipeline_cache
, pipeline_cache
, pipelineCache
);
1500 VkResult result
= VK_SUCCESS
;
1503 for (; i
< count
; i
++) {
1504 result
= compute_pipeline_create(_device
, pipeline_cache
,
1506 pAllocator
, &pPipelines
[i
]);
1507 if (result
!= VK_SUCCESS
) {
1508 for (unsigned j
= 0; j
< i
; j
++) {
1509 anv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);