anv/pipeline: Unify graphics_pipeline_create
[mesa.git] / src / intel / vulkan / genX_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "anv_private.h"
25
26 #include "genxml/gen_macros.h"
27 #include "genxml/genX_pack.h"
28
29 #include "genX_pipeline_util.h"
30
31 static VkResult
32 genX(graphics_pipeline_create)(
33 VkDevice _device,
34 struct anv_pipeline_cache * cache,
35 const VkGraphicsPipelineCreateInfo* pCreateInfo,
36 const VkAllocationCallbacks* pAllocator,
37 VkPipeline* pPipeline)
38 {
39 ANV_FROM_HANDLE(anv_device, device, _device);
40 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
41 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
42 struct anv_pipeline *pipeline;
43 VkResult result;
44
45 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
46
47 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
48 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
49 if (pipeline == NULL)
50 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
51
52 result = anv_pipeline_init(pipeline, device, cache,
53 pCreateInfo, pAllocator);
54 if (result != VK_SUCCESS) {
55 vk_free2(&device->alloc, pAllocator, pipeline);
56 return result;
57 }
58
59 assert(pCreateInfo->pVertexInputState);
60 emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
61 assert(pCreateInfo->pRasterizationState);
62 emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
63 pCreateInfo->pMultisampleState, pass, subpass);
64 emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
65 emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
66 emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
67 pCreateInfo->pMultisampleState);
68
69 emit_urb_setup(pipeline);
70
71 emit_3dstate_clip(pipeline, pCreateInfo->pViewportState,
72 pCreateInfo->pRasterizationState);
73 emit_3dstate_streamout(pipeline, pCreateInfo->pRasterizationState);
74
75 #if 0
76 /* From gen7_vs_state.c */
77
78 /**
79 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
80 * Geometry > Geometry Shader > State:
81 *
82 * "Note: Because of corruption in IVB:GT2, software needs to flush the
83 * whole fixed function pipeline when the GS enable changes value in
84 * the 3DSTATE_GS."
85 *
86 * The hardware architects have clarified that in this context "flush the
87 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
88 * Stall" bit set.
89 */
90 if (!brw->is_haswell && !brw->is_baytrail)
91 gen7_emit_vs_workaround_flush(brw);
92 #endif
93
94 emit_3dstate_vs(pipeline);
95 emit_3dstate_gs(pipeline);
96 emit_3dstate_sbe(pipeline);
97 emit_3dstate_wm(pipeline, pCreateInfo->pMultisampleState);
98 emit_3dstate_ps(pipeline);
99 #if GEN_GEN >= 8
100 emit_3dstate_ps_extra(pipeline);
101 emit_3dstate_vf_topology(pipeline);
102 #endif
103
104 *pPipeline = anv_pipeline_to_handle(pipeline);
105
106 return VK_SUCCESS;
107 }
108
109 static VkResult
110 compute_pipeline_create(
111 VkDevice _device,
112 struct anv_pipeline_cache * cache,
113 const VkComputePipelineCreateInfo* pCreateInfo,
114 const VkAllocationCallbacks* pAllocator,
115 VkPipeline* pPipeline)
116 {
117 ANV_FROM_HANDLE(anv_device, device, _device);
118 const struct anv_physical_device *physical_device =
119 &device->instance->physicalDevice;
120 const struct gen_device_info *devinfo = &physical_device->info;
121 struct anv_pipeline *pipeline;
122 VkResult result;
123
124 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO);
125
126 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
127 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
128 if (pipeline == NULL)
129 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
130
131 pipeline->device = device;
132 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
133
134 pipeline->blend_state.map = NULL;
135
136 result = anv_reloc_list_init(&pipeline->batch_relocs,
137 pAllocator ? pAllocator : &device->alloc);
138 if (result != VK_SUCCESS) {
139 vk_free2(&device->alloc, pAllocator, pipeline);
140 return result;
141 }
142 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
143 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
144 pipeline->batch.relocs = &pipeline->batch_relocs;
145
146 /* When we free the pipeline, we detect stages based on the NULL status
147 * of various prog_data pointers. Make them NULL by default.
148 */
149 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
150
151 pipeline->active_stages = 0;
152
153 pipeline->needs_data_cache = false;
154
155 assert(pCreateInfo->stage.stage == VK_SHADER_STAGE_COMPUTE_BIT);
156 ANV_FROM_HANDLE(anv_shader_module, module, pCreateInfo->stage.module);
157 result = anv_pipeline_compile_cs(pipeline, cache, pCreateInfo, module,
158 pCreateInfo->stage.pName,
159 pCreateInfo->stage.pSpecializationInfo);
160 if (result != VK_SUCCESS) {
161 vk_free2(&device->alloc, pAllocator, pipeline);
162 return result;
163 }
164
165 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
166
167 anv_pipeline_setup_l3_config(pipeline, cs_prog_data->base.total_shared > 0);
168
169 uint32_t group_size = cs_prog_data->local_size[0] *
170 cs_prog_data->local_size[1] * cs_prog_data->local_size[2];
171 uint32_t remainder = group_size & (cs_prog_data->simd_size - 1);
172
173 if (remainder > 0)
174 pipeline->cs_right_mask = ~0u >> (32 - remainder);
175 else
176 pipeline->cs_right_mask = ~0u >> (32 - cs_prog_data->simd_size);
177
178 const uint32_t vfe_curbe_allocation =
179 ALIGN(cs_prog_data->push.per_thread.regs * cs_prog_data->threads +
180 cs_prog_data->push.cross_thread.regs, 2);
181
182 const uint32_t subslices = MAX2(physical_device->subslice_total, 1);
183
184 anv_batch_emit(&pipeline->batch, GENX(MEDIA_VFE_STATE), vfe) {
185 vfe.ScratchSpaceBasePointer = (struct anv_address) {
186 .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
187 MESA_SHADER_COMPUTE,
188 cs_prog_data->base.total_scratch),
189 .offset = 0,
190 };
191 vfe.PerThreadScratchSpace = ffs(cs_prog_data->base.total_scratch / 2048);
192 #if GEN_GEN > 7
193 vfe.StackSize = 0;
194 #else
195 vfe.GPGPUMode = true;
196 #endif
197 vfe.MaximumNumberofThreads =
198 devinfo->max_cs_threads * subslices - 1;
199 vfe.NumberofURBEntries = GEN_GEN <= 7 ? 0 : 2;
200 vfe.ResetGatewayTimer = true;
201 #if GEN_GEN <= 8
202 vfe.BypassGatewayControl = true;
203 #endif
204 vfe.URBEntryAllocationSize = GEN_GEN <= 7 ? 0 : 2;
205 vfe.CURBEAllocationSize = vfe_curbe_allocation;
206 }
207
208 *pPipeline = anv_pipeline_to_handle(pipeline);
209
210 return VK_SUCCESS;
211 }
212
213 VkResult genX(CreateGraphicsPipelines)(
214 VkDevice _device,
215 VkPipelineCache pipelineCache,
216 uint32_t count,
217 const VkGraphicsPipelineCreateInfo* pCreateInfos,
218 const VkAllocationCallbacks* pAllocator,
219 VkPipeline* pPipelines)
220 {
221 ANV_FROM_HANDLE(anv_pipeline_cache, pipeline_cache, pipelineCache);
222
223 VkResult result = VK_SUCCESS;
224
225 unsigned i = 0;
226 for (; i < count; i++) {
227 result = genX(graphics_pipeline_create)(_device,
228 pipeline_cache,
229 &pCreateInfos[i],
230 pAllocator, &pPipelines[i]);
231 if (result != VK_SUCCESS) {
232 for (unsigned j = 0; j < i; j++) {
233 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
234 }
235
236 return result;
237 }
238 }
239
240 return VK_SUCCESS;
241 }
242
243 VkResult genX(CreateComputePipelines)(
244 VkDevice _device,
245 VkPipelineCache pipelineCache,
246 uint32_t count,
247 const VkComputePipelineCreateInfo* pCreateInfos,
248 const VkAllocationCallbacks* pAllocator,
249 VkPipeline* pPipelines)
250 {
251 ANV_FROM_HANDLE(anv_pipeline_cache, pipeline_cache, pipelineCache);
252
253 VkResult result = VK_SUCCESS;
254
255 unsigned i = 0;
256 for (; i < count; i++) {
257 result = compute_pipeline_create(_device, pipeline_cache,
258 &pCreateInfos[i],
259 pAllocator, &pPipelines[i]);
260 if (result != VK_SUCCESS) {
261 for (unsigned j = 0; j < i; j++) {
262 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
263 }
264
265 return result;
266 }
267 }
268
269 return VK_SUCCESS;
270 }