src/intel/vulkan/genX_pipeline_util.h

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 static uint32_t
  25 vertex_element_comp_control(enum isl_format format, unsigned comp)
  26 {
  27    uint8_t bits;
  28    switch (comp) {
  29    case 0: bits = isl_format_layouts[format].channels.r.bits; break;
  30    case 1: bits = isl_format_layouts[format].channels.g.bits; break;
  31    case 2: bits = isl_format_layouts[format].channels.b.bits; break;
  32    case 3: bits = isl_format_layouts[format].channels.a.bits; break;
  33    default: unreachable("Invalid component");
  34    }
  35
  36    if (bits) {
  37       return VFCOMP_STORE_SRC;
  38    } else if (comp < 3) {
  39       return VFCOMP_STORE_0;
  40    } else if (isl_format_layouts[format].channels.r.type == ISL_UINT ||
  41             isl_format_layouts[format].channels.r.type == ISL_SINT) {
  42       assert(comp == 3);
  43       return VFCOMP_STORE_1_INT;
  44    } else {
  45       assert(comp == 3);
  46       return VFCOMP_STORE_1_FP;
  47    }
  48 }
  49
  50 static void
  51 emit_vertex_input(struct anv_pipeline *pipeline,
  52                   const VkPipelineVertexInputStateCreateInfo *info,
  53                   const struct anv_graphics_pipeline_create_info *extra)
  54 {
  55    const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
  56
  57    uint32_t elements;
  58    if (extra && extra->disable_vs) {
  59       /* If the VS is disabled, just assume the user knows what they're
  60        * doing and apply the layout blindly.  This can only come from
  61        * meta, so this *should* be safe.
  62        */
  63       elements = 0;
  64       for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++)
  65          elements |= (1 << info->pVertexAttributeDescriptions[i].location);
  66    } else {
  67       /* Pull inputs_read out of the VS prog data */
  68       uint64_t inputs_read = vs_prog_data->inputs_read;
  69       assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
  70       elements = inputs_read >> VERT_ATTRIB_GENERIC0;
  71    }
  72
  73 #if GEN_GEN >= 8
  74    /* On BDW+, we only need to allocate space for base ids.  Setting up
  75     * the actual vertex and instance id is a separate packet.
  76     */
  77    const bool needs_svgs_elem = vs_prog_data->uses_basevertex ||
  78                                 vs_prog_data->uses_baseinstance;
  79 #else
  80    /* On Haswell and prior, vertex and instance id are created by using the
  81     * ComponentControl fields, so we need an element for any of them.
  82     */
  83    const bool needs_svgs_elem = vs_prog_data->uses_vertexid ||
  84                                 vs_prog_data->uses_instanceid ||
  85                                 vs_prog_data->uses_basevertex ||
  86                                 vs_prog_data->uses_baseinstance;
  87 #endif
  88
  89    uint32_t elem_count = __builtin_popcount(elements) + needs_svgs_elem;
  90    if (elem_count == 0)
  91       return;
  92
  93    uint32_t *p;
  94
  95    const uint32_t num_dwords = 1 + elem_count * 2;
  96    p = anv_batch_emitn(&pipeline->batch, num_dwords,
  97                        GENX(3DSTATE_VERTEX_ELEMENTS));
  98    memset(p + 1, 0, (num_dwords - 1) * 4);
  99
 100    for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
 101       const VkVertexInputAttributeDescription *desc =
 102          &info->pVertexAttributeDescriptions[i];
 103       enum isl_format format = anv_get_isl_format(&pipeline->device->info,
 104                                                   desc->format,
 105                                                   VK_IMAGE_ASPECT_COLOR_BIT,
 106                                                   VK_IMAGE_TILING_LINEAR);
 107
 108       assert(desc->binding < 32);
 109
 110       if ((elements & (1 << desc->location)) == 0)
 111          continue; /* Binding unused */
 112
 113       uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1));
 114
 115       struct GENX(VERTEX_ELEMENT_STATE) element = {
 116          .VertexBufferIndex = desc->binding,
 117          .Valid = true,
 118          .SourceElementFormat = format,
 119          .EdgeFlagEnable = false,
 120          .SourceElementOffset = desc->offset,
 121          .Component0Control = vertex_element_comp_control(format, 0),
 122          .Component1Control = vertex_element_comp_control(format, 1),
 123          .Component2Control = vertex_element_comp_control(format, 2),
 124          .Component3Control = vertex_element_comp_control(format, 3),
 125       };
 126       GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element);
 127
 128 #if GEN_GEN >= 8
 129       /* On Broadwell and later, we have a separate VF_INSTANCING packet
 130        * that controls instancing.  On Haswell and prior, that's part of
 131        * VERTEX_BUFFER_STATE which we emit later.
 132        */
 133       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
 134          vfi.InstancingEnable = pipeline->instancing_enable[desc->binding],
 135          vfi.VertexElementIndex = slot,
 136          /* Vulkan so far doesn't have an instance divisor, so
 137           * this is always 1 (ignored if not instancing). */
 138          vfi.InstanceDataStepRate = 1;
 139       }
 140 #endif
 141    }
 142
 143    const uint32_t id_slot = __builtin_popcount(elements);
 144    if (needs_svgs_elem) {
 145       /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
 146        *    "Within a VERTEX_ELEMENT_STATE structure, if a Component
 147        *    Control field is set to something other than VFCOMP_STORE_SRC,
 148        *    no higher-numbered Component Control fields may be set to
 149        *    VFCOMP_STORE_SRC"
 150        *
 151        * This means, that if we have BaseInstance, we need BaseVertex as
 152        * well.  Just do all or nothing.
 153        */
 154       uint32_t base_ctrl = (vs_prog_data->uses_basevertex ||
 155                             vs_prog_data->uses_baseinstance) ?
 156                            VFCOMP_STORE_SRC : VFCOMP_STORE_0;
 157
 158       struct GENX(VERTEX_ELEMENT_STATE) element = {
 159          .VertexBufferIndex = 32, /* Reserved for this */
 160          .Valid = true,
 161          .SourceElementFormat = ISL_FORMAT_R32G32_UINT,
 162          .Component0Control = base_ctrl,
 163          .Component1Control = base_ctrl,
 164 #if GEN_GEN >= 8
 165          .Component2Control = VFCOMP_STORE_0,
 166          .Component3Control = VFCOMP_STORE_0,
 167 #else
 168          .Component2Control = VFCOMP_STORE_VID,
 169          .Component3Control = VFCOMP_STORE_IID,
 170 #endif
 171       };
 172       GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + id_slot * 2], &element);
 173    }
 174
 175 #if GEN_GEN >= 8
 176    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS), sgvs) {
 177       sgvs.VertexIDEnable              = vs_prog_data->uses_vertexid;
 178       sgvs.VertexIDComponentNumber     = 2;
 179       sgvs.VertexIDElementOffset       = id_slot;
 180       sgvs.InstanceIDEnable            = vs_prog_data->uses_instanceid;
 181       sgvs.InstanceIDComponentNumber   = 3;
 182       sgvs.InstanceIDElementOffset     = id_slot;
 183    }
 184 #endif
 185 }
 186
 187 static inline void
 188 emit_urb_setup(struct anv_pipeline *pipeline)
 189 {
 190 #if GEN_GEN == 7 && !GEN_IS_HASWELL
 191    struct anv_device *device = pipeline->device;
 192
 193    /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
 194     *
 195     *    "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
 196     *    needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 197     *    3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 198     *    3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL
 199     *    needs to be sent before any combination of VS associated 3DSTATE."
 200     */
 201    anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL, pc) {
 202       pc.DepthStallEnable  = true;
 203       pc.PostSyncOperation = WriteImmediateData;
 204       pc.Address           = (struct anv_address) { &device->workaround_bo, 0 };
 205    }
 206 #endif
 207
 208    for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
 209       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_VS), urb) {
 210          urb._3DCommandSubOpcode       = 48 + i;
 211          urb.VSURBStartingAddress      = pipeline->urb.start[i];
 212          urb.VSURBEntryAllocationSize  = pipeline->urb.size[i] - 1;
 213          urb.VSNumberofURBEntries      = pipeline->urb.entries[i];
 214       }
 215    }
 216 }
 217
 218 static void
 219 emit_3dstate_sbe(struct anv_pipeline *pipeline)
 220 {
 221    const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
 222    const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 223    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 224    const struct brw_vue_map *fs_input_map;
 225
 226    if (pipeline->gs_kernel == NO_KERNEL)
 227       fs_input_map = &vs_prog_data->base.vue_map;
 228    else
 229       fs_input_map = &gs_prog_data->base.vue_map;
 230
 231    struct GENX(3DSTATE_SBE) sbe = {
 232       GENX(3DSTATE_SBE_header),
 233       .AttributeSwizzleEnable = true,
 234       .PointSpriteTextureCoordinateOrigin = UPPERLEFT,
 235       .NumberofSFOutputAttributes = wm_prog_data->num_varying_inputs,
 236       .ConstantInterpolationEnable = wm_prog_data->flat_inputs,
 237
 238 #if GEN_GEN >= 9
 239       .Attribute0ActiveComponentFormat = ACF_XYZW,
 240       .Attribute1ActiveComponentFormat = ACF_XYZW,
 241       .Attribute2ActiveComponentFormat = ACF_XYZW,
 242       .Attribute3ActiveComponentFormat = ACF_XYZW,
 243       .Attribute4ActiveComponentFormat = ACF_XYZW,
 244       .Attribute5ActiveComponentFormat = ACF_XYZW,
 245       .Attribute6ActiveComponentFormat = ACF_XYZW,
 246       .Attribute7ActiveComponentFormat = ACF_XYZW,
 247       .Attribute8ActiveComponentFormat = ACF_XYZW,
 248       .Attribute9ActiveComponentFormat = ACF_XYZW,
 249       .Attribute10ActiveComponentFormat = ACF_XYZW,
 250       .Attribute11ActiveComponentFormat = ACF_XYZW,
 251       .Attribute12ActiveComponentFormat = ACF_XYZW,
 252       .Attribute13ActiveComponentFormat = ACF_XYZW,
 253       .Attribute14ActiveComponentFormat = ACF_XYZW,
 254       .Attribute15ActiveComponentFormat = ACF_XYZW,
 255       /* wow, much field, very attribute */
 256       .Attribute16ActiveComponentFormat = ACF_XYZW,
 257       .Attribute17ActiveComponentFormat = ACF_XYZW,
 258       .Attribute18ActiveComponentFormat = ACF_XYZW,
 259       .Attribute19ActiveComponentFormat = ACF_XYZW,
 260       .Attribute20ActiveComponentFormat = ACF_XYZW,
 261       .Attribute21ActiveComponentFormat = ACF_XYZW,
 262       .Attribute22ActiveComponentFormat = ACF_XYZW,
 263       .Attribute23ActiveComponentFormat = ACF_XYZW,
 264       .Attribute24ActiveComponentFormat = ACF_XYZW,
 265       .Attribute25ActiveComponentFormat = ACF_XYZW,
 266       .Attribute26ActiveComponentFormat = ACF_XYZW,
 267       .Attribute27ActiveComponentFormat = ACF_XYZW,
 268       .Attribute28ActiveComponentFormat = ACF_XYZW,
 269       .Attribute29ActiveComponentFormat = ACF_XYZW,
 270       .Attribute28ActiveComponentFormat = ACF_XYZW,
 271       .Attribute29ActiveComponentFormat = ACF_XYZW,
 272       .Attribute30ActiveComponentFormat = ACF_XYZW,
 273 #endif
 274    };
 275
 276 #if GEN_GEN >= 8
 277    /* On Broadwell, they broke 3DSTATE_SBE into two packets */
 278    struct GENX(3DSTATE_SBE_SWIZ) swiz = {
 279       GENX(3DSTATE_SBE_SWIZ_header),
 280    };
 281 #else
 282 #  define swiz sbe
 283 #endif
 284
 285    int max_source_attr = 0;
 286    for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 287       int input_index = wm_prog_data->urb_setup[attr];
 288
 289       if (input_index < 0)
 290          continue;
 291
 292       const int slot = fs_input_map->varying_to_slot[attr];
 293
 294       if (input_index >= 16)
 295          continue;
 296
 297       if (slot == -1) {
 298          /* This attribute does not exist in the VUE--that means that the
 299           * vertex shader did not write to it.  It could be that it's a
 300           * regular varying read by the fragment shader but not written by
 301           * the vertex shader or it's gl_PrimitiveID. In the first case the
 302           * value is undefined, in the second it needs to be
 303           * gl_PrimitiveID.
 304           */
 305          swiz.Attribute[input_index].ConstantSource = PRIM_ID;
 306          swiz.Attribute[input_index].ComponentOverrideX = true;
 307          swiz.Attribute[input_index].ComponentOverrideY = true;
 308          swiz.Attribute[input_index].ComponentOverrideZ = true;
 309          swiz.Attribute[input_index].ComponentOverrideW = true;
 310       } else {
 311          assert(slot >= 2);
 312          const int source_attr = slot - 2;
 313          max_source_attr = MAX2(max_source_attr, source_attr);
 314          /* We have to subtract two slots to accout for the URB entry output
 315           * read offset in the VS and GS stages.
 316           */
 317          swiz.Attribute[input_index].SourceAttribute = source_attr;
 318       }
 319    }
 320
 321    sbe.VertexURBEntryReadOffset = 1; /* Skip the VUE header and position slots */
 322    sbe.VertexURBEntryReadLength = DIV_ROUND_UP(max_source_attr + 1, 2);
 323
 324    uint32_t *dw = anv_batch_emit_dwords(&pipeline->batch,
 325                                         GENX(3DSTATE_SBE_length));
 326    GENX(3DSTATE_SBE_pack)(&pipeline->batch, dw, &sbe);
 327
 328 #if GEN_GEN >= 8
 329    dw = anv_batch_emit_dwords(&pipeline->batch, GENX(3DSTATE_SBE_SWIZ_length));
 330    GENX(3DSTATE_SBE_SWIZ_pack)(&pipeline->batch, dw, &swiz);
 331 #endif
 332 }
 333
 334 static inline uint32_t
 335 scratch_space(const struct brw_stage_prog_data *prog_data)
 336 {
 337    return ffs(prog_data->total_scratch / 2048);
 338 }
 339
 340 static const uint32_t vk_to_gen_cullmode[] = {
 341    [VK_CULL_MODE_NONE]                       = CULLMODE_NONE,
 342    [VK_CULL_MODE_FRONT_BIT]                  = CULLMODE_FRONT,
 343    [VK_CULL_MODE_BACK_BIT]                   = CULLMODE_BACK,
 344    [VK_CULL_MODE_FRONT_AND_BACK]             = CULLMODE_BOTH
 345 };
 346
 347 static const uint32_t vk_to_gen_fillmode[] = {
 348    [VK_POLYGON_MODE_FILL]                    = FILL_MODE_SOLID,
 349    [VK_POLYGON_MODE_LINE]                    = FILL_MODE_WIREFRAME,
 350    [VK_POLYGON_MODE_POINT]                   = FILL_MODE_POINT,
 351 };
 352
 353 static const uint32_t vk_to_gen_front_face[] = {
 354    [VK_FRONT_FACE_COUNTER_CLOCKWISE]         = 1,
 355    [VK_FRONT_FACE_CLOCKWISE]                 = 0
 356 };
 357
 358 static const uint32_t vk_to_gen_logic_op[] = {
 359    [VK_LOGIC_OP_COPY]                        = LOGICOP_COPY,
 360    [VK_LOGIC_OP_CLEAR]                       = LOGICOP_CLEAR,
 361    [VK_LOGIC_OP_AND]                         = LOGICOP_AND,
 362    [VK_LOGIC_OP_AND_REVERSE]                 = LOGICOP_AND_REVERSE,
 363    [VK_LOGIC_OP_AND_INVERTED]                = LOGICOP_AND_INVERTED,
 364    [VK_LOGIC_OP_NO_OP]                       = LOGICOP_NOOP,
 365    [VK_LOGIC_OP_XOR]                         = LOGICOP_XOR,
 366    [VK_LOGIC_OP_OR]                          = LOGICOP_OR,
 367    [VK_LOGIC_OP_NOR]                         = LOGICOP_NOR,
 368    [VK_LOGIC_OP_EQUIVALENT]                  = LOGICOP_EQUIV,
 369    [VK_LOGIC_OP_INVERT]                      = LOGICOP_INVERT,
 370    [VK_LOGIC_OP_OR_REVERSE]                  = LOGICOP_OR_REVERSE,
 371    [VK_LOGIC_OP_COPY_INVERTED]               = LOGICOP_COPY_INVERTED,
 372    [VK_LOGIC_OP_OR_INVERTED]                 = LOGICOP_OR_INVERTED,
 373    [VK_LOGIC_OP_NAND]                        = LOGICOP_NAND,
 374    [VK_LOGIC_OP_SET]                         = LOGICOP_SET,
 375 };
 376
 377 static const uint32_t vk_to_gen_blend[] = {
 378    [VK_BLEND_FACTOR_ZERO]                    = BLENDFACTOR_ZERO,
 379    [VK_BLEND_FACTOR_ONE]                     = BLENDFACTOR_ONE,
 380    [VK_BLEND_FACTOR_SRC_COLOR]               = BLENDFACTOR_SRC_COLOR,
 381    [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR]     = BLENDFACTOR_INV_SRC_COLOR,
 382    [VK_BLEND_FACTOR_DST_COLOR]               = BLENDFACTOR_DST_COLOR,
 383    [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR]     = BLENDFACTOR_INV_DST_COLOR,
 384    [VK_BLEND_FACTOR_SRC_ALPHA]               = BLENDFACTOR_SRC_ALPHA,
 385    [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA]     = BLENDFACTOR_INV_SRC_ALPHA,
 386    [VK_BLEND_FACTOR_DST_ALPHA]               = BLENDFACTOR_DST_ALPHA,
 387    [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA]     = BLENDFACTOR_INV_DST_ALPHA,
 388    [VK_BLEND_FACTOR_CONSTANT_COLOR]          = BLENDFACTOR_CONST_COLOR,
 389    [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]= BLENDFACTOR_INV_CONST_COLOR,
 390    [VK_BLEND_FACTOR_CONSTANT_ALPHA]          = BLENDFACTOR_CONST_ALPHA,
 391    [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]= BLENDFACTOR_INV_CONST_ALPHA,
 392    [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE]      = BLENDFACTOR_SRC_ALPHA_SATURATE,
 393    [VK_BLEND_FACTOR_SRC1_COLOR]              = BLENDFACTOR_SRC1_COLOR,
 394    [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR]    = BLENDFACTOR_INV_SRC1_COLOR,
 395    [VK_BLEND_FACTOR_SRC1_ALPHA]              = BLENDFACTOR_SRC1_ALPHA,
 396    [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA]    = BLENDFACTOR_INV_SRC1_ALPHA,
 397 };
 398
 399 static const uint32_t vk_to_gen_blend_op[] = {
 400    [VK_BLEND_OP_ADD]                         = BLENDFUNCTION_ADD,
 401    [VK_BLEND_OP_SUBTRACT]                    = BLENDFUNCTION_SUBTRACT,
 402    [VK_BLEND_OP_REVERSE_SUBTRACT]            = BLENDFUNCTION_REVERSE_SUBTRACT,
 403    [VK_BLEND_OP_MIN]                         = BLENDFUNCTION_MIN,
 404    [VK_BLEND_OP_MAX]                         = BLENDFUNCTION_MAX,
 405 };
 406
 407 static const uint32_t vk_to_gen_compare_op[] = {
 408    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPNEVER,
 409    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLESS,
 410    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPEQUAL,
 411    [VK_COMPARE_OP_LESS_OR_EQUAL]                = PREFILTEROPLEQUAL,
 412    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGREATER,
 413    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPNOTEQUAL,
 414    [VK_COMPARE_OP_GREATER_OR_EQUAL]             = PREFILTEROPGEQUAL,
 415    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPALWAYS,
 416 };
 417
 418 static const uint32_t vk_to_gen_stencil_op[] = {
 419    [VK_STENCIL_OP_KEEP]                         = STENCILOP_KEEP,
 420    [VK_STENCIL_OP_ZERO]                         = STENCILOP_ZERO,
 421    [VK_STENCIL_OP_REPLACE]                      = STENCILOP_REPLACE,
 422    [VK_STENCIL_OP_INCREMENT_AND_CLAMP]          = STENCILOP_INCRSAT,
 423    [VK_STENCIL_OP_DECREMENT_AND_CLAMP]          = STENCILOP_DECRSAT,
 424    [VK_STENCIL_OP_INVERT]                       = STENCILOP_INVERT,
 425    [VK_STENCIL_OP_INCREMENT_AND_WRAP]           = STENCILOP_INCR,
 426    [VK_STENCIL_OP_DECREMENT_AND_WRAP]           = STENCILOP_DECR,
 427 };