src/intel/vulkan/genX_pipeline_util.h

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 static uint32_t
  25 vertex_element_comp_control(enum isl_format format, unsigned comp)
  26 {
  27    uint8_t bits;
  28    switch (comp) {
  29    case 0: bits = isl_format_layouts[format].channels.r.bits; break;
  30    case 1: bits = isl_format_layouts[format].channels.g.bits; break;
  31    case 2: bits = isl_format_layouts[format].channels.b.bits; break;
  32    case 3: bits = isl_format_layouts[format].channels.a.bits; break;
  33    default: unreachable("Invalid component");
  34    }
  35
  36    if (bits) {
  37       return VFCOMP_STORE_SRC;
  38    } else if (comp < 3) {
  39       return VFCOMP_STORE_0;
  40    } else if (isl_format_layouts[format].channels.r.type == ISL_UINT ||
  41             isl_format_layouts[format].channels.r.type == ISL_SINT) {
  42       assert(comp == 3);
  43       return VFCOMP_STORE_1_INT;
  44    } else {
  45       assert(comp == 3);
  46       return VFCOMP_STORE_1_FP;
  47    }
  48 }
  49
  50 static void
  51 emit_vertex_input(struct anv_pipeline *pipeline,
  52                   const VkPipelineVertexInputStateCreateInfo *info,
  53                   const struct anv_graphics_pipeline_create_info *extra)
  54 {
  55    const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
  56
  57    uint32_t elements;
  58    if (extra && extra->disable_vs) {
  59       /* If the VS is disabled, just assume the user knows what they're
  60        * doing and apply the layout blindly.  This can only come from
  61        * meta, so this *should* be safe.
  62        */
  63       elements = 0;
  64       for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++)
  65          elements |= (1 << info->pVertexAttributeDescriptions[i].location);
  66    } else {
  67       /* Pull inputs_read out of the VS prog data */
  68       uint64_t inputs_read = vs_prog_data->inputs_read;
  69       assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
  70       elements = inputs_read >> VERT_ATTRIB_GENERIC0;
  71    }
  72
  73 #if GEN_GEN >= 8
  74    /* On BDW+, we only need to allocate space for base ids.  Setting up
  75     * the actual vertex and instance id is a separate packet.
  76     */
  77    const bool needs_svgs_elem = vs_prog_data->uses_basevertex ||
  78                                 vs_prog_data->uses_baseinstance;
  79 #else
  80    /* On Haswell and prior, vertex and instance id are created by using the
  81     * ComponentControl fields, so we need an element for any of them.
  82     */
  83    const bool needs_svgs_elem = vs_prog_data->uses_vertexid ||
  84                                 vs_prog_data->uses_instanceid ||
  85                                 vs_prog_data->uses_basevertex ||
  86                                 vs_prog_data->uses_baseinstance;
  87 #endif
  88
  89    uint32_t elem_count = __builtin_popcount(elements) + needs_svgs_elem;
  90    if (elem_count == 0)
  91       return;
  92
  93    uint32_t *p;
  94
  95    const uint32_t num_dwords = 1 + elem_count * 2;
  96    p = anv_batch_emitn(&pipeline->batch, num_dwords,
  97                        GENX(3DSTATE_VERTEX_ELEMENTS));
  98    memset(p + 1, 0, (num_dwords - 1) * 4);
  99
 100    for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
 101       const VkVertexInputAttributeDescription *desc =
 102          &info->pVertexAttributeDescriptions[i];
 103       enum isl_format format = anv_get_isl_format(desc->format,
 104                                                   VK_IMAGE_ASPECT_COLOR_BIT,
 105                                                   VK_IMAGE_TILING_LINEAR);
 106
 107       assert(desc->binding < 32);
 108
 109       if ((elements & (1 << desc->location)) == 0)
 110          continue; /* Binding unused */
 111
 112       uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1));
 113
 114       struct GENX(VERTEX_ELEMENT_STATE) element = {
 115          .VertexBufferIndex = desc->binding,
 116          .Valid = true,
 117          .SourceElementFormat = format,
 118          .EdgeFlagEnable = false,
 119          .SourceElementOffset = desc->offset,
 120          .Component0Control = vertex_element_comp_control(format, 0),
 121          .Component1Control = vertex_element_comp_control(format, 1),
 122          .Component2Control = vertex_element_comp_control(format, 2),
 123          .Component3Control = vertex_element_comp_control(format, 3),
 124       };
 125       GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element);
 126
 127 #if GEN_GEN >= 8
 128       /* On Broadwell and later, we have a separate VF_INSTANCING packet
 129        * that controls instancing.  On Haswell and prior, that's part of
 130        * VERTEX_BUFFER_STATE which we emit later.
 131        */
 132       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
 133          vfi.InstancingEnable = pipeline->instancing_enable[desc->binding],
 134          vfi.VertexElementIndex = slot,
 135          /* Vulkan so far doesn't have an instance divisor, so
 136           * this is always 1 (ignored if not instancing). */
 137          vfi.InstanceDataStepRate = 1;
 138       }
 139 #endif
 140    }
 141
 142    const uint32_t id_slot = __builtin_popcount(elements);
 143    if (needs_svgs_elem) {
 144       /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
 145        *    "Within a VERTEX_ELEMENT_STATE structure, if a Component
 146        *    Control field is set to something other than VFCOMP_STORE_SRC,
 147        *    no higher-numbered Component Control fields may be set to
 148        *    VFCOMP_STORE_SRC"
 149        *
 150        * This means, that if we have BaseInstance, we need BaseVertex as
 151        * well.  Just do all or nothing.
 152        */
 153       uint32_t base_ctrl = (vs_prog_data->uses_basevertex ||
 154                             vs_prog_data->uses_baseinstance) ?
 155                            VFCOMP_STORE_SRC : VFCOMP_STORE_0;
 156
 157       struct GENX(VERTEX_ELEMENT_STATE) element = {
 158          .VertexBufferIndex = 32, /* Reserved for this */
 159          .Valid = true,
 160          .SourceElementFormat = ISL_FORMAT_R32G32_UINT,
 161          .Component0Control = base_ctrl,
 162          .Component1Control = base_ctrl,
 163 #if GEN_GEN >= 8
 164          .Component2Control = VFCOMP_STORE_0,
 165          .Component3Control = VFCOMP_STORE_0,
 166 #else
 167          .Component2Control = VFCOMP_STORE_VID,
 168          .Component3Control = VFCOMP_STORE_IID,
 169 #endif
 170       };
 171       GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + id_slot * 2], &element);
 172    }
 173
 174 #if GEN_GEN >= 8
 175    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS), sgvs) {
 176       sgvs.VertexIDEnable              = vs_prog_data->uses_vertexid;
 177       sgvs.VertexIDComponentNumber     = 2;
 178       sgvs.VertexIDElementOffset       = id_slot;
 179       sgvs.InstanceIDEnable            = vs_prog_data->uses_instanceid;
 180       sgvs.InstanceIDComponentNumber   = 3;
 181       sgvs.InstanceIDElementOffset     = id_slot;
 182    }
 183 #endif
 184 }
 185
 186 static inline void
 187 emit_urb_setup(struct anv_pipeline *pipeline)
 188 {
 189 #if GEN_GEN == 7 && !GEN_IS_HASWELL
 190    struct anv_device *device = pipeline->device;
 191
 192    /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
 193     *
 194     *    "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
 195     *    needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 196     *    3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 197     *    3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL
 198     *    needs to be sent before any combination of VS associated 3DSTATE."
 199     */
 200    anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL, pc) {
 201       pc.DepthStallEnable  = true;
 202       pc.PostSyncOperation = WriteImmediateData;
 203       pc.Address           = (struct anv_address) { &device->workaround_bo, 0 };
 204    }
 205 #endif
 206
 207    unsigned push_start = 0;
 208    for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_FRAGMENT; i++) {
 209       unsigned push_size = pipeline->urb.push_size[i];
 210       anv_batch_emit(&pipeline->batch,
 211                      GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) {
 212          alloc._3DCommandSubOpcode  = 18 + i;
 213          alloc.ConstantBufferOffset = (push_size > 0) ? push_start : 0;
 214          alloc.ConstantBufferSize   = push_size;
 215       }
 216       push_start += pipeline->urb.push_size[i];
 217    }
 218
 219    for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
 220       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_VS), urb) {
 221          urb._3DCommandSubOpcode       = 48 + i;
 222          urb.VSURBStartingAddress      = pipeline->urb.start[i];
 223          urb.VSURBEntryAllocationSize  = pipeline->urb.size[i] - 1;
 224          urb.VSNumberofURBEntries      = pipeline->urb.entries[i];
 225       }
 226    }
 227 }
 228
 229 static void
 230 emit_3dstate_sbe(struct anv_pipeline *pipeline)
 231 {
 232    const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
 233    const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 234    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 235    const struct brw_vue_map *fs_input_map;
 236
 237    if (pipeline->gs_kernel == NO_KERNEL)
 238       fs_input_map = &vs_prog_data->base.vue_map;
 239    else
 240       fs_input_map = &gs_prog_data->base.vue_map;
 241
 242    struct GENX(3DSTATE_SBE) sbe = {
 243       GENX(3DSTATE_SBE_header),
 244       .AttributeSwizzleEnable = true,
 245       .PointSpriteTextureCoordinateOrigin = UPPERLEFT,
 246       .NumberofSFOutputAttributes = wm_prog_data->num_varying_inputs,
 247       .ConstantInterpolationEnable = wm_prog_data->flat_inputs,
 248
 249 #if GEN_GEN >= 9
 250       .Attribute0ActiveComponentFormat = ACF_XYZW,
 251       .Attribute1ActiveComponentFormat = ACF_XYZW,
 252       .Attribute2ActiveComponentFormat = ACF_XYZW,
 253       .Attribute3ActiveComponentFormat = ACF_XYZW,
 254       .Attribute4ActiveComponentFormat = ACF_XYZW,
 255       .Attribute5ActiveComponentFormat = ACF_XYZW,
 256       .Attribute6ActiveComponentFormat = ACF_XYZW,
 257       .Attribute7ActiveComponentFormat = ACF_XYZW,
 258       .Attribute8ActiveComponentFormat = ACF_XYZW,
 259       .Attribute9ActiveComponentFormat = ACF_XYZW,
 260       .Attribute10ActiveComponentFormat = ACF_XYZW,
 261       .Attribute11ActiveComponentFormat = ACF_XYZW,
 262       .Attribute12ActiveComponentFormat = ACF_XYZW,
 263       .Attribute13ActiveComponentFormat = ACF_XYZW,
 264       .Attribute14ActiveComponentFormat = ACF_XYZW,
 265       .Attribute15ActiveComponentFormat = ACF_XYZW,
 266       /* wow, much field, very attribute */
 267       .Attribute16ActiveComponentFormat = ACF_XYZW,
 268       .Attribute17ActiveComponentFormat = ACF_XYZW,
 269       .Attribute18ActiveComponentFormat = ACF_XYZW,
 270       .Attribute19ActiveComponentFormat = ACF_XYZW,
 271       .Attribute20ActiveComponentFormat = ACF_XYZW,
 272       .Attribute21ActiveComponentFormat = ACF_XYZW,
 273       .Attribute22ActiveComponentFormat = ACF_XYZW,
 274       .Attribute23ActiveComponentFormat = ACF_XYZW,
 275       .Attribute24ActiveComponentFormat = ACF_XYZW,
 276       .Attribute25ActiveComponentFormat = ACF_XYZW,
 277       .Attribute26ActiveComponentFormat = ACF_XYZW,
 278       .Attribute27ActiveComponentFormat = ACF_XYZW,
 279       .Attribute28ActiveComponentFormat = ACF_XYZW,
 280       .Attribute29ActiveComponentFormat = ACF_XYZW,
 281       .Attribute28ActiveComponentFormat = ACF_XYZW,
 282       .Attribute29ActiveComponentFormat = ACF_XYZW,
 283       .Attribute30ActiveComponentFormat = ACF_XYZW,
 284 #endif
 285    };
 286
 287 #if GEN_GEN >= 8
 288    /* On Broadwell, they broke 3DSTATE_SBE into two packets */
 289    struct GENX(3DSTATE_SBE_SWIZ) swiz = {
 290       GENX(3DSTATE_SBE_SWIZ_header),
 291    };
 292 #else
 293 #  define swiz sbe
 294 #endif
 295
 296    int max_source_attr = 0;
 297    for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 298       int input_index = wm_prog_data->urb_setup[attr];
 299
 300       if (input_index < 0)
 301          continue;
 302
 303       const int slot = fs_input_map->varying_to_slot[attr];
 304
 305       if (input_index >= 16)
 306          continue;
 307
 308       if (slot == -1) {
 309          /* This attribute does not exist in the VUE--that means that the
 310           * vertex shader did not write to it.  It could be that it's a
 311           * regular varying read by the fragment shader but not written by
 312           * the vertex shader or it's gl_PrimitiveID. In the first case the
 313           * value is undefined, in the second it needs to be
 314           * gl_PrimitiveID.
 315           */
 316          swiz.Attribute[input_index].ConstantSource = PRIM_ID;
 317          swiz.Attribute[input_index].ComponentOverrideX = true;
 318          swiz.Attribute[input_index].ComponentOverrideY = true;
 319          swiz.Attribute[input_index].ComponentOverrideZ = true;
 320          swiz.Attribute[input_index].ComponentOverrideW = true;
 321       } else {
 322          assert(slot >= 2);
 323          const int source_attr = slot - 2;
 324          max_source_attr = MAX2(max_source_attr, source_attr);
 325          /* We have to subtract two slots to accout for the URB entry output
 326           * read offset in the VS and GS stages.
 327           */
 328          swiz.Attribute[input_index].SourceAttribute = source_attr;
 329       }
 330    }
 331
 332    sbe.VertexURBEntryReadOffset = 1; /* Skip the VUE header and position slots */
 333    sbe.VertexURBEntryReadLength = DIV_ROUND_UP(max_source_attr + 1, 2);
 334
 335    uint32_t *dw = anv_batch_emit_dwords(&pipeline->batch,
 336                                         GENX(3DSTATE_SBE_length));
 337    GENX(3DSTATE_SBE_pack)(&pipeline->batch, dw, &sbe);
 338
 339 #if GEN_GEN >= 8
 340    dw = anv_batch_emit_dwords(&pipeline->batch, GENX(3DSTATE_SBE_SWIZ_length));
 341    GENX(3DSTATE_SBE_SWIZ_pack)(&pipeline->batch, dw, &swiz);
 342 #endif
 343 }
 344
 345 static inline uint32_t
 346 scratch_space(const struct brw_stage_prog_data *prog_data)
 347 {
 348    return ffs(prog_data->total_scratch / 2048);
 349 }
 350
 351 static const uint32_t vk_to_gen_cullmode[] = {
 352    [VK_CULL_MODE_NONE]                       = CULLMODE_NONE,
 353    [VK_CULL_MODE_FRONT_BIT]                  = CULLMODE_FRONT,
 354    [VK_CULL_MODE_BACK_BIT]                   = CULLMODE_BACK,
 355    [VK_CULL_MODE_FRONT_AND_BACK]             = CULLMODE_BOTH
 356 };
 357
 358 static const uint32_t vk_to_gen_fillmode[] = {
 359    [VK_POLYGON_MODE_FILL]                    = FILL_MODE_SOLID,
 360    [VK_POLYGON_MODE_LINE]                    = FILL_MODE_WIREFRAME,
 361    [VK_POLYGON_MODE_POINT]                   = FILL_MODE_POINT,
 362 };
 363
 364 static const uint32_t vk_to_gen_front_face[] = {
 365    [VK_FRONT_FACE_COUNTER_CLOCKWISE]         = 1,
 366    [VK_FRONT_FACE_CLOCKWISE]                 = 0
 367 };
 368
 369 static const uint32_t vk_to_gen_logic_op[] = {
 370    [VK_LOGIC_OP_COPY]                        = LOGICOP_COPY,
 371    [VK_LOGIC_OP_CLEAR]                       = LOGICOP_CLEAR,
 372    [VK_LOGIC_OP_AND]                         = LOGICOP_AND,
 373    [VK_LOGIC_OP_AND_REVERSE]                 = LOGICOP_AND_REVERSE,
 374    [VK_LOGIC_OP_AND_INVERTED]                = LOGICOP_AND_INVERTED,
 375    [VK_LOGIC_OP_NO_OP]                       = LOGICOP_NOOP,
 376    [VK_LOGIC_OP_XOR]                         = LOGICOP_XOR,
 377    [VK_LOGIC_OP_OR]                          = LOGICOP_OR,
 378    [VK_LOGIC_OP_NOR]                         = LOGICOP_NOR,
 379    [VK_LOGIC_OP_EQUIVALENT]                  = LOGICOP_EQUIV,
 380    [VK_LOGIC_OP_INVERT]                      = LOGICOP_INVERT,
 381    [VK_LOGIC_OP_OR_REVERSE]                  = LOGICOP_OR_REVERSE,
 382    [VK_LOGIC_OP_COPY_INVERTED]               = LOGICOP_COPY_INVERTED,
 383    [VK_LOGIC_OP_OR_INVERTED]                 = LOGICOP_OR_INVERTED,
 384    [VK_LOGIC_OP_NAND]                        = LOGICOP_NAND,
 385    [VK_LOGIC_OP_SET]                         = LOGICOP_SET,
 386 };
 387
 388 static const uint32_t vk_to_gen_blend[] = {
 389    [VK_BLEND_FACTOR_ZERO]                    = BLENDFACTOR_ZERO,
 390    [VK_BLEND_FACTOR_ONE]                     = BLENDFACTOR_ONE,
 391    [VK_BLEND_FACTOR_SRC_COLOR]               = BLENDFACTOR_SRC_COLOR,
 392    [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR]     = BLENDFACTOR_INV_SRC_COLOR,
 393    [VK_BLEND_FACTOR_DST_COLOR]               = BLENDFACTOR_DST_COLOR,
 394    [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR]     = BLENDFACTOR_INV_DST_COLOR,
 395    [VK_BLEND_FACTOR_SRC_ALPHA]               = BLENDFACTOR_SRC_ALPHA,
 396    [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA]     = BLENDFACTOR_INV_SRC_ALPHA,
 397    [VK_BLEND_FACTOR_DST_ALPHA]               = BLENDFACTOR_DST_ALPHA,
 398    [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA]     = BLENDFACTOR_INV_DST_ALPHA,
 399    [VK_BLEND_FACTOR_CONSTANT_COLOR]          = BLENDFACTOR_CONST_COLOR,
 400    [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]= BLENDFACTOR_INV_CONST_COLOR,
 401    [VK_BLEND_FACTOR_CONSTANT_ALPHA]          = BLENDFACTOR_CONST_ALPHA,
 402    [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]= BLENDFACTOR_INV_CONST_ALPHA,
 403    [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE]      = BLENDFACTOR_SRC_ALPHA_SATURATE,
 404    [VK_BLEND_FACTOR_SRC1_COLOR]              = BLENDFACTOR_SRC1_COLOR,
 405    [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR]    = BLENDFACTOR_INV_SRC1_COLOR,
 406    [VK_BLEND_FACTOR_SRC1_ALPHA]              = BLENDFACTOR_SRC1_ALPHA,
 407    [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA]    = BLENDFACTOR_INV_SRC1_ALPHA,
 408 };
 409
 410 static const uint32_t vk_to_gen_blend_op[] = {
 411    [VK_BLEND_OP_ADD]                         = BLENDFUNCTION_ADD,
 412    [VK_BLEND_OP_SUBTRACT]                    = BLENDFUNCTION_SUBTRACT,
 413    [VK_BLEND_OP_REVERSE_SUBTRACT]            = BLENDFUNCTION_REVERSE_SUBTRACT,
 414    [VK_BLEND_OP_MIN]                         = BLENDFUNCTION_MIN,
 415    [VK_BLEND_OP_MAX]                         = BLENDFUNCTION_MAX,
 416 };
 417
 418 static const uint32_t vk_to_gen_compare_op[] = {
 419    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPNEVER,
 420    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLESS,
 421    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPEQUAL,
 422    [VK_COMPARE_OP_LESS_OR_EQUAL]                = PREFILTEROPLEQUAL,
 423    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGREATER,
 424    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPNOTEQUAL,
 425    [VK_COMPARE_OP_GREATER_OR_EQUAL]             = PREFILTEROPGEQUAL,
 426    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPALWAYS,
 427 };
 428
 429 static const uint32_t vk_to_gen_stencil_op[] = {
 430    [VK_STENCIL_OP_KEEP]                         = STENCILOP_KEEP,
 431    [VK_STENCIL_OP_ZERO]                         = STENCILOP_ZERO,
 432    [VK_STENCIL_OP_REPLACE]                      = STENCILOP_REPLACE,
 433    [VK_STENCIL_OP_INCREMENT_AND_CLAMP]          = STENCILOP_INCRSAT,
 434    [VK_STENCIL_OP_DECREMENT_AND_CLAMP]          = STENCILOP_DECRSAT,
 435    [VK_STENCIL_OP_INVERT]                       = STENCILOP_INVERT,
 436    [VK_STENCIL_OP_INCREMENT_AND_WRAP]           = STENCILOP_INCR,
 437    [VK_STENCIL_OP_DECREMENT_AND_WRAP]           = STENCILOP_DECR,
 438 };