src/intel/vulkan/genX_pipeline_util.h

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "vk_format_info.h"
  25
  26 static uint32_t
  27 vertex_element_comp_control(enum isl_format format, unsigned comp)
  28 {
  29    uint8_t bits;
  30    switch (comp) {
  31    case 0: bits = isl_format_layouts[format].channels.r.bits; break;
  32    case 1: bits = isl_format_layouts[format].channels.g.bits; break;
  33    case 2: bits = isl_format_layouts[format].channels.b.bits; break;
  34    case 3: bits = isl_format_layouts[format].channels.a.bits; break;
  35    default: unreachable("Invalid component");
  36    }
  37
  38    if (bits) {
  39       return VFCOMP_STORE_SRC;
  40    } else if (comp < 3) {
  41       return VFCOMP_STORE_0;
  42    } else if (isl_format_layouts[format].channels.r.type == ISL_UINT ||
  43             isl_format_layouts[format].channels.r.type == ISL_SINT) {
  44       assert(comp == 3);
  45       return VFCOMP_STORE_1_INT;
  46    } else {
  47       assert(comp == 3);
  48       return VFCOMP_STORE_1_FP;
  49    }
  50 }
  51
  52 static void
  53 emit_vertex_input(struct anv_pipeline *pipeline,
  54                   const VkPipelineVertexInputStateCreateInfo *info,
  55                   const struct anv_graphics_pipeline_create_info *extra)
  56 {
  57    const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
  58
  59    uint32_t elements;
  60    if (extra && extra->disable_vs) {
  61       /* If the VS is disabled, just assume the user knows what they're
  62        * doing and apply the layout blindly.  This can only come from
  63        * meta, so this *should* be safe.
  64        */
  65       elements = 0;
  66       for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++)
  67          elements |= (1 << info->pVertexAttributeDescriptions[i].location);
  68    } else {
  69       /* Pull inputs_read out of the VS prog data */
  70       uint64_t inputs_read = vs_prog_data->inputs_read;
  71       assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
  72       elements = inputs_read >> VERT_ATTRIB_GENERIC0;
  73    }
  74
  75 #if GEN_GEN >= 8
  76    /* On BDW+, we only need to allocate space for base ids.  Setting up
  77     * the actual vertex and instance id is a separate packet.
  78     */
  79    const bool needs_svgs_elem = vs_prog_data->uses_basevertex ||
  80                                 vs_prog_data->uses_baseinstance;
  81 #else
  82    /* On Haswell and prior, vertex and instance id are created by using the
  83     * ComponentControl fields, so we need an element for any of them.
  84     */
  85    const bool needs_svgs_elem = vs_prog_data->uses_vertexid ||
  86                                 vs_prog_data->uses_instanceid ||
  87                                 vs_prog_data->uses_basevertex ||
  88                                 vs_prog_data->uses_baseinstance;
  89 #endif
  90
  91    uint32_t elem_count = __builtin_popcount(elements) + needs_svgs_elem;
  92    if (elem_count == 0)
  93       return;
  94
  95    uint32_t *p;
  96
  97    const uint32_t num_dwords = 1 + elem_count * 2;
  98    p = anv_batch_emitn(&pipeline->batch, num_dwords,
  99                        GENX(3DSTATE_VERTEX_ELEMENTS));
 100    memset(p + 1, 0, (num_dwords - 1) * 4);
 101
 102    for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
 103       const VkVertexInputAttributeDescription *desc =
 104          &info->pVertexAttributeDescriptions[i];
 105       enum isl_format format = anv_get_isl_format(&pipeline->device->info,
 106                                                   desc->format,
 107                                                   VK_IMAGE_ASPECT_COLOR_BIT,
 108                                                   VK_IMAGE_TILING_LINEAR);
 109
 110       assert(desc->binding < 32);
 111
 112       if ((elements & (1 << desc->location)) == 0)
 113          continue; /* Binding unused */
 114
 115       uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1));
 116
 117       struct GENX(VERTEX_ELEMENT_STATE) element = {
 118          .VertexBufferIndex = desc->binding,
 119          .Valid = true,
 120          .SourceElementFormat = format,
 121          .EdgeFlagEnable = false,
 122          .SourceElementOffset = desc->offset,
 123          .Component0Control = vertex_element_comp_control(format, 0),
 124          .Component1Control = vertex_element_comp_control(format, 1),
 125          .Component2Control = vertex_element_comp_control(format, 2),
 126          .Component3Control = vertex_element_comp_control(format, 3),
 127       };
 128       GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element);
 129
 130 #if GEN_GEN >= 8
 131       /* On Broadwell and later, we have a separate VF_INSTANCING packet
 132        * that controls instancing.  On Haswell and prior, that's part of
 133        * VERTEX_BUFFER_STATE which we emit later.
 134        */
 135       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
 136          vfi.InstancingEnable = pipeline->instancing_enable[desc->binding],
 137          vfi.VertexElementIndex = slot,
 138          /* Vulkan so far doesn't have an instance divisor, so
 139           * this is always 1 (ignored if not instancing). */
 140          vfi.InstanceDataStepRate = 1;
 141       }
 142 #endif
 143    }
 144
 145    const uint32_t id_slot = __builtin_popcount(elements);
 146    if (needs_svgs_elem) {
 147       /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
 148        *    "Within a VERTEX_ELEMENT_STATE structure, if a Component
 149        *    Control field is set to something other than VFCOMP_STORE_SRC,
 150        *    no higher-numbered Component Control fields may be set to
 151        *    VFCOMP_STORE_SRC"
 152        *
 153        * This means, that if we have BaseInstance, we need BaseVertex as
 154        * well.  Just do all or nothing.
 155        */
 156       uint32_t base_ctrl = (vs_prog_data->uses_basevertex ||
 157                             vs_prog_data->uses_baseinstance) ?
 158                            VFCOMP_STORE_SRC : VFCOMP_STORE_0;
 159
 160       struct GENX(VERTEX_ELEMENT_STATE) element = {
 161          .VertexBufferIndex = 32, /* Reserved for this */
 162          .Valid = true,
 163          .SourceElementFormat = ISL_FORMAT_R32G32_UINT,
 164          .Component0Control = base_ctrl,
 165          .Component1Control = base_ctrl,
 166 #if GEN_GEN >= 8
 167          .Component2Control = VFCOMP_STORE_0,
 168          .Component3Control = VFCOMP_STORE_0,
 169 #else
 170          .Component2Control = VFCOMP_STORE_VID,
 171          .Component3Control = VFCOMP_STORE_IID,
 172 #endif
 173       };
 174       GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + id_slot * 2], &element);
 175    }
 176
 177 #if GEN_GEN >= 8
 178    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS), sgvs) {
 179       sgvs.VertexIDEnable              = vs_prog_data->uses_vertexid;
 180       sgvs.VertexIDComponentNumber     = 2;
 181       sgvs.VertexIDElementOffset       = id_slot;
 182       sgvs.InstanceIDEnable            = vs_prog_data->uses_instanceid;
 183       sgvs.InstanceIDComponentNumber   = 3;
 184       sgvs.InstanceIDElementOffset     = id_slot;
 185    }
 186 #endif
 187 }
 188
 189 static inline void
 190 emit_urb_setup(struct anv_pipeline *pipeline)
 191 {
 192 #if GEN_GEN == 7 && !GEN_IS_HASWELL
 193    struct anv_device *device = pipeline->device;
 194
 195    /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
 196     *
 197     *    "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
 198     *    needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 199     *    3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 200     *    3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL
 201     *    needs to be sent before any combination of VS associated 3DSTATE."
 202     */
 203    anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL, pc) {
 204       pc.DepthStallEnable  = true;
 205       pc.PostSyncOperation = WriteImmediateData;
 206       pc.Address           = (struct anv_address) { &device->workaround_bo, 0 };
 207    }
 208 #endif
 209
 210    for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
 211       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_VS), urb) {
 212          urb._3DCommandSubOpcode       = 48 + i;
 213          urb.VSURBStartingAddress      = pipeline->urb.start[i];
 214          urb.VSURBEntryAllocationSize  = pipeline->urb.size[i] - 1;
 215          urb.VSNumberofURBEntries      = pipeline->urb.entries[i];
 216       }
 217    }
 218 }
 219
 220 static void
 221 emit_3dstate_sbe(struct anv_pipeline *pipeline)
 222 {
 223    const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
 224    const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 225    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 226    const struct brw_vue_map *fs_input_map;
 227
 228    if (pipeline->gs_kernel == NO_KERNEL)
 229       fs_input_map = &vs_prog_data->base.vue_map;
 230    else
 231       fs_input_map = &gs_prog_data->base.vue_map;
 232
 233    struct GENX(3DSTATE_SBE) sbe = {
 234       GENX(3DSTATE_SBE_header),
 235       .AttributeSwizzleEnable = true,
 236       .PointSpriteTextureCoordinateOrigin = UPPERLEFT,
 237       .NumberofSFOutputAttributes = wm_prog_data->num_varying_inputs,
 238       .ConstantInterpolationEnable = wm_prog_data->flat_inputs,
 239
 240 #if GEN_GEN >= 9
 241       .Attribute0ActiveComponentFormat = ACF_XYZW,
 242       .Attribute1ActiveComponentFormat = ACF_XYZW,
 243       .Attribute2ActiveComponentFormat = ACF_XYZW,
 244       .Attribute3ActiveComponentFormat = ACF_XYZW,
 245       .Attribute4ActiveComponentFormat = ACF_XYZW,
 246       .Attribute5ActiveComponentFormat = ACF_XYZW,
 247       .Attribute6ActiveComponentFormat = ACF_XYZW,
 248       .Attribute7ActiveComponentFormat = ACF_XYZW,
 249       .Attribute8ActiveComponentFormat = ACF_XYZW,
 250       .Attribute9ActiveComponentFormat = ACF_XYZW,
 251       .Attribute10ActiveComponentFormat = ACF_XYZW,
 252       .Attribute11ActiveComponentFormat = ACF_XYZW,
 253       .Attribute12ActiveComponentFormat = ACF_XYZW,
 254       .Attribute13ActiveComponentFormat = ACF_XYZW,
 255       .Attribute14ActiveComponentFormat = ACF_XYZW,
 256       .Attribute15ActiveComponentFormat = ACF_XYZW,
 257       /* wow, much field, very attribute */
 258       .Attribute16ActiveComponentFormat = ACF_XYZW,
 259       .Attribute17ActiveComponentFormat = ACF_XYZW,
 260       .Attribute18ActiveComponentFormat = ACF_XYZW,
 261       .Attribute19ActiveComponentFormat = ACF_XYZW,
 262       .Attribute20ActiveComponentFormat = ACF_XYZW,
 263       .Attribute21ActiveComponentFormat = ACF_XYZW,
 264       .Attribute22ActiveComponentFormat = ACF_XYZW,
 265       .Attribute23ActiveComponentFormat = ACF_XYZW,
 266       .Attribute24ActiveComponentFormat = ACF_XYZW,
 267       .Attribute25ActiveComponentFormat = ACF_XYZW,
 268       .Attribute26ActiveComponentFormat = ACF_XYZW,
 269       .Attribute27ActiveComponentFormat = ACF_XYZW,
 270       .Attribute28ActiveComponentFormat = ACF_XYZW,
 271       .Attribute29ActiveComponentFormat = ACF_XYZW,
 272       .Attribute28ActiveComponentFormat = ACF_XYZW,
 273       .Attribute29ActiveComponentFormat = ACF_XYZW,
 274       .Attribute30ActiveComponentFormat = ACF_XYZW,
 275 #endif
 276    };
 277
 278 #if GEN_GEN >= 8
 279    /* On Broadwell, they broke 3DSTATE_SBE into two packets */
 280    struct GENX(3DSTATE_SBE_SWIZ) swiz = {
 281       GENX(3DSTATE_SBE_SWIZ_header),
 282    };
 283 #else
 284 #  define swiz sbe
 285 #endif
 286
 287    int max_source_attr = 0;
 288    for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 289       int input_index = wm_prog_data->urb_setup[attr];
 290
 291       if (input_index < 0)
 292          continue;
 293
 294       const int slot = fs_input_map->varying_to_slot[attr];
 295
 296       if (input_index >= 16)
 297          continue;
 298
 299       if (slot == -1) {
 300          /* This attribute does not exist in the VUE--that means that the
 301           * vertex shader did not write to it.  It could be that it's a
 302           * regular varying read by the fragment shader but not written by
 303           * the vertex shader or it's gl_PrimitiveID. In the first case the
 304           * value is undefined, in the second it needs to be
 305           * gl_PrimitiveID.
 306           */
 307          swiz.Attribute[input_index].ConstantSource = PRIM_ID;
 308          swiz.Attribute[input_index].ComponentOverrideX = true;
 309          swiz.Attribute[input_index].ComponentOverrideY = true;
 310          swiz.Attribute[input_index].ComponentOverrideZ = true;
 311          swiz.Attribute[input_index].ComponentOverrideW = true;
 312       } else {
 313          assert(slot >= 2);
 314          const int source_attr = slot - 2;
 315          max_source_attr = MAX2(max_source_attr, source_attr);
 316          /* We have to subtract two slots to accout for the URB entry output
 317           * read offset in the VS and GS stages.
 318           */
 319          swiz.Attribute[input_index].SourceAttribute = source_attr;
 320       }
 321    }
 322
 323    sbe.VertexURBEntryReadOffset = 1; /* Skip the VUE header and position slots */
 324    sbe.VertexURBEntryReadLength = DIV_ROUND_UP(max_source_attr + 1, 2);
 325
 326    uint32_t *dw = anv_batch_emit_dwords(&pipeline->batch,
 327                                         GENX(3DSTATE_SBE_length));
 328    GENX(3DSTATE_SBE_pack)(&pipeline->batch, dw, &sbe);
 329
 330 #if GEN_GEN >= 8
 331    dw = anv_batch_emit_dwords(&pipeline->batch, GENX(3DSTATE_SBE_SWIZ_length));
 332    GENX(3DSTATE_SBE_SWIZ_pack)(&pipeline->batch, dw, &swiz);
 333 #endif
 334 }
 335
 336 static inline uint32_t
 337 scratch_space(const struct brw_stage_prog_data *prog_data)
 338 {
 339    return ffs(prog_data->total_scratch / 2048);
 340 }
 341
 342 static const uint32_t vk_to_gen_cullmode[] = {
 343    [VK_CULL_MODE_NONE]                       = CULLMODE_NONE,
 344    [VK_CULL_MODE_FRONT_BIT]                  = CULLMODE_FRONT,
 345    [VK_CULL_MODE_BACK_BIT]                   = CULLMODE_BACK,
 346    [VK_CULL_MODE_FRONT_AND_BACK]             = CULLMODE_BOTH
 347 };
 348
 349 static const uint32_t vk_to_gen_fillmode[] = {
 350    [VK_POLYGON_MODE_FILL]                    = FILL_MODE_SOLID,
 351    [VK_POLYGON_MODE_LINE]                    = FILL_MODE_WIREFRAME,
 352    [VK_POLYGON_MODE_POINT]                   = FILL_MODE_POINT,
 353 };
 354
 355 static const uint32_t vk_to_gen_front_face[] = {
 356    [VK_FRONT_FACE_COUNTER_CLOCKWISE]         = 1,
 357    [VK_FRONT_FACE_CLOCKWISE]                 = 0
 358 };
 359
 360 static const uint32_t vk_to_gen_logic_op[] = {
 361    [VK_LOGIC_OP_COPY]                        = LOGICOP_COPY,
 362    [VK_LOGIC_OP_CLEAR]                       = LOGICOP_CLEAR,
 363    [VK_LOGIC_OP_AND]                         = LOGICOP_AND,
 364    [VK_LOGIC_OP_AND_REVERSE]                 = LOGICOP_AND_REVERSE,
 365    [VK_LOGIC_OP_AND_INVERTED]                = LOGICOP_AND_INVERTED,
 366    [VK_LOGIC_OP_NO_OP]                       = LOGICOP_NOOP,
 367    [VK_LOGIC_OP_XOR]                         = LOGICOP_XOR,
 368    [VK_LOGIC_OP_OR]                          = LOGICOP_OR,
 369    [VK_LOGIC_OP_NOR]                         = LOGICOP_NOR,
 370    [VK_LOGIC_OP_EQUIVALENT]                  = LOGICOP_EQUIV,
 371    [VK_LOGIC_OP_INVERT]                      = LOGICOP_INVERT,
 372    [VK_LOGIC_OP_OR_REVERSE]                  = LOGICOP_OR_REVERSE,
 373    [VK_LOGIC_OP_COPY_INVERTED]               = LOGICOP_COPY_INVERTED,
 374    [VK_LOGIC_OP_OR_INVERTED]                 = LOGICOP_OR_INVERTED,
 375    [VK_LOGIC_OP_NAND]                        = LOGICOP_NAND,
 376    [VK_LOGIC_OP_SET]                         = LOGICOP_SET,
 377 };
 378
 379 static const uint32_t vk_to_gen_blend[] = {
 380    [VK_BLEND_FACTOR_ZERO]                    = BLENDFACTOR_ZERO,
 381    [VK_BLEND_FACTOR_ONE]                     = BLENDFACTOR_ONE,
 382    [VK_BLEND_FACTOR_SRC_COLOR]               = BLENDFACTOR_SRC_COLOR,
 383    [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR]     = BLENDFACTOR_INV_SRC_COLOR,
 384    [VK_BLEND_FACTOR_DST_COLOR]               = BLENDFACTOR_DST_COLOR,
 385    [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR]     = BLENDFACTOR_INV_DST_COLOR,
 386    [VK_BLEND_FACTOR_SRC_ALPHA]               = BLENDFACTOR_SRC_ALPHA,
 387    [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA]     = BLENDFACTOR_INV_SRC_ALPHA,
 388    [VK_BLEND_FACTOR_DST_ALPHA]               = BLENDFACTOR_DST_ALPHA,
 389    [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA]     = BLENDFACTOR_INV_DST_ALPHA,
 390    [VK_BLEND_FACTOR_CONSTANT_COLOR]          = BLENDFACTOR_CONST_COLOR,
 391    [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]= BLENDFACTOR_INV_CONST_COLOR,
 392    [VK_BLEND_FACTOR_CONSTANT_ALPHA]          = BLENDFACTOR_CONST_ALPHA,
 393    [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]= BLENDFACTOR_INV_CONST_ALPHA,
 394    [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE]      = BLENDFACTOR_SRC_ALPHA_SATURATE,
 395    [VK_BLEND_FACTOR_SRC1_COLOR]              = BLENDFACTOR_SRC1_COLOR,
 396    [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR]    = BLENDFACTOR_INV_SRC1_COLOR,
 397    [VK_BLEND_FACTOR_SRC1_ALPHA]              = BLENDFACTOR_SRC1_ALPHA,
 398    [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA]    = BLENDFACTOR_INV_SRC1_ALPHA,
 399 };
 400
 401 static const uint32_t vk_to_gen_blend_op[] = {
 402    [VK_BLEND_OP_ADD]                         = BLENDFUNCTION_ADD,
 403    [VK_BLEND_OP_SUBTRACT]                    = BLENDFUNCTION_SUBTRACT,
 404    [VK_BLEND_OP_REVERSE_SUBTRACT]            = BLENDFUNCTION_REVERSE_SUBTRACT,
 405    [VK_BLEND_OP_MIN]                         = BLENDFUNCTION_MIN,
 406    [VK_BLEND_OP_MAX]                         = BLENDFUNCTION_MAX,
 407 };
 408
 409 static const uint32_t vk_to_gen_compare_op[] = {
 410    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPNEVER,
 411    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLESS,
 412    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPEQUAL,
 413    [VK_COMPARE_OP_LESS_OR_EQUAL]                = PREFILTEROPLEQUAL,
 414    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGREATER,
 415    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPNOTEQUAL,
 416    [VK_COMPARE_OP_GREATER_OR_EQUAL]             = PREFILTEROPGEQUAL,
 417    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPALWAYS,
 418 };
 419
 420 static const uint32_t vk_to_gen_stencil_op[] = {
 421    [VK_STENCIL_OP_KEEP]                         = STENCILOP_KEEP,
 422    [VK_STENCIL_OP_ZERO]                         = STENCILOP_ZERO,
 423    [VK_STENCIL_OP_REPLACE]                      = STENCILOP_REPLACE,
 424    [VK_STENCIL_OP_INCREMENT_AND_CLAMP]          = STENCILOP_INCRSAT,
 425    [VK_STENCIL_OP_DECREMENT_AND_CLAMP]          = STENCILOP_DECRSAT,
 426    [VK_STENCIL_OP_INVERT]                       = STENCILOP_INVERT,
 427    [VK_STENCIL_OP_INCREMENT_AND_WRAP]           = STENCILOP_INCR,
 428    [VK_STENCIL_OP_DECREMENT_AND_WRAP]           = STENCILOP_DECR,
 429 };
 430
 431 static void
 432 emit_ds_state(struct anv_pipeline *pipeline,
 433               const VkPipelineDepthStencilStateCreateInfo *info,
 434               const struct anv_render_pass *pass,
 435               const struct anv_subpass *subpass)
 436 {
 437 #if GEN_GEN == 7
 438 #  define depth_stencil_dw pipeline->gen7.depth_stencil_state
 439 #elif GEN_GEN == 8
 440 #  define depth_stencil_dw pipeline->gen8.wm_depth_stencil
 441 #else
 442 #  define depth_stencil_dw pipeline->gen9.wm_depth_stencil
 443 #endif
 444
 445    if (info == NULL) {
 446       /* We're going to OR this together with the dynamic state.  We need
 447        * to make sure it's initialized to something useful.
 448        */
 449       memset(depth_stencil_dw, 0, sizeof(depth_stencil_dw));
 450       return;
 451    }
 452
 453    /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
 454
 455 #if GEN_GEN <= 7
 456    struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
 457 #else
 458    struct GENX(3DSTATE_WM_DEPTH_STENCIL) depth_stencil = {
 459 #endif
 460       .DepthTestEnable = info->depthTestEnable,
 461       .DepthBufferWriteEnable = info->depthWriteEnable,
 462       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
 463       .DoubleSidedStencilEnable = true,
 464
 465       .StencilTestEnable = info->stencilTestEnable,
 466       .StencilBufferWriteEnable = info->stencilTestEnable,
 467       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
 468       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
 469       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
 470       .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
 471       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
 472       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
 473       .BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info->back.depthFailOp],
 474       .BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
 475    };
 476
 477    VkImageAspectFlags aspects = 0;
 478    if (pass->attachments == NULL) {
 479       /* This comes from meta.  Assume we have verything. */
 480       aspects = VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT;
 481    } else if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
 482       VkFormat depth_stencil_format =
 483          pass->attachments[subpass->depth_stencil_attachment].format;
 484       aspects = vk_format_aspects(depth_stencil_format);
 485    }
 486
 487    /* The Vulkan spec requires that if either depth or stencil is not present,
 488     * the pipeline is to act as if the test silently passes.
 489     */
 490    if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
 491       depth_stencil.DepthBufferWriteEnable = false;
 492       depth_stencil.DepthTestFunction = PREFILTEROPALWAYS;
 493    }
 494
 495    if (!(aspects & VK_IMAGE_ASPECT_STENCIL_BIT)) {
 496       depth_stencil.StencilBufferWriteEnable = false;
 497       depth_stencil.StencilTestFunction = PREFILTEROPALWAYS;
 498       depth_stencil.BackfaceStencilTestFunction = PREFILTEROPALWAYS;
 499    }
 500
 501    /* From the Broadwell PRM:
 502     *
 503     *    "If Depth_Test_Enable = 1 AND Depth_Test_func = EQUAL, the
 504     *    Depth_Write_Enable must be set to 0."
 505     */
 506    if (info->depthTestEnable && info->depthCompareOp == VK_COMPARE_OP_EQUAL)
 507       depth_stencil.DepthBufferWriteEnable = false;
 508
 509 #if GEN_GEN <= 7
 510    GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
 511 #else
 512    GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, depth_stencil_dw, &depth_stencil);
 513 #endif
 514 }