2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 vertex_element_comp_control(enum isl_format format
, unsigned comp
)
29 case 0: bits
= isl_format_layouts
[format
].channels
.r
.bits
; break;
30 case 1: bits
= isl_format_layouts
[format
].channels
.g
.bits
; break;
31 case 2: bits
= isl_format_layouts
[format
].channels
.b
.bits
; break;
32 case 3: bits
= isl_format_layouts
[format
].channels
.a
.bits
; break;
33 default: unreachable("Invalid component");
37 return VFCOMP_STORE_SRC
;
38 } else if (comp
< 3) {
39 return VFCOMP_STORE_0
;
40 } else if (isl_format_layouts
[format
].channels
.r
.type
== ISL_UINT
||
41 isl_format_layouts
[format
].channels
.r
.type
== ISL_SINT
) {
43 return VFCOMP_STORE_1_INT
;
46 return VFCOMP_STORE_1_FP
;
51 emit_vertex_input(struct anv_pipeline
*pipeline
,
52 const VkPipelineVertexInputStateCreateInfo
*info
,
53 const struct anv_graphics_pipeline_create_info
*extra
)
55 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
58 if (extra
&& extra
->disable_vs
) {
59 /* If the VS is disabled, just assume the user knows what they're
60 * doing and apply the layout blindly. This can only come from
61 * meta, so this *should* be safe.
64 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++)
65 elements
|= (1 << info
->pVertexAttributeDescriptions
[i
].location
);
67 /* Pull inputs_read out of the VS prog data */
68 uint64_t inputs_read
= vs_prog_data
->inputs_read
;
69 assert((inputs_read
& ((1 << VERT_ATTRIB_GENERIC0
) - 1)) == 0);
70 elements
= inputs_read
>> VERT_ATTRIB_GENERIC0
;
74 /* On BDW+, we only need to allocate space for base ids. Setting up
75 * the actual vertex and instance id is a separate packet.
77 const bool needs_svgs_elem
= vs_prog_data
->uses_basevertex
||
78 vs_prog_data
->uses_baseinstance
;
80 /* On Haswell and prior, vertex and instance id are created by using the
81 * ComponentControl fields, so we need an element for any of them.
83 const bool needs_svgs_elem
= vs_prog_data
->uses_vertexid
||
84 vs_prog_data
->uses_instanceid
||
85 vs_prog_data
->uses_basevertex
||
86 vs_prog_data
->uses_baseinstance
;
89 uint32_t elem_count
= __builtin_popcount(elements
) + needs_svgs_elem
;
95 const uint32_t num_dwords
= 1 + elem_count
* 2;
96 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
97 GENX(3DSTATE_VERTEX_ELEMENTS
));
98 memset(p
+ 1, 0, (num_dwords
- 1) * 4);
100 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
101 const VkVertexInputAttributeDescription
*desc
=
102 &info
->pVertexAttributeDescriptions
[i
];
103 enum isl_format format
= anv_get_isl_format(desc
->format
,
104 VK_IMAGE_ASPECT_COLOR_BIT
,
105 VK_IMAGE_TILING_LINEAR
,
108 assert(desc
->binding
< 32);
110 if ((elements
& (1 << desc
->location
)) == 0)
111 continue; /* Binding unused */
113 uint32_t slot
= __builtin_popcount(elements
& ((1 << desc
->location
) - 1));
115 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
116 .VertexBufferIndex
= desc
->binding
,
118 .SourceElementFormat
= format
,
119 .EdgeFlagEnable
= false,
120 .SourceElementOffset
= desc
->offset
,
121 .Component0Control
= vertex_element_comp_control(format
, 0),
122 .Component1Control
= vertex_element_comp_control(format
, 1),
123 .Component2Control
= vertex_element_comp_control(format
, 2),
124 .Component3Control
= vertex_element_comp_control(format
, 3),
126 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + slot
* 2], &element
);
129 /* On Broadwell and later, we have a separate VF_INSTANCING packet
130 * that controls instancing. On Haswell and prior, that's part of
131 * VERTEX_BUFFER_STATE which we emit later.
133 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_INSTANCING
),
134 .InstancingEnable
= pipeline
->instancing_enable
[desc
->binding
],
135 .VertexElementIndex
= slot
,
136 /* Vulkan so far doesn't have an instance divisor, so
137 * this is always 1 (ignored if not instancing). */
138 .InstanceDataStepRate
= 1);
142 const uint32_t id_slot
= __builtin_popcount(elements
);
143 if (needs_svgs_elem
) {
144 /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
145 * "Within a VERTEX_ELEMENT_STATE structure, if a Component
146 * Control field is set to something other than VFCOMP_STORE_SRC,
147 * no higher-numbered Component Control fields may be set to
150 * This means, that if we have BaseInstance, we need BaseVertex as
151 * well. Just do all or nothing.
153 uint32_t base_ctrl
= (vs_prog_data
->uses_basevertex
||
154 vs_prog_data
->uses_baseinstance
) ?
155 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
157 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
158 .VertexBufferIndex
= 32, /* Reserved for this */
160 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
161 .Component0Control
= base_ctrl
,
162 .Component1Control
= base_ctrl
,
164 .Component2Control
= VFCOMP_STORE_0
,
165 .Component3Control
= VFCOMP_STORE_0
,
167 .Component2Control
= VFCOMP_STORE_VID
,
168 .Component3Control
= VFCOMP_STORE_IID
,
171 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + id_slot
* 2], &element
);
175 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_SGVS
),
176 .VertexIDEnable
= vs_prog_data
->uses_vertexid
,
177 .VertexIDComponentNumber
= 2,
178 .VertexIDElementOffset
= id_slot
,
179 .InstanceIDEnable
= vs_prog_data
->uses_instanceid
,
180 .InstanceIDComponentNumber
= 3,
181 .InstanceIDElementOffset
= id_slot
);
186 emit_urb_setup(struct anv_pipeline
*pipeline
)
188 #if GEN_GEN == 7 && !GEN_IS_HASWELL
189 struct anv_device
*device
= pipeline
->device
;
191 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
193 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
194 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
195 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
196 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
197 * needs to be sent before any combination of VS associated 3DSTATE."
199 anv_batch_emit(&pipeline
->batch
, GEN7_PIPE_CONTROL
,
200 .DepthStallEnable
= true,
201 .PostSyncOperation
= WriteImmediateData
,
202 .Address
= { &device
->workaround_bo
, 0 });
205 unsigned push_start
= 0;
206 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_FRAGMENT
; i
++) {
207 unsigned push_size
= pipeline
->urb
.push_size
[i
];
208 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
),
209 ._3DCommandSubOpcode
= 18 + i
,
210 .ConstantBufferOffset
= (push_size
> 0) ? push_start
: 0,
211 .ConstantBufferSize
= push_size
);
212 push_start
+= pipeline
->urb
.push_size
[i
];
215 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
216 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_URB_VS
),
217 ._3DCommandSubOpcode
= 48 + i
,
218 .VSURBStartingAddress
= pipeline
->urb
.start
[i
],
219 .VSURBEntryAllocationSize
= pipeline
->urb
.size
[i
] - 1,
220 .VSNumberofURBEntries
= pipeline
->urb
.entries
[i
]);
225 emit_3dstate_sbe(struct anv_pipeline
*pipeline
)
227 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
228 const struct brw_gs_prog_data
*gs_prog_data
= get_gs_prog_data(pipeline
);
229 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
230 const struct brw_vue_map
*fs_input_map
;
232 if (pipeline
->gs_kernel
== NO_KERNEL
)
233 fs_input_map
= &vs_prog_data
->base
.vue_map
;
235 fs_input_map
= &gs_prog_data
->base
.vue_map
;
237 struct GENX(3DSTATE_SBE
) sbe
= {
238 GENX(3DSTATE_SBE_header
),
239 .AttributeSwizzleEnable
= true,
240 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
,
241 .NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
,
244 .Attribute0ActiveComponentFormat
= ACF_XYZW
,
245 .Attribute1ActiveComponentFormat
= ACF_XYZW
,
246 .Attribute2ActiveComponentFormat
= ACF_XYZW
,
247 .Attribute3ActiveComponentFormat
= ACF_XYZW
,
248 .Attribute4ActiveComponentFormat
= ACF_XYZW
,
249 .Attribute5ActiveComponentFormat
= ACF_XYZW
,
250 .Attribute6ActiveComponentFormat
= ACF_XYZW
,
251 .Attribute7ActiveComponentFormat
= ACF_XYZW
,
252 .Attribute8ActiveComponentFormat
= ACF_XYZW
,
253 .Attribute9ActiveComponentFormat
= ACF_XYZW
,
254 .Attribute10ActiveComponentFormat
= ACF_XYZW
,
255 .Attribute11ActiveComponentFormat
= ACF_XYZW
,
256 .Attribute12ActiveComponentFormat
= ACF_XYZW
,
257 .Attribute13ActiveComponentFormat
= ACF_XYZW
,
258 .Attribute14ActiveComponentFormat
= ACF_XYZW
,
259 .Attribute15ActiveComponentFormat
= ACF_XYZW
,
260 /* wow, much field, very attribute */
261 .Attribute16ActiveComponentFormat
= ACF_XYZW
,
262 .Attribute17ActiveComponentFormat
= ACF_XYZW
,
263 .Attribute18ActiveComponentFormat
= ACF_XYZW
,
264 .Attribute19ActiveComponentFormat
= ACF_XYZW
,
265 .Attribute20ActiveComponentFormat
= ACF_XYZW
,
266 .Attribute21ActiveComponentFormat
= ACF_XYZW
,
267 .Attribute22ActiveComponentFormat
= ACF_XYZW
,
268 .Attribute23ActiveComponentFormat
= ACF_XYZW
,
269 .Attribute24ActiveComponentFormat
= ACF_XYZW
,
270 .Attribute25ActiveComponentFormat
= ACF_XYZW
,
271 .Attribute26ActiveComponentFormat
= ACF_XYZW
,
272 .Attribute27ActiveComponentFormat
= ACF_XYZW
,
273 .Attribute28ActiveComponentFormat
= ACF_XYZW
,
274 .Attribute29ActiveComponentFormat
= ACF_XYZW
,
275 .Attribute28ActiveComponentFormat
= ACF_XYZW
,
276 .Attribute29ActiveComponentFormat
= ACF_XYZW
,
277 .Attribute30ActiveComponentFormat
= ACF_XYZW
,
282 /* On Broadwell, they broke 3DSTATE_SBE into two packets */
283 struct GENX(3DSTATE_SBE_SWIZ
) swiz
= {
284 GENX(3DSTATE_SBE_SWIZ_header
),
290 int max_source_attr
= 0;
291 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
292 int input_index
= wm_prog_data
->urb_setup
[attr
];
297 const int slot
= fs_input_map
->varying_to_slot
[attr
];
299 if (input_index
>= 16)
303 /* This attribute does not exist in the VUE--that means that the
304 * vertex shader did not write to it. It could be that it's a
305 * regular varying read by the fragment shader but not written by
306 * the vertex shader or it's gl_PrimitiveID. In the first case the
307 * value is undefined, in the second it needs to be
310 swiz
.Attribute
[input_index
].ConstantSource
= PRIM_ID
;
311 swiz
.Attribute
[input_index
].ComponentOverrideX
= true;
312 swiz
.Attribute
[input_index
].ComponentOverrideY
= true;
313 swiz
.Attribute
[input_index
].ComponentOverrideZ
= true;
314 swiz
.Attribute
[input_index
].ComponentOverrideW
= true;
317 const int source_attr
= slot
- 2;
318 max_source_attr
= MAX2(max_source_attr
, source_attr
);
319 /* We have to subtract two slots to accout for the URB entry output
320 * read offset in the VS and GS stages.
322 swiz
.Attribute
[input_index
].SourceAttribute
= source_attr
;
326 sbe
.VertexURBEntryReadOffset
= 1; /* Skip the VUE header and position slots */
327 sbe
.VertexURBEntryReadLength
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
329 uint32_t *dw
= anv_batch_emit_dwords(&pipeline
->batch
,
330 GENX(3DSTATE_SBE_length
));
331 GENX(3DSTATE_SBE_pack
)(&pipeline
->batch
, dw
, &sbe
);
334 dw
= anv_batch_emit_dwords(&pipeline
->batch
, GENX(3DSTATE_SBE_SWIZ_length
));
335 GENX(3DSTATE_SBE_SWIZ_pack
)(&pipeline
->batch
, dw
, &swiz
);
339 static inline uint32_t
340 scratch_space(const struct brw_stage_prog_data
*prog_data
)
342 return ffs(prog_data
->total_scratch
/ 2048);
345 static const uint32_t vk_to_gen_cullmode
[] = {
346 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
347 [VK_CULL_MODE_FRONT_BIT
] = CULLMODE_FRONT
,
348 [VK_CULL_MODE_BACK_BIT
] = CULLMODE_BACK
,
349 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
352 static const uint32_t vk_to_gen_fillmode
[] = {
353 [VK_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
354 [VK_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
355 [VK_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
358 static const uint32_t vk_to_gen_front_face
[] = {
359 [VK_FRONT_FACE_COUNTER_CLOCKWISE
] = 1,
360 [VK_FRONT_FACE_CLOCKWISE
] = 0
363 static const uint32_t vk_to_gen_logic_op
[] = {
364 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
365 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
366 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
367 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
368 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
369 [VK_LOGIC_OP_NO_OP
] = LOGICOP_NOOP
,
370 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
371 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
372 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
373 [VK_LOGIC_OP_EQUIVALENT
] = LOGICOP_EQUIV
,
374 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
375 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
376 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
377 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
378 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
379 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
382 static const uint32_t vk_to_gen_blend
[] = {
383 [VK_BLEND_FACTOR_ZERO
] = BLENDFACTOR_ZERO
,
384 [VK_BLEND_FACTOR_ONE
] = BLENDFACTOR_ONE
,
385 [VK_BLEND_FACTOR_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
386 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
387 [VK_BLEND_FACTOR_DST_COLOR
] = BLENDFACTOR_DST_COLOR
,
388 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
389 [VK_BLEND_FACTOR_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
390 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
391 [VK_BLEND_FACTOR_DST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
392 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
393 [VK_BLEND_FACTOR_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
394 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
]= BLENDFACTOR_INV_CONST_COLOR
,
395 [VK_BLEND_FACTOR_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
396 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
]= BLENDFACTOR_INV_CONST_ALPHA
,
397 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
398 [VK_BLEND_FACTOR_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
399 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
400 [VK_BLEND_FACTOR_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
401 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
404 static const uint32_t vk_to_gen_blend_op
[] = {
405 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
406 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
407 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
408 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
409 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
412 static const uint32_t vk_to_gen_compare_op
[] = {
413 [VK_COMPARE_OP_NEVER
] = PREFILTEROPNEVER
,
414 [VK_COMPARE_OP_LESS
] = PREFILTEROPLESS
,
415 [VK_COMPARE_OP_EQUAL
] = PREFILTEROPEQUAL
,
416 [VK_COMPARE_OP_LESS_OR_EQUAL
] = PREFILTEROPLEQUAL
,
417 [VK_COMPARE_OP_GREATER
] = PREFILTEROPGREATER
,
418 [VK_COMPARE_OP_NOT_EQUAL
] = PREFILTEROPNOTEQUAL
,
419 [VK_COMPARE_OP_GREATER_OR_EQUAL
] = PREFILTEROPGEQUAL
,
420 [VK_COMPARE_OP_ALWAYS
] = PREFILTEROPALWAYS
,
423 static const uint32_t vk_to_gen_stencil_op
[] = {
424 [VK_STENCIL_OP_KEEP
] = STENCILOP_KEEP
,
425 [VK_STENCIL_OP_ZERO
] = STENCILOP_ZERO
,
426 [VK_STENCIL_OP_REPLACE
] = STENCILOP_REPLACE
,
427 [VK_STENCIL_OP_INCREMENT_AND_CLAMP
] = STENCILOP_INCRSAT
,
428 [VK_STENCIL_OP_DECREMENT_AND_CLAMP
] = STENCILOP_DECRSAT
,
429 [VK_STENCIL_OP_INVERT
] = STENCILOP_INVERT
,
430 [VK_STENCIL_OP_INCREMENT_AND_WRAP
] = STENCILOP_INCR
,
431 [VK_STENCIL_OP_DECREMENT_AND_WRAP
] = STENCILOP_DECR
,