2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 vertex_element_comp_control(enum isl_format format
, unsigned comp
)
29 case 0: bits
= isl_format_layouts
[format
].channels
.r
.bits
; break;
30 case 1: bits
= isl_format_layouts
[format
].channels
.g
.bits
; break;
31 case 2: bits
= isl_format_layouts
[format
].channels
.b
.bits
; break;
32 case 3: bits
= isl_format_layouts
[format
].channels
.a
.bits
; break;
33 default: unreachable("Invalid component");
37 return VFCOMP_STORE_SRC
;
38 } else if (comp
< 3) {
39 return VFCOMP_STORE_0
;
40 } else if (isl_format_layouts
[format
].channels
.r
.type
== ISL_UINT
||
41 isl_format_layouts
[format
].channels
.r
.type
== ISL_SINT
) {
43 return VFCOMP_STORE_1_INT
;
46 return VFCOMP_STORE_1_FP
;
51 emit_vertex_input(struct anv_pipeline
*pipeline
,
52 const VkPipelineVertexInputStateCreateInfo
*info
,
53 const struct anv_graphics_pipeline_create_info
*extra
)
56 if (extra
&& extra
->disable_vs
) {
57 /* If the VS is disabled, just assume the user knows what they're
58 * doing and apply the layout blindly. This can only come from
59 * meta, so this *should* be safe.
62 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++)
63 elements
|= (1 << info
->pVertexAttributeDescriptions
[i
].location
);
65 /* Pull inputs_read out of the VS prog data */
66 uint64_t inputs_read
= pipeline
->vs_prog_data
.inputs_read
;
67 assert((inputs_read
& ((1 << VERT_ATTRIB_GENERIC0
) - 1)) == 0);
68 elements
= inputs_read
>> VERT_ATTRIB_GENERIC0
;
72 /* On BDW+, we only need to allocate space for base ids. Setting up
73 * the actual vertex and instance id is a separate packet.
75 const bool needs_svgs_elem
= pipeline
->vs_prog_data
.uses_basevertex
||
76 pipeline
->vs_prog_data
.uses_baseinstance
;
78 /* On Haswell and prior, vertex and instance id are created by using the
79 * ComponentControl fields, so we need an element for any of them.
81 const bool needs_svgs_elem
= pipeline
->vs_prog_data
.uses_vertexid
||
82 pipeline
->vs_prog_data
.uses_instanceid
||
83 pipeline
->vs_prog_data
.uses_basevertex
||
84 pipeline
->vs_prog_data
.uses_baseinstance
;
87 uint32_t elem_count
= __builtin_popcount(elements
) + needs_svgs_elem
;
93 const uint32_t num_dwords
= 1 + elem_count
* 2;
94 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
95 GENX(3DSTATE_VERTEX_ELEMENTS
));
96 memset(p
+ 1, 0, (num_dwords
- 1) * 4);
98 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
99 const VkVertexInputAttributeDescription
*desc
=
100 &info
->pVertexAttributeDescriptions
[i
];
101 enum isl_format format
= anv_get_isl_format(desc
->format
,
102 VK_IMAGE_ASPECT_COLOR_BIT
,
103 VK_IMAGE_TILING_LINEAR
,
106 assert(desc
->binding
< 32);
108 if ((elements
& (1 << desc
->location
)) == 0)
109 continue; /* Binding unused */
111 uint32_t slot
= __builtin_popcount(elements
& ((1 << desc
->location
) - 1));
113 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
114 .VertexBufferIndex
= desc
->binding
,
116 .SourceElementFormat
= format
,
117 .EdgeFlagEnable
= false,
118 .SourceElementOffset
= desc
->offset
,
119 .Component0Control
= vertex_element_comp_control(format
, 0),
120 .Component1Control
= vertex_element_comp_control(format
, 1),
121 .Component2Control
= vertex_element_comp_control(format
, 2),
122 .Component3Control
= vertex_element_comp_control(format
, 3),
124 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + slot
* 2], &element
);
127 /* On Broadwell and later, we have a separate VF_INSTANCING packet
128 * that controls instancing. On Haswell and prior, that's part of
129 * VERTEX_BUFFER_STATE which we emit later.
131 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_INSTANCING
),
132 .InstancingEnable
= pipeline
->instancing_enable
[desc
->binding
],
133 .VertexElementIndex
= slot
,
134 /* Vulkan so far doesn't have an instance divisor, so
135 * this is always 1 (ignored if not instancing). */
136 .InstanceDataStepRate
= 1);
140 const uint32_t id_slot
= __builtin_popcount(elements
);
141 if (needs_svgs_elem
) {
142 /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
143 * "Within a VERTEX_ELEMENT_STATE structure, if a Component
144 * Control field is set to something other than VFCOMP_STORE_SRC,
145 * no higher-numbered Component Control fields may be set to
148 * This means, that if we have BaseInstance, we need BaseVertex as
149 * well. Just do all or nothing.
151 uint32_t base_ctrl
= (pipeline
->vs_prog_data
.uses_basevertex
||
152 pipeline
->vs_prog_data
.uses_baseinstance
) ?
153 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
155 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
156 .VertexBufferIndex
= 32, /* Reserved for this */
158 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
159 .Component0Control
= base_ctrl
,
160 .Component1Control
= base_ctrl
,
162 .Component2Control
= VFCOMP_STORE_0
,
163 .Component3Control
= VFCOMP_STORE_0
,
165 .Component2Control
= VFCOMP_STORE_VID
,
166 .Component3Control
= VFCOMP_STORE_IID
,
169 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + id_slot
* 2], &element
);
173 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_SGVS
),
174 .VertexIDEnable
= pipeline
->vs_prog_data
.uses_vertexid
,
175 .VertexIDComponentNumber
= 2,
176 .VertexIDElementOffset
= id_slot
,
177 .InstanceIDEnable
= pipeline
->vs_prog_data
.uses_instanceid
,
178 .InstanceIDComponentNumber
= 3,
179 .InstanceIDElementOffset
= id_slot
);
184 emit_urb_setup(struct anv_pipeline
*pipeline
)
186 #if GEN_GEN == 7 && !GEN_IS_HASWELL
187 struct anv_device
*device
= pipeline
->device
;
189 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
191 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
192 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
193 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
194 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
195 * needs to be sent before any combination of VS associated 3DSTATE."
197 anv_batch_emit(&pipeline
->batch
, GEN7_PIPE_CONTROL
,
198 .DepthStallEnable
= true,
199 .PostSyncOperation
= WriteImmediateData
,
200 .Address
= { &device
->workaround_bo
, 0 });
203 unsigned push_start
= 0;
204 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_FRAGMENT
; i
++) {
205 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
),
206 ._3DCommandSubOpcode
= 18 + i
,
207 .ConstantBufferOffset
= push_start
,
208 .ConstantBufferSize
= pipeline
->urb
.push_size
[i
]);
209 push_start
+= pipeline
->urb
.push_size
[i
];
212 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
213 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_URB_VS
),
214 ._3DCommandSubOpcode
= 48 + i
,
215 .VSURBStartingAddress
= pipeline
->urb
.start
[i
],
216 .VSURBEntryAllocationSize
= pipeline
->urb
.size
[i
] - 1,
217 .VSNumberofURBEntries
= pipeline
->urb
.entries
[i
]);
221 static inline uint32_t
222 scratch_space(const struct brw_stage_prog_data
*prog_data
)
224 return ffs(prog_data
->total_scratch
/ 2048);
227 static const uint32_t vk_to_gen_cullmode
[] = {
228 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
229 [VK_CULL_MODE_FRONT_BIT
] = CULLMODE_FRONT
,
230 [VK_CULL_MODE_BACK_BIT
] = CULLMODE_BACK
,
231 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
234 static const uint32_t vk_to_gen_fillmode
[] = {
235 [VK_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
236 [VK_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
237 [VK_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
240 static const uint32_t vk_to_gen_front_face
[] = {
241 [VK_FRONT_FACE_COUNTER_CLOCKWISE
] = 1,
242 [VK_FRONT_FACE_CLOCKWISE
] = 0
245 static const uint32_t vk_to_gen_logic_op
[] = {
246 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
247 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
248 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
249 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
250 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
251 [VK_LOGIC_OP_NO_OP
] = LOGICOP_NOOP
,
252 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
253 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
254 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
255 [VK_LOGIC_OP_EQUIVALENT
] = LOGICOP_EQUIV
,
256 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
257 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
258 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
259 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
260 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
261 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
264 static const uint32_t vk_to_gen_blend
[] = {
265 [VK_BLEND_FACTOR_ZERO
] = BLENDFACTOR_ZERO
,
266 [VK_BLEND_FACTOR_ONE
] = BLENDFACTOR_ONE
,
267 [VK_BLEND_FACTOR_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
268 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
269 [VK_BLEND_FACTOR_DST_COLOR
] = BLENDFACTOR_DST_COLOR
,
270 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
271 [VK_BLEND_FACTOR_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
272 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
273 [VK_BLEND_FACTOR_DST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
274 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
275 [VK_BLEND_FACTOR_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
276 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
]= BLENDFACTOR_INV_CONST_COLOR
,
277 [VK_BLEND_FACTOR_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
278 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
]= BLENDFACTOR_INV_CONST_ALPHA
,
279 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
280 [VK_BLEND_FACTOR_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
281 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
282 [VK_BLEND_FACTOR_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
283 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
286 static const uint32_t vk_to_gen_blend_op
[] = {
287 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
288 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
289 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
290 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
291 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
294 static const uint32_t vk_to_gen_compare_op
[] = {
295 [VK_COMPARE_OP_NEVER
] = PREFILTEROPNEVER
,
296 [VK_COMPARE_OP_LESS
] = PREFILTEROPLESS
,
297 [VK_COMPARE_OP_EQUAL
] = PREFILTEROPEQUAL
,
298 [VK_COMPARE_OP_LESS_OR_EQUAL
] = PREFILTEROPLEQUAL
,
299 [VK_COMPARE_OP_GREATER
] = PREFILTEROPGREATER
,
300 [VK_COMPARE_OP_NOT_EQUAL
] = PREFILTEROPNOTEQUAL
,
301 [VK_COMPARE_OP_GREATER_OR_EQUAL
] = PREFILTEROPGEQUAL
,
302 [VK_COMPARE_OP_ALWAYS
] = PREFILTEROPALWAYS
,
305 static const uint32_t vk_to_gen_stencil_op
[] = {
306 [VK_STENCIL_OP_KEEP
] = STENCILOP_KEEP
,
307 [VK_STENCIL_OP_ZERO
] = STENCILOP_ZERO
,
308 [VK_STENCIL_OP_REPLACE
] = STENCILOP_REPLACE
,
309 [VK_STENCIL_OP_INCREMENT_AND_CLAMP
] = STENCILOP_INCRSAT
,
310 [VK_STENCIL_OP_DECREMENT_AND_CLAMP
] = STENCILOP_DECRSAT
,
311 [VK_STENCIL_OP_INVERT
] = STENCILOP_INVERT
,
312 [VK_STENCIL_OP_INCREMENT_AND_WRAP
] = STENCILOP_INCR
,
313 [VK_STENCIL_OP_DECREMENT_AND_WRAP
] = STENCILOP_DECR
,