2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
35 VkResult
genX(CreateQueryPool
)(
37 const VkQueryPoolCreateInfo
* pCreateInfo
,
38 const VkAllocationCallbacks
* pAllocator
,
39 VkQueryPool
* pQueryPool
)
41 ANV_FROM_HANDLE(anv_device
, device
, _device
);
42 const struct anv_physical_device
*pdevice
= &device
->instance
->physicalDevice
;
43 struct anv_query_pool
*pool
;
46 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_QUERY_POOL_CREATE_INFO
);
48 /* Query pool slots are made up of some number of 64-bit values packed
49 * tightly together. The first 64-bit value is always the "available" bit
50 * which is 0 when the query is unavailable and 1 when it is available.
51 * The 64-bit values that follow are determined by the type of query.
53 uint32_t uint64s_per_slot
= 1;
55 VkQueryPipelineStatisticFlags pipeline_statistics
= 0;
56 switch (pCreateInfo
->queryType
) {
57 case VK_QUERY_TYPE_OCCLUSION
:
58 /* Occlusion queries have two values: begin and end. */
59 uint64s_per_slot
+= 2;
61 case VK_QUERY_TYPE_TIMESTAMP
:
62 /* Timestamps just have the one timestamp value */
63 uint64s_per_slot
+= 1;
65 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
66 pipeline_statistics
= pCreateInfo
->pipelineStatistics
;
67 /* We're going to trust this field implicitly so we need to ensure that
68 * no unhandled extension bits leak in.
70 pipeline_statistics
&= ANV_PIPELINE_STATISTICS_MASK
;
72 /* Statistics queries have a min and max for every statistic */
73 uint64s_per_slot
+= 2 * util_bitcount(pipeline_statistics
);
76 assert(!"Invalid query type");
79 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
80 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
82 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
84 pool
->type
= pCreateInfo
->queryType
;
85 pool
->pipeline_statistics
= pipeline_statistics
;
86 pool
->stride
= uint64s_per_slot
* sizeof(uint64_t);
87 pool
->slots
= pCreateInfo
->queryCount
;
89 uint64_t size
= pool
->slots
* pool
->stride
;
90 result
= anv_bo_init_new(&pool
->bo
, device
, size
);
91 if (result
!= VK_SUCCESS
)
94 if (pdevice
->supports_48bit_addresses
)
95 pool
->bo
.flags
|= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
97 if (pdevice
->use_softpin
)
98 pool
->bo
.flags
|= EXEC_OBJECT_PINNED
;
100 if (pdevice
->has_exec_async
)
101 pool
->bo
.flags
|= EXEC_OBJECT_ASYNC
;
103 anv_vma_alloc(device
, &pool
->bo
);
105 /* For query pools, we set the caching mode to I915_CACHING_CACHED. On LLC
106 * platforms, this does nothing. On non-LLC platforms, this means snooping
107 * which comes at a slight cost. However, the buffers aren't big, won't be
108 * written frequently, and trying to handle the flushing manually without
109 * doing too much flushing is extremely painful.
111 anv_gem_set_caching(device
, pool
->bo
.gem_handle
, I915_CACHING_CACHED
);
113 pool
->bo
.map
= anv_gem_mmap(device
, pool
->bo
.gem_handle
, 0, size
, 0);
115 *pQueryPool
= anv_query_pool_to_handle(pool
);
120 vk_free2(&device
->alloc
, pAllocator
, pool
);
125 void genX(DestroyQueryPool
)(
128 const VkAllocationCallbacks
* pAllocator
)
130 ANV_FROM_HANDLE(anv_device
, device
, _device
);
131 ANV_FROM_HANDLE(anv_query_pool
, pool
, _pool
);
136 anv_gem_munmap(pool
->bo
.map
, pool
->bo
.size
);
137 anv_vma_free(device
, &pool
->bo
);
138 anv_gem_close(device
, pool
->bo
.gem_handle
);
139 vk_free2(&device
->alloc
, pAllocator
, pool
);
142 static struct anv_address
143 anv_query_address(struct anv_query_pool
*pool
, uint32_t query
)
145 return (struct anv_address
) {
147 .offset
= query
* pool
->stride
,
152 cpu_write_query_result(void *dst_slot
, VkQueryResultFlags flags
,
153 uint32_t value_index
, uint64_t result
)
155 if (flags
& VK_QUERY_RESULT_64_BIT
) {
156 uint64_t *dst64
= dst_slot
;
157 dst64
[value_index
] = result
;
159 uint32_t *dst32
= dst_slot
;
160 dst32
[value_index
] = result
;
165 query_is_available(uint64_t *slot
)
167 return *(volatile uint64_t *)slot
;
171 wait_for_available(struct anv_device
*device
,
172 struct anv_query_pool
*pool
, uint64_t *slot
)
175 if (query_is_available(slot
))
178 int ret
= anv_gem_busy(device
, pool
->bo
.gem_handle
);
180 /* The BO is still busy, keep waiting. */
182 } else if (ret
== -1) {
183 /* We don't know the real error. */
185 return vk_errorf(device
->instance
, device
, VK_ERROR_DEVICE_LOST
,
186 "gem wait failed: %m");
189 /* The BO is no longer busy. */
190 if (query_is_available(slot
)) {
193 VkResult status
= anv_device_query_status(device
);
194 if (status
!= VK_SUCCESS
)
197 /* If we haven't seen availability yet, then we never will. This
198 * can only happen if we have a client error where they call
199 * GetQueryPoolResults on a query that they haven't submitted to
200 * the GPU yet. The spec allows us to do anything in this case,
201 * but returning VK_SUCCESS doesn't seem right and we shouldn't
202 * just keep spinning.
210 VkResult
genX(GetQueryPoolResults
)(
212 VkQueryPool queryPool
,
218 VkQueryResultFlags flags
)
220 ANV_FROM_HANDLE(anv_device
, device
, _device
);
221 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
223 assert(pool
->type
== VK_QUERY_TYPE_OCCLUSION
||
224 pool
->type
== VK_QUERY_TYPE_PIPELINE_STATISTICS
||
225 pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
227 if (unlikely(device
->lost
))
228 return VK_ERROR_DEVICE_LOST
;
233 void *data_end
= pData
+ dataSize
;
235 VkResult status
= VK_SUCCESS
;
236 for (uint32_t i
= 0; i
< queryCount
; i
++) {
237 uint64_t *slot
= pool
->bo
.map
+ (firstQuery
+ i
) * pool
->stride
;
239 /* Availability is always at the start of the slot */
240 bool available
= slot
[0];
242 if (!available
&& (flags
& VK_QUERY_RESULT_WAIT_BIT
)) {
243 status
= wait_for_available(device
, pool
, slot
);
244 if (status
!= VK_SUCCESS
)
250 /* From the Vulkan 1.0.42 spec:
252 * "If VK_QUERY_RESULT_WAIT_BIT and VK_QUERY_RESULT_PARTIAL_BIT are
253 * both not set then no result values are written to pData for
254 * queries that are in the unavailable state at the time of the call,
255 * and vkGetQueryPoolResults returns VK_NOT_READY. However,
256 * availability state is still written to pData for those queries if
257 * VK_QUERY_RESULT_WITH_AVAILABILITY_BIT is set."
259 bool write_results
= available
|| (flags
& VK_QUERY_RESULT_PARTIAL_BIT
);
262 switch (pool
->type
) {
263 case VK_QUERY_TYPE_OCCLUSION
:
265 cpu_write_query_result(pData
, flags
, idx
, slot
[2] - slot
[1]);
269 case VK_QUERY_TYPE_PIPELINE_STATISTICS
: {
270 uint32_t statistics
= pool
->pipeline_statistics
;
272 uint32_t stat
= u_bit_scan(&statistics
);
274 uint64_t result
= slot
[idx
* 2 + 2] - slot
[idx
* 2 + 1];
276 /* WaDividePSInvocationCountBy4:HSW,BDW */
277 if ((device
->info
.gen
== 8 || device
->info
.is_haswell
) &&
278 (1 << stat
) == VK_QUERY_PIPELINE_STATISTIC_FRAGMENT_SHADER_INVOCATIONS_BIT
)
281 cpu_write_query_result(pData
, flags
, idx
, result
);
285 assert(idx
== util_bitcount(pool
->pipeline_statistics
));
289 case VK_QUERY_TYPE_TIMESTAMP
:
291 cpu_write_query_result(pData
, flags
, idx
, slot
[1]);
296 unreachable("invalid pool type");
300 status
= VK_NOT_READY
;
302 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
)
303 cpu_write_query_result(pData
, flags
, idx
, available
);
306 if (pData
>= data_end
)
314 emit_ps_depth_count(struct anv_cmd_buffer
*cmd_buffer
,
315 struct anv_address addr
)
317 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
318 pc
.DestinationAddressType
= DAT_PPGTT
;
319 pc
.PostSyncOperation
= WritePSDepthCount
;
320 pc
.DepthStallEnable
= true;
323 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
324 pc
.CommandStreamerStallEnable
= true;
329 emit_query_availability(struct anv_cmd_buffer
*cmd_buffer
,
330 struct anv_address addr
)
332 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
333 pc
.DestinationAddressType
= DAT_PPGTT
;
334 pc
.PostSyncOperation
= WriteImmediateData
;
336 pc
.ImmediateData
= 1;
341 * Goes through a series of consecutive query indices in the given pool
342 * setting all element values to 0 and emitting them as available.
345 emit_zero_queries(struct anv_cmd_buffer
*cmd_buffer
,
346 struct anv_query_pool
*pool
,
347 uint32_t first_index
, uint32_t num_queries
)
349 const uint32_t num_elements
= pool
->stride
/ sizeof(uint64_t);
351 for (uint32_t i
= 0; i
< num_queries
; i
++) {
352 struct anv_address slot_addr
=
353 anv_query_address(pool
, first_index
+ i
);
354 for (uint32_t j
= 1; j
< num_elements
; j
++) {
355 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
356 sdi
.Address
= anv_address_add(slot_addr
, j
* sizeof(uint64_t));
357 sdi
.ImmediateData
= 0ull;
359 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
360 sdi
.Address
= anv_address_add(slot_addr
, j
* sizeof(uint64_t) + 4);
361 sdi
.ImmediateData
= 0ull;
364 emit_query_availability(cmd_buffer
, slot_addr
);
368 void genX(CmdResetQueryPool
)(
369 VkCommandBuffer commandBuffer
,
370 VkQueryPool queryPool
,
374 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
375 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
377 for (uint32_t i
= 0; i
< queryCount
; i
++) {
378 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdm
) {
379 sdm
.Address
= anv_query_address(pool
, firstQuery
+ i
);
380 sdm
.ImmediateData
= 0;
385 static const uint32_t vk_pipeline_stat_to_reg
[] = {
386 GENX(IA_VERTICES_COUNT_num
),
387 GENX(IA_PRIMITIVES_COUNT_num
),
388 GENX(VS_INVOCATION_COUNT_num
),
389 GENX(GS_INVOCATION_COUNT_num
),
390 GENX(GS_PRIMITIVES_COUNT_num
),
391 GENX(CL_INVOCATION_COUNT_num
),
392 GENX(CL_PRIMITIVES_COUNT_num
),
393 GENX(PS_INVOCATION_COUNT_num
),
394 GENX(HS_INVOCATION_COUNT_num
),
395 GENX(DS_INVOCATION_COUNT_num
),
396 GENX(CS_INVOCATION_COUNT_num
),
400 emit_pipeline_stat(struct anv_cmd_buffer
*cmd_buffer
, uint32_t stat
,
401 struct anv_address addr
)
403 STATIC_ASSERT(ANV_PIPELINE_STATISTICS_MASK
==
404 (1 << ARRAY_SIZE(vk_pipeline_stat_to_reg
)) - 1);
406 assert(stat
< ARRAY_SIZE(vk_pipeline_stat_to_reg
));
407 uint32_t reg
= vk_pipeline_stat_to_reg
[stat
];
409 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), lrm
) {
410 lrm
.RegisterAddress
= reg
;
411 lrm
.MemoryAddress
= anv_address_add(addr
, 0);
413 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), lrm
) {
414 lrm
.RegisterAddress
= reg
+ 4;
415 lrm
.MemoryAddress
= anv_address_add(addr
, 4);
419 void genX(CmdBeginQuery
)(
420 VkCommandBuffer commandBuffer
,
421 VkQueryPool queryPool
,
423 VkQueryControlFlags flags
)
425 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
426 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
427 struct anv_address query_addr
= anv_query_address(pool
, query
);
429 switch (pool
->type
) {
430 case VK_QUERY_TYPE_OCCLUSION
:
431 emit_ps_depth_count(cmd_buffer
, anv_address_add(query_addr
, 8));
434 case VK_QUERY_TYPE_PIPELINE_STATISTICS
: {
435 /* TODO: This might only be necessary for certain stats */
436 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
437 pc
.CommandStreamerStallEnable
= true;
438 pc
.StallAtPixelScoreboard
= true;
441 uint32_t statistics
= pool
->pipeline_statistics
;
444 uint32_t stat
= u_bit_scan(&statistics
);
445 emit_pipeline_stat(cmd_buffer
, stat
,
446 anv_address_add(query_addr
, offset
));
457 void genX(CmdEndQuery
)(
458 VkCommandBuffer commandBuffer
,
459 VkQueryPool queryPool
,
462 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
463 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
464 struct anv_address query_addr
= anv_query_address(pool
, query
);
466 switch (pool
->type
) {
467 case VK_QUERY_TYPE_OCCLUSION
:
468 emit_ps_depth_count(cmd_buffer
, anv_address_add(query_addr
, 16));
469 emit_query_availability(cmd_buffer
, query_addr
);
472 case VK_QUERY_TYPE_PIPELINE_STATISTICS
: {
473 /* TODO: This might only be necessary for certain stats */
474 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
475 pc
.CommandStreamerStallEnable
= true;
476 pc
.StallAtPixelScoreboard
= true;
479 uint32_t statistics
= pool
->pipeline_statistics
;
480 uint32_t offset
= 16;
482 uint32_t stat
= u_bit_scan(&statistics
);
483 emit_pipeline_stat(cmd_buffer
, stat
,
484 anv_address_add(query_addr
, offset
));
488 emit_query_availability(cmd_buffer
, query_addr
);
496 /* When multiview is active the spec requires that N consecutive query
497 * indices are used, where N is the number of active views in the subpass.
498 * The spec allows that we only write the results to one of the queries
499 * but we still need to manage result availability for all the query indices.
500 * Since we only emit a single query for all active views in the
501 * first index, mark the other query indices as being already available
504 if (cmd_buffer
->state
.subpass
&& cmd_buffer
->state
.subpass
->view_mask
) {
505 const uint32_t num_queries
=
506 util_bitcount(cmd_buffer
->state
.subpass
->view_mask
);
508 emit_zero_queries(cmd_buffer
, pool
, query
+ 1, num_queries
- 1);
512 #define TIMESTAMP 0x2358
514 void genX(CmdWriteTimestamp
)(
515 VkCommandBuffer commandBuffer
,
516 VkPipelineStageFlagBits pipelineStage
,
517 VkQueryPool queryPool
,
520 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
521 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
522 struct anv_address query_addr
= anv_query_address(pool
, query
);
524 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
526 switch (pipelineStage
) {
527 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
528 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
529 srm
.RegisterAddress
= TIMESTAMP
;
530 srm
.MemoryAddress
= anv_address_add(query_addr
, 8);
532 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
533 srm
.RegisterAddress
= TIMESTAMP
+ 4;
534 srm
.MemoryAddress
= anv_address_add(query_addr
, 12);
539 /* Everything else is bottom-of-pipe */
540 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
541 pc
.DestinationAddressType
= DAT_PPGTT
;
542 pc
.PostSyncOperation
= WriteTimestamp
;
543 pc
.Address
= anv_address_add(query_addr
, 8);
545 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
546 pc
.CommandStreamerStallEnable
= true;
551 emit_query_availability(cmd_buffer
, query_addr
);
553 /* When multiview is active the spec requires that N consecutive query
554 * indices are used, where N is the number of active views in the subpass.
555 * The spec allows that we only write the results to one of the queries
556 * but we still need to manage result availability for all the query indices.
557 * Since we only emit a single query for all active views in the
558 * first index, mark the other query indices as being already available
561 if (cmd_buffer
->state
.subpass
&& cmd_buffer
->state
.subpass
->view_mask
) {
562 const uint32_t num_queries
=
563 util_bitcount(cmd_buffer
->state
.subpass
->view_mask
);
565 emit_zero_queries(cmd_buffer
, pool
, query
+ 1, num_queries
- 1);
569 #if GEN_GEN > 7 || GEN_IS_HASWELL
572 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
574 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
576 .Operand1
= operand1
,
577 .Operand2
= operand2
,
581 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
586 #define CS_GPR(n) (0x2600 + (n) * 8)
589 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
590 struct anv_address addr
)
592 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
593 lrm
.RegisterAddress
= reg
;
594 lrm
.MemoryAddress
= anv_address_add(addr
, 0);
596 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
597 lrm
.RegisterAddress
= reg
+ 4;
598 lrm
.MemoryAddress
= anv_address_add(addr
, 4);
603 emit_load_alu_reg_imm32(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
605 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
606 lri
.RegisterOffset
= reg
;
612 emit_load_alu_reg_imm64(struct anv_batch
*batch
, uint32_t reg
, uint64_t imm
)
614 emit_load_alu_reg_imm32(batch
, reg
, (uint32_t)imm
);
615 emit_load_alu_reg_imm32(batch
, reg
+ 4, (uint32_t)(imm
>> 32));
619 emit_load_alu_reg_reg32(struct anv_batch
*batch
, uint32_t src
, uint32_t dst
)
621 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
622 lrr
.SourceRegisterAddress
= src
;
623 lrr
.DestinationRegisterAddress
= dst
;
628 * GPR0 = GPR0 & ((1ull << n) - 1);
631 keep_gpr0_lower_n_bits(struct anv_batch
*batch
, uint32_t n
)
634 emit_load_alu_reg_imm64(batch
, CS_GPR(1), (1ull << n
) - 1);
636 uint32_t *dw
= anv_batch_emitn(batch
, 5, GENX(MI_MATH
));
638 anv_batch_set_error(batch
, VK_ERROR_OUT_OF_HOST_MEMORY
);
642 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
643 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
644 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
645 dw
[4] = mi_alu(MI_ALU_STORE
, MI_ALU_REG0
, MI_ALU_ACCU
);
652 shl_gpr0_by_30_bits(struct anv_batch
*batch
)
654 /* First we mask 34 bits of GPR0 to prevent overflow */
655 keep_gpr0_lower_n_bits(batch
, 34);
657 const uint32_t outer_count
= 5;
658 const uint32_t inner_count
= 6;
659 STATIC_ASSERT(outer_count
* inner_count
== 30);
660 const uint32_t cmd_len
= 1 + inner_count
* 4;
662 /* We'll emit 5 commands, each shifting GPR0 left by 6 bits, for a total of
665 for (int o
= 0; o
< outer_count
; o
++) {
666 /* Submit one MI_MATH to shift left by 6 bits */
667 uint32_t *dw
= anv_batch_emitn(batch
, cmd_len
, GENX(MI_MATH
));
669 anv_batch_set_error(batch
, VK_ERROR_OUT_OF_HOST_MEMORY
);
674 for (int i
= 0; i
< inner_count
; i
++, dw
+= 4) {
675 dw
[0] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
676 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG0
);
677 dw
[2] = mi_alu(MI_ALU_ADD
, 0, 0);
678 dw
[3] = mi_alu(MI_ALU_STORE
, MI_ALU_REG0
, MI_ALU_ACCU
);
686 * Note that the upper 30 bits of GPR are lost!
689 shr_gpr0_by_2_bits(struct anv_batch
*batch
)
691 shl_gpr0_by_30_bits(batch
);
692 emit_load_alu_reg_reg32(batch
, CS_GPR(0) + 4, CS_GPR(0));
693 emit_load_alu_reg_imm32(batch
, CS_GPR(0) + 4, 0);
697 gpu_write_query_result(struct anv_batch
*batch
,
698 struct anv_address dst_addr
,
699 VkQueryResultFlags flags
,
700 uint32_t value_index
, uint32_t reg
)
702 if (flags
& VK_QUERY_RESULT_64_BIT
)
703 dst_addr
= anv_address_add(dst_addr
, value_index
* 8);
705 dst_addr
= anv_address_add(dst_addr
, value_index
* 4);
707 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
708 srm
.RegisterAddress
= reg
;
709 srm
.MemoryAddress
= anv_address_add(dst_addr
, 0);
712 if (flags
& VK_QUERY_RESULT_64_BIT
) {
713 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
714 srm
.RegisterAddress
= reg
+ 4;
715 srm
.MemoryAddress
= anv_address_add(dst_addr
, 4);
721 compute_query_result(struct anv_batch
*batch
, uint32_t dst_reg
,
722 struct anv_address addr
)
724 emit_load_alu_reg_u64(batch
, CS_GPR(0), anv_address_add(addr
, 0));
725 emit_load_alu_reg_u64(batch
, CS_GPR(1), anv_address_add(addr
, 8));
727 /* FIXME: We need to clamp the result for 32 bit. */
729 uint32_t *dw
= anv_batch_emitn(batch
, 5, GENX(MI_MATH
));
731 anv_batch_set_error(batch
, VK_ERROR_OUT_OF_HOST_MEMORY
);
735 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG1
);
736 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG0
);
737 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
738 dw
[4] = mi_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
741 void genX(CmdCopyQueryPoolResults
)(
742 VkCommandBuffer commandBuffer
,
743 VkQueryPool queryPool
,
747 VkDeviceSize destOffset
,
748 VkDeviceSize destStride
,
749 VkQueryResultFlags flags
)
751 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
752 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
753 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
755 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
756 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
757 pc
.CommandStreamerStallEnable
= true;
758 pc
.StallAtPixelScoreboard
= true;
762 struct anv_address dest_addr
= anv_address_add(buffer
->address
, destOffset
);
763 for (uint32_t i
= 0; i
< queryCount
; i
++) {
764 struct anv_address query_addr
= anv_query_address(pool
, firstQuery
+ i
);
766 switch (pool
->type
) {
767 case VK_QUERY_TYPE_OCCLUSION
:
768 compute_query_result(&cmd_buffer
->batch
, MI_ALU_REG2
,
769 anv_address_add(query_addr
, 8));
770 gpu_write_query_result(&cmd_buffer
->batch
, dest_addr
,
771 flags
, idx
++, CS_GPR(2));
774 case VK_QUERY_TYPE_PIPELINE_STATISTICS
: {
775 uint32_t statistics
= pool
->pipeline_statistics
;
777 uint32_t stat
= u_bit_scan(&statistics
);
779 compute_query_result(&cmd_buffer
->batch
, MI_ALU_REG0
,
780 anv_address_add(query_addr
, idx
* 16 + 8));
782 /* WaDividePSInvocationCountBy4:HSW,BDW */
783 if ((cmd_buffer
->device
->info
.gen
== 8 ||
784 cmd_buffer
->device
->info
.is_haswell
) &&
785 (1 << stat
) == VK_QUERY_PIPELINE_STATISTIC_FRAGMENT_SHADER_INVOCATIONS_BIT
) {
786 shr_gpr0_by_2_bits(&cmd_buffer
->batch
);
789 gpu_write_query_result(&cmd_buffer
->batch
, dest_addr
,
790 flags
, idx
++, CS_GPR(0));
792 assert(idx
== util_bitcount(pool
->pipeline_statistics
));
796 case VK_QUERY_TYPE_TIMESTAMP
:
797 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
798 CS_GPR(2), anv_address_add(query_addr
, 8));
799 gpu_write_query_result(&cmd_buffer
->batch
, dest_addr
,
800 flags
, 0, CS_GPR(2));
804 unreachable("unhandled query type");
807 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
808 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0), query_addr
);
809 gpu_write_query_result(&cmd_buffer
->batch
, dest_addr
,
810 flags
, idx
, CS_GPR(0));
813 dest_addr
= anv_address_add(dest_addr
, destStride
);
818 void genX(CmdCopyQueryPoolResults
)(
819 VkCommandBuffer commandBuffer
,
820 VkQueryPool queryPool
,
824 VkDeviceSize destOffset
,
825 VkDeviceSize destStride
,
826 VkQueryResultFlags flags
)
828 anv_finishme("Queries not yet supported on Ivy Bridge");