src/intel/vulkan/genX_state.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "common/gen_sample_positions.h"
  33 #include "genxml/gen_macros.h"
  34 #include "genxml/genX_pack.h"
  35
  36 #include "vk_util.h"
  37
  38 #if GEN_GEN == 10
  39 /**
  40  * From Gen10 Workarounds page in h/w specs:
  41  * WaSampleOffsetIZ:
  42  *    "Prior to the 3DSTATE_SAMPLE_PATTERN driver must ensure there are no
  43  *     markers in the pipeline by programming a PIPE_CONTROL with stall."
  44  */
  45 static void
  46 gen10_emit_wa_cs_stall_flush(struct anv_batch *batch)
  47 {
  48
  49    anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
  50       pc.CommandStreamerStallEnable = true;
  51       pc.StallAtPixelScoreboard = true;
  52    }
  53 }
  54
  55 /**
  56  * From Gen10 Workarounds page in h/w specs:
  57  * WaSampleOffsetIZ:_cs_stall_flush
  58  *    "When 3DSTATE_SAMPLE_PATTERN is programmed, driver must then issue an
  59  *     MI_LOAD_REGISTER_IMM command to an offset between 0x7000 and 0x7FFF(SVL)
  60  *     after the command to ensure the state has been delivered prior to any
  61  *     command causing a marker in the pipeline."
  62  */
  63 static void
  64 gen10_emit_wa_lri_to_cache_mode_zero(struct anv_batch *batch)
  65 {
  66    /* Before changing the value of CACHE_MODE_0 register, GFX pipeline must
  67     * be idle; i.e., full flush is required.
  68     */
  69    anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
  70       pc.DepthCacheFlushEnable = true;
  71       pc.DCFlushEnable = true;
  72       pc.RenderTargetCacheFlushEnable = true;
  73       pc.InstructionCacheInvalidateEnable = true;
  74       pc.StateCacheInvalidationEnable = true;
  75       pc.TextureCacheInvalidationEnable = true;
  76       pc.VFCacheInvalidationEnable = true;
  77       pc.ConstantCacheInvalidationEnable =true;
  78    }
  79
  80    /* Write to CACHE_MODE_0 (0x7000) */
  81    uint32_t cache_mode_0 = 0;
  82    anv_pack_struct(&cache_mode_0, GENX(CACHE_MODE_0));
  83
  84    anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
  85       lri.RegisterOffset = GENX(CACHE_MODE_0_num);
  86       lri.DataDWord      = cache_mode_0;
  87    }
  88 }
  89 #endif
  90
  91 VkResult
  92 genX(init_device_state)(struct anv_device *device)
  93 {
  94    GENX(MEMORY_OBJECT_CONTROL_STATE_pack)(NULL, &device->default_mocs,
  95                                           &GENX(MOCS));
  96 #if GEN_GEN >= 8
  97    GENX(MEMORY_OBJECT_CONTROL_STATE_pack)(NULL, &device->external_mocs,
  98                                           &GENX(EXTERNAL_MOCS));
  99 #else
 100    device->external_mocs = device->default_mocs;
 101 #endif
 102
 103    struct anv_batch batch;
 104
 105    uint32_t cmds[64];
 106    batch.start = batch.next = cmds;
 107    batch.end = (void *) cmds + sizeof(cmds);
 108
 109    anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
 110 #if GEN_GEN >= 9
 111       ps.MaskBits = 3;
 112 #endif
 113       ps.PipelineSelection = _3D;
 114    }
 115
 116 #if GEN_GEN == 9
 117    uint32_t cache_mode_1;
 118    anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
 119                    .FloatBlendOptimizationEnable = true,
 120                    .FloatBlendOptimizationEnableMask = true,
 121                    .PartialResolveDisableInVC = true,
 122                    .PartialResolveDisableInVCMask = true);
 123
 124    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 125       lri.RegisterOffset = GENX(CACHE_MODE_1_num);
 126       lri.DataDWord      = cache_mode_1;
 127    }
 128 #endif
 129
 130    anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
 131
 132    anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
 133       rect.ClippedDrawingRectangleYMin = 0;
 134       rect.ClippedDrawingRectangleXMin = 0;
 135       rect.ClippedDrawingRectangleYMax = UINT16_MAX;
 136       rect.ClippedDrawingRectangleXMax = UINT16_MAX;
 137       rect.DrawingRectangleOriginY = 0;
 138       rect.DrawingRectangleOriginX = 0;
 139    }
 140
 141 #if GEN_GEN >= 8
 142    anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
 143
 144 #if GEN_GEN == 10
 145    gen10_emit_wa_cs_stall_flush(&batch);
 146 #endif
 147
 148    /* See the Vulkan 1.0 spec Table 24.1 "Standard sample locations" and
 149     * VkPhysicalDeviceFeatures::standardSampleLocations.
 150     */
 151    anv_batch_emit(&batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {
 152       GEN_SAMPLE_POS_1X(sp._1xSample);
 153       GEN_SAMPLE_POS_2X(sp._2xSample);
 154       GEN_SAMPLE_POS_4X(sp._4xSample);
 155       GEN_SAMPLE_POS_8X(sp._8xSample);
 156 #if GEN_GEN >= 9
 157       GEN_SAMPLE_POS_16X(sp._16xSample);
 158 #endif
 159    }
 160
 161    /* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the
 162     * section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
 163     * Clear." It mentions that the packet overrides GPU state for the clear
 164     * operation and needs to be reset to 0s to clear the overrides. Depending
 165     * on the kernel, we may not get a context with the state for this packet
 166     * zeroed. Do it ourselves just in case. We've observed this to prevent a
 167     * number of GPU hangs on ICL.
 168     */
 169    anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);
 170 #endif
 171
 172 #if GEN_GEN == 10
 173    gen10_emit_wa_lri_to_cache_mode_zero(&batch);
 174 #endif
 175
 176 #if GEN_GEN == 11
 177    /* The default behavior of bit 5 "Headerless Message for Pre-emptable
 178     * Contexts" in SAMPLER MODE register is set to 0, which means
 179     * headerless sampler messages are not allowed for pre-emptable
 180     * contexts. Set the bit 5 to 1 to allow them.
 181     */
 182    uint32_t sampler_mode;
 183    anv_pack_struct(&sampler_mode, GENX(SAMPLER_MODE),
 184                    .HeaderlessMessageforPreemptableContexts = true,
 185                    .HeaderlessMessageforPreemptableContextsMask = true);
 186
 187     anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 188       lri.RegisterOffset = GENX(SAMPLER_MODE_num);
 189       lri.DataDWord      = sampler_mode;
 190    }
 191
 192    /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
 193     * HALF_SLICE_CHICKEN7 register.
 194     */
 195    uint32_t half_slice_chicken7;
 196    anv_pack_struct(&half_slice_chicken7, GENX(HALF_SLICE_CHICKEN7),
 197                    .EnabledTexelOffsetPrecisionFix = true,
 198                    .EnabledTexelOffsetPrecisionFixMask = true);
 199
 200     anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 201       lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num);
 202       lri.DataDWord      = half_slice_chicken7;
 203    }
 204
 205 #endif
 206
 207    /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
 208     * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
 209     *
 210     * This is only safe on kernels with context isolation support.
 211     */
 212    if (GEN_GEN >= 8 &&
 213        device->instance->physicalDevice.has_context_isolation) {
 214       UNUSED uint32_t tmp_reg;
 215 #if GEN_GEN >= 9
 216       anv_pack_struct(&tmp_reg, GENX(CS_DEBUG_MODE2),
 217                       .CONSTANT_BUFFERAddressOffsetDisable = true,
 218                       .CONSTANT_BUFFERAddressOffsetDisableMask = true);
 219       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 220          lri.RegisterOffset = GENX(CS_DEBUG_MODE2_num);
 221          lri.DataDWord      = tmp_reg;
 222       }
 223 #elif GEN_GEN == 8
 224       anv_pack_struct(&tmp_reg, GENX(INSTPM),
 225                       .CONSTANT_BUFFERAddressOffsetDisable = true,
 226                       .CONSTANT_BUFFERAddressOffsetDisableMask = true);
 227       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 228          lri.RegisterOffset = GENX(INSTPM_num);
 229          lri.DataDWord      = tmp_reg;
 230       }
 231 #endif
 232    }
 233
 234    anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
 235
 236    assert(batch.next <= batch.end);
 237
 238    return anv_device_submit_simple_batch(device, &batch);
 239 }
 240
 241 static uint32_t
 242 vk_to_gen_tex_filter(VkFilter filter, bool anisotropyEnable)
 243 {
 244    switch (filter) {
 245    default:
 246       assert(!"Invalid filter");
 247    case VK_FILTER_NEAREST:
 248       return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_NEAREST;
 249    case VK_FILTER_LINEAR:
 250       return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_LINEAR;
 251    }
 252 }
 253
 254 static uint32_t
 255 vk_to_gen_max_anisotropy(float ratio)
 256 {
 257    return (anv_clamp_f(ratio, 2, 16) - 2) / 2;
 258 }
 259
 260 static const uint32_t vk_to_gen_mipmap_mode[] = {
 261    [VK_SAMPLER_MIPMAP_MODE_NEAREST]          = MIPFILTER_NEAREST,
 262    [VK_SAMPLER_MIPMAP_MODE_LINEAR]           = MIPFILTER_LINEAR
 263 };
 264
 265 static const uint32_t vk_to_gen_tex_address[] = {
 266    [VK_SAMPLER_ADDRESS_MODE_REPEAT]          = TCM_WRAP,
 267    [VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT] = TCM_MIRROR,
 268    [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE]   = TCM_CLAMP,
 269    [VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
 270    [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
 271 };
 272
 273 /* Vulkan specifies the result of shadow comparisons as:
 274  *     1     if   ref <op> texel,
 275  *     0     otherwise.
 276  *
 277  * The hardware does:
 278  *     0     if texel <op> ref,
 279  *     1     otherwise.
 280  *
 281  * So, these look a bit strange because there's both a negation
 282  * and swapping of the arguments involved.
 283  */
 284 static const uint32_t vk_to_gen_shadow_compare_op[] = {
 285    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPALWAYS,
 286    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLEQUAL,
 287    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPNOTEQUAL,
 288    [VK_COMPARE_OP_LESS_OR_EQUAL]                = PREFILTEROPLESS,
 289    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGEQUAL,
 290    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPEQUAL,
 291    [VK_COMPARE_OP_GREATER_OR_EQUAL]             = PREFILTEROPGREATER,
 292    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPNEVER,
 293 };
 294
 295 #if GEN_GEN >= 9
 296 static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
 297    [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
 298    [VK_SAMPLER_REDUCTION_MODE_MIN_EXT]              = MINIMUM,
 299    [VK_SAMPLER_REDUCTION_MODE_MAX_EXT]              = MAXIMUM,
 300 };
 301 #endif
 302
 303 VkResult genX(CreateSampler)(
 304     VkDevice                                    _device,
 305     const VkSamplerCreateInfo*                  pCreateInfo,
 306     const VkAllocationCallbacks*                pAllocator,
 307     VkSampler*                                  pSampler)
 308 {
 309    ANV_FROM_HANDLE(anv_device, device, _device);
 310    struct anv_sampler *sampler;
 311
 312    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
 313
 314    sampler = vk_zalloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
 315                         VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 316    if (!sampler)
 317       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 318
 319    sampler->n_planes = 1;
 320
 321    uint32_t border_color_offset = device->border_colors.offset +
 322                                   pCreateInfo->borderColor * 64;
 323
 324 #if GEN_GEN >= 9
 325    unsigned sampler_reduction_mode = STD_FILTER;
 326    bool enable_sampler_reduction = false;
 327 #endif
 328
 329    vk_foreach_struct(ext, pCreateInfo->pNext) {
 330       switch (ext->sType) {
 331       case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
 332          VkSamplerYcbcrConversionInfo *pSamplerConversion =
 333             (VkSamplerYcbcrConversionInfo *) ext;
 334          ANV_FROM_HANDLE(anv_ycbcr_conversion, conversion,
 335                          pSamplerConversion->conversion);
 336
 337          if (conversion == NULL)
 338             break;
 339
 340          sampler->n_planes = conversion->format->n_planes;
 341          sampler->conversion = conversion;
 342          break;
 343       }
 344 #if GEN_GEN >= 9
 345       case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT: {
 346          struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
 347             (struct VkSamplerReductionModeCreateInfoEXT *) ext;
 348          sampler_reduction_mode =
 349             vk_to_gen_sampler_reduction_mode[sampler_reduction->reductionMode];
 350          enable_sampler_reduction = true;
 351          break;
 352       }
 353 #endif
 354       default:
 355          anv_debug_ignored_stype(ext->sType);
 356          break;
 357       }
 358    }
 359
 360    for (unsigned p = 0; p < sampler->n_planes; p++) {
 361       const bool plane_has_chroma =
 362          sampler->conversion && sampler->conversion->format->planes[p].has_chroma;
 363       const VkFilter min_filter =
 364          plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->minFilter;
 365       const VkFilter mag_filter =
 366          plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->magFilter;
 367       const bool enable_min_filter_addr_rounding = min_filter != VK_FILTER_NEAREST;
 368       const bool enable_mag_filter_addr_rounding = mag_filter != VK_FILTER_NEAREST;
 369       /* From Broadwell PRM, SAMPLER_STATE:
 370        *   "Mip Mode Filter must be set to MIPFILTER_NONE for Planar YUV surfaces."
 371        */
 372       const uint32_t mip_filter_mode =
 373          (sampler->conversion &&
 374           isl_format_is_yuv(sampler->conversion->format->planes[0].isl_format)) ?
 375          MIPFILTER_NONE : vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode];
 376
 377       struct GENX(SAMPLER_STATE) sampler_state = {
 378          .SamplerDisable = false,
 379          .TextureBorderColorMode = DX10OGL,
 380
 381 #if GEN_GEN >= 8
 382          .LODPreClampMode = CLAMP_MODE_OGL,
 383 #else
 384          .LODPreClampEnable = CLAMP_ENABLE_OGL,
 385 #endif
 386
 387 #if GEN_GEN == 8
 388          .BaseMipLevel = 0.0,
 389 #endif
 390          .MipModeFilter = mip_filter_mode,
 391          .MagModeFilter = vk_to_gen_tex_filter(mag_filter, pCreateInfo->anisotropyEnable),
 392          .MinModeFilter = vk_to_gen_tex_filter(min_filter, pCreateInfo->anisotropyEnable),
 393          .TextureLODBias = anv_clamp_f(pCreateInfo->mipLodBias, -16, 15.996),
 394          .AnisotropicAlgorithm = EWAApproximation,
 395          .MinLOD = anv_clamp_f(pCreateInfo->minLod, 0, 14),
 396          .MaxLOD = anv_clamp_f(pCreateInfo->maxLod, 0, 14),
 397          .ChromaKeyEnable = 0,
 398          .ChromaKeyIndex = 0,
 399          .ChromaKeyMode = 0,
 400          .ShadowFunction = vk_to_gen_shadow_compare_op[pCreateInfo->compareOp],
 401          .CubeSurfaceControlMode = OVERRIDE,
 402
 403          .BorderColorPointer = border_color_offset,
 404
 405 #if GEN_GEN >= 8
 406          .LODClampMagnificationMode = MIPNONE,
 407 #endif
 408
 409          .MaximumAnisotropy = vk_to_gen_max_anisotropy(pCreateInfo->maxAnisotropy),
 410          .RAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
 411          .RAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
 412          .VAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
 413          .VAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
 414          .UAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
 415          .UAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
 416          .TrilinearFilterQuality = 0,
 417          .NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates,
 418          .TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU],
 419          .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV],
 420          .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW],
 421
 422 #if GEN_GEN >= 9
 423          .ReductionType = sampler_reduction_mode,
 424          .ReductionTypeEnable = enable_sampler_reduction,
 425 #endif
 426       };
 427
 428       GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state);
 429    }
 430
 431    *pSampler = anv_sampler_to_handle(sampler);
 432
 433    return VK_SUCCESS;
 434 }