2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34 void PRINTFLIKE(3, 4) UNUSED
35 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
41 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
44 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
48 isl_device_init(struct isl_device
*dev
,
49 const struct brw_device_info
*info
)
52 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
54 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
55 * device properties at buildtime. Verify that the macros with the device
56 * properties chosen during runtime.
58 assert(ISL_DEV_GEN(dev
) == dev
->info
->gen
);
59 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
) == dev
->use_separate_stencil
);
61 /* Did we break hiz or stencil? */
62 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
63 assert(info
->has_hiz_and_separate_stencil
);
64 if (info
->must_use_separate_stencil
)
65 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
69 * @param[out] info is written only on success
72 isl_tiling_get_info(const struct isl_device
*dev
,
73 enum isl_tiling tiling
,
74 uint32_t format_block_size
,
75 struct isl_tile_info
*tile_info
)
77 const uint32_t bs
= format_block_size
;
78 uint32_t width
, height
;
83 case ISL_TILING_LINEAR
:
99 /* XXX: Should W tile be same as Y? */
105 case ISL_TILING_Ys
: {
106 if (ISL_DEV_GEN(dev
) < 9)
109 if (!isl_is_pow2(bs
))
112 bool is_Ys
= tiling
== ISL_TILING_Ys
;
114 width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
115 height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
120 *tile_info
= (struct isl_tile_info
) {
124 .size
= width
* height
,
131 isl_tiling_get_extent(const struct isl_device
*dev
,
132 enum isl_tiling tiling
,
133 uint32_t format_block_size
,
134 struct isl_extent2d
*e
)
136 struct isl_tile_info tile_info
;
137 isl_tiling_get_info(dev
, tiling
, format_block_size
, &tile_info
);
138 *e
= isl_extent2d(tile_info
.width
, tile_info
.height
);
142 * @param[out] tiling is set only on success
145 isl_surf_choose_tiling(const struct isl_device
*dev
,
146 const struct isl_surf_init_info
*restrict info
,
147 enum isl_tiling
*tiling
)
149 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
151 if (ISL_DEV_GEN(dev
) >= 7) {
152 gen7_filter_tiling(dev
, info
, &tiling_flags
);
154 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
155 gen7_filter_tiling(dev
, info
, &tiling_flags
);
158 #define CHOOSE(__tiling) \
160 if (tiling_flags & (1u << (__tiling))) { \
161 *tiling = (__tiling); \
166 /* Of the tiling modes remaining, choose the one that offers the best
170 if (info
->dim
== ISL_SURF_DIM_1D
) {
171 /* Prefer linear for 1D surfaces because they do not benefit from
172 * tiling. To the contrary, tiling leads to wasted memory and poor
173 * memory locality due to the swizzling and alignment restrictions
174 * required in tiled surfaces.
176 CHOOSE(ISL_TILING_LINEAR
);
179 CHOOSE(ISL_TILING_Ys
);
180 CHOOSE(ISL_TILING_Yf
);
181 CHOOSE(ISL_TILING_Y0
);
182 CHOOSE(ISL_TILING_X
);
183 CHOOSE(ISL_TILING_W
);
184 CHOOSE(ISL_TILING_LINEAR
);
188 /* No tiling mode accomodates the inputs. */
193 isl_choose_msaa_layout(const struct isl_device
*dev
,
194 const struct isl_surf_init_info
*info
,
195 enum isl_tiling tiling
,
196 enum isl_msaa_layout
*msaa_layout
)
198 if (ISL_DEV_GEN(dev
) >= 8) {
199 return gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
200 } else if (ISL_DEV_GEN(dev
) >= 7) {
201 return gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
202 } else if (ISL_DEV_GEN(dev
) >= 6) {
203 return gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
205 return gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
210 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
211 uint32_t *width
, uint32_t *height
)
213 assert(isl_is_pow2(samples
));
215 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
218 * If the surface is multisampled and it is a depth or stencil surface
219 * or Multisampled Surface StorageFormat in SURFACE_STATE is
220 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
224 *width
= isl_align(*width
, 2) << ((ffs(samples
) - 0) / 2);
226 *height
= isl_align(*height
, 2) << ((ffs(samples
) - 1) / 2);
229 static enum isl_array_pitch_span
230 isl_choose_array_pitch_span(const struct isl_device
*dev
,
231 const struct isl_surf_init_info
*restrict info
,
232 enum isl_dim_layout dim_layout
,
233 const struct isl_extent4d
*phys_level0_sa
)
235 switch (dim_layout
) {
236 case ISL_DIM_LAYOUT_GEN9_1D
:
237 case ISL_DIM_LAYOUT_GEN4_2D
:
238 if (ISL_DEV_GEN(dev
) >= 8) {
239 /* QPitch becomes programmable in Broadwell. So choose the
240 * most compact QPitch possible in order to conserve memory.
242 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
243 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
245 * - Software must ensure that this field is set to a value
246 * sufficiently large such that the array slices in the surface
247 * do not overlap. Refer to the Memory Data Formats section for
248 * information on how surfaces are stored in memory.
250 * - This field specifies the distance in rows between array
251 * slices. It is used only in the following cases:
253 * - Surface Array is enabled OR
254 * - Number of Mulitsamples is not NUMSAMPLES_1 and
255 * Multisampled Surface Storage Format set to MSFMT_MSS OR
256 * - Surface Type is SURFTYPE_CUBE
258 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
259 } else if (ISL_DEV_GEN(dev
) >= 7) {
260 /* Note that Ivybridge introduces
261 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
262 * driver more control over the QPitch.
265 if (phys_level0_sa
->array_len
== 1) {
266 /* The hardware will never use the QPitch. So choose the most
267 * compact QPitch possible in order to conserve memory.
269 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
272 if (isl_surf_usage_is_depth_or_stencil(info
->usage
)) {
273 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
274 * Section 6.18.4.7: Surface Arrays (p112):
276 * If Surface Array Spacing is set to ARYSPC_FULL (note that
277 * the depth buffer and stencil buffer have an implied value of
280 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
283 if (info
->levels
== 1) {
284 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
287 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
290 return ISL_ARRAY_PITCH_SPAN_FULL
;
291 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
292 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
293 isl_surf_usage_is_stencil(info
->usage
)) {
294 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
295 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
297 * The separate stencil buffer does not support mip mapping, thus
298 * the storage for LODs other than LOD 0 is not needed.
300 assert(info
->levels
== 1);
301 assert(phys_level0_sa
->array_len
== 1);
302 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
304 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
305 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
306 isl_surf_usage_is_stencil(info
->usage
)) {
307 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
308 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
310 * The separate stencil buffer does not support mip mapping,
311 * thus the storage for LODs other than LOD 0 is not needed.
313 assert(info
->levels
== 1);
314 assert(phys_level0_sa
->array_len
== 1);
315 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
318 if (phys_level0_sa
->array_len
== 1) {
319 /* The hardware will never use the QPitch. So choose the most
320 * compact QPitch possible in order to conserve memory.
322 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
325 return ISL_ARRAY_PITCH_SPAN_FULL
;
328 case ISL_DIM_LAYOUT_GEN4_3D
:
329 /* The hardware will never use the QPitch. So choose the most
330 * compact QPitch possible in order to conserve memory.
332 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
335 unreachable("bad isl_dim_layout");
336 return ISL_ARRAY_PITCH_SPAN_FULL
;
340 isl_choose_image_alignment_el(const struct isl_device
*dev
,
341 const struct isl_surf_init_info
*restrict info
,
342 enum isl_tiling tiling
,
343 enum isl_msaa_layout msaa_layout
,
344 struct isl_extent3d
*image_align_el
)
346 if (ISL_DEV_GEN(dev
) >= 9) {
347 gen9_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
349 } else if (ISL_DEV_GEN(dev
) >= 8) {
350 gen8_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
352 } else if (ISL_DEV_GEN(dev
) >= 7) {
353 gen7_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
355 } else if (ISL_DEV_GEN(dev
) >= 6) {
356 gen6_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
359 gen4_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
364 static enum isl_dim_layout
365 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
366 enum isl_surf_dim logical_dim
)
368 if (ISL_DEV_GEN(dev
) >= 9) {
369 switch (logical_dim
) {
370 case ISL_SURF_DIM_1D
:
371 return ISL_DIM_LAYOUT_GEN9_1D
;
372 case ISL_SURF_DIM_2D
:
373 case ISL_SURF_DIM_3D
:
374 return ISL_DIM_LAYOUT_GEN4_2D
;
377 switch (logical_dim
) {
378 case ISL_SURF_DIM_1D
:
379 case ISL_SURF_DIM_2D
:
380 return ISL_DIM_LAYOUT_GEN4_2D
;
381 case ISL_SURF_DIM_3D
:
382 return ISL_DIM_LAYOUT_GEN4_3D
;
386 unreachable("bad isl_surf_dim");
387 return ISL_DIM_LAYOUT_GEN4_2D
;
391 * Calculate the physical extent of the surface's first level, in units of
392 * surface samples. The result is aligned to the format's compression block.
395 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
396 const struct isl_surf_init_info
*restrict info
,
397 enum isl_dim_layout dim_layout
,
398 enum isl_tiling tiling
,
399 enum isl_msaa_layout msaa_layout
,
400 struct isl_extent4d
*phys_level0_sa
)
402 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
404 if (isl_format_is_yuv(info
->format
))
405 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
408 case ISL_SURF_DIM_1D
:
409 assert(info
->height
== 1);
410 assert(info
->depth
== 1);
411 assert(info
->samples
== 1);
412 assert(!isl_format_is_compressed(info
->format
));
414 switch (dim_layout
) {
415 case ISL_DIM_LAYOUT_GEN4_3D
:
416 unreachable("bad isl_dim_layout");
418 case ISL_DIM_LAYOUT_GEN9_1D
:
419 case ISL_DIM_LAYOUT_GEN4_2D
:
420 *phys_level0_sa
= (struct isl_extent4d
) {
424 .a
= info
->array_len
,
430 case ISL_SURF_DIM_2D
:
431 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
433 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
434 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
436 switch (msaa_layout
) {
437 case ISL_MSAA_LAYOUT_NONE
:
438 assert(info
->depth
== 1);
439 assert(info
->samples
== 1);
441 *phys_level0_sa
= (struct isl_extent4d
) {
442 .w
= isl_align(info
->width
, fmtl
->bw
),
443 .h
= isl_align(info
->height
, fmtl
->bh
),
445 .a
= info
->array_len
,
449 case ISL_MSAA_LAYOUT_ARRAY
:
450 assert(info
->depth
== 1);
451 assert(info
->array_len
== 1);
452 assert(!isl_format_is_compressed(info
->format
));
454 *phys_level0_sa
= (struct isl_extent4d
) {
462 case ISL_MSAA_LAYOUT_INTERLEAVED
:
463 assert(info
->depth
== 1);
464 assert(info
->array_len
== 1);
465 assert(!isl_format_is_compressed(info
->format
));
467 *phys_level0_sa
= (struct isl_extent4d
) {
474 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
481 case ISL_SURF_DIM_3D
:
482 assert(info
->array_len
== 1);
483 assert(info
->samples
== 1);
486 isl_finishme("%s:%s: compression block with depth > 1",
490 switch (dim_layout
) {
491 case ISL_DIM_LAYOUT_GEN9_1D
:
492 unreachable("bad isl_dim_layout");
494 case ISL_DIM_LAYOUT_GEN4_2D
:
495 assert(ISL_DEV_GEN(dev
) >= 9);
497 *phys_level0_sa
= (struct isl_extent4d
) {
498 .w
= isl_align(info
->width
, fmtl
->bw
),
499 .h
= isl_align(info
->height
, fmtl
->bh
),
505 case ISL_DIM_LAYOUT_GEN4_3D
:
506 assert(ISL_DEV_GEN(dev
) < 9);
507 *phys_level0_sa
= (struct isl_extent4d
) {
508 .w
= isl_align(info
->width
, fmtl
->bw
),
509 .h
= isl_align(info
->height
, fmtl
->bh
),
520 * A variant of isl_calc_phys_slice0_extent_sa() specific to
521 * ISL_DIM_LAYOUT_GEN4_2D.
524 isl_calc_phys_slice0_extent_sa_gen4_2d(
525 const struct isl_device
*dev
,
526 const struct isl_surf_init_info
*restrict info
,
527 enum isl_msaa_layout msaa_layout
,
528 const struct isl_extent3d
*image_align_sa
,
529 const struct isl_extent4d
*phys_level0_sa
,
530 struct isl_extent2d
*phys_slice0_sa
)
532 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
534 assert(phys_level0_sa
->depth
== 1);
536 if (info
->levels
== 1 && msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
) {
537 /* Do not pad the surface to the image alignment. Instead, pad it only
538 * to the pixel format's block alignment.
540 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
541 * cycles on the below mipmap layout caluclations. Reducing the
542 * alignment here is safe because we later align the row pitch and array
543 * pitch to the tile boundary. It is safe even for
544 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
545 * to accomodate the interleaved samples.
547 * For linear surfaces, reducing the alignment here permits us to later
548 * choose an arbitrary, non-aligned row pitch. If the surface backs
549 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
550 * VkBufferImageCopy::bufferRowLength.
552 *phys_slice0_sa
= (struct isl_extent2d
) {
553 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
554 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
559 uint32_t slice_top_w
= 0;
560 uint32_t slice_bottom_w
= 0;
561 uint32_t slice_left_h
= 0;
562 uint32_t slice_right_h
= 0;
564 uint32_t W0
= phys_level0_sa
->w
;
565 uint32_t H0
= phys_level0_sa
->h
;
567 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
568 uint32_t W
= isl_minify(W0
, l
);
569 uint32_t H
= isl_minify(H0
, l
);
571 if (msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
572 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
575 * If the surface is multisampled and it is a depth or stencil
576 * surface or Multisampled Surface StorageFormat in
577 * SURFACE_STATE is MSFMT_DEPTH_STENCIL, W_L and H_L must be
578 * adjusted as follows before proceeding: [...]
580 isl_msaa_interleaved_scale_px_to_sa(info
->samples
, &W
, &H
);
583 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
584 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
601 *phys_slice0_sa
= (struct isl_extent2d
) {
602 .w
= MAX(slice_top_w
, slice_bottom_w
),
603 .h
= MAX(slice_left_h
, slice_right_h
),
608 * A variant of isl_calc_phys_slice0_extent_sa() specific to
609 * ISL_DIM_LAYOUT_GEN4_3D.
612 isl_calc_phys_slice0_extent_sa_gen4_3d(
613 const struct isl_device
*dev
,
614 const struct isl_surf_init_info
*restrict info
,
615 const struct isl_extent3d
*image_align_sa
,
616 const struct isl_extent4d
*phys_level0_sa
,
617 struct isl_extent2d
*phys_slice0_sa
)
619 assert(info
->samples
== 1);
620 assert(phys_level0_sa
->array_len
== 1);
622 uint32_t slice_w
= 0;
623 uint32_t slice_h
= 0;
625 uint32_t W0
= phys_level0_sa
->w
;
626 uint32_t H0
= phys_level0_sa
->h
;
627 uint32_t D0
= phys_level0_sa
->d
;
629 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
630 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
631 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
632 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
634 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
635 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
637 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
638 slice_h
+= level_h
* max_layers_vert
;
641 *phys_slice0_sa
= (struct isl_extent2d
) {
648 * A variant of isl_calc_phys_slice0_extent_sa() specific to
649 * ISL_DIM_LAYOUT_GEN9_1D.
652 isl_calc_phys_slice0_extent_sa_gen9_1d(
653 const struct isl_device
*dev
,
654 const struct isl_surf_init_info
*restrict info
,
655 const struct isl_extent3d
*image_align_sa
,
656 const struct isl_extent4d
*phys_level0_sa
,
657 struct isl_extent2d
*phys_slice0_sa
)
659 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
661 assert(phys_level0_sa
->height
== 1);
662 assert(phys_level0_sa
->depth
== 1);
663 assert(info
->samples
== 1);
664 assert(image_align_sa
->w
>= fmtl
->bw
);
666 uint32_t slice_w
= 0;
667 const uint32_t W0
= phys_level0_sa
->w
;
669 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
670 uint32_t W
= isl_minify(W0
, l
);
671 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
676 *phys_slice0_sa
= isl_extent2d(slice_w
, 1);
680 * Calculate the physical extent of the surface's first array slice, in units
681 * of surface samples. If the surface is multi-leveled, then the result will
682 * be aligned to \a image_align_sa.
685 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
686 const struct isl_surf_init_info
*restrict info
,
687 enum isl_dim_layout dim_layout
,
688 enum isl_msaa_layout msaa_layout
,
689 const struct isl_extent3d
*image_align_sa
,
690 const struct isl_extent4d
*phys_level0_sa
,
691 struct isl_extent2d
*phys_slice0_sa
)
693 switch (dim_layout
) {
694 case ISL_DIM_LAYOUT_GEN9_1D
:
695 isl_calc_phys_slice0_extent_sa_gen9_1d(dev
, info
,
696 image_align_sa
, phys_level0_sa
,
699 case ISL_DIM_LAYOUT_GEN4_2D
:
700 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
701 image_align_sa
, phys_level0_sa
,
704 case ISL_DIM_LAYOUT_GEN4_3D
:
705 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
706 phys_level0_sa
, phys_slice0_sa
);
712 * Calculate the pitch between physical array slices, in units of rows of
716 isl_calc_array_pitch_el_rows(const struct isl_device
*dev
,
717 const struct isl_surf_init_info
*restrict info
,
718 const struct isl_tile_info
*tile_info
,
719 enum isl_dim_layout dim_layout
,
720 enum isl_array_pitch_span array_pitch_span
,
721 const struct isl_extent3d
*image_align_sa
,
722 const struct isl_extent4d
*phys_level0_sa
,
723 const struct isl_extent2d
*phys_slice0_sa
)
725 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
726 uint32_t pitch_sa_rows
= 0;
728 switch (dim_layout
) {
729 case ISL_DIM_LAYOUT_GEN9_1D
:
730 /* Each row is an array slice */
733 case ISL_DIM_LAYOUT_GEN4_2D
:
734 switch (array_pitch_span
) {
735 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
736 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
737 case ISL_ARRAY_PITCH_SPAN_FULL
: {
738 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
739 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
740 * Surfaces >> Surface Arrays.
742 uint32_t H0_sa
= phys_level0_sa
->h
;
743 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
745 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
746 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
749 if (ISL_DEV_GEN(dev
) >= 7) {
750 /* The QPitch equation changed slightly in Ivybridge. */
756 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
758 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
759 (info
->height
% 4 == 1)) {
760 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
761 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
763 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
764 * the value calculated in the equation above , for every
765 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
767 * XXX(chadv): Is the errata natural corollary of the physical
768 * layout of interleaved samples?
773 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
778 case ISL_DIM_LAYOUT_GEN4_3D
:
779 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
780 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
783 unreachable("bad isl_dim_layout");
787 assert(pitch_sa_rows
% fmtl
->bh
== 0);
788 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
790 if (ISL_DEV_GEN(dev
) >= 9 &&
791 info
->dim
== ISL_SURF_DIM_3D
&&
792 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
793 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
795 * Tile Mode != Linear: This field must be set to an integer multiple
798 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->height
);
801 return pitch_el_rows
;
805 * Calculate the pitch of each surface row, in bytes.
808 isl_calc_row_pitch(const struct isl_device
*dev
,
809 const struct isl_surf_init_info
*restrict info
,
810 const struct isl_tile_info
*tile_info
,
811 const struct isl_extent3d
*image_align_sa
,
812 const struct isl_extent2d
*phys_slice0_sa
)
814 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
816 uint32_t row_pitch
= info
->min_pitch
;
818 /* First, align the surface to a cache line boundary, as the PRM explains
821 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
822 * Formats >> Surface Padding Requirements >> Render Target and Media
825 * The data port accesses data (pixels) outside of the surface if they
826 * are contained in the same cache request as pixels that are within the
827 * surface. These pixels will not be returned by the requesting message,
828 * however if these pixels lie outside of defined pages in the GTT,
829 * a GTT error will result when the cache request is processed. In order
830 * to avoid these GTT errors, “padding” at the bottom of the surface is
831 * sometimes necessary.
833 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
834 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
836 * The sampling engine accesses texels outside of the surface if they
837 * are contained in the same cache line as texels that are within the
838 * surface. These texels will not participate in any calculation
839 * performed by the sampling engine and will not affect the result of
840 * any sampling engine operation, however if these texels lie outside of
841 * defined pages in the GTT, a GTT error will result when the cache line
842 * is accessed. In order to avoid these GTT errors, “padding” at the
843 * bottom and right side of a sampling engine surface is sometimes
846 * It is possible that a cache line will straddle a page boundary if the
847 * base address or pitch is not aligned. All pages included in the cache
848 * lines that are part of the surface must map to valid GTT entries to
849 * avoid errors. To determine the necessary padding on the bottom and
850 * right side of the surface, refer to the table in Alignment Unit Size
851 * section for the i and j parameters for the surface format in use. The
852 * surface must then be extended to the next multiple of the alignment
853 * unit size in each dimension, and all texels contained in this
854 * extended surface must have valid GTT entries.
856 * For example, suppose the surface size is 15 texels by 10 texels and
857 * the alignment parameters are i=4 and j=2. In this case, the extended
858 * surface would be 16 by 10. Note that these calculations are done in
859 * texels, and must be converted to bytes based on the surface format
860 * being used to determine whether additional pages need to be defined.
862 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
863 row_pitch
= MAX(row_pitch
, fmtl
->bs
* phys_slice0_sa
->w
);
865 switch (tile_info
->tiling
) {
866 case ISL_TILING_LINEAR
:
867 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
868 * RENDER_SURFACE_STATE Surface Pitch (p349):
870 * - For linear render target surfaces and surfaces accessed with the
871 * typed data port messages, the pitch must be a multiple of the
872 * element size for non-YUV surface formats. Pitch must be
873 * a multiple of 2 * element size for YUV surface formats.
875 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
876 * ignore because isl doesn't do buffers.]
878 * - For other linear surfaces, the pitch can be any multiple of
881 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
882 if (isl_format_is_yuv(info
->format
)) {
883 row_pitch
= isl_align_npot(row_pitch
, 2 * fmtl
->bs
);
885 row_pitch
= isl_align_npot(row_pitch
, fmtl
->bs
);
890 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
891 * RENDER_SURFACE_STATE Surface Pitch (p349):
893 * - For tiled surfaces, the pitch must be a multiple of the tile
896 row_pitch
= isl_align(row_pitch
, tile_info
->width
);
904 * Calculate the surface's total height, including padding, in units of
908 isl_calc_total_height_el(const struct isl_device
*dev
,
909 const struct isl_surf_init_info
*restrict info
,
910 const struct isl_tile_info
*tile_info
,
911 uint32_t phys_array_len
,
913 uint32_t array_pitch_el_rows
)
915 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
917 uint32_t total_h_el
= phys_array_len
* array_pitch_el_rows
;
918 uint32_t pad_bytes
= 0;
920 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
921 * Formats >> Surface Padding Requirements >> Render Target and Media
924 * The data port accesses data (pixels) outside of the surface if they
925 * are contained in the same cache request as pixels that are within the
926 * surface. These pixels will not be returned by the requesting message,
927 * however if these pixels lie outside of defined pages in the GTT,
928 * a GTT error will result when the cache request is processed. In
929 * order to avoid these GTT errors, “padding” at the bottom of the
930 * surface is sometimes necessary.
932 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
933 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
935 * ... Lots of padding requirements, all listed separately below.
938 /* We can safely ignore the first padding requirement, quoted below,
939 * because isl doesn't do buffers.
941 * - [pre-BDW] For buffers, which have no inherent “height,” padding
942 * requirements are different. A buffer must be padded to the next
943 * multiple of 256 array elements, with an additional 16 bytes added
944 * beyond that to account for the L1 cache line.
948 * - For compressed textures [...], padding at the bottom of the surface
949 * is to an even compressed row.
951 if (isl_format_is_compressed(info
->format
))
952 total_h_el
= isl_align(total_h_el
, 2);
955 * - For cube surfaces, an additional two rows of padding are required
956 * at the bottom of the surface.
958 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
962 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
963 * additional padding is required. These surfaces require an extra row
964 * plus 16 bytes of padding at the bottom in addition to the general
965 * padding requirements.
967 if (isl_format_is_yuv(info
->format
) &&
968 (fmtl
->bs
== 96 || fmtl
->bs
== 48|| fmtl
->bs
== 24)) {
974 * - For linear surfaces, additional padding of 64 bytes is required at
975 * the bottom of the surface. This is in addition to the padding
978 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
981 /* The below text weakens, not strengthens, the padding requirements for
982 * linear surfaces. Therefore we can safely ignore it.
984 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
985 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
986 * padding requirement is to the next aligned 64-byte boundary beyond
987 * the end of the surface. The rest of the padding requirements
988 * documented above do not apply to these surfaces.
992 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
993 * height % 4 != 0, the surface must be padded with
994 * 4-(height % 4)*Surface Pitch # of bytes.
996 if (ISL_DEV_GEN(dev
) >= 9 &&
997 tile_info
->tiling
== ISL_TILING_LINEAR
&&
998 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
999 total_h_el
= isl_align(total_h_el
, 4);
1003 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1004 * to 4 times the Surface Pitch # of bytes
1006 if (ISL_DEV_GEN(dev
) >= 9 &&
1007 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1008 info
->dim
== ISL_SURF_DIM_1D
) {
1012 /* Be sloppy. Align any leftover padding to a row boundary. */
1013 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1019 isl_surf_init_s(const struct isl_device
*dev
,
1020 struct isl_surf
*surf
,
1021 const struct isl_surf_init_info
*restrict info
)
1023 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1025 const struct isl_extent4d logical_level0_px
= {
1029 .a
= info
->array_len
,
1032 enum isl_dim_layout dim_layout
=
1033 isl_surf_choose_dim_layout(dev
, info
->dim
);
1035 enum isl_tiling tiling
;
1036 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1039 struct isl_tile_info tile_info
;
1040 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bs
, &tile_info
))
1043 enum isl_msaa_layout msaa_layout
;
1044 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1047 struct isl_extent3d image_align_el
;
1048 isl_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
1051 struct isl_extent3d image_align_sa
=
1052 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1054 struct isl_extent4d phys_level0_sa
;
1055 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1057 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1058 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1060 enum isl_array_pitch_span array_pitch_span
=
1061 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1063 struct isl_extent2d phys_slice0_sa
;
1064 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1065 &image_align_sa
, &phys_level0_sa
,
1067 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1068 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1070 const uint32_t row_pitch
= isl_calc_row_pitch(dev
, info
, &tile_info
,
1074 const uint32_t array_pitch_el_rows
=
1075 isl_calc_array_pitch_el_rows(dev
, info
, &tile_info
, dim_layout
,
1076 array_pitch_span
, &image_align_sa
,
1077 &phys_level0_sa
, &phys_slice0_sa
);
1079 const uint32_t total_h_el
=
1080 isl_calc_total_height_el(dev
, info
, &tile_info
,
1081 phys_level0_sa
.array_len
, row_pitch
,
1082 array_pitch_el_rows
);
1084 const uint32_t total_h_sa
= total_h_el
* fmtl
->bh
;
1085 const uint32_t size
= row_pitch
* isl_align(total_h_sa
, tile_info
.height
);
1087 /* Alignment of surface base address, in bytes */
1088 uint32_t base_alignment
= MAX(1, info
->min_alignment
);
1089 assert(isl_is_pow2(base_alignment
) && isl_is_pow2(tile_info
.size
));
1090 base_alignment
= MAX(base_alignment
, tile_info
.size
);
1092 *surf
= (struct isl_surf
) {
1094 .dim_layout
= dim_layout
,
1095 .msaa_layout
= msaa_layout
,
1097 .format
= info
->format
,
1099 .levels
= info
->levels
,
1100 .samples
= info
->samples
,
1102 .image_alignment_el
= image_align_el
,
1103 .logical_level0_px
= logical_level0_px
,
1104 .phys_level0_sa
= phys_level0_sa
,
1107 .alignment
= base_alignment
,
1108 .row_pitch
= row_pitch
,
1109 .array_pitch_el_rows
= array_pitch_el_rows
,
1110 .array_pitch_span
= array_pitch_span
,
1112 .usage
= info
->usage
,
1119 * A variant of isl_surf_get_image_offset_sa() specific to
1120 * ISL_DIM_LAYOUT_GEN4_2D.
1123 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1124 uint32_t level
, uint32_t layer
,
1125 uint32_t *x_offset_sa
,
1126 uint32_t *y_offset_sa
)
1128 assert(level
< surf
->levels
);
1129 assert(layer
< surf
->phys_level0_sa
.array_len
);
1130 assert(surf
->phys_level0_sa
.depth
== 1);
1132 const struct isl_extent3d image_align_sa
=
1133 isl_surf_get_image_alignment_sa(surf
);
1135 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1136 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1139 uint32_t y
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1141 for (uint32_t l
= 0; l
< level
; ++l
) {
1143 uint32_t W
= isl_minify(W0
, l
);
1145 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1146 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, &W
, NULL
);
1148 x
+= isl_align_npot(W
, image_align_sa
.w
);
1150 uint32_t H
= isl_minify(H0
, l
);
1152 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1153 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, NULL
, &H
);
1155 y
+= isl_align_npot(H
, image_align_sa
.h
);
1164 * A variant of isl_surf_get_image_offset_sa() specific to
1165 * ISL_DIM_LAYOUT_GEN4_3D.
1168 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1169 uint32_t level
, uint32_t logical_z_offset_px
,
1170 uint32_t *x_offset_sa
,
1171 uint32_t *y_offset_sa
)
1173 assert(level
< surf
->levels
);
1174 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1175 assert(surf
->phys_level0_sa
.array_len
== 1);
1177 const struct isl_extent3d image_align_sa
=
1178 isl_surf_get_image_alignment_sa(surf
);
1180 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1181 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1182 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1187 for (uint32_t l
= 0; l
< level
; ++l
) {
1188 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1189 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1190 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1192 y
+= level_h
* max_layers_vert
;
1195 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1196 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1197 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1199 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1200 const uint32_t max_layers_vert
= isl_align_div(level_d
, 1u << level
);
1202 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1203 y
+= level_h
* (logical_z_offset_px
/ max_layers_vert
);
1210 * A variant of isl_surf_get_image_offset_sa() specific to
1211 * ISL_DIM_LAYOUT_GEN9_1D.
1214 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
1215 uint32_t level
, uint32_t layer
,
1216 uint32_t *x_offset_sa
,
1217 uint32_t *y_offset_sa
)
1219 assert(level
< surf
->levels
);
1220 assert(layer
< surf
->phys_level0_sa
.array_len
);
1221 assert(surf
->phys_level0_sa
.height
== 1);
1222 assert(surf
->phys_level0_sa
.depth
== 1);
1223 assert(surf
->samples
== 1);
1225 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1226 const struct isl_extent3d image_align_sa
=
1227 isl_surf_get_image_alignment_sa(surf
);
1229 uint32_t x
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1231 for (uint32_t l
= 0; l
< level
; ++l
) {
1232 uint32_t W
= isl_minify(W0
, l
);
1233 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
1243 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1245 uint32_t logical_array_layer
,
1246 uint32_t logical_z_offset_px
,
1247 uint32_t *x_offset_sa
,
1248 uint32_t *y_offset_sa
)
1250 assert(level
< surf
->levels
);
1251 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1252 assert(logical_z_offset_px
1253 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1255 switch (surf
->dim_layout
) {
1256 case ISL_DIM_LAYOUT_GEN9_1D
:
1257 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
1258 x_offset_sa
, y_offset_sa
);
1260 case ISL_DIM_LAYOUT_GEN4_2D
:
1261 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
,
1262 x_offset_sa
, y_offset_sa
);
1264 case ISL_DIM_LAYOUT_GEN4_3D
:
1265 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1266 x_offset_sa
, y_offset_sa
);