2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34 void PRINTFLIKE(3, 4) UNUSED
35 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
41 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
44 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
48 isl_device_init(struct isl_device
*dev
,
49 const struct brw_device_info
*info
)
52 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
54 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
55 * device properties at buildtime. Verify that the macros with the device
56 * properties chosen during runtime.
58 assert(ISL_DEV_GEN(dev
) == dev
->info
->gen
);
59 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
) == dev
->use_separate_stencil
);
61 /* Did we break hiz or stencil? */
62 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
63 assert(info
->has_hiz_and_separate_stencil
);
64 if (info
->must_use_separate_stencil
)
65 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
69 isl_format_has_sint_channel(enum isl_format fmt
)
71 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
73 return fmtl
->channels
.r
.type
== ISL_SINT
||
74 fmtl
->channels
.g
.type
== ISL_SINT
||
75 fmtl
->channels
.b
.type
== ISL_SINT
||
76 fmtl
->channels
.a
.type
== ISL_SINT
||
77 fmtl
->channels
.l
.type
== ISL_SINT
||
78 fmtl
->channels
.i
.type
== ISL_SINT
||
79 fmtl
->channels
.p
.type
== ISL_SINT
||
80 fmtl
->channels
.g
.type
== ISL_SINT
;
84 * @param[out] info is written only on success
87 isl_tiling_get_info(const struct isl_device
*dev
,
88 enum isl_tiling tiling
,
89 uint32_t format_block_size
,
90 struct isl_tile_info
*tile_info
)
92 const uint32_t bs
= format_block_size
;
93 uint32_t width
, height
;
98 case ISL_TILING_LINEAR
:
114 /* XXX: Should W tile be same as Y? */
120 case ISL_TILING_Ys
: {
121 if (ISL_DEV_GEN(dev
) < 9)
124 if (!isl_is_pow2(bs
))
127 bool is_Ys
= tiling
== ISL_TILING_Ys
;
129 width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
130 height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
135 *tile_info
= (struct isl_tile_info
) {
139 .size
= width
* height
,
146 isl_tiling_get_extent(const struct isl_device
*dev
,
147 enum isl_tiling tiling
,
148 uint32_t format_block_size
,
149 struct isl_extent2d
*e
)
151 struct isl_tile_info tile_info
;
152 isl_tiling_get_info(dev
, tiling
, format_block_size
, &tile_info
);
153 *e
= isl_extent2d(tile_info
.width
, tile_info
.height
);
157 * @param[out] tiling is set only on success
160 isl_surf_choose_tiling(const struct isl_device
*dev
,
161 const struct isl_surf_init_info
*restrict info
,
162 enum isl_tiling
*tiling
)
164 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
166 if (ISL_DEV_GEN(dev
) >= 7) {
167 gen7_filter_tiling(dev
, info
, &tiling_flags
);
169 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
170 gen7_filter_tiling(dev
, info
, &tiling_flags
);
173 #define CHOOSE(__tiling) \
175 if (tiling_flags & (1u << (__tiling))) { \
176 *tiling = (__tiling); \
181 /* Of the tiling modes remaining, choose the one that offers the best
184 CHOOSE(ISL_TILING_Ys
);
185 CHOOSE(ISL_TILING_Yf
);
186 CHOOSE(ISL_TILING_Y0
);
187 CHOOSE(ISL_TILING_X
);
188 CHOOSE(ISL_TILING_W
);
189 CHOOSE(ISL_TILING_LINEAR
);
193 /* No tiling mode accomodates the inputs. */
198 isl_choose_msaa_layout(const struct isl_device
*dev
,
199 const struct isl_surf_init_info
*info
,
200 enum isl_tiling tiling
,
201 enum isl_msaa_layout
*msaa_layout
)
203 if (ISL_DEV_GEN(dev
) >= 8) {
204 return gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
205 } else if (ISL_DEV_GEN(dev
) >= 7) {
206 return gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
207 } else if (ISL_DEV_GEN(dev
) >= 6) {
208 return gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
210 return gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
215 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
216 uint32_t *width
, uint32_t *height
)
218 assert(isl_is_pow2(samples
));
220 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
223 * If the surface is multisampled and it is a depth or stencil surface
224 * or Multisampled Surface StorageFormat in SURFACE_STATE is
225 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
229 *width
= isl_align(*width
, 2) << ((ffs(samples
) - 0) / 2);
231 *height
= isl_align(*height
, 2) << ((ffs(samples
) - 1) / 2);
234 static enum isl_array_pitch_span
235 isl_choose_array_pitch_span(const struct isl_device
*dev
,
236 const struct isl_surf_init_info
*restrict info
,
237 enum isl_dim_layout dim_layout
,
238 const struct isl_extent4d
*phys_level0_sa
)
240 switch (dim_layout
) {
241 case ISL_DIM_LAYOUT_GEN9_1D
:
242 if (ISL_DEV_GEN(dev
) >= 9)
243 isl_finishme("%s:%s: [SKL+] 1d surface layout", __FILE__
, __func__
);
246 case ISL_DIM_LAYOUT_GEN4_2D
:
247 if (ISL_DEV_GEN(dev
) >= 8) {
248 /* QPitch becomes programmable in Broadwell. So choose the
249 * most compact QPitch possible in order to conserve memory.
251 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
252 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
254 * - Software must ensure that this field is set to a value
255 * sufficiently large such that the array slices in the surface
256 * do not overlap. Refer to the Memory Data Formats section for
257 * information on how surfaces are stored in memory.
259 * - This field specifies the distance in rows between array
260 * slices. It is used only in the following cases:
262 * - Surface Array is enabled OR
263 * - Number of Mulitsamples is not NUMSAMPLES_1 and
264 * Multisampled Surface Storage Format set to MSFMT_MSS OR
265 * - Surface Type is SURFTYPE_CUBE
267 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
268 } else if (ISL_DEV_GEN(dev
) >= 7) {
269 /* Note that Ivybridge introduces
270 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
271 * driver more control over the QPitch.
274 if (phys_level0_sa
->array_len
== 1) {
275 /* The hardware will never use the QPitch. So choose the most
276 * compact QPitch possible in order to conserve memory.
278 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
281 if (isl_surf_usage_is_depth_or_stencil(info
->usage
)) {
282 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
283 * Section 6.18.4.7: Surface Arrays (p112):
285 * If Surface Array Spacing is set to ARYSPC_FULL (note that
286 * the depth buffer and stencil buffer have an implied value of
289 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
292 if (info
->levels
== 1) {
293 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
296 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
299 return ISL_ARRAY_PITCH_SPAN_FULL
;
300 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
301 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
302 isl_surf_usage_is_stencil(info
->usage
)) {
303 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
304 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
306 * The separate stencil buffer does not support mip mapping, thus
307 * the storage for LODs other than LOD 0 is not needed.
309 assert(info
->levels
== 1);
310 assert(phys_level0_sa
->array_len
== 1);
311 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
313 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
314 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
315 isl_surf_usage_is_stencil(info
->usage
)) {
316 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
317 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
319 * The separate stencil buffer does not support mip mapping,
320 * thus the storage for LODs other than LOD 0 is not needed.
322 assert(info
->levels
== 1);
323 assert(phys_level0_sa
->array_len
== 1);
324 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
327 if (phys_level0_sa
->array_len
== 1) {
328 /* The hardware will never use the QPitch. So choose the most
329 * compact QPitch possible in order to conserve memory.
331 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
334 return ISL_ARRAY_PITCH_SPAN_FULL
;
337 case ISL_DIM_LAYOUT_GEN4_3D
:
338 /* The hardware will never use the QPitch. So choose the most
339 * compact QPitch possible in order to conserve memory.
341 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
344 unreachable("bad isl_dim_layout");
345 return ISL_ARRAY_PITCH_SPAN_FULL
;
349 isl_choose_image_alignment_el(const struct isl_device
*dev
,
350 const struct isl_surf_init_info
*restrict info
,
351 enum isl_tiling tiling
,
352 enum isl_msaa_layout msaa_layout
,
353 struct isl_extent3d
*image_align_el
)
355 if (ISL_DEV_GEN(dev
) >= 9) {
356 gen9_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
358 } else if (ISL_DEV_GEN(dev
) >= 8) {
359 gen8_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
361 } else if (ISL_DEV_GEN(dev
) >= 7) {
362 gen7_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
364 } else if (ISL_DEV_GEN(dev
) >= 6) {
365 gen6_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
368 gen4_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
373 static enum isl_dim_layout
374 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
375 enum isl_surf_dim logical_dim
)
377 if (ISL_DEV_GEN(dev
) >= 9) {
378 switch (logical_dim
) {
379 case ISL_SURF_DIM_1D
:
380 return ISL_DIM_LAYOUT_GEN9_1D
;
381 case ISL_SURF_DIM_2D
:
382 case ISL_SURF_DIM_3D
:
383 return ISL_DIM_LAYOUT_GEN4_2D
;
386 switch (logical_dim
) {
387 case ISL_SURF_DIM_1D
:
388 case ISL_SURF_DIM_2D
:
389 return ISL_DIM_LAYOUT_GEN4_2D
;
390 case ISL_SURF_DIM_3D
:
391 return ISL_DIM_LAYOUT_GEN4_3D
;
395 unreachable("bad isl_surf_dim");
396 return ISL_DIM_LAYOUT_GEN4_2D
;
400 * Calculate the physical extent of the surface's first level, in units of
404 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
405 const struct isl_surf_init_info
*restrict info
,
406 enum isl_dim_layout dim_layout
,
407 enum isl_tiling tiling
,
408 enum isl_msaa_layout msaa_layout
,
409 struct isl_extent4d
*phys_level0_sa
)
411 if (isl_format_is_yuv(info
->format
))
412 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
415 case ISL_SURF_DIM_1D
:
416 assert(info
->height
== 1);
417 assert(info
->depth
== 1);
418 assert(info
->samples
== 1);
420 switch (dim_layout
) {
421 case ISL_DIM_LAYOUT_GEN4_3D
:
422 unreachable("bad isl_dim_layout");
424 case ISL_DIM_LAYOUT_GEN9_1D
:
425 if (ISL_DEV_GEN(dev
) >= 9)
426 isl_finishme("%s:%s: [SKL+] 1d surface layout", __FILE__
, __func__
);
429 case ISL_DIM_LAYOUT_GEN4_2D
:
430 *phys_level0_sa
= (struct isl_extent4d
) {
434 .a
= info
->array_len
,
440 case ISL_SURF_DIM_2D
:
441 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
443 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
444 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
446 switch (msaa_layout
) {
447 case ISL_MSAA_LAYOUT_NONE
:
448 assert(info
->depth
== 1);
449 assert(info
->samples
== 1);
451 *phys_level0_sa
= (struct isl_extent4d
) {
455 .a
= info
->array_len
,
459 case ISL_MSAA_LAYOUT_ARRAY
:
460 assert(info
->depth
== 1);
461 assert(info
->array_len
== 1);
462 assert(!isl_format_is_compressed(info
->format
));
464 *phys_level0_sa
= (struct isl_extent4d
) {
472 case ISL_MSAA_LAYOUT_INTERLEAVED
:
473 assert(info
->depth
== 1);
474 assert(info
->array_len
== 1);
475 assert(!isl_format_is_compressed(info
->format
));
477 *phys_level0_sa
= (struct isl_extent4d
) {
484 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
491 case ISL_SURF_DIM_3D
:
492 assert(info
->array_len
== 1);
493 assert(info
->samples
== 1);
495 switch (dim_layout
) {
496 case ISL_DIM_LAYOUT_GEN9_1D
:
497 unreachable("bad isl_dim_layout");
499 case ISL_DIM_LAYOUT_GEN4_2D
:
500 assert(ISL_DEV_GEN(dev
) >= 9);
502 *phys_level0_sa
= (struct isl_extent4d
) {
510 case ISL_DIM_LAYOUT_GEN4_3D
:
511 assert(ISL_DEV_GEN(dev
) < 9);
512 *phys_level0_sa
= (struct isl_extent4d
) {
525 * A variant of isl_calc_phys_slice0_extent_sa() specific to
526 * ISL_DIM_LAYOUT_GEN4_2D.
529 isl_calc_phys_slice0_extent_sa_gen4_2d(
530 const struct isl_device
*dev
,
531 const struct isl_surf_init_info
*restrict info
,
532 enum isl_msaa_layout msaa_layout
,
533 const struct isl_extent3d
*image_align_sa
,
534 const struct isl_extent4d
*phys_level0_sa
,
535 struct isl_extent2d
*phys_slice0_sa
)
537 assert(phys_level0_sa
->depth
== 1);
539 if (info
->levels
== 1) {
540 /* Do not align single-level surfaces to the image alignment.
542 * For tiled surfaces, skipping the alignment here avoids wasting CPU
543 * cycles on the below mipmap layout caluclations. Skipping the
544 * alignment here is safe because we later align the row pitch and array
545 * pitch to the tile boundary. It is safe even for
546 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
547 * to accomodate the interleaved samples.
549 * For linear surfaces, skipping the alignment here permits us to later
550 * choose an arbitrary, non-aligned row pitch. If the surface backs
551 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
552 * VkBufferImageCopy::bufferRowLength.
554 *phys_slice0_sa
= isl_extent2d(phys_level0_sa
->w
, phys_level0_sa
->h
);
558 uint32_t slice_top_w
= 0;
559 uint32_t slice_bottom_w
= 0;
560 uint32_t slice_left_h
= 0;
561 uint32_t slice_right_h
= 0;
563 uint32_t W0
= phys_level0_sa
->w
;
564 uint32_t H0
= phys_level0_sa
->h
;
566 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
567 uint32_t W
= isl_minify(W0
, l
);
568 uint32_t H
= isl_minify(H0
, l
);
570 if (msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
571 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
574 * If the surface is multisampled and it is a depth or stencil
575 * surface or Multisampled Surface StorageFormat in
576 * SURFACE_STATE is MSFMT_DEPTH_STENCIL, W_L and H_L must be
577 * adjusted as follows before proceeding: [...]
579 isl_msaa_interleaved_scale_px_to_sa(info
->samples
, &W
, &H
);
582 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
583 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
600 *phys_slice0_sa
= (struct isl_extent2d
) {
601 .w
= MAX(slice_top_w
, slice_bottom_w
),
602 .h
= MAX(slice_left_h
, slice_right_h
),
607 * A variant of isl_calc_phys_slice0_extent_sa() specific to
608 * ISL_DIM_LAYOUT_GEN4_3D.
611 isl_calc_phys_slice0_extent_sa_gen4_3d(
612 const struct isl_device
*dev
,
613 const struct isl_surf_init_info
*restrict info
,
614 const struct isl_extent3d
*image_align_sa
,
615 const struct isl_extent4d
*phys_level0_sa
,
616 struct isl_extent2d
*phys_slice0_sa
)
618 assert(info
->samples
== 1);
619 assert(phys_level0_sa
->array_len
== 1);
621 uint32_t slice_w
= 0;
622 uint32_t slice_h
= 0;
624 uint32_t W0
= phys_level0_sa
->w
;
625 uint32_t H0
= phys_level0_sa
->h
;
626 uint32_t D0
= phys_level0_sa
->d
;
628 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
629 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
630 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
631 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
633 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
634 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
636 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
637 slice_h
+= level_h
* max_layers_vert
;
640 *phys_slice0_sa
= (struct isl_extent2d
) {
647 * Calculate the physical extent of the surface's first array slice, in units
648 * of surface samples. If the surface is multi-leveled, then the result will
649 * be aligned to \a image_align_sa.
652 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
653 const struct isl_surf_init_info
*restrict info
,
654 enum isl_dim_layout dim_layout
,
655 enum isl_msaa_layout msaa_layout
,
656 const struct isl_extent3d
*image_align_sa
,
657 const struct isl_extent4d
*phys_level0_sa
,
658 struct isl_extent2d
*phys_slice0_sa
)
660 switch (dim_layout
) {
661 case ISL_DIM_LAYOUT_GEN9_1D
:
662 if (ISL_DEV_GEN(dev
) >= 9)
663 isl_finishme("%s:%s: [SKL+] physical layout of 1d surfaces",
666 case ISL_DIM_LAYOUT_GEN4_2D
:
667 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
668 image_align_sa
, phys_level0_sa
,
671 case ISL_DIM_LAYOUT_GEN4_3D
:
672 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
673 phys_level0_sa
, phys_slice0_sa
);
679 * Calculate the pitch between physical array slices, in units of rows of
680 * surface samples. The result is aligned to \a image_align_sa.
683 isl_calc_array_pitch_sa_rows(const struct isl_device
*dev
,
684 const struct isl_surf_init_info
*restrict info
,
685 enum isl_dim_layout dim_layout
,
686 enum isl_array_pitch_span array_pitch_span
,
687 const struct isl_extent3d
*image_align_sa
,
688 const struct isl_extent4d
*phys_level0_sa
,
689 const struct isl_extent2d
*phys_slice0_sa
)
691 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
693 switch (dim_layout
) {
694 case ISL_DIM_LAYOUT_GEN9_1D
:
695 if (ISL_DEV_GEN(dev
) >= 9)
696 isl_finishme("%s:%s: [SKL+] physical layout of 1d surfaces",
700 case ISL_DIM_LAYOUT_GEN4_2D
:
701 switch (array_pitch_span
) {
702 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
703 return isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
704 case ISL_ARRAY_PITCH_SPAN_FULL
: {
705 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
706 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
707 * Surfaces >> Surface Arrays.
709 uint32_t H0_sa
= phys_level0_sa
->h
;
710 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
712 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
713 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
716 if (ISL_DEV_GEN(dev
) >= 7) {
717 /* The QPitch equation changed slightly in Ivybridge. */
723 uint32_t pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
725 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
726 (info
->height
% 4 == 1)) {
727 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
728 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
730 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
731 * the value calculated in the equation above , for every
732 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
734 * XXX(chadv): Is the errata natural corollary of the physical
735 * layout of interleaved samples?
740 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
742 return pitch_sa_rows
;
748 case ISL_DIM_LAYOUT_GEN4_3D
:
749 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
750 return isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
753 unreachable("bad isl_dim_layout");
758 * Calculate the pitch of each surface row, in bytes.
761 isl_calc_row_pitch(const struct isl_device
*dev
,
762 const struct isl_surf_init_info
*restrict info
,
763 const struct isl_tile_info
*tile_info
,
764 const struct isl_extent3d
*image_align_sa
,
765 const struct isl_extent2d
*phys_slice0_sa
)
767 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
769 uint32_t row_pitch
= info
->min_pitch
;
771 /* First, align the surface to a cache line boundary, as the PRM explains
774 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
775 * Formats >> Surface Padding Requirements >> Render Target and Media
778 * The data port accesses data (pixels) outside of the surface if they
779 * are contained in the same cache request as pixels that are within the
780 * surface. These pixels will not be returned by the requesting message,
781 * however if these pixels lie outside of defined pages in the GTT,
782 * a GTT error will result when the cache request is processed. In order
783 * to avoid these GTT errors, “padding” at the bottom of the surface is
784 * sometimes necessary.
786 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
787 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
789 * The sampling engine accesses texels outside of the surface if they
790 * are contained in the same cache line as texels that are within the
791 * surface. These texels will not participate in any calculation
792 * performed by the sampling engine and will not affect the result of
793 * any sampling engine operation, however if these texels lie outside of
794 * defined pages in the GTT, a GTT error will result when the cache line
795 * is accessed. In order to avoid these GTT errors, “padding” at the
796 * bottom and right side of a sampling engine surface is sometimes
799 * It is possible that a cache line will straddle a page boundary if the
800 * base address or pitch is not aligned. All pages included in the cache
801 * lines that are part of the surface must map to valid GTT entries to
802 * avoid errors. To determine the necessary padding on the bottom and
803 * right side of the surface, refer to the table in Alignment Unit Size
804 * section for the i and j parameters for the surface format in use. The
805 * surface must then be extended to the next multiple of the alignment
806 * unit size in each dimension, and all texels contained in this
807 * extended surface must have valid GTT entries.
809 * For example, suppose the surface size is 15 texels by 10 texels and
810 * the alignment parameters are i=4 and j=2. In this case, the extended
811 * surface would be 16 by 10. Note that these calculations are done in
812 * texels, and must be converted to bytes based on the surface format
813 * being used to determine whether additional pages need to be defined.
815 row_pitch
= MAX(row_pitch
,
816 fmtl
->bs
* isl_align_div_npot(phys_slice0_sa
->w
, fmtl
->bw
));
818 switch (tile_info
->tiling
) {
819 case ISL_TILING_LINEAR
:
820 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
821 * RENDER_SURFACE_STATE Surface Pitch (p349):
823 * - For linear render target surfaces and surfaces accessed with the
824 * typed data port messages, the pitch must be a multiple of the
825 * element size for non-YUV surface formats. Pitch must be
826 * a multiple of 2 * element size for YUV surface formats.
828 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
829 * ignore because isl doesn't do buffers.]
831 * - For other linear surfaces, the pitch can be any multiple of
834 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
835 if (isl_format_is_yuv(info
->format
)) {
836 row_pitch
= isl_align(row_pitch
, 2 * fmtl
->bs
);
838 row_pitch
= isl_align(row_pitch
, fmtl
->bs
);
843 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
844 * RENDER_SURFACE_STATE Surface Pitch (p349):
846 * - For tiled surfaces, the pitch must be a multiple of the tile
849 row_pitch
= isl_align(row_pitch
, tile_info
->width
);
857 * Calculate the surface's total height, including padding, in units of
861 isl_calc_total_height_el(const struct isl_device
*dev
,
862 const struct isl_surf_init_info
*restrict info
,
863 const struct isl_tile_info
*tile_info
,
864 uint32_t phys_array_len
,
866 uint32_t array_pitch_el_rows
)
868 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
870 uint32_t total_h_el
= phys_array_len
* array_pitch_el_rows
;
871 uint32_t pad_bytes
= 0;
873 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
874 * Formats >> Surface Padding Requirements >> Render Target and Media
877 * The data port accesses data (pixels) outside of the surface if they
878 * are contained in the same cache request as pixels that are within the
879 * surface. These pixels will not be returned by the requesting message,
880 * however if these pixels lie outside of defined pages in the GTT,
881 * a GTT error will result when the cache request is processed. In
882 * order to avoid these GTT errors, “padding” at the bottom of the
883 * surface is sometimes necessary.
885 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
886 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
888 * ... Lots of padding requirements, all listed separately below.
891 /* We can safely ignore the first padding requirement, quoted below,
892 * because isl doesn't do buffers.
894 * - [pre-BDW] For buffers, which have no inherent “height,” padding
895 * requirements are different. A buffer must be padded to the next
896 * multiple of 256 array elements, with an additional 16 bytes added
897 * beyond that to account for the L1 cache line.
901 * - For compressed textures [...], padding at the bottom of the surface
902 * is to an even compressed row.
904 if (isl_format_is_compressed(info
->format
))
905 total_h_el
= isl_align(total_h_el
, 2);
908 * - For cube surfaces, an additional two rows of padding are required
909 * at the bottom of the surface.
911 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
915 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
916 * additional padding is required. These surfaces require an extra row
917 * plus 16 bytes of padding at the bottom in addition to the general
918 * padding requirements.
920 if (isl_format_is_yuv(info
->format
) &&
921 (fmtl
->bs
== 96 || fmtl
->bs
== 48|| fmtl
->bs
== 24)) {
927 * - For linear surfaces, additional padding of 64 bytes is required at
928 * the bottom of the surface. This is in addition to the padding
931 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
934 /* The below text weakens, not strengthens, the padding requirements for
935 * linear surfaces. Therefore we can safely ignore it.
937 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
938 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
939 * padding requirement is to the next aligned 64-byte boundary beyond
940 * the end of the surface. The rest of the padding requirements
941 * documented above do not apply to these surfaces.
945 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
946 * height % 4 != 0, the surface must be padded with
947 * 4-(height % 4)*Surface Pitch # of bytes.
949 if (ISL_DEV_GEN(dev
) >= 9 &&
950 tile_info
->tiling
== ISL_TILING_LINEAR
&&
951 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
952 total_h_el
= isl_align(total_h_el
, 4);
956 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
957 * to 4 times the Surface Pitch # of bytes
959 if (ISL_DEV_GEN(dev
) >= 9 &&
960 tile_info
->tiling
== ISL_TILING_LINEAR
&&
961 info
->dim
== ISL_SURF_DIM_1D
) {
965 /* Be sloppy. Align any leftover padding to a row boundary. */
966 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
972 isl_surf_init_s(const struct isl_device
*dev
,
973 struct isl_surf
*surf
,
974 const struct isl_surf_init_info
*restrict info
)
976 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
978 const struct isl_extent4d logical_level0_px
= {
982 .a
= info
->array_len
,
985 enum isl_dim_layout dim_layout
=
986 isl_surf_choose_dim_layout(dev
, info
->dim
);
988 enum isl_tiling tiling
;
989 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
992 struct isl_tile_info tile_info
;
993 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bs
, &tile_info
))
996 enum isl_msaa_layout msaa_layout
;
997 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1000 struct isl_extent3d image_align_el
;
1001 isl_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
1004 struct isl_extent3d image_align_sa
=
1005 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1007 struct isl_extent4d phys_level0_sa
;
1008 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1011 enum isl_array_pitch_span array_pitch_span
=
1012 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1014 struct isl_extent2d phys_slice0_sa
;
1015 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1016 &image_align_sa
, &phys_level0_sa
,
1018 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1019 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1021 const uint32_t row_pitch
= isl_calc_row_pitch(dev
, info
, &tile_info
,
1025 const uint32_t array_pitch_sa_rows
=
1026 isl_calc_array_pitch_sa_rows(dev
, info
, dim_layout
, array_pitch_span
,
1027 &image_align_sa
, &phys_level0_sa
,
1029 assert(array_pitch_sa_rows
% fmtl
->bh
== 0);
1031 const uint32_t array_pitch_el_rows
= array_pitch_sa_rows
/ fmtl
->bh
;
1033 const uint32_t total_h_el
=
1034 isl_calc_total_height_el(dev
, info
, &tile_info
,
1035 phys_level0_sa
.array_len
, row_pitch
,
1036 array_pitch_el_rows
);
1038 const uint32_t total_h_sa
= total_h_el
* fmtl
->bh
;
1039 const uint32_t size
= row_pitch
* isl_align(total_h_sa
, tile_info
.height
);
1041 /* Alignment of surface base address, in bytes */
1042 uint32_t base_alignment
= info
->min_alignment
;
1043 base_alignment
= isl_align(base_alignment
, tile_info
.size
);
1045 *surf
= (struct isl_surf
) {
1047 .dim_layout
= dim_layout
,
1048 .msaa_layout
= msaa_layout
,
1050 .format
= info
->format
,
1052 .levels
= info
->levels
,
1053 .samples
= info
->samples
,
1055 .image_alignment_el
= image_align_el
,
1056 .logical_level0_px
= logical_level0_px
,
1057 .phys_level0_sa
= phys_level0_sa
,
1060 .alignment
= base_alignment
,
1061 .row_pitch
= row_pitch
,
1062 .array_pitch_el_rows
= array_pitch_el_rows
,
1063 .array_pitch_span
= array_pitch_span
,
1065 .usage
= info
->usage
,
1072 * A variant of isl_surf_get_image_offset_sa() specific to
1073 * ISL_DIM_LAYOUT_GEN4_2D.
1076 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1077 uint32_t level
, uint32_t layer
,
1078 uint32_t *x_offset_sa
,
1079 uint32_t *y_offset_sa
)
1081 assert(level
< surf
->levels
);
1082 assert(layer
< surf
->phys_level0_sa
.array_len
);
1083 assert(surf
->phys_level0_sa
.depth
== 1);
1085 const struct isl_extent3d image_align_sa
=
1086 isl_surf_get_image_alignment_sa(surf
);
1088 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1089 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1092 uint32_t y
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1094 for (uint32_t l
= 0; l
< level
; ++l
) {
1096 uint32_t W
= isl_minify(W0
, l
);
1098 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1099 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, &W
, NULL
);
1101 x
+= isl_align_npot(W
, image_align_sa
.w
);
1103 uint32_t H
= isl_minify(H0
, l
);
1105 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1106 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, NULL
, &H
);
1108 y
+= isl_align_npot(H
, image_align_sa
.h
);
1117 * A variant of isl_surf_get_image_offset_sa() specific to
1118 * ISL_DIM_LAYOUT_GEN4_3D.
1121 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1122 uint32_t level
, uint32_t logical_z_offset_px
,
1123 uint32_t *x_offset_sa
,
1124 uint32_t *y_offset_sa
)
1126 assert(level
< surf
->levels
);
1127 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1128 assert(surf
->phys_level0_sa
.array_len
== 1);
1130 const struct isl_extent3d image_align_sa
=
1131 isl_surf_get_image_alignment_sa(surf
);
1133 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1134 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1135 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1140 for (uint32_t l
= 0; l
< level
; ++l
) {
1141 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1142 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1143 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1145 y
+= level_h
* max_layers_vert
;
1148 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1149 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1150 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1152 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1153 const uint32_t max_layers_vert
= isl_align_div(level_d
, 1u << level
);
1155 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1156 y
+= level_h
* (logical_z_offset_px
/ max_layers_vert
);
1163 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1165 uint32_t logical_array_layer
,
1166 uint32_t logical_z_offset_px
,
1167 uint32_t *x_offset_sa
,
1168 uint32_t *y_offset_sa
)
1170 assert(level
< surf
->levels
);
1171 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1172 assert(logical_z_offset_px
1173 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1175 switch (surf
->dim_layout
) {
1176 case ISL_DIM_LAYOUT_GEN9_1D
:
1177 isl_finishme("%s:%s: gen9 1d surfaces", __FILE__
, __func__
);
1178 case ISL_DIM_LAYOUT_GEN4_2D
:
1179 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
,
1180 x_offset_sa
, y_offset_sa
);
1182 case ISL_DIM_LAYOUT_GEN4_3D
:
1183 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1184 x_offset_sa
, y_offset_sa
);