2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34 void PRINTFLIKE(3, 4) UNUSED
35 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
41 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
44 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
48 isl_device_init(struct isl_device
*dev
,
49 const struct brw_device_info
*info
,
50 bool has_bit6_swizzling
)
53 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
54 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
56 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
57 * device properties at buildtime. Verify that the macros with the device
58 * properties chosen during runtime.
60 assert(ISL_DEV_GEN(dev
) == dev
->info
->gen
);
61 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
) == dev
->use_separate_stencil
);
63 /* Did we break hiz or stencil? */
64 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
65 assert(info
->has_hiz_and_separate_stencil
);
66 if (info
->must_use_separate_stencil
)
67 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
71 * @param[out] info is written only on success
74 isl_tiling_get_info(const struct isl_device
*dev
,
75 enum isl_tiling tiling
,
76 uint32_t format_block_size
,
77 struct isl_tile_info
*tile_info
)
79 const uint32_t bs
= format_block_size
;
80 uint32_t width
, height
;
85 case ISL_TILING_LINEAR
:
101 /* XXX: Should W tile be same as Y? */
107 case ISL_TILING_Ys
: {
108 if (ISL_DEV_GEN(dev
) < 9)
111 if (!isl_is_pow2(bs
))
114 bool is_Ys
= tiling
== ISL_TILING_Ys
;
116 width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
117 height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
122 *tile_info
= (struct isl_tile_info
) {
126 .size
= width
* height
,
133 isl_tiling_get_extent(const struct isl_device
*dev
,
134 enum isl_tiling tiling
,
135 uint32_t format_block_size
,
136 struct isl_extent2d
*e
)
138 struct isl_tile_info tile_info
;
139 isl_tiling_get_info(dev
, tiling
, format_block_size
, &tile_info
);
140 *e
= isl_extent2d(tile_info
.width
, tile_info
.height
);
144 * @param[out] tiling is set only on success
147 isl_surf_choose_tiling(const struct isl_device
*dev
,
148 const struct isl_surf_init_info
*restrict info
,
149 enum isl_tiling
*tiling
)
151 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
153 if (ISL_DEV_GEN(dev
) >= 7) {
154 gen7_filter_tiling(dev
, info
, &tiling_flags
);
156 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
157 gen7_filter_tiling(dev
, info
, &tiling_flags
);
160 #define CHOOSE(__tiling) \
162 if (tiling_flags & (1u << (__tiling))) { \
163 *tiling = (__tiling); \
168 /* Of the tiling modes remaining, choose the one that offers the best
172 if (info
->dim
== ISL_SURF_DIM_1D
) {
173 /* Prefer linear for 1D surfaces because they do not benefit from
174 * tiling. To the contrary, tiling leads to wasted memory and poor
175 * memory locality due to the swizzling and alignment restrictions
176 * required in tiled surfaces.
178 CHOOSE(ISL_TILING_LINEAR
);
181 CHOOSE(ISL_TILING_Ys
);
182 CHOOSE(ISL_TILING_Yf
);
183 CHOOSE(ISL_TILING_Y0
);
184 CHOOSE(ISL_TILING_X
);
185 CHOOSE(ISL_TILING_W
);
186 CHOOSE(ISL_TILING_LINEAR
);
190 /* No tiling mode accomodates the inputs. */
195 isl_choose_msaa_layout(const struct isl_device
*dev
,
196 const struct isl_surf_init_info
*info
,
197 enum isl_tiling tiling
,
198 enum isl_msaa_layout
*msaa_layout
)
200 if (ISL_DEV_GEN(dev
) >= 8) {
201 return gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
202 } else if (ISL_DEV_GEN(dev
) >= 7) {
203 return gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
204 } else if (ISL_DEV_GEN(dev
) >= 6) {
205 return gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
207 return gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
212 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
213 uint32_t *width
, uint32_t *height
)
215 assert(isl_is_pow2(samples
));
217 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
220 * If the surface is multisampled and it is a depth or stencil surface
221 * or Multisampled Surface StorageFormat in SURFACE_STATE is
222 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
226 *width
= isl_align(*width
, 2) << ((ffs(samples
) - 0) / 2);
228 *height
= isl_align(*height
, 2) << ((ffs(samples
) - 1) / 2);
231 static enum isl_array_pitch_span
232 isl_choose_array_pitch_span(const struct isl_device
*dev
,
233 const struct isl_surf_init_info
*restrict info
,
234 enum isl_dim_layout dim_layout
,
235 const struct isl_extent4d
*phys_level0_sa
)
237 switch (dim_layout
) {
238 case ISL_DIM_LAYOUT_GEN9_1D
:
239 case ISL_DIM_LAYOUT_GEN4_2D
:
240 if (ISL_DEV_GEN(dev
) >= 8) {
241 /* QPitch becomes programmable in Broadwell. So choose the
242 * most compact QPitch possible in order to conserve memory.
244 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
245 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
247 * - Software must ensure that this field is set to a value
248 * sufficiently large such that the array slices in the surface
249 * do not overlap. Refer to the Memory Data Formats section for
250 * information on how surfaces are stored in memory.
252 * - This field specifies the distance in rows between array
253 * slices. It is used only in the following cases:
255 * - Surface Array is enabled OR
256 * - Number of Mulitsamples is not NUMSAMPLES_1 and
257 * Multisampled Surface Storage Format set to MSFMT_MSS OR
258 * - Surface Type is SURFTYPE_CUBE
260 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
261 } else if (ISL_DEV_GEN(dev
) >= 7) {
262 /* Note that Ivybridge introduces
263 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
264 * driver more control over the QPitch.
267 if (phys_level0_sa
->array_len
== 1) {
268 /* The hardware will never use the QPitch. So choose the most
269 * compact QPitch possible in order to conserve memory.
271 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
274 if (isl_surf_usage_is_depth_or_stencil(info
->usage
)) {
275 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
276 * Section 6.18.4.7: Surface Arrays (p112):
278 * If Surface Array Spacing is set to ARYSPC_FULL (note that
279 * the depth buffer and stencil buffer have an implied value of
282 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
285 if (info
->levels
== 1) {
286 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
289 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
292 return ISL_ARRAY_PITCH_SPAN_FULL
;
293 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
294 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
295 isl_surf_usage_is_stencil(info
->usage
)) {
296 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
297 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
299 * The separate stencil buffer does not support mip mapping, thus
300 * the storage for LODs other than LOD 0 is not needed.
302 assert(info
->levels
== 1);
303 assert(phys_level0_sa
->array_len
== 1);
304 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
306 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
307 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
308 isl_surf_usage_is_stencil(info
->usage
)) {
309 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
310 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
312 * The separate stencil buffer does not support mip mapping,
313 * thus the storage for LODs other than LOD 0 is not needed.
315 assert(info
->levels
== 1);
316 assert(phys_level0_sa
->array_len
== 1);
317 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
320 if (phys_level0_sa
->array_len
== 1) {
321 /* The hardware will never use the QPitch. So choose the most
322 * compact QPitch possible in order to conserve memory.
324 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
327 return ISL_ARRAY_PITCH_SPAN_FULL
;
330 case ISL_DIM_LAYOUT_GEN4_3D
:
331 /* The hardware will never use the QPitch. So choose the most
332 * compact QPitch possible in order to conserve memory.
334 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
337 unreachable("bad isl_dim_layout");
338 return ISL_ARRAY_PITCH_SPAN_FULL
;
342 isl_choose_image_alignment_el(const struct isl_device
*dev
,
343 const struct isl_surf_init_info
*restrict info
,
344 enum isl_tiling tiling
,
345 enum isl_msaa_layout msaa_layout
,
346 struct isl_extent3d
*image_align_el
)
348 if (ISL_DEV_GEN(dev
) >= 9) {
349 gen9_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
351 } else if (ISL_DEV_GEN(dev
) >= 8) {
352 gen8_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
354 } else if (ISL_DEV_GEN(dev
) >= 7) {
355 gen7_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
357 } else if (ISL_DEV_GEN(dev
) >= 6) {
358 gen6_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
361 gen4_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
366 static enum isl_dim_layout
367 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
368 enum isl_surf_dim logical_dim
)
370 if (ISL_DEV_GEN(dev
) >= 9) {
371 switch (logical_dim
) {
372 case ISL_SURF_DIM_1D
:
373 return ISL_DIM_LAYOUT_GEN9_1D
;
374 case ISL_SURF_DIM_2D
:
375 case ISL_SURF_DIM_3D
:
376 return ISL_DIM_LAYOUT_GEN4_2D
;
379 switch (logical_dim
) {
380 case ISL_SURF_DIM_1D
:
381 case ISL_SURF_DIM_2D
:
382 return ISL_DIM_LAYOUT_GEN4_2D
;
383 case ISL_SURF_DIM_3D
:
384 return ISL_DIM_LAYOUT_GEN4_3D
;
388 unreachable("bad isl_surf_dim");
389 return ISL_DIM_LAYOUT_GEN4_2D
;
393 * Calculate the physical extent of the surface's first level, in units of
394 * surface samples. The result is aligned to the format's compression block.
397 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
398 const struct isl_surf_init_info
*restrict info
,
399 enum isl_dim_layout dim_layout
,
400 enum isl_tiling tiling
,
401 enum isl_msaa_layout msaa_layout
,
402 struct isl_extent4d
*phys_level0_sa
)
404 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
406 if (isl_format_is_yuv(info
->format
))
407 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
410 case ISL_SURF_DIM_1D
:
411 assert(info
->height
== 1);
412 assert(info
->depth
== 1);
413 assert(info
->samples
== 1);
414 assert(!isl_format_is_compressed(info
->format
));
416 switch (dim_layout
) {
417 case ISL_DIM_LAYOUT_GEN4_3D
:
418 unreachable("bad isl_dim_layout");
420 case ISL_DIM_LAYOUT_GEN9_1D
:
421 case ISL_DIM_LAYOUT_GEN4_2D
:
422 *phys_level0_sa
= (struct isl_extent4d
) {
426 .a
= info
->array_len
,
432 case ISL_SURF_DIM_2D
:
433 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
435 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
436 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
438 switch (msaa_layout
) {
439 case ISL_MSAA_LAYOUT_NONE
:
440 assert(info
->depth
== 1);
441 assert(info
->samples
== 1);
443 *phys_level0_sa
= (struct isl_extent4d
) {
444 .w
= isl_align(info
->width
, fmtl
->bw
),
445 .h
= isl_align(info
->height
, fmtl
->bh
),
447 .a
= info
->array_len
,
451 case ISL_MSAA_LAYOUT_ARRAY
:
452 assert(info
->depth
== 1);
453 assert(info
->array_len
== 1);
454 assert(!isl_format_is_compressed(info
->format
));
456 *phys_level0_sa
= (struct isl_extent4d
) {
464 case ISL_MSAA_LAYOUT_INTERLEAVED
:
465 assert(info
->depth
== 1);
466 assert(info
->array_len
== 1);
467 assert(!isl_format_is_compressed(info
->format
));
469 *phys_level0_sa
= (struct isl_extent4d
) {
476 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
483 case ISL_SURF_DIM_3D
:
484 assert(info
->array_len
== 1);
485 assert(info
->samples
== 1);
488 isl_finishme("%s:%s: compression block with depth > 1",
492 switch (dim_layout
) {
493 case ISL_DIM_LAYOUT_GEN9_1D
:
494 unreachable("bad isl_dim_layout");
496 case ISL_DIM_LAYOUT_GEN4_2D
:
497 assert(ISL_DEV_GEN(dev
) >= 9);
499 *phys_level0_sa
= (struct isl_extent4d
) {
500 .w
= isl_align(info
->width
, fmtl
->bw
),
501 .h
= isl_align(info
->height
, fmtl
->bh
),
507 case ISL_DIM_LAYOUT_GEN4_3D
:
508 assert(ISL_DEV_GEN(dev
) < 9);
509 *phys_level0_sa
= (struct isl_extent4d
) {
510 .w
= isl_align(info
->width
, fmtl
->bw
),
511 .h
= isl_align(info
->height
, fmtl
->bh
),
522 * A variant of isl_calc_phys_slice0_extent_sa() specific to
523 * ISL_DIM_LAYOUT_GEN4_2D.
526 isl_calc_phys_slice0_extent_sa_gen4_2d(
527 const struct isl_device
*dev
,
528 const struct isl_surf_init_info
*restrict info
,
529 enum isl_msaa_layout msaa_layout
,
530 const struct isl_extent3d
*image_align_sa
,
531 const struct isl_extent4d
*phys_level0_sa
,
532 struct isl_extent2d
*phys_slice0_sa
)
534 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
536 assert(phys_level0_sa
->depth
== 1);
538 if (info
->levels
== 1 && msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
) {
539 /* Do not pad the surface to the image alignment. Instead, pad it only
540 * to the pixel format's block alignment.
542 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
543 * cycles on the below mipmap layout caluclations. Reducing the
544 * alignment here is safe because we later align the row pitch and array
545 * pitch to the tile boundary. It is safe even for
546 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
547 * to accomodate the interleaved samples.
549 * For linear surfaces, reducing the alignment here permits us to later
550 * choose an arbitrary, non-aligned row pitch. If the surface backs
551 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
552 * VkBufferImageCopy::bufferRowLength.
554 *phys_slice0_sa
= (struct isl_extent2d
) {
555 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
556 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
561 uint32_t slice_top_w
= 0;
562 uint32_t slice_bottom_w
= 0;
563 uint32_t slice_left_h
= 0;
564 uint32_t slice_right_h
= 0;
566 uint32_t W0
= phys_level0_sa
->w
;
567 uint32_t H0
= phys_level0_sa
->h
;
569 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
570 uint32_t W
= isl_minify(W0
, l
);
571 uint32_t H
= isl_minify(H0
, l
);
573 if (msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
574 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
577 * If the surface is multisampled and it is a depth or stencil
578 * surface or Multisampled Surface StorageFormat in
579 * SURFACE_STATE is MSFMT_DEPTH_STENCIL, W_L and H_L must be
580 * adjusted as follows before proceeding: [...]
582 isl_msaa_interleaved_scale_px_to_sa(info
->samples
, &W
, &H
);
585 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
586 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
603 *phys_slice0_sa
= (struct isl_extent2d
) {
604 .w
= MAX(slice_top_w
, slice_bottom_w
),
605 .h
= MAX(slice_left_h
, slice_right_h
),
610 * A variant of isl_calc_phys_slice0_extent_sa() specific to
611 * ISL_DIM_LAYOUT_GEN4_3D.
614 isl_calc_phys_slice0_extent_sa_gen4_3d(
615 const struct isl_device
*dev
,
616 const struct isl_surf_init_info
*restrict info
,
617 const struct isl_extent3d
*image_align_sa
,
618 const struct isl_extent4d
*phys_level0_sa
,
619 struct isl_extent2d
*phys_slice0_sa
)
621 assert(info
->samples
== 1);
622 assert(phys_level0_sa
->array_len
== 1);
624 uint32_t slice_w
= 0;
625 uint32_t slice_h
= 0;
627 uint32_t W0
= phys_level0_sa
->w
;
628 uint32_t H0
= phys_level0_sa
->h
;
629 uint32_t D0
= phys_level0_sa
->d
;
631 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
632 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
633 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
634 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
636 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
637 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
639 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
640 slice_h
+= level_h
* max_layers_vert
;
643 *phys_slice0_sa
= (struct isl_extent2d
) {
650 * A variant of isl_calc_phys_slice0_extent_sa() specific to
651 * ISL_DIM_LAYOUT_GEN9_1D.
654 isl_calc_phys_slice0_extent_sa_gen9_1d(
655 const struct isl_device
*dev
,
656 const struct isl_surf_init_info
*restrict info
,
657 const struct isl_extent3d
*image_align_sa
,
658 const struct isl_extent4d
*phys_level0_sa
,
659 struct isl_extent2d
*phys_slice0_sa
)
661 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
663 assert(phys_level0_sa
->height
== 1);
664 assert(phys_level0_sa
->depth
== 1);
665 assert(info
->samples
== 1);
666 assert(image_align_sa
->w
>= fmtl
->bw
);
668 uint32_t slice_w
= 0;
669 const uint32_t W0
= phys_level0_sa
->w
;
671 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
672 uint32_t W
= isl_minify(W0
, l
);
673 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
678 *phys_slice0_sa
= isl_extent2d(slice_w
, 1);
682 * Calculate the physical extent of the surface's first array slice, in units
683 * of surface samples. If the surface is multi-leveled, then the result will
684 * be aligned to \a image_align_sa.
687 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
688 const struct isl_surf_init_info
*restrict info
,
689 enum isl_dim_layout dim_layout
,
690 enum isl_msaa_layout msaa_layout
,
691 const struct isl_extent3d
*image_align_sa
,
692 const struct isl_extent4d
*phys_level0_sa
,
693 struct isl_extent2d
*phys_slice0_sa
)
695 switch (dim_layout
) {
696 case ISL_DIM_LAYOUT_GEN9_1D
:
697 isl_calc_phys_slice0_extent_sa_gen9_1d(dev
, info
,
698 image_align_sa
, phys_level0_sa
,
701 case ISL_DIM_LAYOUT_GEN4_2D
:
702 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
703 image_align_sa
, phys_level0_sa
,
706 case ISL_DIM_LAYOUT_GEN4_3D
:
707 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
708 phys_level0_sa
, phys_slice0_sa
);
714 * Calculate the pitch between physical array slices, in units of rows of
718 isl_calc_array_pitch_el_rows(const struct isl_device
*dev
,
719 const struct isl_surf_init_info
*restrict info
,
720 const struct isl_tile_info
*tile_info
,
721 enum isl_dim_layout dim_layout
,
722 enum isl_array_pitch_span array_pitch_span
,
723 const struct isl_extent3d
*image_align_sa
,
724 const struct isl_extent4d
*phys_level0_sa
,
725 const struct isl_extent2d
*phys_slice0_sa
)
727 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
728 uint32_t pitch_sa_rows
= 0;
730 switch (dim_layout
) {
731 case ISL_DIM_LAYOUT_GEN9_1D
:
732 /* Each row is an array slice */
735 case ISL_DIM_LAYOUT_GEN4_2D
:
736 switch (array_pitch_span
) {
737 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
738 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
740 case ISL_ARRAY_PITCH_SPAN_FULL
: {
741 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
742 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
743 * Surfaces >> Surface Arrays.
745 uint32_t H0_sa
= phys_level0_sa
->h
;
746 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
748 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
749 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
752 if (ISL_DEV_GEN(dev
) >= 7) {
753 /* The QPitch equation changed slightly in Ivybridge. */
759 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
761 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
762 (info
->height
% 4 == 1)) {
763 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
764 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
766 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
767 * the value calculated in the equation above , for every
768 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
770 * XXX(chadv): Is the errata natural corollary of the physical
771 * layout of interleaved samples?
776 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
781 case ISL_DIM_LAYOUT_GEN4_3D
:
782 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
783 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
786 unreachable("bad isl_dim_layout");
790 assert(pitch_sa_rows
% fmtl
->bh
== 0);
791 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
793 if (ISL_DEV_GEN(dev
) >= 9 &&
794 info
->dim
== ISL_SURF_DIM_3D
&&
795 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
796 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
798 * Tile Mode != Linear: This field must be set to an integer multiple
801 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->height
);
804 return pitch_el_rows
;
808 * Calculate the pitch of each surface row, in bytes.
811 isl_calc_row_pitch(const struct isl_device
*dev
,
812 const struct isl_surf_init_info
*restrict info
,
813 const struct isl_tile_info
*tile_info
,
814 const struct isl_extent3d
*image_align_sa
,
815 const struct isl_extent2d
*phys_slice0_sa
)
817 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
819 uint32_t row_pitch
= info
->min_pitch
;
821 /* First, align the surface to a cache line boundary, as the PRM explains
824 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
825 * Formats >> Surface Padding Requirements >> Render Target and Media
828 * The data port accesses data (pixels) outside of the surface if they
829 * are contained in the same cache request as pixels that are within the
830 * surface. These pixels will not be returned by the requesting message,
831 * however if these pixels lie outside of defined pages in the GTT,
832 * a GTT error will result when the cache request is processed. In order
833 * to avoid these GTT errors, “padding” at the bottom of the surface is
834 * sometimes necessary.
836 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
837 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
839 * The sampling engine accesses texels outside of the surface if they
840 * are contained in the same cache line as texels that are within the
841 * surface. These texels will not participate in any calculation
842 * performed by the sampling engine and will not affect the result of
843 * any sampling engine operation, however if these texels lie outside of
844 * defined pages in the GTT, a GTT error will result when the cache line
845 * is accessed. In order to avoid these GTT errors, “padding” at the
846 * bottom and right side of a sampling engine surface is sometimes
849 * It is possible that a cache line will straddle a page boundary if the
850 * base address or pitch is not aligned. All pages included in the cache
851 * lines that are part of the surface must map to valid GTT entries to
852 * avoid errors. To determine the necessary padding on the bottom and
853 * right side of the surface, refer to the table in Alignment Unit Size
854 * section for the i and j parameters for the surface format in use. The
855 * surface must then be extended to the next multiple of the alignment
856 * unit size in each dimension, and all texels contained in this
857 * extended surface must have valid GTT entries.
859 * For example, suppose the surface size is 15 texels by 10 texels and
860 * the alignment parameters are i=4 and j=2. In this case, the extended
861 * surface would be 16 by 10. Note that these calculations are done in
862 * texels, and must be converted to bytes based on the surface format
863 * being used to determine whether additional pages need to be defined.
865 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
866 row_pitch
= MAX(row_pitch
, fmtl
->bs
* phys_slice0_sa
->w
);
868 switch (tile_info
->tiling
) {
869 case ISL_TILING_LINEAR
:
870 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
871 * RENDER_SURFACE_STATE Surface Pitch (p349):
873 * - For linear render target surfaces and surfaces accessed with the
874 * typed data port messages, the pitch must be a multiple of the
875 * element size for non-YUV surface formats. Pitch must be
876 * a multiple of 2 * element size for YUV surface formats.
878 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
879 * ignore because isl doesn't do buffers.]
881 * - For other linear surfaces, the pitch can be any multiple of
884 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
885 if (isl_format_is_yuv(info
->format
)) {
886 row_pitch
= isl_align_npot(row_pitch
, 2 * fmtl
->bs
);
888 row_pitch
= isl_align_npot(row_pitch
, fmtl
->bs
);
893 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
894 * RENDER_SURFACE_STATE Surface Pitch (p349):
896 * - For tiled surfaces, the pitch must be a multiple of the tile
899 row_pitch
= isl_align(row_pitch
, tile_info
->width
);
907 * Calculate the surface's total height, including padding, in units of
911 isl_calc_total_height_el(const struct isl_device
*dev
,
912 const struct isl_surf_init_info
*restrict info
,
913 const struct isl_tile_info
*tile_info
,
914 uint32_t phys_array_len
,
916 uint32_t array_pitch_el_rows
)
918 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
920 uint32_t total_h_el
= phys_array_len
* array_pitch_el_rows
;
921 uint32_t pad_bytes
= 0;
923 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
924 * Formats >> Surface Padding Requirements >> Render Target and Media
927 * The data port accesses data (pixels) outside of the surface if they
928 * are contained in the same cache request as pixels that are within the
929 * surface. These pixels will not be returned by the requesting message,
930 * however if these pixels lie outside of defined pages in the GTT,
931 * a GTT error will result when the cache request is processed. In
932 * order to avoid these GTT errors, “padding” at the bottom of the
933 * surface is sometimes necessary.
935 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
936 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
938 * ... Lots of padding requirements, all listed separately below.
941 /* We can safely ignore the first padding requirement, quoted below,
942 * because isl doesn't do buffers.
944 * - [pre-BDW] For buffers, which have no inherent “height,” padding
945 * requirements are different. A buffer must be padded to the next
946 * multiple of 256 array elements, with an additional 16 bytes added
947 * beyond that to account for the L1 cache line.
951 * - For compressed textures [...], padding at the bottom of the surface
952 * is to an even compressed row.
954 if (isl_format_is_compressed(info
->format
))
955 total_h_el
= isl_align(total_h_el
, 2);
958 * - For cube surfaces, an additional two rows of padding are required
959 * at the bottom of the surface.
961 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
965 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
966 * additional padding is required. These surfaces require an extra row
967 * plus 16 bytes of padding at the bottom in addition to the general
968 * padding requirements.
970 if (isl_format_is_yuv(info
->format
) &&
971 (fmtl
->bs
== 96 || fmtl
->bs
== 48|| fmtl
->bs
== 24)) {
977 * - For linear surfaces, additional padding of 64 bytes is required at
978 * the bottom of the surface. This is in addition to the padding
981 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
984 /* The below text weakens, not strengthens, the padding requirements for
985 * linear surfaces. Therefore we can safely ignore it.
987 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
988 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
989 * padding requirement is to the next aligned 64-byte boundary beyond
990 * the end of the surface. The rest of the padding requirements
991 * documented above do not apply to these surfaces.
995 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
996 * height % 4 != 0, the surface must be padded with
997 * 4-(height % 4)*Surface Pitch # of bytes.
999 if (ISL_DEV_GEN(dev
) >= 9 &&
1000 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1001 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1002 total_h_el
= isl_align(total_h_el
, 4);
1006 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1007 * to 4 times the Surface Pitch # of bytes
1009 if (ISL_DEV_GEN(dev
) >= 9 &&
1010 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1011 info
->dim
== ISL_SURF_DIM_1D
) {
1015 /* Be sloppy. Align any leftover padding to a row boundary. */
1016 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1022 isl_surf_init_s(const struct isl_device
*dev
,
1023 struct isl_surf
*surf
,
1024 const struct isl_surf_init_info
*restrict info
)
1026 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1028 const struct isl_extent4d logical_level0_px
= {
1032 .a
= info
->array_len
,
1035 enum isl_dim_layout dim_layout
=
1036 isl_surf_choose_dim_layout(dev
, info
->dim
);
1038 enum isl_tiling tiling
;
1039 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1042 struct isl_tile_info tile_info
;
1043 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bs
, &tile_info
))
1046 enum isl_msaa_layout msaa_layout
;
1047 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1050 struct isl_extent3d image_align_el
;
1051 isl_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
1054 struct isl_extent3d image_align_sa
=
1055 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1057 struct isl_extent4d phys_level0_sa
;
1058 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1060 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1061 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1063 enum isl_array_pitch_span array_pitch_span
=
1064 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1066 struct isl_extent2d phys_slice0_sa
;
1067 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1068 &image_align_sa
, &phys_level0_sa
,
1070 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1071 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1073 const uint32_t row_pitch
= isl_calc_row_pitch(dev
, info
, &tile_info
,
1077 const uint32_t array_pitch_el_rows
=
1078 isl_calc_array_pitch_el_rows(dev
, info
, &tile_info
, dim_layout
,
1079 array_pitch_span
, &image_align_sa
,
1080 &phys_level0_sa
, &phys_slice0_sa
);
1082 const uint32_t total_h_el
=
1083 isl_calc_total_height_el(dev
, info
, &tile_info
,
1084 phys_level0_sa
.array_len
, row_pitch
,
1085 array_pitch_el_rows
);
1087 const uint32_t total_h_sa
= total_h_el
* fmtl
->bh
;
1088 const uint32_t size
= row_pitch
* isl_align(total_h_sa
, tile_info
.height
);
1090 /* Alignment of surface base address, in bytes */
1091 uint32_t base_alignment
= MAX(1, info
->min_alignment
);
1092 assert(isl_is_pow2(base_alignment
) && isl_is_pow2(tile_info
.size
));
1093 base_alignment
= MAX(base_alignment
, tile_info
.size
);
1095 *surf
= (struct isl_surf
) {
1097 .dim_layout
= dim_layout
,
1098 .msaa_layout
= msaa_layout
,
1100 .format
= info
->format
,
1102 .levels
= info
->levels
,
1103 .samples
= info
->samples
,
1105 .image_alignment_el
= image_align_el
,
1106 .logical_level0_px
= logical_level0_px
,
1107 .phys_level0_sa
= phys_level0_sa
,
1110 .alignment
= base_alignment
,
1111 .row_pitch
= row_pitch
,
1112 .array_pitch_el_rows
= array_pitch_el_rows
,
1113 .array_pitch_span
= array_pitch_span
,
1115 .usage
= info
->usage
,
1122 * A variant of isl_surf_get_image_offset_sa() specific to
1123 * ISL_DIM_LAYOUT_GEN4_2D.
1126 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1127 uint32_t level
, uint32_t layer
,
1128 uint32_t *x_offset_sa
,
1129 uint32_t *y_offset_sa
)
1131 assert(level
< surf
->levels
);
1132 assert(layer
< surf
->phys_level0_sa
.array_len
);
1133 assert(surf
->phys_level0_sa
.depth
== 1);
1135 const struct isl_extent3d image_align_sa
=
1136 isl_surf_get_image_alignment_sa(surf
);
1138 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1139 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1142 uint32_t y
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1144 for (uint32_t l
= 0; l
< level
; ++l
) {
1146 uint32_t W
= isl_minify(W0
, l
);
1148 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1149 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, &W
, NULL
);
1151 x
+= isl_align_npot(W
, image_align_sa
.w
);
1153 uint32_t H
= isl_minify(H0
, l
);
1155 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1156 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, NULL
, &H
);
1158 y
+= isl_align_npot(H
, image_align_sa
.h
);
1167 * A variant of isl_surf_get_image_offset_sa() specific to
1168 * ISL_DIM_LAYOUT_GEN4_3D.
1171 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1172 uint32_t level
, uint32_t logical_z_offset_px
,
1173 uint32_t *x_offset_sa
,
1174 uint32_t *y_offset_sa
)
1176 assert(level
< surf
->levels
);
1177 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1178 assert(surf
->phys_level0_sa
.array_len
== 1);
1180 const struct isl_extent3d image_align_sa
=
1181 isl_surf_get_image_alignment_sa(surf
);
1183 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1184 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1185 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1190 for (uint32_t l
= 0; l
< level
; ++l
) {
1191 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1192 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1193 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1195 y
+= level_h
* max_layers_vert
;
1198 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1199 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1200 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1202 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1204 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1205 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1212 * A variant of isl_surf_get_image_offset_sa() specific to
1213 * ISL_DIM_LAYOUT_GEN9_1D.
1216 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
1217 uint32_t level
, uint32_t layer
,
1218 uint32_t *x_offset_sa
,
1219 uint32_t *y_offset_sa
)
1221 assert(level
< surf
->levels
);
1222 assert(layer
< surf
->phys_level0_sa
.array_len
);
1223 assert(surf
->phys_level0_sa
.height
== 1);
1224 assert(surf
->phys_level0_sa
.depth
== 1);
1225 assert(surf
->samples
== 1);
1227 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1228 const struct isl_extent3d image_align_sa
=
1229 isl_surf_get_image_alignment_sa(surf
);
1231 uint32_t x
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1233 for (uint32_t l
= 0; l
< level
; ++l
) {
1234 uint32_t W
= isl_minify(W0
, l
);
1235 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
1245 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1247 uint32_t logical_array_layer
,
1248 uint32_t logical_z_offset_px
,
1249 uint32_t *x_offset_sa
,
1250 uint32_t *y_offset_sa
)
1252 assert(level
< surf
->levels
);
1253 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1254 assert(logical_z_offset_px
1255 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1257 switch (surf
->dim_layout
) {
1258 case ISL_DIM_LAYOUT_GEN9_1D
:
1259 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
1260 x_offset_sa
, y_offset_sa
);
1262 case ISL_DIM_LAYOUT_GEN4_2D
:
1263 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
,
1264 x_offset_sa
, y_offset_sa
);
1266 case ISL_DIM_LAYOUT_GEN4_3D
:
1267 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1268 x_offset_sa
, y_offset_sa
);