2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34 void PRINTFLIKE(3, 4) UNUSED
35 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
41 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
44 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
48 isl_device_init(struct isl_device
*dev
,
49 const struct brw_device_info
*info
)
52 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
54 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
55 * device properties at buildtime. Verify that the macros with the device
56 * properties chosen during runtime.
58 assert(ISL_DEV_GEN(dev
) == dev
->info
->gen
);
59 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
) == dev
->use_separate_stencil
);
61 /* Did we break hiz or stencil? */
62 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
63 assert(info
->has_hiz_and_separate_stencil
);
64 if (info
->must_use_separate_stencil
)
65 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
69 * @param[out] info is written only on success
72 isl_tiling_get_info(const struct isl_device
*dev
,
73 enum isl_tiling tiling
,
74 uint32_t format_block_size
,
75 struct isl_tile_info
*tile_info
)
77 const uint32_t bs
= format_block_size
;
78 uint32_t width
, height
;
83 case ISL_TILING_LINEAR
:
99 /* XXX: Should W tile be same as Y? */
105 case ISL_TILING_Ys
: {
106 if (ISL_DEV_GEN(dev
) < 9)
109 if (!isl_is_pow2(bs
))
112 bool is_Ys
= tiling
== ISL_TILING_Ys
;
114 width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
115 height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
120 *tile_info
= (struct isl_tile_info
) {
124 .size
= width
* height
,
131 isl_tiling_get_extent(const struct isl_device
*dev
,
132 enum isl_tiling tiling
,
133 uint32_t format_block_size
,
134 struct isl_extent2d
*e
)
136 struct isl_tile_info tile_info
;
137 isl_tiling_get_info(dev
, tiling
, format_block_size
, &tile_info
);
138 *e
= isl_extent2d(tile_info
.width
, tile_info
.height
);
142 * @param[out] tiling is set only on success
145 isl_surf_choose_tiling(const struct isl_device
*dev
,
146 const struct isl_surf_init_info
*restrict info
,
147 enum isl_tiling
*tiling
)
149 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
151 if (ISL_DEV_GEN(dev
) >= 7) {
152 gen7_filter_tiling(dev
, info
, &tiling_flags
);
154 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
155 gen7_filter_tiling(dev
, info
, &tiling_flags
);
158 #define CHOOSE(__tiling) \
160 if (tiling_flags & (1u << (__tiling))) { \
161 *tiling = (__tiling); \
166 /* Of the tiling modes remaining, choose the one that offers the best
170 if (info
->dim
== ISL_SURF_DIM_1D
) {
171 /* Prefer linear for 1D surfaces because they do not benefit from
172 * tiling. To the contrary, tiling leads to wasted memory and poor
173 * memory locality due to the swizzling and alignment restrictions
174 * required in tiled surfaces.
176 CHOOSE(ISL_TILING_LINEAR
);
179 CHOOSE(ISL_TILING_Ys
);
180 CHOOSE(ISL_TILING_Yf
);
181 CHOOSE(ISL_TILING_Y0
);
182 CHOOSE(ISL_TILING_X
);
183 CHOOSE(ISL_TILING_W
);
184 CHOOSE(ISL_TILING_LINEAR
);
188 /* No tiling mode accomodates the inputs. */
193 isl_choose_msaa_layout(const struct isl_device
*dev
,
194 const struct isl_surf_init_info
*info
,
195 enum isl_tiling tiling
,
196 enum isl_msaa_layout
*msaa_layout
)
198 if (ISL_DEV_GEN(dev
) >= 8) {
199 return gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
200 } else if (ISL_DEV_GEN(dev
) >= 7) {
201 return gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
202 } else if (ISL_DEV_GEN(dev
) >= 6) {
203 return gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
205 return gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
210 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
211 uint32_t *width
, uint32_t *height
)
213 assert(isl_is_pow2(samples
));
215 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
218 * If the surface is multisampled and it is a depth or stencil surface
219 * or Multisampled Surface StorageFormat in SURFACE_STATE is
220 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
224 *width
= isl_align(*width
, 2) << ((ffs(samples
) - 0) / 2);
226 *height
= isl_align(*height
, 2) << ((ffs(samples
) - 1) / 2);
229 static enum isl_array_pitch_span
230 isl_choose_array_pitch_span(const struct isl_device
*dev
,
231 const struct isl_surf_init_info
*restrict info
,
232 enum isl_dim_layout dim_layout
,
233 const struct isl_extent4d
*phys_level0_sa
)
235 switch (dim_layout
) {
236 case ISL_DIM_LAYOUT_GEN9_1D
:
237 if (ISL_DEV_GEN(dev
) >= 9)
238 isl_finishme("%s:%s: [SKL+] 1d surface layout", __FILE__
, __func__
);
241 case ISL_DIM_LAYOUT_GEN4_2D
:
242 if (ISL_DEV_GEN(dev
) >= 8) {
243 /* QPitch becomes programmable in Broadwell. So choose the
244 * most compact QPitch possible in order to conserve memory.
246 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
247 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
249 * - Software must ensure that this field is set to a value
250 * sufficiently large such that the array slices in the surface
251 * do not overlap. Refer to the Memory Data Formats section for
252 * information on how surfaces are stored in memory.
254 * - This field specifies the distance in rows between array
255 * slices. It is used only in the following cases:
257 * - Surface Array is enabled OR
258 * - Number of Mulitsamples is not NUMSAMPLES_1 and
259 * Multisampled Surface Storage Format set to MSFMT_MSS OR
260 * - Surface Type is SURFTYPE_CUBE
262 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
263 } else if (ISL_DEV_GEN(dev
) >= 7) {
264 /* Note that Ivybridge introduces
265 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
266 * driver more control over the QPitch.
269 if (phys_level0_sa
->array_len
== 1) {
270 /* The hardware will never use the QPitch. So choose the most
271 * compact QPitch possible in order to conserve memory.
273 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
276 if (isl_surf_usage_is_depth_or_stencil(info
->usage
)) {
277 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
278 * Section 6.18.4.7: Surface Arrays (p112):
280 * If Surface Array Spacing is set to ARYSPC_FULL (note that
281 * the depth buffer and stencil buffer have an implied value of
284 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
287 if (info
->levels
== 1) {
288 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
291 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
294 return ISL_ARRAY_PITCH_SPAN_FULL
;
295 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
296 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
297 isl_surf_usage_is_stencil(info
->usage
)) {
298 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
299 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
301 * The separate stencil buffer does not support mip mapping, thus
302 * the storage for LODs other than LOD 0 is not needed.
304 assert(info
->levels
== 1);
305 assert(phys_level0_sa
->array_len
== 1);
306 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
308 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
309 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
310 isl_surf_usage_is_stencil(info
->usage
)) {
311 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
312 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
314 * The separate stencil buffer does not support mip mapping,
315 * thus the storage for LODs other than LOD 0 is not needed.
317 assert(info
->levels
== 1);
318 assert(phys_level0_sa
->array_len
== 1);
319 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
322 if (phys_level0_sa
->array_len
== 1) {
323 /* The hardware will never use the QPitch. So choose the most
324 * compact QPitch possible in order to conserve memory.
326 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
329 return ISL_ARRAY_PITCH_SPAN_FULL
;
332 case ISL_DIM_LAYOUT_GEN4_3D
:
333 /* The hardware will never use the QPitch. So choose the most
334 * compact QPitch possible in order to conserve memory.
336 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
339 unreachable("bad isl_dim_layout");
340 return ISL_ARRAY_PITCH_SPAN_FULL
;
344 isl_choose_image_alignment_el(const struct isl_device
*dev
,
345 const struct isl_surf_init_info
*restrict info
,
346 enum isl_tiling tiling
,
347 enum isl_msaa_layout msaa_layout
,
348 struct isl_extent3d
*image_align_el
)
350 if (ISL_DEV_GEN(dev
) >= 9) {
351 gen9_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
353 } else if (ISL_DEV_GEN(dev
) >= 8) {
354 gen8_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
356 } else if (ISL_DEV_GEN(dev
) >= 7) {
357 gen7_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
359 } else if (ISL_DEV_GEN(dev
) >= 6) {
360 gen6_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
363 gen4_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
368 static enum isl_dim_layout
369 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
370 enum isl_surf_dim logical_dim
)
372 if (ISL_DEV_GEN(dev
) >= 9) {
373 switch (logical_dim
) {
374 case ISL_SURF_DIM_1D
:
375 return ISL_DIM_LAYOUT_GEN9_1D
;
376 case ISL_SURF_DIM_2D
:
377 case ISL_SURF_DIM_3D
:
378 return ISL_DIM_LAYOUT_GEN4_2D
;
381 switch (logical_dim
) {
382 case ISL_SURF_DIM_1D
:
383 case ISL_SURF_DIM_2D
:
384 return ISL_DIM_LAYOUT_GEN4_2D
;
385 case ISL_SURF_DIM_3D
:
386 return ISL_DIM_LAYOUT_GEN4_3D
;
390 unreachable("bad isl_surf_dim");
391 return ISL_DIM_LAYOUT_GEN4_2D
;
395 * Calculate the physical extent of the surface's first level, in units of
396 * surface samples. The result is aligned to the format's compression block.
399 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
400 const struct isl_surf_init_info
*restrict info
,
401 enum isl_dim_layout dim_layout
,
402 enum isl_tiling tiling
,
403 enum isl_msaa_layout msaa_layout
,
404 struct isl_extent4d
*phys_level0_sa
)
406 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
408 if (isl_format_is_yuv(info
->format
))
409 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
412 case ISL_SURF_DIM_1D
:
413 assert(info
->height
== 1);
414 assert(info
->depth
== 1);
415 assert(info
->samples
== 1);
416 assert(!isl_format_is_compressed(info
->format
));
418 switch (dim_layout
) {
419 case ISL_DIM_LAYOUT_GEN4_3D
:
420 unreachable("bad isl_dim_layout");
422 case ISL_DIM_LAYOUT_GEN9_1D
:
423 if (ISL_DEV_GEN(dev
) >= 9)
424 isl_finishme("%s:%s: [SKL+] 1d surface layout", __FILE__
, __func__
);
427 case ISL_DIM_LAYOUT_GEN4_2D
:
428 *phys_level0_sa
= (struct isl_extent4d
) {
432 .a
= info
->array_len
,
438 case ISL_SURF_DIM_2D
:
439 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
441 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
442 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
444 switch (msaa_layout
) {
445 case ISL_MSAA_LAYOUT_NONE
:
446 assert(info
->depth
== 1);
447 assert(info
->samples
== 1);
449 *phys_level0_sa
= (struct isl_extent4d
) {
450 .w
= isl_align(info
->width
, fmtl
->bw
),
451 .h
= isl_align(info
->height
, fmtl
->bh
),
453 .a
= info
->array_len
,
457 case ISL_MSAA_LAYOUT_ARRAY
:
458 assert(info
->depth
== 1);
459 assert(info
->array_len
== 1);
460 assert(!isl_format_is_compressed(info
->format
));
462 *phys_level0_sa
= (struct isl_extent4d
) {
470 case ISL_MSAA_LAYOUT_INTERLEAVED
:
471 assert(info
->depth
== 1);
472 assert(info
->array_len
== 1);
473 assert(!isl_format_is_compressed(info
->format
));
475 *phys_level0_sa
= (struct isl_extent4d
) {
482 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
489 case ISL_SURF_DIM_3D
:
490 assert(info
->array_len
== 1);
491 assert(info
->samples
== 1);
494 isl_finishme("%s:%s: compression block with depth > 1",
498 switch (dim_layout
) {
499 case ISL_DIM_LAYOUT_GEN9_1D
:
500 unreachable("bad isl_dim_layout");
502 case ISL_DIM_LAYOUT_GEN4_2D
:
503 assert(ISL_DEV_GEN(dev
) >= 9);
505 *phys_level0_sa
= (struct isl_extent4d
) {
506 .w
= isl_align(info
->width
, fmtl
->bw
),
507 .h
= isl_align(info
->height
, fmtl
->bh
),
513 case ISL_DIM_LAYOUT_GEN4_3D
:
514 assert(ISL_DEV_GEN(dev
) < 9);
515 *phys_level0_sa
= (struct isl_extent4d
) {
516 .w
= isl_align(info
->width
, fmtl
->bw
),
517 .h
= isl_align(info
->height
, fmtl
->bh
),
528 * A variant of isl_calc_phys_slice0_extent_sa() specific to
529 * ISL_DIM_LAYOUT_GEN4_2D.
532 isl_calc_phys_slice0_extent_sa_gen4_2d(
533 const struct isl_device
*dev
,
534 const struct isl_surf_init_info
*restrict info
,
535 enum isl_msaa_layout msaa_layout
,
536 const struct isl_extent3d
*image_align_sa
,
537 const struct isl_extent4d
*phys_level0_sa
,
538 struct isl_extent2d
*phys_slice0_sa
)
540 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
542 assert(phys_level0_sa
->depth
== 1);
544 if (info
->levels
== 1 && msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
) {
545 /* Do not pad the surface to the image alignment. Instead, pad it only
546 * to the pixel format's block alignment.
548 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
549 * cycles on the below mipmap layout caluclations. Reducing the
550 * alignment here is safe because we later align the row pitch and array
551 * pitch to the tile boundary. It is safe even for
552 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
553 * to accomodate the interleaved samples.
555 * For linear surfaces, reducing the alignment here permits us to later
556 * choose an arbitrary, non-aligned row pitch. If the surface backs
557 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
558 * VkBufferImageCopy::bufferRowLength.
560 *phys_slice0_sa
= (struct isl_extent2d
) {
561 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
562 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
567 uint32_t slice_top_w
= 0;
568 uint32_t slice_bottom_w
= 0;
569 uint32_t slice_left_h
= 0;
570 uint32_t slice_right_h
= 0;
572 uint32_t W0
= phys_level0_sa
->w
;
573 uint32_t H0
= phys_level0_sa
->h
;
575 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
576 uint32_t W
= isl_minify(W0
, l
);
577 uint32_t H
= isl_minify(H0
, l
);
579 if (msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
580 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
583 * If the surface is multisampled and it is a depth or stencil
584 * surface or Multisampled Surface StorageFormat in
585 * SURFACE_STATE is MSFMT_DEPTH_STENCIL, W_L and H_L must be
586 * adjusted as follows before proceeding: [...]
588 isl_msaa_interleaved_scale_px_to_sa(info
->samples
, &W
, &H
);
591 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
592 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
609 *phys_slice0_sa
= (struct isl_extent2d
) {
610 .w
= MAX(slice_top_w
, slice_bottom_w
),
611 .h
= MAX(slice_left_h
, slice_right_h
),
616 * A variant of isl_calc_phys_slice0_extent_sa() specific to
617 * ISL_DIM_LAYOUT_GEN4_3D.
620 isl_calc_phys_slice0_extent_sa_gen4_3d(
621 const struct isl_device
*dev
,
622 const struct isl_surf_init_info
*restrict info
,
623 const struct isl_extent3d
*image_align_sa
,
624 const struct isl_extent4d
*phys_level0_sa
,
625 struct isl_extent2d
*phys_slice0_sa
)
627 assert(info
->samples
== 1);
628 assert(phys_level0_sa
->array_len
== 1);
630 uint32_t slice_w
= 0;
631 uint32_t slice_h
= 0;
633 uint32_t W0
= phys_level0_sa
->w
;
634 uint32_t H0
= phys_level0_sa
->h
;
635 uint32_t D0
= phys_level0_sa
->d
;
637 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
638 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
639 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
640 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
642 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
643 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
645 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
646 slice_h
+= level_h
* max_layers_vert
;
649 *phys_slice0_sa
= (struct isl_extent2d
) {
656 * Calculate the physical extent of the surface's first array slice, in units
657 * of surface samples. If the surface is multi-leveled, then the result will
658 * be aligned to \a image_align_sa.
661 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
662 const struct isl_surf_init_info
*restrict info
,
663 enum isl_dim_layout dim_layout
,
664 enum isl_msaa_layout msaa_layout
,
665 const struct isl_extent3d
*image_align_sa
,
666 const struct isl_extent4d
*phys_level0_sa
,
667 struct isl_extent2d
*phys_slice0_sa
)
669 switch (dim_layout
) {
670 case ISL_DIM_LAYOUT_GEN9_1D
:
671 if (ISL_DEV_GEN(dev
) >= 9)
672 isl_finishme("%s:%s: [SKL+] physical layout of 1d surfaces",
675 case ISL_DIM_LAYOUT_GEN4_2D
:
676 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
677 image_align_sa
, phys_level0_sa
,
680 case ISL_DIM_LAYOUT_GEN4_3D
:
681 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
682 phys_level0_sa
, phys_slice0_sa
);
688 * Calculate the pitch between physical array slices, in units of rows of
689 * surface samples. The result is aligned to \a image_align_sa.
692 isl_calc_array_pitch_sa_rows(const struct isl_device
*dev
,
693 const struct isl_surf_init_info
*restrict info
,
694 enum isl_dim_layout dim_layout
,
695 enum isl_array_pitch_span array_pitch_span
,
696 const struct isl_extent3d
*image_align_sa
,
697 const struct isl_extent4d
*phys_level0_sa
,
698 const struct isl_extent2d
*phys_slice0_sa
)
700 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
702 switch (dim_layout
) {
703 case ISL_DIM_LAYOUT_GEN9_1D
:
704 if (ISL_DEV_GEN(dev
) >= 9)
705 isl_finishme("%s:%s: [SKL+] physical layout of 1d surfaces",
709 case ISL_DIM_LAYOUT_GEN4_2D
:
710 switch (array_pitch_span
) {
711 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
712 return isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
713 case ISL_ARRAY_PITCH_SPAN_FULL
: {
714 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
715 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
716 * Surfaces >> Surface Arrays.
718 uint32_t H0_sa
= phys_level0_sa
->h
;
719 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
721 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
722 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
725 if (ISL_DEV_GEN(dev
) >= 7) {
726 /* The QPitch equation changed slightly in Ivybridge. */
732 uint32_t pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
734 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
735 (info
->height
% 4 == 1)) {
736 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
737 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
739 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
740 * the value calculated in the equation above , for every
741 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
743 * XXX(chadv): Is the errata natural corollary of the physical
744 * layout of interleaved samples?
749 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
751 return pitch_sa_rows
;
757 case ISL_DIM_LAYOUT_GEN4_3D
:
758 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
759 return isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
762 unreachable("bad isl_dim_layout");
767 * Calculate the pitch of each surface row, in bytes.
770 isl_calc_row_pitch(const struct isl_device
*dev
,
771 const struct isl_surf_init_info
*restrict info
,
772 const struct isl_tile_info
*tile_info
,
773 const struct isl_extent3d
*image_align_sa
,
774 const struct isl_extent2d
*phys_slice0_sa
)
776 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
778 uint32_t row_pitch
= info
->min_pitch
;
780 /* First, align the surface to a cache line boundary, as the PRM explains
783 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
784 * Formats >> Surface Padding Requirements >> Render Target and Media
787 * The data port accesses data (pixels) outside of the surface if they
788 * are contained in the same cache request as pixels that are within the
789 * surface. These pixels will not be returned by the requesting message,
790 * however if these pixels lie outside of defined pages in the GTT,
791 * a GTT error will result when the cache request is processed. In order
792 * to avoid these GTT errors, “padding” at the bottom of the surface is
793 * sometimes necessary.
795 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
796 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
798 * The sampling engine accesses texels outside of the surface if they
799 * are contained in the same cache line as texels that are within the
800 * surface. These texels will not participate in any calculation
801 * performed by the sampling engine and will not affect the result of
802 * any sampling engine operation, however if these texels lie outside of
803 * defined pages in the GTT, a GTT error will result when the cache line
804 * is accessed. In order to avoid these GTT errors, “padding” at the
805 * bottom and right side of a sampling engine surface is sometimes
808 * It is possible that a cache line will straddle a page boundary if the
809 * base address or pitch is not aligned. All pages included in the cache
810 * lines that are part of the surface must map to valid GTT entries to
811 * avoid errors. To determine the necessary padding on the bottom and
812 * right side of the surface, refer to the table in Alignment Unit Size
813 * section for the i and j parameters for the surface format in use. The
814 * surface must then be extended to the next multiple of the alignment
815 * unit size in each dimension, and all texels contained in this
816 * extended surface must have valid GTT entries.
818 * For example, suppose the surface size is 15 texels by 10 texels and
819 * the alignment parameters are i=4 and j=2. In this case, the extended
820 * surface would be 16 by 10. Note that these calculations are done in
821 * texels, and must be converted to bytes based on the surface format
822 * being used to determine whether additional pages need to be defined.
824 row_pitch
= MAX(row_pitch
,
825 fmtl
->bs
* isl_align_div_npot(phys_slice0_sa
->w
, fmtl
->bw
));
827 switch (tile_info
->tiling
) {
828 case ISL_TILING_LINEAR
:
829 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
830 * RENDER_SURFACE_STATE Surface Pitch (p349):
832 * - For linear render target surfaces and surfaces accessed with the
833 * typed data port messages, the pitch must be a multiple of the
834 * element size for non-YUV surface formats. Pitch must be
835 * a multiple of 2 * element size for YUV surface formats.
837 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
838 * ignore because isl doesn't do buffers.]
840 * - For other linear surfaces, the pitch can be any multiple of
843 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
844 if (isl_format_is_yuv(info
->format
)) {
845 row_pitch
= isl_align_npot(row_pitch
, 2 * fmtl
->bs
);
847 row_pitch
= isl_align_npot(row_pitch
, fmtl
->bs
);
852 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
853 * RENDER_SURFACE_STATE Surface Pitch (p349):
855 * - For tiled surfaces, the pitch must be a multiple of the tile
858 row_pitch
= isl_align(row_pitch
, tile_info
->width
);
866 * Calculate the surface's total height, including padding, in units of
870 isl_calc_total_height_el(const struct isl_device
*dev
,
871 const struct isl_surf_init_info
*restrict info
,
872 const struct isl_tile_info
*tile_info
,
873 uint32_t phys_array_len
,
875 uint32_t array_pitch_el_rows
)
877 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
879 uint32_t total_h_el
= phys_array_len
* array_pitch_el_rows
;
880 uint32_t pad_bytes
= 0;
882 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
883 * Formats >> Surface Padding Requirements >> Render Target and Media
886 * The data port accesses data (pixels) outside of the surface if they
887 * are contained in the same cache request as pixels that are within the
888 * surface. These pixels will not be returned by the requesting message,
889 * however if these pixels lie outside of defined pages in the GTT,
890 * a GTT error will result when the cache request is processed. In
891 * order to avoid these GTT errors, “padding” at the bottom of the
892 * surface is sometimes necessary.
894 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
895 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
897 * ... Lots of padding requirements, all listed separately below.
900 /* We can safely ignore the first padding requirement, quoted below,
901 * because isl doesn't do buffers.
903 * - [pre-BDW] For buffers, which have no inherent “height,” padding
904 * requirements are different. A buffer must be padded to the next
905 * multiple of 256 array elements, with an additional 16 bytes added
906 * beyond that to account for the L1 cache line.
910 * - For compressed textures [...], padding at the bottom of the surface
911 * is to an even compressed row.
913 if (isl_format_is_compressed(info
->format
))
914 total_h_el
= isl_align(total_h_el
, 2);
917 * - For cube surfaces, an additional two rows of padding are required
918 * at the bottom of the surface.
920 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
924 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
925 * additional padding is required. These surfaces require an extra row
926 * plus 16 bytes of padding at the bottom in addition to the general
927 * padding requirements.
929 if (isl_format_is_yuv(info
->format
) &&
930 (fmtl
->bs
== 96 || fmtl
->bs
== 48|| fmtl
->bs
== 24)) {
936 * - For linear surfaces, additional padding of 64 bytes is required at
937 * the bottom of the surface. This is in addition to the padding
940 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
943 /* The below text weakens, not strengthens, the padding requirements for
944 * linear surfaces. Therefore we can safely ignore it.
946 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
947 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
948 * padding requirement is to the next aligned 64-byte boundary beyond
949 * the end of the surface. The rest of the padding requirements
950 * documented above do not apply to these surfaces.
954 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
955 * height % 4 != 0, the surface must be padded with
956 * 4-(height % 4)*Surface Pitch # of bytes.
958 if (ISL_DEV_GEN(dev
) >= 9 &&
959 tile_info
->tiling
== ISL_TILING_LINEAR
&&
960 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
961 total_h_el
= isl_align(total_h_el
, 4);
965 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
966 * to 4 times the Surface Pitch # of bytes
968 if (ISL_DEV_GEN(dev
) >= 9 &&
969 tile_info
->tiling
== ISL_TILING_LINEAR
&&
970 info
->dim
== ISL_SURF_DIM_1D
) {
974 /* Be sloppy. Align any leftover padding to a row boundary. */
975 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
981 isl_surf_init_s(const struct isl_device
*dev
,
982 struct isl_surf
*surf
,
983 const struct isl_surf_init_info
*restrict info
)
985 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
987 const struct isl_extent4d logical_level0_px
= {
991 .a
= info
->array_len
,
994 enum isl_dim_layout dim_layout
=
995 isl_surf_choose_dim_layout(dev
, info
->dim
);
997 enum isl_tiling tiling
;
998 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1001 struct isl_tile_info tile_info
;
1002 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bs
, &tile_info
))
1005 enum isl_msaa_layout msaa_layout
;
1006 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1009 struct isl_extent3d image_align_el
;
1010 isl_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
1013 struct isl_extent3d image_align_sa
=
1014 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1016 struct isl_extent4d phys_level0_sa
;
1017 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1019 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1020 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1022 enum isl_array_pitch_span array_pitch_span
=
1023 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1025 struct isl_extent2d phys_slice0_sa
;
1026 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1027 &image_align_sa
, &phys_level0_sa
,
1029 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1030 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1032 const uint32_t row_pitch
= isl_calc_row_pitch(dev
, info
, &tile_info
,
1036 const uint32_t array_pitch_sa_rows
=
1037 isl_calc_array_pitch_sa_rows(dev
, info
, dim_layout
, array_pitch_span
,
1038 &image_align_sa
, &phys_level0_sa
,
1040 assert(array_pitch_sa_rows
% fmtl
->bh
== 0);
1042 const uint32_t array_pitch_el_rows
= array_pitch_sa_rows
/ fmtl
->bh
;
1044 const uint32_t total_h_el
=
1045 isl_calc_total_height_el(dev
, info
, &tile_info
,
1046 phys_level0_sa
.array_len
, row_pitch
,
1047 array_pitch_el_rows
);
1049 const uint32_t total_h_sa
= total_h_el
* fmtl
->bh
;
1050 const uint32_t size
= row_pitch
* isl_align(total_h_sa
, tile_info
.height
);
1052 /* Alignment of surface base address, in bytes */
1053 uint32_t base_alignment
= info
->min_alignment
;
1054 base_alignment
= isl_align(base_alignment
, tile_info
.size
);
1056 *surf
= (struct isl_surf
) {
1058 .dim_layout
= dim_layout
,
1059 .msaa_layout
= msaa_layout
,
1061 .format
= info
->format
,
1063 .levels
= info
->levels
,
1064 .samples
= info
->samples
,
1066 .image_alignment_el
= image_align_el
,
1067 .logical_level0_px
= logical_level0_px
,
1068 .phys_level0_sa
= phys_level0_sa
,
1071 .alignment
= base_alignment
,
1072 .row_pitch
= row_pitch
,
1073 .array_pitch_el_rows
= array_pitch_el_rows
,
1074 .array_pitch_span
= array_pitch_span
,
1076 .usage
= info
->usage
,
1083 * A variant of isl_surf_get_image_offset_sa() specific to
1084 * ISL_DIM_LAYOUT_GEN4_2D.
1087 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1088 uint32_t level
, uint32_t layer
,
1089 uint32_t *x_offset_sa
,
1090 uint32_t *y_offset_sa
)
1092 assert(level
< surf
->levels
);
1093 assert(layer
< surf
->phys_level0_sa
.array_len
);
1094 assert(surf
->phys_level0_sa
.depth
== 1);
1096 const struct isl_extent3d image_align_sa
=
1097 isl_surf_get_image_alignment_sa(surf
);
1099 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1100 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1103 uint32_t y
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1105 for (uint32_t l
= 0; l
< level
; ++l
) {
1107 uint32_t W
= isl_minify(W0
, l
);
1109 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1110 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, &W
, NULL
);
1112 x
+= isl_align_npot(W
, image_align_sa
.w
);
1114 uint32_t H
= isl_minify(H0
, l
);
1116 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1117 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, NULL
, &H
);
1119 y
+= isl_align_npot(H
, image_align_sa
.h
);
1128 * A variant of isl_surf_get_image_offset_sa() specific to
1129 * ISL_DIM_LAYOUT_GEN4_3D.
1132 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1133 uint32_t level
, uint32_t logical_z_offset_px
,
1134 uint32_t *x_offset_sa
,
1135 uint32_t *y_offset_sa
)
1137 assert(level
< surf
->levels
);
1138 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1139 assert(surf
->phys_level0_sa
.array_len
== 1);
1141 const struct isl_extent3d image_align_sa
=
1142 isl_surf_get_image_alignment_sa(surf
);
1144 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1145 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1146 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1151 for (uint32_t l
= 0; l
< level
; ++l
) {
1152 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1153 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1154 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1156 y
+= level_h
* max_layers_vert
;
1159 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1160 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1161 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1163 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1164 const uint32_t max_layers_vert
= isl_align_div(level_d
, 1u << level
);
1166 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1167 y
+= level_h
* (logical_z_offset_px
/ max_layers_vert
);
1174 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1176 uint32_t logical_array_layer
,
1177 uint32_t logical_z_offset_px
,
1178 uint32_t *x_offset_sa
,
1179 uint32_t *y_offset_sa
)
1181 assert(level
< surf
->levels
);
1182 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1183 assert(logical_z_offset_px
1184 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1186 switch (surf
->dim_layout
) {
1187 case ISL_DIM_LAYOUT_GEN9_1D
:
1188 isl_finishme("%s:%s: gen9 1d surfaces", __FILE__
, __func__
);
1189 case ISL_DIM_LAYOUT_GEN4_2D
:
1190 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
,
1191 x_offset_sa
, y_offset_sa
);
1193 case ISL_DIM_LAYOUT_GEN4_3D
:
1194 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1195 x_offset_sa
, y_offset_sa
);