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[mesa.git] / src / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * =============
30 *
31 * The header is ordered as:
32 * - forward declarations
33 * - macros that may be overridden at compile-time for specific gens
34 * - enums and constants
35 * - structs and unions
36 * - functions
37 *
38 *
39 * Surface Units
40 * =============
41 *
42 * Intro
43 * -----
44 * ISL takes care in its equations to correctly handle conversion among
45 * surface units (such as pixels and compression blocks) and to carefully
46 * distinguish between a surface's logical layout in the client API and its
47 * physical layout in memory.
48 *
49 * Symbol names often explicitly declare their unit with a suffix:
50 *
51 * - px: logical pixels
52 * - sa: physical surface samples
53 * - el: physical surface elements
54 * - sa_rows: rows of physical surface samples
55 * - el_rows: rows of physical surface elements
56 *
57 * Logical units are independent of hardware generation and are closely
58 * related to the user-facing API (OpenGL and Vulkan). Physical units are
59 * dependent on hardware generation and reflect the surface's layout in
60 * memory.
61 *
62 * Definitions
63 * -----------
64 * - Logical Pixels (px):
65 *
66 * The surface's layout from the perspective of the client API (OpenGL and
67 * Vulkan) is in units of logical pixels. Logical pixels are independent of
68 * the surface's layout in memory.
69 *
70 * A surface's width and height, in units of logical pixels, is not affected
71 * by the surface's sample count. For example, consider a VkImage created
72 * with VkImageCreateInfo{width=w0, height=h0, samples=s0}. The surface's
73 * width and height at level 0 is, in units of logical pixels, w0 and h0
74 * regardless of the value of s0.
75 *
76 * For example, the logical array length of a 3D surface is always 1, even
77 * on Gen9 where the surface's memory layout is that of an array surface
78 * (ISL_DIM_LAYOUT_GEN4_2D).
79 *
80 * - Physical Surface Samples (sa):
81 *
82 * For a multisampled surface, this unit has the obvious meaning.
83 * A singlesampled surface, from ISL's perspective, is simply a multisampled
84 * surface whose sample count is 1.
85 *
86 * For example, consider a 2D single-level non-array surface with samples=4,
87 * width_px=64, and height_px=64 (note that the suffix 'px' indicates
88 * logical pixels). If the surface's multisample layout is
89 * ISL_MSAA_LAYOUT_INTERLEAVED, then the extent of level 0 is, in units of
90 * physical surface samples, width_sa=128, height_sa=128, depth_sa=1,
91 * array_length_sa=1. If ISL_MSAA_LAYOUT_ARRAY, then width_sa=64,
92 * height_sa=64, depth_sa=1, array_length_sa=4.
93 *
94 * - Physical Surface Elements (el):
95 *
96 * This unit allows ISL to treat compressed and uncompressed formats
97 * identically in many calculations.
98 *
99 * If the surface's pixel format is compressed, such as ETC2, then a surface
100 * element is equivalent to a compression block. If uncompressed, then
101 * a surface element is equivalent to a surface sample. As a corollary, for
102 * a given surface a surface element is at least as large as a surface
103 * sample.
104 *
105 * Errata
106 * ------
107 * ISL acquired the term 'element' from the Broadwell PRM [1], which defines
108 * a surface element as follows:
109 *
110 * An element is defined as a pixel in uncompresed surface formats, and as
111 * a compression block in compressed surface formats. For
112 * MSFMT_DEPTH_STENCIL type multisampled surfaces, an element is a sample.
113 *
114 * [1]: Broadwell PRM >> Volume 2d: Command Reference: Structures >>
115 * RENDER_SURFACE_STATE Surface Vertical Alignment (p325)
116 */
117
118 #pragma once
119
120 #include <assert.h>
121 #include <stdbool.h>
122 #include <stdint.h>
123
124 #include "util/macros.h"
125
126 #ifdef __cplusplus
127 extern "C" {
128 #endif
129
130 struct brw_device_info;
131 struct brw_image_param;
132
133 #ifndef ISL_DEV_GEN
134 /**
135 * @brief Get the hardware generation of isl_device.
136 *
137 * You can define this as a compile-time constant in the CFLAGS. For example,
138 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
139 */
140 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
141 #endif
142
143 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
144 /**
145 * You can define this as a compile-time constant in the CFLAGS. For example,
146 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
147 */
148 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
149 #endif
150
151 /**
152 * Hardware enumeration SURFACE_FORMAT.
153 *
154 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
155 * Enumerations: SURFACE_FORMAT.
156 */
157 enum isl_format {
158 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
159 ISL_FORMAT_R32G32B32A32_SINT = 1,
160 ISL_FORMAT_R32G32B32A32_UINT = 2,
161 ISL_FORMAT_R32G32B32A32_UNORM = 3,
162 ISL_FORMAT_R32G32B32A32_SNORM = 4,
163 ISL_FORMAT_R64G64_FLOAT = 5,
164 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
165 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
166 ISL_FORMAT_R32G32B32A32_USCALED = 8,
167 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
168 ISL_FORMAT_R64G64_PASSTHRU = 33,
169 ISL_FORMAT_R32G32B32_FLOAT = 64,
170 ISL_FORMAT_R32G32B32_SINT = 65,
171 ISL_FORMAT_R32G32B32_UINT = 66,
172 ISL_FORMAT_R32G32B32_UNORM = 67,
173 ISL_FORMAT_R32G32B32_SNORM = 68,
174 ISL_FORMAT_R32G32B32_SSCALED = 69,
175 ISL_FORMAT_R32G32B32_USCALED = 70,
176 ISL_FORMAT_R32G32B32_SFIXED = 80,
177 ISL_FORMAT_R16G16B16A16_UNORM = 128,
178 ISL_FORMAT_R16G16B16A16_SNORM = 129,
179 ISL_FORMAT_R16G16B16A16_SINT = 130,
180 ISL_FORMAT_R16G16B16A16_UINT = 131,
181 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
182 ISL_FORMAT_R32G32_FLOAT = 133,
183 ISL_FORMAT_R32G32_SINT = 134,
184 ISL_FORMAT_R32G32_UINT = 135,
185 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
186 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
187 ISL_FORMAT_L32A32_FLOAT = 138,
188 ISL_FORMAT_R32G32_UNORM = 139,
189 ISL_FORMAT_R32G32_SNORM = 140,
190 ISL_FORMAT_R64_FLOAT = 141,
191 ISL_FORMAT_R16G16B16X16_UNORM = 142,
192 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
193 ISL_FORMAT_A32X32_FLOAT = 144,
194 ISL_FORMAT_L32X32_FLOAT = 145,
195 ISL_FORMAT_I32X32_FLOAT = 146,
196 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
197 ISL_FORMAT_R16G16B16A16_USCALED = 148,
198 ISL_FORMAT_R32G32_SSCALED = 149,
199 ISL_FORMAT_R32G32_USCALED = 150,
200 ISL_FORMAT_R32G32_SFIXED = 160,
201 ISL_FORMAT_R64_PASSTHRU = 161,
202 ISL_FORMAT_B8G8R8A8_UNORM = 192,
203 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
204 ISL_FORMAT_R10G10B10A2_UNORM = 194,
205 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
206 ISL_FORMAT_R10G10B10A2_UINT = 196,
207 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
208 ISL_FORMAT_R8G8B8A8_UNORM = 199,
209 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
210 ISL_FORMAT_R8G8B8A8_SNORM = 201,
211 ISL_FORMAT_R8G8B8A8_SINT = 202,
212 ISL_FORMAT_R8G8B8A8_UINT = 203,
213 ISL_FORMAT_R16G16_UNORM = 204,
214 ISL_FORMAT_R16G16_SNORM = 205,
215 ISL_FORMAT_R16G16_SINT = 206,
216 ISL_FORMAT_R16G16_UINT = 207,
217 ISL_FORMAT_R16G16_FLOAT = 208,
218 ISL_FORMAT_B10G10R10A2_UNORM = 209,
219 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
220 ISL_FORMAT_R11G11B10_FLOAT = 211,
221 ISL_FORMAT_R32_SINT = 214,
222 ISL_FORMAT_R32_UINT = 215,
223 ISL_FORMAT_R32_FLOAT = 216,
224 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
225 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
226 ISL_FORMAT_L32_UNORM = 221,
227 ISL_FORMAT_A32_UNORM = 222,
228 ISL_FORMAT_L16A16_UNORM = 223,
229 ISL_FORMAT_I24X8_UNORM = 224,
230 ISL_FORMAT_L24X8_UNORM = 225,
231 ISL_FORMAT_A24X8_UNORM = 226,
232 ISL_FORMAT_I32_FLOAT = 227,
233 ISL_FORMAT_L32_FLOAT = 228,
234 ISL_FORMAT_A32_FLOAT = 229,
235 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
236 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
237 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
238 ISL_FORMAT_B8G8R8X8_UNORM = 233,
239 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
240 ISL_FORMAT_R8G8B8X8_UNORM = 235,
241 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
242 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
243 ISL_FORMAT_B10G10R10X2_UNORM = 238,
244 ISL_FORMAT_L16A16_FLOAT = 240,
245 ISL_FORMAT_R32_UNORM = 241,
246 ISL_FORMAT_R32_SNORM = 242,
247 ISL_FORMAT_R10G10B10X2_USCALED = 243,
248 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
249 ISL_FORMAT_R8G8B8A8_USCALED = 245,
250 ISL_FORMAT_R16G16_SSCALED = 246,
251 ISL_FORMAT_R16G16_USCALED = 247,
252 ISL_FORMAT_R32_SSCALED = 248,
253 ISL_FORMAT_R32_USCALED = 249,
254 ISL_FORMAT_B5G6R5_UNORM = 256,
255 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
256 ISL_FORMAT_B5G5R5A1_UNORM = 258,
257 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
258 ISL_FORMAT_B4G4R4A4_UNORM = 260,
259 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
260 ISL_FORMAT_R8G8_UNORM = 262,
261 ISL_FORMAT_R8G8_SNORM = 263,
262 ISL_FORMAT_R8G8_SINT = 264,
263 ISL_FORMAT_R8G8_UINT = 265,
264 ISL_FORMAT_R16_UNORM = 266,
265 ISL_FORMAT_R16_SNORM = 267,
266 ISL_FORMAT_R16_SINT = 268,
267 ISL_FORMAT_R16_UINT = 269,
268 ISL_FORMAT_R16_FLOAT = 270,
269 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
270 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
271 ISL_FORMAT_I16_UNORM = 273,
272 ISL_FORMAT_L16_UNORM = 274,
273 ISL_FORMAT_A16_UNORM = 275,
274 ISL_FORMAT_L8A8_UNORM = 276,
275 ISL_FORMAT_I16_FLOAT = 277,
276 ISL_FORMAT_L16_FLOAT = 278,
277 ISL_FORMAT_A16_FLOAT = 279,
278 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
279 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
280 ISL_FORMAT_B5G5R5X1_UNORM = 282,
281 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
282 ISL_FORMAT_R8G8_SSCALED = 284,
283 ISL_FORMAT_R8G8_USCALED = 285,
284 ISL_FORMAT_R16_SSCALED = 286,
285 ISL_FORMAT_R16_USCALED = 287,
286 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
287 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
288 ISL_FORMAT_A1B5G5R5_UNORM = 292,
289 ISL_FORMAT_A4B4G4R4_UNORM = 293,
290 ISL_FORMAT_L8A8_UINT = 294,
291 ISL_FORMAT_L8A8_SINT = 295,
292 ISL_FORMAT_R8_UNORM = 320,
293 ISL_FORMAT_R8_SNORM = 321,
294 ISL_FORMAT_R8_SINT = 322,
295 ISL_FORMAT_R8_UINT = 323,
296 ISL_FORMAT_A8_UNORM = 324,
297 ISL_FORMAT_I8_UNORM = 325,
298 ISL_FORMAT_L8_UNORM = 326,
299 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
300 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
301 ISL_FORMAT_R8_SSCALED = 329,
302 ISL_FORMAT_R8_USCALED = 330,
303 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
304 ISL_FORMAT_L8_UNORM_SRGB = 332,
305 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
306 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
307 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
308 ISL_FORMAT_Y8_UNORM = 336,
309 ISL_FORMAT_L8_UINT = 338,
310 ISL_FORMAT_L8_SINT = 339,
311 ISL_FORMAT_I8_UINT = 340,
312 ISL_FORMAT_I8_SINT = 341,
313 ISL_FORMAT_DXT1_RGB_SRGB = 384,
314 ISL_FORMAT_R1_UNORM = 385,
315 ISL_FORMAT_YCRCB_NORMAL = 386,
316 ISL_FORMAT_YCRCB_SWAPUVY = 387,
317 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
318 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
319 ISL_FORMAT_BC1_UNORM = 390,
320 ISL_FORMAT_BC2_UNORM = 391,
321 ISL_FORMAT_BC3_UNORM = 392,
322 ISL_FORMAT_BC4_UNORM = 393,
323 ISL_FORMAT_BC5_UNORM = 394,
324 ISL_FORMAT_BC1_UNORM_SRGB = 395,
325 ISL_FORMAT_BC2_UNORM_SRGB = 396,
326 ISL_FORMAT_BC3_UNORM_SRGB = 397,
327 ISL_FORMAT_MONO8 = 398,
328 ISL_FORMAT_YCRCB_SWAPUV = 399,
329 ISL_FORMAT_YCRCB_SWAPY = 400,
330 ISL_FORMAT_DXT1_RGB = 401,
331 ISL_FORMAT_FXT1 = 402,
332 ISL_FORMAT_R8G8B8_UNORM = 403,
333 ISL_FORMAT_R8G8B8_SNORM = 404,
334 ISL_FORMAT_R8G8B8_SSCALED = 405,
335 ISL_FORMAT_R8G8B8_USCALED = 406,
336 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
337 ISL_FORMAT_R64G64B64_FLOAT = 408,
338 ISL_FORMAT_BC4_SNORM = 409,
339 ISL_FORMAT_BC5_SNORM = 410,
340 ISL_FORMAT_R16G16B16_FLOAT = 411,
341 ISL_FORMAT_R16G16B16_UNORM = 412,
342 ISL_FORMAT_R16G16B16_SNORM = 413,
343 ISL_FORMAT_R16G16B16_SSCALED = 414,
344 ISL_FORMAT_R16G16B16_USCALED = 415,
345 ISL_FORMAT_BC6H_SF16 = 417,
346 ISL_FORMAT_BC7_UNORM = 418,
347 ISL_FORMAT_BC7_UNORM_SRGB = 419,
348 ISL_FORMAT_BC6H_UF16 = 420,
349 ISL_FORMAT_PLANAR_420_8 = 421,
350 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
351 ISL_FORMAT_ETC1_RGB8 = 425,
352 ISL_FORMAT_ETC2_RGB8 = 426,
353 ISL_FORMAT_EAC_R11 = 427,
354 ISL_FORMAT_EAC_RG11 = 428,
355 ISL_FORMAT_EAC_SIGNED_R11 = 429,
356 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
357 ISL_FORMAT_ETC2_SRGB8 = 431,
358 ISL_FORMAT_R16G16B16_UINT = 432,
359 ISL_FORMAT_R16G16B16_SINT = 433,
360 ISL_FORMAT_R32_SFIXED = 434,
361 ISL_FORMAT_R10G10B10A2_SNORM = 435,
362 ISL_FORMAT_R10G10B10A2_USCALED = 436,
363 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
364 ISL_FORMAT_R10G10B10A2_SINT = 438,
365 ISL_FORMAT_B10G10R10A2_SNORM = 439,
366 ISL_FORMAT_B10G10R10A2_USCALED = 440,
367 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
368 ISL_FORMAT_B10G10R10A2_UINT = 442,
369 ISL_FORMAT_B10G10R10A2_SINT = 443,
370 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
371 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
372 ISL_FORMAT_ETC2_RGB8_PTA = 448,
373 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
374 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
375 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
376 ISL_FORMAT_R8G8B8_UINT = 456,
377 ISL_FORMAT_R8G8B8_SINT = 457,
378 ISL_FORMAT_RAW = 511,
379
380 /* Hardware doesn't understand this out-of-band value */
381 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
382 };
383
384 /**
385 * Numerical base type for channels of isl_format.
386 */
387 enum isl_base_type {
388 ISL_VOID,
389 ISL_RAW,
390 ISL_UNORM,
391 ISL_SNORM,
392 ISL_UFLOAT,
393 ISL_SFLOAT,
394 ISL_UFIXED,
395 ISL_SFIXED,
396 ISL_UINT,
397 ISL_SINT,
398 ISL_USCALED,
399 ISL_SSCALED,
400 };
401
402 /**
403 * Colorspace of isl_format.
404 */
405 enum isl_colorspace {
406 ISL_COLORSPACE_NONE = 0,
407 ISL_COLORSPACE_LINEAR,
408 ISL_COLORSPACE_SRGB,
409 ISL_COLORSPACE_YUV,
410 };
411
412 /**
413 * Texture compression mode of isl_format.
414 */
415 enum isl_txc {
416 ISL_TXC_NONE = 0,
417 ISL_TXC_DXT1,
418 ISL_TXC_DXT3,
419 ISL_TXC_DXT5,
420 ISL_TXC_FXT1,
421 ISL_TXC_RGTC1,
422 ISL_TXC_RGTC2,
423 ISL_TXC_BPTC,
424 ISL_TXC_ETC1,
425 ISL_TXC_ETC2,
426 };
427
428 /**
429 * @brief Hardware tile mode
430 *
431 * WARNING: These values differ from the hardware enum values, which are
432 * unstable across hardware generations.
433 *
434 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
435 * clearly distinguish it from Yf and Ys.
436 */
437 enum isl_tiling {
438 ISL_TILING_LINEAR = 0,
439 ISL_TILING_W,
440 ISL_TILING_X,
441 ISL_TILING_Y0, /**< Legacy Y tiling */
442 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
443 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
444 };
445
446 /**
447 * @defgroup Tiling Flags
448 * @{
449 */
450 typedef uint32_t isl_tiling_flags_t;
451 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
452 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
453 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
454 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
455 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
456 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
457 #define ISL_TILING_ANY_MASK (~0u)
458 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
459
460 /** Any Y tiling, including legacy Y tiling. */
461 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
462 ISL_TILING_Yf_BIT | \
463 ISL_TILING_Ys_BIT)
464
465 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
466 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
467 ISL_TILING_Ys_BIT)
468 /** @} */
469
470 /**
471 * @brief Logical dimension of surface.
472 *
473 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
474 * as 2D array surfaces.
475 */
476 enum isl_surf_dim {
477 ISL_SURF_DIM_1D,
478 ISL_SURF_DIM_2D,
479 ISL_SURF_DIM_3D,
480 };
481
482 /**
483 * @brief Physical layout of the surface's dimensions.
484 */
485 enum isl_dim_layout {
486 /**
487 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
488 * 6.17.3: 2D Surfaces.
489 *
490 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
491 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
492 *
493 * One-dimensional surfaces are identical to 2D surfaces with height of
494 * one.
495 *
496 * @invariant isl_surf::phys_level0_sa::depth == 1
497 */
498 ISL_DIM_LAYOUT_GEN4_2D,
499
500 /**
501 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
502 * 6.17.5: 3D Surfaces.
503 *
504 * @invariant isl_surf::phys_level0_sa::array_len == 1
505 */
506 ISL_DIM_LAYOUT_GEN4_3D,
507
508 /**
509 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
510 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
511 */
512 ISL_DIM_LAYOUT_GEN9_1D,
513 };
514
515 /* TODO(chadv): Explain */
516 enum isl_array_pitch_span {
517 ISL_ARRAY_PITCH_SPAN_FULL,
518 ISL_ARRAY_PITCH_SPAN_COMPACT,
519 };
520
521 /**
522 * @defgroup Surface Usage
523 * @{
524 */
525 typedef uint64_t isl_surf_usage_flags_t;
526 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
527 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
528 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
529 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
530 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
531 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
532 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
533 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
534 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
535 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
536 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
537 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
538 /** @} */
539
540 /**
541 * @brief Multisample Format
542 */
543 enum isl_msaa_layout {
544 /**
545 * @brief Suface is single-sampled.
546 */
547 ISL_MSAA_LAYOUT_NONE,
548
549 /**
550 * @brief [SNB+] Interleaved Multisample Format
551 *
552 * In this format, multiple samples are interleaved into each cacheline.
553 * In other words, the sample index is swizzled into the low 6 bits of the
554 * surface's virtual address space.
555 *
556 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
557 * and its pixel format is 32bpp. Then the first cacheline is arranged
558 * thus:
559 *
560 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
561 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
562 *
563 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
564 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
565 *
566 * The hardware docs refer to this format with multiple terms. In
567 * Sandybridge, this is the only multisample format; so no term is used.
568 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
569 * Multisample Surface). Later hardware docs additionally refer to this
570 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
571 * color surfaces).
572 *
573 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
574 * Surface Behavior".
575 *
576 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
577 * Multisampled Surfaces".
578 */
579 ISL_MSAA_LAYOUT_INTERLEAVED,
580
581 /**
582 * @brief [IVB+] Array Multisample Format
583 *
584 * In this format, the surface's physical layout resembles that of a
585 * 2D array surface.
586 *
587 * Suppose the multisample surface's logical extent is (w, h) and its
588 * sample count is N. Then surface's physical extent is the same as
589 * a singlesample 2D surface whose logical extent is (w, h) and array
590 * length is N. Array slice `i` contains the pixel values for sample
591 * index `i`.
592 *
593 * The Ivybridge docs refer to surfaces in this format as UMS
594 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
595 * Surface). The Broadwell docs additionally refer to this format as
596 * MSFMT_MSS (MSS=Multisample Surface Storage).
597 *
598 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
599 * Multisample Surfaces".
600 *
601 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
602 * Multisample Surfaces".
603 */
604 ISL_MSAA_LAYOUT_ARRAY,
605 };
606
607
608 struct isl_device {
609 const struct brw_device_info *info;
610 bool use_separate_stencil;
611 };
612
613 struct isl_extent2d {
614 union { uint32_t w, width; };
615 union { uint32_t h, height; };
616 };
617
618 struct isl_extent3d {
619 union { uint32_t w, width; };
620 union { uint32_t h, height; };
621 union { uint32_t d, depth; };
622 };
623
624 struct isl_extent4d {
625 union { uint32_t w, width; };
626 union { uint32_t h, height; };
627 union { uint32_t d, depth; };
628 union { uint32_t a, array_len; };
629 };
630
631 struct isl_channel_layout {
632 enum isl_base_type type;
633 uint8_t bits; /**< Size in bits */
634 };
635
636 /**
637 * Each format has 3D block extent (width, height, depth). The block extent
638 * of compressed formats is that of the format's compression block. For
639 * example, the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1).
640 * The block extent of uncompressed pixel formats, such as
641 * ISL_FORMAT_R8G8B8A8_UNORM, is is (w=1, h=1, d=1).
642 */
643 struct isl_format_layout {
644 enum isl_format format;
645
646 uint8_t bs; /**< Block size, in bytes, rounded towards 0 */
647 uint8_t bw; /**< Block width, in pixels */
648 uint8_t bh; /**< Block height, in pixels */
649 uint8_t bd; /**< Block depth, in pixels */
650
651 struct {
652 struct isl_channel_layout r; /**< Red channel */
653 struct isl_channel_layout g; /**< Green channel */
654 struct isl_channel_layout b; /**< Blue channel */
655 struct isl_channel_layout a; /**< Alpha channel */
656 struct isl_channel_layout l; /**< Luminance channel */
657 struct isl_channel_layout i; /**< Intensity channel */
658 struct isl_channel_layout p; /**< Palette channel */
659 } channels;
660
661 enum isl_colorspace colorspace;
662 enum isl_txc txc;
663 };
664
665 struct isl_tile_info {
666 enum isl_tiling tiling;
667 uint32_t width; /**< in bytes */
668 uint32_t height; /**< in rows of memory */
669 uint32_t size; /**< in bytes */
670 };
671
672 /**
673 * @brief Input to surface initialization
674 *
675 * @invariant width >= 1
676 * @invariant height >= 1
677 * @invariant depth >= 1
678 * @invariant levels >= 1
679 * @invariant samples >= 1
680 * @invariant array_len >= 1
681 *
682 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
683 * @invariant if 2D then depth == 1
684 * @invariant if 3D then array_len == 1 and samples == 1
685 */
686 struct isl_surf_init_info {
687 enum isl_surf_dim dim;
688 enum isl_format format;
689
690 uint32_t width;
691 uint32_t height;
692 uint32_t depth;
693 uint32_t levels;
694 uint32_t array_len;
695 uint32_t samples;
696
697 /** Lower bound for isl_surf::alignment, in bytes. */
698 uint32_t min_alignment;
699
700 /** Lower bound for isl_surf::pitch, in bytes. */
701 uint32_t min_pitch;
702
703 isl_surf_usage_flags_t usage;
704
705 /** Flags that alter how ISL selects isl_surf::tiling. */
706 isl_tiling_flags_t tiling_flags;
707 };
708
709 struct isl_surf {
710 enum isl_surf_dim dim;
711 enum isl_dim_layout dim_layout;
712 enum isl_msaa_layout msaa_layout;
713 enum isl_tiling tiling;
714 enum isl_format format;
715
716 /**
717 * Alignment of the upper-left sample of each subimage, in units of surface
718 * elements.
719 */
720 struct isl_extent3d image_alignment_el;
721
722 /**
723 * Logical extent of the surface's base level, in units of pixels. This is
724 * identical to the extent defined in isl_surf_init_info.
725 */
726 struct isl_extent4d logical_level0_px;
727
728 /**
729 * Physical extent of the surface's base level, in units of physical
730 * surface samples and aligned to the format's compression block.
731 *
732 * Consider isl_dim_layout as an operator that transforms a logical surface
733 * layout to a physical surface layout. Then
734 *
735 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
736 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
737 */
738 struct isl_extent4d phys_level0_sa;
739
740 uint32_t levels;
741 uint32_t samples;
742
743 /** Total size of the surface, in bytes. */
744 uint32_t size;
745
746 /** Required alignment for the surface's base address. */
747 uint32_t alignment;
748
749 /**
750 * Pitch between vertically adjacent surface elements, in bytes.
751 */
752 uint32_t row_pitch;
753
754 /**
755 * Pitch between physical array slices, in rows of surface elements.
756 */
757 uint32_t array_pitch_el_rows;
758
759 enum isl_array_pitch_span array_pitch_span;
760
761 /** Copy of isl_surf_init_info::usage. */
762 isl_surf_usage_flags_t usage;
763 };
764
765 extern const struct isl_format_layout isl_format_layouts[];
766
767 void
768 isl_device_init(struct isl_device *dev,
769 const struct brw_device_info *info);
770
771 static inline const struct isl_format_layout * ATTRIBUTE_CONST
772 isl_format_get_layout(enum isl_format fmt)
773 {
774 return &isl_format_layouts[fmt];
775 }
776
777 bool
778 isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
779
780 static inline bool
781 isl_format_is_compressed(enum isl_format fmt)
782 {
783 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
784
785 return fmtl->txc != ISL_TXC_NONE;
786 }
787
788 static inline bool
789 isl_format_has_bc_compression(enum isl_format fmt)
790 {
791 switch (isl_format_get_layout(fmt)->txc) {
792 case ISL_TXC_DXT1:
793 case ISL_TXC_DXT3:
794 case ISL_TXC_DXT5:
795 return true;
796 case ISL_TXC_NONE:
797 case ISL_TXC_FXT1:
798 case ISL_TXC_RGTC1:
799 case ISL_TXC_RGTC2:
800 case ISL_TXC_BPTC:
801 case ISL_TXC_ETC1:
802 case ISL_TXC_ETC2:
803 return false;
804 }
805
806 unreachable("bad texture compression mode");
807 return false;
808 }
809
810 static inline bool
811 isl_format_is_yuv(enum isl_format fmt)
812 {
813 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
814
815 return fmtl->colorspace == ISL_COLORSPACE_YUV;
816 }
817
818 static inline bool
819 isl_format_block_is_1x1x1(enum isl_format fmt)
820 {
821 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
822
823 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
824 }
825
826 static inline bool
827 isl_format_is_rgb(enum isl_format fmt)
828 {
829 return isl_format_layouts[fmt].channels.r.bits > 0 &&
830 isl_format_layouts[fmt].channels.g.bits > 0 &&
831 isl_format_layouts[fmt].channels.b.bits > 0 &&
832 isl_format_layouts[fmt].channels.a.bits == 0;
833 }
834
835 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
836 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
837
838 bool isl_is_storage_image_format(enum isl_format fmt);
839
840 enum isl_format
841 isl_lower_storage_image_format(const struct isl_device *dev,
842 enum isl_format fmt);
843
844 static inline bool
845 isl_tiling_is_std_y(enum isl_tiling tiling)
846 {
847 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
848 }
849
850 bool
851 isl_tiling_get_info(const struct isl_device *dev,
852 enum isl_tiling tiling,
853 uint32_t format_block_size,
854 struct isl_tile_info *info);
855
856 void
857 isl_tiling_get_extent(const struct isl_device *dev,
858 enum isl_tiling tiling,
859 uint32_t format_block_size,
860 struct isl_extent2d *e);
861 bool
862 isl_surf_choose_tiling(const struct isl_device *dev,
863 const struct isl_surf_init_info *restrict info,
864 enum isl_tiling *tiling);
865
866 static inline bool
867 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
868 {
869 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
870 }
871
872 static inline bool
873 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
874 {
875 return usage & ISL_SURF_USAGE_DEPTH_BIT;
876 }
877
878 static inline bool
879 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
880 {
881 return usage & ISL_SURF_USAGE_STENCIL_BIT;
882 }
883
884 static inline bool
885 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
886 {
887 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
888 (usage & ISL_SURF_USAGE_STENCIL_BIT);
889 }
890
891 static inline bool
892 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
893 {
894 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
895 }
896
897 static inline bool
898 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
899 {
900 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
901 (info->format == ISL_FORMAT_R16_UNORM);
902 }
903
904 static inline bool
905 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
906 {
907 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
908 (info->format == ISL_FORMAT_R32_FLOAT);
909 }
910
911 static inline struct isl_extent2d
912 isl_extent2d(uint32_t width, uint32_t height)
913 {
914 return (struct isl_extent2d) { .w = width, .h = height };
915 }
916
917 static inline struct isl_extent3d
918 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
919 {
920 return (struct isl_extent3d) { .w = width, .h = height, .d = depth };
921 }
922
923 static inline struct isl_extent4d
924 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
925 uint32_t array_len)
926 {
927 return (struct isl_extent4d) {
928 .w = width,
929 .h = height,
930 .d = depth,
931 .a = array_len,
932 };
933 }
934
935 #define isl_surf_init(dev, surf, ...) \
936 isl_surf_init_s((dev), (surf), \
937 &(struct isl_surf_init_info) { __VA_ARGS__ });
938
939 bool
940 isl_surf_init_s(const struct isl_device *dev,
941 struct isl_surf *surf,
942 const struct isl_surf_init_info *restrict info);
943
944 /**
945 * Alignment of the upper-left sample of each subimage, in units of surface
946 * elements.
947 */
948 static inline struct isl_extent3d
949 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
950 {
951 return surf->image_alignment_el;
952 }
953
954 /**
955 * Alignment of the upper-left sample of each subimage, in units of surface
956 * samples.
957 */
958 static inline struct isl_extent3d
959 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
960 {
961 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
962
963 return (struct isl_extent3d) {
964 .w = fmtl->bw * surf->image_alignment_el.w,
965 .h = fmtl->bh * surf->image_alignment_el.h,
966 .d = fmtl->bd * surf->image_alignment_el.d,
967 };
968 }
969
970 /**
971 * Pitch between physical array slices, in rows of surface elements.
972 */
973 static inline uint32_t
974 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
975 {
976 return surf->array_pitch_el_rows;
977 }
978
979 /**
980 * Pitch between physical array slices, in rows of surface samples.
981 */
982 static inline uint32_t
983 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
984 {
985 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
986 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
987 }
988
989 /**
990 * Pitch between physical array slices, in bytes.
991 */
992 static inline uint32_t
993 isl_surf_get_array_pitch(const struct isl_surf *surf)
994 {
995 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
996 }
997
998 /**
999 * Get the offset to an subimage within the surface, in units of surface
1000 * samples.
1001 *
1002 * @invariant level < surface levels
1003 * @invariant logical_array_layer < logical array length of surface
1004 * @invariant logical_z_offset_px < logical depth of surface at level
1005 */
1006 void
1007 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
1008 uint32_t level,
1009 uint32_t logical_array_layer,
1010 uint32_t logical_z_offset_px,
1011 uint32_t *x_offset_sa,
1012 uint32_t *y_offset_sa);
1013
1014 #ifdef __cplusplus
1015 }
1016 #endif