2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * @brief Intel Surface Layout
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
44 #include "util/macros.h"
50 struct brw_device_info
;
51 struct brw_image_param
;
55 * @brief Get the hardware generation of isl_device.
57 * You can define this as a compile-time constant in the CFLAGS. For example,
58 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
60 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
63 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
65 * You can define this as a compile-time constant in the CFLAGS. For example,
66 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
68 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
72 * Hardware enumeration SURFACE_FORMAT.
74 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
75 * Enumerations: SURFACE_FORMAT.
78 ISL_FORMAT_R32G32B32A32_FLOAT
= 0,
79 ISL_FORMAT_R32G32B32A32_SINT
= 1,
80 ISL_FORMAT_R32G32B32A32_UINT
= 2,
81 ISL_FORMAT_R32G32B32A32_UNORM
= 3,
82 ISL_FORMAT_R32G32B32A32_SNORM
= 4,
83 ISL_FORMAT_R64G64_FLOAT
= 5,
84 ISL_FORMAT_R32G32B32X32_FLOAT
= 6,
85 ISL_FORMAT_R32G32B32A32_SSCALED
= 7,
86 ISL_FORMAT_R32G32B32A32_USCALED
= 8,
87 ISL_FORMAT_R32G32B32A32_SFIXED
= 32,
88 ISL_FORMAT_R64G64_PASSTHRU
= 33,
89 ISL_FORMAT_R32G32B32_FLOAT
= 64,
90 ISL_FORMAT_R32G32B32_SINT
= 65,
91 ISL_FORMAT_R32G32B32_UINT
= 66,
92 ISL_FORMAT_R32G32B32_UNORM
= 67,
93 ISL_FORMAT_R32G32B32_SNORM
= 68,
94 ISL_FORMAT_R32G32B32_SSCALED
= 69,
95 ISL_FORMAT_R32G32B32_USCALED
= 70,
96 ISL_FORMAT_R32G32B32_SFIXED
= 80,
97 ISL_FORMAT_R16G16B16A16_UNORM
= 128,
98 ISL_FORMAT_R16G16B16A16_SNORM
= 129,
99 ISL_FORMAT_R16G16B16A16_SINT
= 130,
100 ISL_FORMAT_R16G16B16A16_UINT
= 131,
101 ISL_FORMAT_R16G16B16A16_FLOAT
= 132,
102 ISL_FORMAT_R32G32_FLOAT
= 133,
103 ISL_FORMAT_R32G32_SINT
= 134,
104 ISL_FORMAT_R32G32_UINT
= 135,
105 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
= 136,
106 ISL_FORMAT_X32_TYPELESS_G8X24_UINT
= 137,
107 ISL_FORMAT_L32A32_FLOAT
= 138,
108 ISL_FORMAT_R32G32_UNORM
= 139,
109 ISL_FORMAT_R32G32_SNORM
= 140,
110 ISL_FORMAT_R64_FLOAT
= 141,
111 ISL_FORMAT_R16G16B16X16_UNORM
= 142,
112 ISL_FORMAT_R16G16B16X16_FLOAT
= 143,
113 ISL_FORMAT_A32X32_FLOAT
= 144,
114 ISL_FORMAT_L32X32_FLOAT
= 145,
115 ISL_FORMAT_I32X32_FLOAT
= 146,
116 ISL_FORMAT_R16G16B16A16_SSCALED
= 147,
117 ISL_FORMAT_R16G16B16A16_USCALED
= 148,
118 ISL_FORMAT_R32G32_SSCALED
= 149,
119 ISL_FORMAT_R32G32_USCALED
= 150,
120 ISL_FORMAT_R32G32_SFIXED
= 160,
121 ISL_FORMAT_R64_PASSTHRU
= 161,
122 ISL_FORMAT_B8G8R8A8_UNORM
= 192,
123 ISL_FORMAT_B8G8R8A8_UNORM_SRGB
= 193,
124 ISL_FORMAT_R10G10B10A2_UNORM
= 194,
125 ISL_FORMAT_R10G10B10A2_UNORM_SRGB
= 195,
126 ISL_FORMAT_R10G10B10A2_UINT
= 196,
127 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM
= 197,
128 ISL_FORMAT_R8G8B8A8_UNORM
= 199,
129 ISL_FORMAT_R8G8B8A8_UNORM_SRGB
= 200,
130 ISL_FORMAT_R8G8B8A8_SNORM
= 201,
131 ISL_FORMAT_R8G8B8A8_SINT
= 202,
132 ISL_FORMAT_R8G8B8A8_UINT
= 203,
133 ISL_FORMAT_R16G16_UNORM
= 204,
134 ISL_FORMAT_R16G16_SNORM
= 205,
135 ISL_FORMAT_R16G16_SINT
= 206,
136 ISL_FORMAT_R16G16_UINT
= 207,
137 ISL_FORMAT_R16G16_FLOAT
= 208,
138 ISL_FORMAT_B10G10R10A2_UNORM
= 209,
139 ISL_FORMAT_B10G10R10A2_UNORM_SRGB
= 210,
140 ISL_FORMAT_R11G11B10_FLOAT
= 211,
141 ISL_FORMAT_R32_SINT
= 214,
142 ISL_FORMAT_R32_UINT
= 215,
143 ISL_FORMAT_R32_FLOAT
= 216,
144 ISL_FORMAT_R24_UNORM_X8_TYPELESS
= 217,
145 ISL_FORMAT_X24_TYPELESS_G8_UINT
= 218,
146 ISL_FORMAT_L32_UNORM
= 221,
147 ISL_FORMAT_A32_UNORM
= 222,
148 ISL_FORMAT_L16A16_UNORM
= 223,
149 ISL_FORMAT_I24X8_UNORM
= 224,
150 ISL_FORMAT_L24X8_UNORM
= 225,
151 ISL_FORMAT_A24X8_UNORM
= 226,
152 ISL_FORMAT_I32_FLOAT
= 227,
153 ISL_FORMAT_L32_FLOAT
= 228,
154 ISL_FORMAT_A32_FLOAT
= 229,
155 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM
= 230,
156 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM
= 231,
157 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM
= 232,
158 ISL_FORMAT_B8G8R8X8_UNORM
= 233,
159 ISL_FORMAT_B8G8R8X8_UNORM_SRGB
= 234,
160 ISL_FORMAT_R8G8B8X8_UNORM
= 235,
161 ISL_FORMAT_R8G8B8X8_UNORM_SRGB
= 236,
162 ISL_FORMAT_R9G9B9E5_SHAREDEXP
= 237,
163 ISL_FORMAT_B10G10R10X2_UNORM
= 238,
164 ISL_FORMAT_L16A16_FLOAT
= 240,
165 ISL_FORMAT_R32_UNORM
= 241,
166 ISL_FORMAT_R32_SNORM
= 242,
167 ISL_FORMAT_R10G10B10X2_USCALED
= 243,
168 ISL_FORMAT_R8G8B8A8_SSCALED
= 244,
169 ISL_FORMAT_R8G8B8A8_USCALED
= 245,
170 ISL_FORMAT_R16G16_SSCALED
= 246,
171 ISL_FORMAT_R16G16_USCALED
= 247,
172 ISL_FORMAT_R32_SSCALED
= 248,
173 ISL_FORMAT_R32_USCALED
= 249,
174 ISL_FORMAT_B5G6R5_UNORM
= 256,
175 ISL_FORMAT_B5G6R5_UNORM_SRGB
= 257,
176 ISL_FORMAT_B5G5R5A1_UNORM
= 258,
177 ISL_FORMAT_B5G5R5A1_UNORM_SRGB
= 259,
178 ISL_FORMAT_B4G4R4A4_UNORM
= 260,
179 ISL_FORMAT_B4G4R4A4_UNORM_SRGB
= 261,
180 ISL_FORMAT_R8G8_UNORM
= 262,
181 ISL_FORMAT_R8G8_SNORM
= 263,
182 ISL_FORMAT_R8G8_SINT
= 264,
183 ISL_FORMAT_R8G8_UINT
= 265,
184 ISL_FORMAT_R16_UNORM
= 266,
185 ISL_FORMAT_R16_SNORM
= 267,
186 ISL_FORMAT_R16_SINT
= 268,
187 ISL_FORMAT_R16_UINT
= 269,
188 ISL_FORMAT_R16_FLOAT
= 270,
189 ISL_FORMAT_A8P8_UNORM_PALETTE0
= 271,
190 ISL_FORMAT_A8P8_UNORM_PALETTE1
= 272,
191 ISL_FORMAT_I16_UNORM
= 273,
192 ISL_FORMAT_L16_UNORM
= 274,
193 ISL_FORMAT_A16_UNORM
= 275,
194 ISL_FORMAT_L8A8_UNORM
= 276,
195 ISL_FORMAT_I16_FLOAT
= 277,
196 ISL_FORMAT_L16_FLOAT
= 278,
197 ISL_FORMAT_A16_FLOAT
= 279,
198 ISL_FORMAT_L8A8_UNORM_SRGB
= 280,
199 ISL_FORMAT_R5G5_SNORM_B6_UNORM
= 281,
200 ISL_FORMAT_B5G5R5X1_UNORM
= 282,
201 ISL_FORMAT_B5G5R5X1_UNORM_SRGB
= 283,
202 ISL_FORMAT_R8G8_SSCALED
= 284,
203 ISL_FORMAT_R8G8_USCALED
= 285,
204 ISL_FORMAT_R16_SSCALED
= 286,
205 ISL_FORMAT_R16_USCALED
= 287,
206 ISL_FORMAT_P8A8_UNORM_PALETTE0
= 290,
207 ISL_FORMAT_P8A8_UNORM_PALETTE1
= 291,
208 ISL_FORMAT_A1B5G5R5_UNORM
= 292,
209 ISL_FORMAT_A4B4G4R4_UNORM
= 293,
210 ISL_FORMAT_L8A8_UINT
= 294,
211 ISL_FORMAT_L8A8_SINT
= 295,
212 ISL_FORMAT_R8_UNORM
= 320,
213 ISL_FORMAT_R8_SNORM
= 321,
214 ISL_FORMAT_R8_SINT
= 322,
215 ISL_FORMAT_R8_UINT
= 323,
216 ISL_FORMAT_A8_UNORM
= 324,
217 ISL_FORMAT_I8_UNORM
= 325,
218 ISL_FORMAT_L8_UNORM
= 326,
219 ISL_FORMAT_P4A4_UNORM_PALETTE0
= 327,
220 ISL_FORMAT_A4P4_UNORM_PALETTE0
= 328,
221 ISL_FORMAT_R8_SSCALED
= 329,
222 ISL_FORMAT_R8_USCALED
= 330,
223 ISL_FORMAT_P8_UNORM_PALETTE0
= 331,
224 ISL_FORMAT_L8_UNORM_SRGB
= 332,
225 ISL_FORMAT_P8_UNORM_PALETTE1
= 333,
226 ISL_FORMAT_P4A4_UNORM_PALETTE1
= 334,
227 ISL_FORMAT_A4P4_UNORM_PALETTE1
= 335,
228 ISL_FORMAT_Y8_UNORM
= 336,
229 ISL_FORMAT_L8_UINT
= 338,
230 ISL_FORMAT_L8_SINT
= 339,
231 ISL_FORMAT_I8_UINT
= 340,
232 ISL_FORMAT_I8_SINT
= 341,
233 ISL_FORMAT_DXT1_RGB_SRGB
= 384,
234 ISL_FORMAT_R1_UNORM
= 385,
235 ISL_FORMAT_YCRCB_NORMAL
= 386,
236 ISL_FORMAT_YCRCB_SWAPUVY
= 387,
237 ISL_FORMAT_P2_UNORM_PALETTE0
= 388,
238 ISL_FORMAT_P2_UNORM_PALETTE1
= 389,
239 ISL_FORMAT_BC1_UNORM
= 390,
240 ISL_FORMAT_BC2_UNORM
= 391,
241 ISL_FORMAT_BC3_UNORM
= 392,
242 ISL_FORMAT_BC4_UNORM
= 393,
243 ISL_FORMAT_BC5_UNORM
= 394,
244 ISL_FORMAT_BC1_UNORM_SRGB
= 395,
245 ISL_FORMAT_BC2_UNORM_SRGB
= 396,
246 ISL_FORMAT_BC3_UNORM_SRGB
= 397,
247 ISL_FORMAT_MONO8
= 398,
248 ISL_FORMAT_YCRCB_SWAPUV
= 399,
249 ISL_FORMAT_YCRCB_SWAPY
= 400,
250 ISL_FORMAT_DXT1_RGB
= 401,
251 ISL_FORMAT_FXT1
= 402,
252 ISL_FORMAT_R8G8B8_UNORM
= 403,
253 ISL_FORMAT_R8G8B8_SNORM
= 404,
254 ISL_FORMAT_R8G8B8_SSCALED
= 405,
255 ISL_FORMAT_R8G8B8_USCALED
= 406,
256 ISL_FORMAT_R64G64B64A64_FLOAT
= 407,
257 ISL_FORMAT_R64G64B64_FLOAT
= 408,
258 ISL_FORMAT_BC4_SNORM
= 409,
259 ISL_FORMAT_BC5_SNORM
= 410,
260 ISL_FORMAT_R16G16B16_FLOAT
= 411,
261 ISL_FORMAT_R16G16B16_UNORM
= 412,
262 ISL_FORMAT_R16G16B16_SNORM
= 413,
263 ISL_FORMAT_R16G16B16_SSCALED
= 414,
264 ISL_FORMAT_R16G16B16_USCALED
= 415,
265 ISL_FORMAT_BC6H_SF16
= 417,
266 ISL_FORMAT_BC7_UNORM
= 418,
267 ISL_FORMAT_BC7_UNORM_SRGB
= 419,
268 ISL_FORMAT_BC6H_UF16
= 420,
269 ISL_FORMAT_PLANAR_420_8
= 421,
270 ISL_FORMAT_R8G8B8_UNORM_SRGB
= 424,
271 ISL_FORMAT_ETC1_RGB8
= 425,
272 ISL_FORMAT_ETC2_RGB8
= 426,
273 ISL_FORMAT_EAC_R11
= 427,
274 ISL_FORMAT_EAC_RG11
= 428,
275 ISL_FORMAT_EAC_SIGNED_R11
= 429,
276 ISL_FORMAT_EAC_SIGNED_RG11
= 430,
277 ISL_FORMAT_ETC2_SRGB8
= 431,
278 ISL_FORMAT_R16G16B16_UINT
= 432,
279 ISL_FORMAT_R16G16B16_SINT
= 433,
280 ISL_FORMAT_R32_SFIXED
= 434,
281 ISL_FORMAT_R10G10B10A2_SNORM
= 435,
282 ISL_FORMAT_R10G10B10A2_USCALED
= 436,
283 ISL_FORMAT_R10G10B10A2_SSCALED
= 437,
284 ISL_FORMAT_R10G10B10A2_SINT
= 438,
285 ISL_FORMAT_B10G10R10A2_SNORM
= 439,
286 ISL_FORMAT_B10G10R10A2_USCALED
= 440,
287 ISL_FORMAT_B10G10R10A2_SSCALED
= 441,
288 ISL_FORMAT_B10G10R10A2_UINT
= 442,
289 ISL_FORMAT_B10G10R10A2_SINT
= 443,
290 ISL_FORMAT_R64G64B64A64_PASSTHRU
= 444,
291 ISL_FORMAT_R64G64B64_PASSTHRU
= 445,
292 ISL_FORMAT_ETC2_RGB8_PTA
= 448,
293 ISL_FORMAT_ETC2_SRGB8_PTA
= 449,
294 ISL_FORMAT_ETC2_EAC_RGBA8
= 450,
295 ISL_FORMAT_ETC2_EAC_SRGB8_A8
= 451,
296 ISL_FORMAT_R8G8B8_UINT
= 456,
297 ISL_FORMAT_R8G8B8_SINT
= 457,
298 ISL_FORMAT_RAW
= 511,
300 /* Hardware doesn't understand this out-of-band value */
301 ISL_FORMAT_UNSUPPORTED
= UINT16_MAX
,
305 * Numerical base type for channels of isl_format.
323 * Colorspace of isl_format.
325 enum isl_colorspace
{
326 ISL_COLORSPACE_NONE
= 0,
327 ISL_COLORSPACE_LINEAR
,
333 * Texture compression mode of isl_format.
349 * @brief Hardware tile mode
351 * WARNING: These values differ from the hardware enum values, which are
352 * unstable across hardware generations.
354 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
355 * clearly distinguish it from Yf and Ys.
358 ISL_TILING_LINEAR
= 0,
361 ISL_TILING_Y0
, /**< Legacy Y tiling */
362 ISL_TILING_Yf
, /**< Standard 4K tiling. The 'f' means "four". */
363 ISL_TILING_Ys
, /**< Standard 64K tiling. The 's' means "sixty-four". */
367 * @defgroup Tiling Flags
370 typedef uint32_t isl_tiling_flags_t
;
371 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
372 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
373 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
374 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
375 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
376 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
377 #define ISL_TILING_ANY_MASK (~0u)
378 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
380 /** Any Y tiling, including legacy Y tiling. */
381 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
382 ISL_TILING_Yf_BIT | \
385 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
386 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
391 * @brief Logical dimension of surface.
393 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
394 * as 2D array surfaces.
403 * @brief Physical layout of the surface's dimensions.
405 enum isl_dim_layout
{
407 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
408 * 6.17.3: 2D Surfaces.
410 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
411 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
413 * One-dimensional surfaces are identical to 2D surfaces with height of
416 * @invariant isl_surf::phys_level0_sa::depth == 1
418 ISL_DIM_LAYOUT_GEN4_2D
,
421 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
422 * 6.17.5: 3D Surfaces.
424 * @invariant isl_surf::phys_level0_sa::array_len == 1
426 ISL_DIM_LAYOUT_GEN4_3D
,
429 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
430 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
432 ISL_DIM_LAYOUT_GEN9_1D
,
435 /* TODO(chadv): Explain */
436 enum isl_array_pitch_span
{
437 ISL_ARRAY_PITCH_SPAN_FULL
,
438 ISL_ARRAY_PITCH_SPAN_COMPACT
,
442 * @defgroup Surface Usage
445 typedef uint64_t isl_surf_usage_flags_t
;
446 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
447 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
448 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
449 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
450 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
451 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
452 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
453 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
454 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
455 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
456 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
457 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
461 * @brief Multisample Format
463 enum isl_msaa_layout
{
465 * @brief Suface is single-sampled.
467 ISL_MSAA_LAYOUT_NONE
,
470 * @brief [SNB+] Interleaved Multisample Format
472 * In this format, multiple samples are interleaved into each cacheline.
473 * In other words, the sample index is swizzled into the low 6 bits of the
474 * surface's virtual address space.
476 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
477 * and its pixel format is 32bpp. Then the first cacheline is arranged
480 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
481 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
483 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
484 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
486 * The hardware docs refer to this format with multiple terms. In
487 * Sandybridge, this is the only multisample format; so no term is used.
488 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
489 * Multisample Surface). Later hardware docs additionally refer to this
490 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
493 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
496 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
497 * Multisampled Surfaces".
499 ISL_MSAA_LAYOUT_INTERLEAVED
,
502 * @brief [IVB+] Array Multisample Format
504 * In this format, the surface's physical layout resembles that of a
507 * Suppose the multisample surface's logical extent is (w, h) and its
508 * sample count is N. Then surface's physical extent is the same as
509 * a singlesample 2D surface whose logical extent is (w, h) and array
510 * length is N. Array slice `i` contains the pixel values for sample
513 * The Ivybridge docs refer to surfaces in this format as UMS
514 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
515 * Surface). The Broadwell docs additionally refer to this format as
516 * MSFMT_MSS (MSS=Multisample Surface Storage).
518 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
519 * Multisample Surfaces".
521 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
522 * Multisample Surfaces".
524 ISL_MSAA_LAYOUT_ARRAY
,
529 const struct brw_device_info
*info
;
530 bool use_separate_stencil
;
531 bool has_bit6_swizzling
;
534 struct isl_extent2d
{
535 union { uint32_t w
, width
; };
536 union { uint32_t h
, height
; };
539 struct isl_extent3d
{
540 union { uint32_t w
, width
; };
541 union { uint32_t h
, height
; };
542 union { uint32_t d
, depth
; };
545 struct isl_extent4d
{
546 union { uint32_t w
, width
; };
547 union { uint32_t h
, height
; };
548 union { uint32_t d
, depth
; };
549 union { uint32_t a
, array_len
; };
552 struct isl_channel_layout
{
553 enum isl_base_type type
;
554 uint8_t bits
; /**< Size in bits */
558 * Each format has 3D block extent (width, height, depth). The block extent
559 * of compressed formats is that of the format's compression block. For
560 * example, the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1).
561 * The block extent of uncompressed pixel formats, such as
562 * ISL_FORMAT_R8G8B8A8_UNORM, is is (w=1, h=1, d=1).
564 struct isl_format_layout
{
565 enum isl_format format
;
567 uint8_t bs
; /**< Block size, in bytes, rounded towards 0 */
568 uint8_t bw
; /**< Block width, in pixels */
569 uint8_t bh
; /**< Block height, in pixels */
570 uint8_t bd
; /**< Block depth, in pixels */
573 struct isl_channel_layout r
; /**< Red channel */
574 struct isl_channel_layout g
; /**< Green channel */
575 struct isl_channel_layout b
; /**< Blue channel */
576 struct isl_channel_layout a
; /**< Alpha channel */
577 struct isl_channel_layout l
; /**< Luminance channel */
578 struct isl_channel_layout i
; /**< Intensity channel */
579 struct isl_channel_layout p
; /**< Palette channel */
582 enum isl_colorspace colorspace
;
586 struct isl_tile_info
{
587 enum isl_tiling tiling
;
588 uint32_t width
; /**< in bytes */
589 uint32_t height
; /**< in rows of memory */
590 uint32_t size
; /**< in bytes */
594 * @brief Input to surface initialization
596 * @invariant width >= 1
597 * @invariant height >= 1
598 * @invariant depth >= 1
599 * @invariant levels >= 1
600 * @invariant samples >= 1
601 * @invariant array_len >= 1
603 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
604 * @invariant if 2D then depth == 1
605 * @invariant if 3D then array_len == 1 and samples == 1
607 struct isl_surf_init_info
{
608 enum isl_surf_dim dim
;
609 enum isl_format format
;
618 /** Lower bound for isl_surf::alignment, in bytes. */
619 uint32_t min_alignment
;
621 /** Lower bound for isl_surf::pitch, in bytes. */
624 isl_surf_usage_flags_t usage
;
626 /** Flags that alter how ISL selects isl_surf::tiling. */
627 isl_tiling_flags_t tiling_flags
;
631 enum isl_surf_dim dim
;
632 enum isl_dim_layout dim_layout
;
633 enum isl_msaa_layout msaa_layout
;
634 enum isl_tiling tiling
;
635 enum isl_format format
;
638 * Alignment of the upper-left sample of each subimage, in units of surface
641 struct isl_extent3d image_alignment_el
;
644 * Logical extent of the surface's base level, in units of pixels. This is
645 * identical to the extent defined in isl_surf_init_info.
647 struct isl_extent4d logical_level0_px
;
650 * Physical extent of the surface's base level, in units of physical
651 * surface samples and aligned to the format's compression block.
653 * Consider isl_dim_layout as an operator that transforms a logical surface
654 * layout to a physical surface layout. Then
656 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
657 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
659 struct isl_extent4d phys_level0_sa
;
664 /** Total size of the surface, in bytes. */
667 /** Required alignment for the surface's base address. */
671 * Pitch between vertically adjacent surface elements, in bytes.
676 * Pitch between physical array slices, in rows of surface elements.
678 uint32_t array_pitch_el_rows
;
680 enum isl_array_pitch_span array_pitch_span
;
682 /** Copy of isl_surf_init_info::usage. */
683 isl_surf_usage_flags_t usage
;
686 extern const struct isl_format_layout isl_format_layouts
[];
689 isl_device_init(struct isl_device
*dev
,
690 const struct brw_device_info
*info
,
691 bool has_bit6_swizzling
);
693 static inline const struct isl_format_layout
* ATTRIBUTE_CONST
694 isl_format_get_layout(enum isl_format fmt
)
696 return &isl_format_layouts
[fmt
];
700 isl_format_has_sint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
703 isl_format_is_compressed(enum isl_format fmt
)
705 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
707 return fmtl
->txc
!= ISL_TXC_NONE
;
711 isl_format_has_bc_compression(enum isl_format fmt
)
713 switch (isl_format_get_layout(fmt
)->txc
) {
728 unreachable("bad texture compression mode");
733 isl_format_is_yuv(enum isl_format fmt
)
735 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
737 return fmtl
->colorspace
== ISL_COLORSPACE_YUV
;
741 isl_format_block_is_1x1x1(enum isl_format fmt
)
743 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
745 return fmtl
->bw
== 1 && fmtl
->bh
== 1 && fmtl
->bd
== 1;
749 isl_format_is_rgb(enum isl_format fmt
)
751 return isl_format_layouts
[fmt
].channels
.r
.bits
> 0 &&
752 isl_format_layouts
[fmt
].channels
.g
.bits
> 0 &&
753 isl_format_layouts
[fmt
].channels
.b
.bits
> 0 &&
754 isl_format_layouts
[fmt
].channels
.a
.bits
== 0;
757 enum isl_format
isl_format_rgb_to_rgba(enum isl_format rgb
) ATTRIBUTE_CONST
;
758 enum isl_format
isl_format_rgb_to_rgbx(enum isl_format rgb
) ATTRIBUTE_CONST
;
760 bool isl_is_storage_image_format(enum isl_format fmt
);
763 isl_lower_storage_image_format(const struct isl_device
*dev
,
764 enum isl_format fmt
);
767 isl_tiling_is_std_y(enum isl_tiling tiling
)
769 return (1u << tiling
) & ISL_TILING_STD_Y_MASK
;
773 isl_tiling_get_info(const struct isl_device
*dev
,
774 enum isl_tiling tiling
,
775 uint32_t format_block_size
,
776 struct isl_tile_info
*info
);
779 isl_tiling_get_extent(const struct isl_device
*dev
,
780 enum isl_tiling tiling
,
781 uint32_t format_block_size
,
782 struct isl_extent2d
*e
);
784 isl_surf_choose_tiling(const struct isl_device
*dev
,
785 const struct isl_surf_init_info
*restrict info
,
786 enum isl_tiling
*tiling
);
789 isl_surf_usage_is_display(isl_surf_usage_flags_t usage
)
791 return usage
& ISL_SURF_USAGE_DISPLAY_BIT
;
795 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage
)
797 return usage
& ISL_SURF_USAGE_DEPTH_BIT
;
801 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage
)
803 return usage
& ISL_SURF_USAGE_STENCIL_BIT
;
807 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage
)
809 return (usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
810 (usage
& ISL_SURF_USAGE_STENCIL_BIT
);
814 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage
)
816 return usage
& (ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
);
820 isl_surf_info_is_z16(const struct isl_surf_init_info
*info
)
822 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
823 (info
->format
== ISL_FORMAT_R16_UNORM
);
827 isl_surf_info_is_z32_float(const struct isl_surf_init_info
*info
)
829 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
830 (info
->format
== ISL_FORMAT_R32_FLOAT
);
833 static inline struct isl_extent2d
834 isl_extent2d(uint32_t width
, uint32_t height
)
836 return (struct isl_extent2d
) { .w
= width
, .h
= height
};
839 static inline struct isl_extent3d
840 isl_extent3d(uint32_t width
, uint32_t height
, uint32_t depth
)
842 return (struct isl_extent3d
) { .w
= width
, .h
= height
, .d
= depth
};
845 static inline struct isl_extent4d
846 isl_extent4d(uint32_t width
, uint32_t height
, uint32_t depth
,
849 return (struct isl_extent4d
) {
857 #define isl_surf_init(dev, surf, ...) \
858 isl_surf_init_s((dev), (surf), \
859 &(struct isl_surf_init_info) { __VA_ARGS__ });
862 isl_surf_init_s(const struct isl_device
*dev
,
863 struct isl_surf
*surf
,
864 const struct isl_surf_init_info
*restrict info
);
867 * Alignment of the upper-left sample of each subimage, in units of surface
870 static inline struct isl_extent3d
871 isl_surf_get_image_alignment_el(const struct isl_surf
*surf
)
873 return surf
->image_alignment_el
;
877 * Alignment of the upper-left sample of each subimage, in units of surface
880 static inline struct isl_extent3d
881 isl_surf_get_image_alignment_sa(const struct isl_surf
*surf
)
883 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
885 return (struct isl_extent3d
) {
886 .w
= fmtl
->bw
* surf
->image_alignment_el
.w
,
887 .h
= fmtl
->bh
* surf
->image_alignment_el
.h
,
888 .d
= fmtl
->bd
* surf
->image_alignment_el
.d
,
893 * Pitch between vertically adjacent surface elements, in bytes.
895 static inline uint32_t
896 isl_surf_get_row_pitch(const struct isl_surf
*surf
)
898 return surf
->row_pitch
;
902 * Pitch between vertically adjacent surface elements, in units of surface elements.
904 static inline uint32_t
905 isl_surf_get_row_pitch_el(const struct isl_surf
*surf
)
907 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
909 assert(surf
->row_pitch
% fmtl
->bs
== 0);
910 return surf
->row_pitch
/ fmtl
->bs
;
914 * Pitch between physical array slices, in rows of surface elements.
916 static inline uint32_t
917 isl_surf_get_array_pitch_el_rows(const struct isl_surf
*surf
)
919 return surf
->array_pitch_el_rows
;
923 * Pitch between physical array slices, in units of surface elements.
925 static inline uint32_t
926 isl_surf_get_array_pitch_el(const struct isl_surf
*surf
)
928 return isl_surf_get_array_pitch_el_rows(surf
) *
929 isl_surf_get_row_pitch_el(surf
);
933 * Pitch between physical array slices, in rows of surface samples.
935 static inline uint32_t
936 isl_surf_get_array_pitch_sa_rows(const struct isl_surf
*surf
)
938 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
939 return fmtl
->bh
* isl_surf_get_array_pitch_el_rows(surf
);
943 * Pitch between physical array slices, in bytes.
945 static inline uint32_t
946 isl_surf_get_array_pitch(const struct isl_surf
*surf
)
948 return isl_surf_get_array_pitch_sa_rows(surf
) * surf
->row_pitch
;
952 * Get the offset to an subimage within the surface, in units of surface
955 * @invariant level < surface levels
956 * @invariant logical_array_layer < logical array length of surface
957 * @invariant logical_z_offset_px < logical depth of surface at level
960 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
962 uint32_t logical_array_layer
,
963 uint32_t logical_z_offset_px
,
964 uint32_t *x_offset_sa
,
965 uint32_t *y_offset_sa
);