Merge zizzer.eecs.umich.edu:/bk/newmem
[gem5.git] / src / kern / system_events.cc
1 /*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Lisa Hsu
29 * Nathan Binkert
30 */
31
32 #include "cpu/base.hh"
33 #include "cpu/thread_context.hh"
34 #include "kern/kernel_stats.hh"
35 #include "kern/system_events.hh"
36 #include "sim/system.hh"
37
38 using namespace TheISA;
39
40 void
41 SkipFuncEvent::process(ThreadContext *tc)
42 {
43 Addr newpc = tc->readIntReg(ReturnAddressReg);
44
45 DPRINTF(PCEvent, "skipping %s: pc=%x, newpc=%x\n", description,
46 tc->readPC(), newpc);
47
48 tc->setPC(newpc);
49 tc->setNextPC(tc->readPC() + sizeof(TheISA::MachInst));
50 /*
51 BranchPred *bp = tc->getCpuPtr()->getBranchPred();
52 if (bp != NULL) {
53 bp->popRAS(tc->getThreadNum());
54 }
55 */
56 }
57
58 void
59 IdleStartEvent::process(ThreadContext *tc)
60 {
61 if (tc->getKernelStats())
62 tc->getKernelStats()->setIdleProcess(
63 tc->readMiscReg(AlphaISA::IPR_PALtemp23), tc);
64 remove();
65 }