src/learning_gem5/part2/SimpleCache.py

   1 # -*- coding: utf-8 -*-
   2 # Copyright (c) 2017 Jason Lowe-Power
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
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   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
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  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27
  28 from m5.params import *
  29 from m5.proxy import *
  30 from m5.objects.ClockedObject import ClockedObject
  31
  32 class SimpleCache(ClockedObject):
  33     type = 'SimpleCache'
  34     cxx_header = "learning_gem5/part2/simple_cache.hh"
  35
  36     # Vector port example. Both the instruction and data ports connect to this
  37     # port which is automatically split out into two ports.
  38     cpu_side = VectorSlavePort("CPU side port, receives requests")
  39     mem_side = RequestPort("Memory side port, sends requests")
  40
  41     latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss")
  42
  43     size = Param.MemorySize('16kB', "The size of the cache")
  44
  45     system = Param.System(Parent.any, "The system this cache is part of")