2 /*=== Project imports ==*/
4 /*======================*/
5 // =========================== Clock divider module ================ //
6 interface Ifc_ClockDiv#(numeric type width);
7 interface Clock slowclock;
8 method Action divisor(Bit#(width) in);
11 module mkClockDiv(Ifc_ClockDiv#(width));
12 let defclock <- exposeCurrentClock;
13 Reg#(Bit#(1)) clk <- mkReg(0);
14 Reg#(Bit#(width)) rg_divisor <- mkReg(0);
15 Reg#(Bit#(width)) rg_counter <- mkReg(0);
16 MakeClockIfc#(Bit#(1)) new_clock <- mkUngatedClock(0);
17 MuxClkIfc clock_selector <- mkUngatedClockMux(new_clock.new_clk,defclock);
18 Bool clockmux_sel = rg_divisor!=0;
19 rule increment_counter;
20 if(rg_divisor!=0 && rg_counter >= rg_divisor)begin
25 rg_counter <= rg_counter + 1;
29 new_clock.setClockValue(clk);
33 clock_selector.select(clockmux_sel);
36 method Action divisor(Bit#(width) in);
37 rg_divisor <= in != 0 ? in - 1 : 0;
40 interface slowclock=clock_selector.clock_out;
42 // ============================================================== //