1 // See LICENSE for license details.
2 package sifive.blocks.devices.i2c
5 import freechips.rocketchip.config.Field
6 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
7 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
9 case object PeripheryI2CKey extends Field[Seq[I2CParams]]
11 trait HasPeripheryI2C extends HasPeripheryBus {
12 val i2cParams = p(PeripheryI2CKey)
13 val i2c = i2cParams map { params =>
14 val i2c = LazyModule(new TLI2C(pbus.beatBytes, params))
15 i2c.node := pbus.toVariableWidthSlaves
16 ibus.fromSync := i2c.intnode
21 trait HasPeripheryI2CBundle {
25 trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {
26 val outer: HasPeripheryI2C
27 val i2c = IO(Vec(outer.i2cParams.size, new I2CPort))
29 (i2c zip outer.i2c).foreach { case (io, device) =>
30 io <> device.module.io.port