1 // See LICENSE for license details.
2 package sifive.blocks.devices.mockaon
5 import Chisel.ImplicitConversions._
6 import util.AsyncResetReg
8 import sifive.blocks.util.{SlaveRegIF, GenericTimer}
10 object WatchdogTimer {
11 def writeAnyExceptKey(regs: Bundle, keyReg: SlaveRegIF): Bool = {
12 regs.elements.values.filter(_ ne keyReg).map({
13 case v: Vec[SlaveRegIF] @unchecked => v.map(_.write.valid).reduce(_||_)
14 case s: SlaveRegIF => s.write.valid
21 class WatchdogTimer extends GenericTimer {
22 protected def countWidth = 31
23 protected def cmpWidth = 16
24 protected def ncmp = 1
25 protected lazy val countAlways = AsyncResetReg(io.regs.cfg.write.bits(12), io.regs.cfg.write.valid && unlocked)(0)
26 override protected lazy val countAwake = AsyncResetReg(io.regs.cfg.write.bits(13), io.regs.cfg.write.valid && unlocked)(0)
27 protected lazy val countEn = {
28 val corerstSynchronized = Reg(next = Reg(next = io.corerst))
29 countAlways || (countAwake && !corerstSynchronized)
31 override protected lazy val rsten = AsyncResetReg(io.regs.cfg.write.bits(8), io.regs.cfg.write.valid && unlocked)(0)
32 protected lazy val ip = RegEnable(io.regs.cfg.write.bits(28) || elapsed(0), (io.regs.cfg.write.valid && unlocked) || elapsed(0))
33 override protected lazy val unlocked = {
34 val writeAny = WatchdogTimer.writeAnyExceptKey(io.regs, io.regs.key)
35 AsyncResetReg(io.regs.key.write.bits === WatchdogTimer.key && !writeAny, io.regs.key.write.valid || writeAny)(0)
37 protected lazy val feed = {
39 unlocked && io.regs.feed.write.valid && io.regs.feed.write.bits === food
41 lazy val io = new GenericTimerIO {
42 val corerst = Bool(INPUT)
43 val rst = Bool(OUTPUT)
45 io.rst := AsyncResetReg(Bool(true), rsten && elapsed(0))
48 class RTC extends GenericTimer {
49 protected def countWidth = 48
50 protected def cmpWidth = 32
51 protected def ncmp = 1
52 protected def countEn = countAlways
53 override protected lazy val ip = Reg(next = elapsed(0))
54 override protected lazy val zerocmp = Bool(false)
55 protected lazy val countAlways = AsyncResetReg(io.regs.cfg.write.bits(12), io.regs.cfg.write.valid && unlocked)(0)
56 protected lazy val feed = Bool(false)
57 lazy val io = new GenericTimerIO