1 // See LICENSE for license details.
2 package sifive.blocks.devices.spi
5 import freechips.rocketchip.config.Field
6 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
7 import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp,BufferParams}
8 import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer}
9 import freechips.rocketchip.util.HeterogeneousBag
11 case object PeripherySPIKey extends Field[Seq[SPIParams]]
13 trait HasPeripherySPI extends HasPeripheryBus with HasInterruptBus {
14 val spiParams = p(PeripherySPIKey)
15 val spis = spiParams map { params =>
16 val spi = LazyModule(new TLSPI(pbus.beatBytes, params))
17 spi.rnode := pbus.toVariableWidthSlaves
18 ibus.fromSync := spi.intnode
23 trait HasPeripherySPIBundle {
24 val spi: HeterogeneousBag[SPIPortIO]
28 trait HasPeripherySPIModuleImp extends LazyModuleImp with HasPeripherySPIBundle {
29 val outer: HasPeripherySPI
30 val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
32 (spi zip outer.spis).foreach { case (io, device) =>
33 io <> device.module.io.port
37 case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
39 trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
40 val spiFlashParams = p(PeripherySPIFlashKey)
41 val qspis = spiFlashParams map { params =>
42 val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
43 qspi.rnode := pbus.toVariableWidthSlaves
45 := TLFragmenter(1, pbus.blockBytes)
46 := TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)
47 := pbus.toFixedWidthSlaves)
48 ibus.fromSync := qspi.intnode
53 trait HasPeripherySPIFlashBundle {
54 val qspi: HeterogeneousBag[SPIPortIO]
58 trait HasPeripherySPIFlashModuleImp extends LazyModuleImp with HasPeripherySPIFlashBundle {
59 val outer: HasPeripherySPIFlash
60 val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
62 (qspi zip outer.qspis) foreach { case (io, device) =>
63 io <> device.module.io.port