1 // See LICENSE for license details.
2 package sifive.blocks.devices.spi
5 import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
7 class SPIPinsIO(c: SPIConfigBase) extends SPIBundle(c) {
9 val dq = Vec(4, new GPIOPin)
10 val cs = Vec(c.csWidth, new GPIOPin)
13 class SPIGPIOPort(c: SPIConfigBase, syncStages: Int = 0, driveStrength: Bool = Bool(false)) extends Module {
14 val io = new SPIBundle(c) {
15 val spi = new SPIPortIO(c).flip
16 val pins = new SPIPinsIO(c)
19 GPIOOutputPinCtrl(io.pins.sck, io.spi.sck, ds = driveStrength)
21 GPIOOutputPinCtrl(io.pins.dq, Bits(0, io.spi.dq.size))
22 (io.pins.dq zip io.spi.dq).foreach {
28 p.o.ds := driveStrength
29 s.i := ShiftRegister(p.i.ival, syncStages)
32 GPIOOutputPinCtrl(io.pins.cs, io.spi.cs.asUInt)
33 io.pins.cs.foreach(_.o.ds := driveStrength)