src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala

   1 // See LICENSE for license details.
   2 package sifive.freedom.unleashed.u500vc707devkit
   3
   4 import Chisel._
   5 import chisel3.experimental.{withClockAndReset}
   6
   7 import freechips.rocketchip.config._
   8 import freechips.rocketchip.diplomacy._
   9
  10 import sifive.blocks.devices.gpio._
  11 import sifive.blocks.devices.pinctrl.{BasePin}
  12
  13 import sifive.fpgashells.shell.xilinx.vc707shell._
  14 import sifive.fpgashells.ip.xilinx.{IOBUF}
  15
  16 //-------------------------------------------------------------------------
  17 // PinGen
  18 //-------------------------------------------------------------------------
  19
  20 object PinGen {
  21   def apply(): BasePin = {
  22     new BasePin()
  23   }
  24 }
  25
  26 //-------------------------------------------------------------------------
  27 // U500VC707DevKitFPGAChip
  28 //-------------------------------------------------------------------------
  29
  30 class U500VC707DevKitFPGAChip(implicit override val p: Parameters)
  31     extends VC707Shell
  32     with HasPCIe
  33     with HasDDR3 {
  34
  35   //-----------------------------------------------------------------------
  36   // DUT
  37   //-----------------------------------------------------------------------
  38
  39   // Connect the clock to the 50 Mhz output from the PLL
  40   dut_clock := clk50
  41   withClockAndReset(dut_clock, dut_reset) {
  42     val dut = Module(LazyModule(new U500VC707DevKitSystem).module)
  43
  44     //---------------------------------------------------------------------
  45     // Connect peripherals
  46     //---------------------------------------------------------------------
  47
  48     connectDebugJTAG(dut)
  49     connectSPI      (dut)
  50     connectUART     (dut)
  51     connectPCIe     (dut)
  52     connectMIG      (dut)
  53
  54     //---------------------------------------------------------------------
  55     // GPIO
  56     //---------------------------------------------------------------------
  57
  58     val gpioParams = p(PeripheryGPIOKey)
  59     val gpio_pins = Wire(new GPIOPins(() => PinGen(), gpioParams(0)))
  60
  61     GPIOPinsFromPort(gpio_pins, dut.gpio(0))
  62
  63     gpio_pins.pins.foreach { _.i.ival := Bool(false) }
  64     gpio_pins.pins.zipWithIndex.foreach {
  65       case(pin, idx) => led(idx) := pin.o.oval
  66     }
  67
  68     // tie to zero
  69     for( idx <- 7 to 4 ) { led(idx) := false.B }
  70   }
  71
  72 }