src/mem/Bus.py

   1 # Copyright (c) 2012 ARM Limited
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  13 # Copyright (c) 2005-2008 The Regents of The University of Michigan
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  38 #
  39 # Authors: Nathan Binkert
  40 #          Andreas Hansson
  41
  42 from MemObject import MemObject
  43 from m5.params import *
  44
  45 class BaseBus(MemObject):
  46     type = 'BaseBus'
  47     abstract = True
  48     slave = VectorSlavePort("vector port for connecting masters")
  49     master = VectorMasterPort("vector port for connecting slaves")
  50     clock = Param.Clock("1GHz", "bus clock speed")
  51     header_cycles = Param.Int(1, "cycles of overhead per transaction")
  52     width = Param.Int(64, "bus width (bytes)")
  53     block_size = Param.Int(64, "The default block size if not set by " \
  54                                "any connected module")
  55
  56     # The default port can be left unconnected, or be used to connect
  57     # a default slave port
  58     default = MasterPort("Port for connecting an optional default slave")
  59
  60     # The default port can be used unconditionally, or based on
  61     # address range, in which case it may overlap with other
  62     # ports. The default range is always checked first, thus creating
  63     # a two-level hierarchical lookup. This is useful e.g. for the PCI
  64     # bus configuration.
  65     use_default_range = Param.Bool(False, "Perform address mapping for " \
  66                                        "the default port")
  67
  68 class NoncoherentBus(BaseBus):
  69     type = 'NoncoherentBus'
  70
  71 class CoherentBus(BaseBus):
  72     type = 'CoherentBus'