1 # Copyright (c) 2012 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Thomas Grass
39 from m5
.params
import *
40 from m5
.proxy
import *
41 from m5
.objects
.MemObject
import MemObject
42 from m5
.objects
.System
import System
44 # The communication monitor will most typically be used in combination
45 # with periodic dumping and resetting of stats using schedStatEvent
46 class CommMonitor(MemObject
):
48 cxx_header
= "mem/comm_monitor.hh"
50 system
= Param
.System(Parent
.any
, "System that the monitor belongs to.")
52 # one port in each direction
53 master
= MasterPort("Master port")
54 slave
= SlavePort("Slave port")
56 # control the sample period window length of this monitor
57 sample_period
= Param
.Clock("1ms", "Sample period for histograms")
59 # for each histogram, set the number of bins and enable the user
60 # to disable the measurement, reads and writes use the same
63 # histogram of burst length of packets (not using sample period)
64 burst_length_bins
= Param
.Unsigned('20', "# bins in burst length " \
66 disable_burst_length_hists
= Param
.Bool(False, "Disable burst length " \
69 # bandwidth per sample period
70 bandwidth_bins
= Param
.Unsigned('20', "# bins in bandwidth histograms")
71 disable_bandwidth_hists
= Param
.Bool(False, "Disable bandwidth histograms")
73 # latency from request to response (not using sample period)
74 latency_bins
= Param
.Unsigned('20', "# bins in latency histograms")
75 disable_latency_hists
= Param
.Bool(False, "Disable latency histograms")
77 # inter transaction time (ITT) distributions in uniformly sized
78 # bins up to the maximum, independently for read-to-read,
79 # write-to-write and the combined request-to-request that does not
80 # separate read and write requests
81 itt_bins
= Param
.Unsigned('20', "# bins in ITT distributions")
82 itt_max_bin
= Param
.Latency('100ns', "Max bin of ITT distributions")
83 disable_itt_dists
= Param
.Bool(False, "Disable ITT distributions")
85 # outstanding requests (that did not yet get a response) per
87 outstanding_bins
= Param
.Unsigned('20', "# bins in outstanding " \
88 "requests histograms")
89 disable_outstanding_hists
= Param
.Bool(False, "Disable outstanding " \
90 "requests histograms")
92 # transactions (requests) observed per sample period
93 transaction_bins
= Param
.Unsigned('20', "# bins in transaction " \
95 disable_transaction_hists
= Param
.Bool(False, "Disable transaction count " \
98 # address distributions (heatmaps) with associated address masks
99 # to selectively only look at certain bits of the address
100 read_addr_mask
= Param
.Addr(MaxAddr
, "Address mask for read address")
101 write_addr_mask
= Param
.Addr(MaxAddr
, "Address mask for write address")
102 disable_addr_dists
= Param
.Bool(True, "Disable address distributions")