src/mem/DRAMCtrl.py

   1 # Copyright (c) 2012-2020 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2013 Amin Farmahini-Farahani
  14 # Copyright (c) 2015 University of Kaiserslautern
  15 # Copyright (c) 2015 The University of Bologna
  16 # All rights reserved.
  17 #
  18 # Redistribution and use in source and binary forms, with or without
  19 # modification, are permitted provided that the following conditions are
  20 # met: redistributions of source code must retain the above copyright
  21 # notice, this list of conditions and the following disclaimer;
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  23 # notice, this list of conditions and the following disclaimer in the
  24 # documentation and/or other materials provided with the distribution;
  25 # neither the name of the copyright holders nor the names of its
  26 # contributors may be used to endorse or promote products derived from
  27 # this software without specific prior written permission.
  28 #
  29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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  35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40
  41 from m5.params import *
  42 from m5.proxy import *
  43 from m5.objects.AbstractMemory import *
  44 from m5.objects.QoSMemCtrl import *
  45
  46 # Enum for memory scheduling algorithms, currently First-Come
  47 # First-Served and a First-Row Hit then First-Come First-Served
  48 class MemSched(Enum): vals = ['fcfs', 'frfcfs']
  49
  50 # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
  51 # channel, rank, bank, row and column, respectively, and going from
  52 # MSB to LSB.  Available are RoRaBaChCo and RoRaBaCoCh, that are
  53 # suitable for an open-page policy, optimising for sequential accesses
  54 # hitting in the open row. For a closed-page policy, RoCoRaBaCh
  55 # maximises parallelism.
  56 class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
  57
  58 # Enum for the page policy, either open, open_adaptive, close, or
  59 # close_adaptive.
  60 class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
  61                                 'close_adaptive']
  62
  63 # DRAMCtrl is a single-channel single-ported DRAM controller model
  64 # that aims to model the most important system-level performance
  65 # effects of a DRAM without getting into too much detail of the DRAM
  66 # itself.
  67 class DRAMCtrl(QoSMemCtrl):
  68     type = 'DRAMCtrl'
  69     cxx_header = "mem/dram_ctrl.hh"
  70
  71     # single-ported on the system interface side, instantiate with a
  72     # bus in front of the controller for multiple ports
  73     port = SlavePort("Slave port")
  74
  75     # the basic configuration of the controller architecture, note
  76     # that each entry corresponds to a burst for the specific DRAM
  77     # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
  78     # the cacheline size or request/packet size
  79     write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
  80     read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
  81
  82     # threshold in percent for when to forcefully trigger writes and
  83     # start emptying the write buffer
  84     write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
  85
  86     # threshold in percentage for when to start writes if the read
  87     # queue is empty
  88     write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
  89
  90     # minimum write bursts to schedule before switching back to reads
  91     min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
  92                                            "switching to reads")
  93
  94     # scheduler, address map and page policy
  95     mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
  96     addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
  97     page_policy = Param.PageManage('open_adaptive', "Page management policy")
  98
  99     # enforce a limit on the number of accesses per row
 100     max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
 101                                           "closing");
 102
 103     # size of DRAM Chip in Bytes
 104     device_size = Param.MemorySize("Size of DRAM chip")
 105
 106     # pipeline latency of the controller and PHY, split into a
 107     # frontend part and a backend part, with reads and writes serviced
 108     # by the queues only seeing the frontend contribution, and reads
 109     # serviced by the memory seeing the sum of the two
 110     static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
 111     static_backend_latency = Param.Latency("10ns", "Static backend latency")
 112
 113     # the physical organisation of the DRAM
 114     device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
 115                                       "device/chip")
 116     burst_length = Param.Unsigned("Burst lenght (BL) in beats")
 117     device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
 118                                            "device/chip")
 119     devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
 120     ranks_per_channel = Param.Unsigned("Number of ranks per channel")
 121
 122     # default to 0 bank groups per rank, indicating bank group architecture
 123     # is not used
 124     # update per memory class when bank group architecture is supported
 125     bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
 126     banks_per_rank = Param.Unsigned("Number of banks per rank")
 127
 128     # Enable DRAM powerdown states if True. This is False by default due to
 129     # performance being lower when enabled
 130     enable_dram_powerdown = Param.Bool(False, "Enable powerdown states")
 131
 132     # For power modelling we need to know if the DRAM has a DLL or not
 133     dll = Param.Bool(True, "DRAM has DLL or not")
 134
 135     # DRAMPower provides in addition to the core power, the possibility to
 136     # include RD/WR termination and IO power. This calculation assumes some
 137     # default values. The integration of DRAMPower with gem5 does not include
 138     # IO and RD/WR termination power by default. This might be added as an
 139     # additional feature in the future.
 140
 141     # timing behaviour and constraints - all in nanoseconds
 142
 143     # the base clock period of the DRAM
 144     tCK = Param.Latency("Clock period")
 145
 146     # the amount of time in nanoseconds from issuing an activate command
 147     # to the data being available in the row buffer for a read/write
 148     tRCD = Param.Latency("RAS to CAS delay")
 149
 150     # the time from issuing a read/write command to seeing the actual data
 151     tCL = Param.Latency("CAS latency")
 152
 153     # minimum time between a precharge and subsequent activate
 154     tRP = Param.Latency("Row precharge time")
 155
 156     # minimum time between an activate and a precharge to the same row
 157     tRAS = Param.Latency("ACT to PRE delay")
 158
 159     # minimum time between a write data transfer and a precharge
 160     tWR = Param.Latency("Write recovery time")
 161
 162     # minimum time between a read and precharge command
 163     tRTP = Param.Latency("Read to precharge")
 164
 165     # time to complete a burst transfer, typically the burst length
 166     # divided by two due to the DDR bus, but by making it a parameter
 167     # it is easier to also evaluate SDR memories like WideIO.
 168     # This parameter has to account for burst length.
 169     # Read/Write requests with data size larger than one full burst are broken
 170     # down into multiple requests in the controller
 171     # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
 172     # With bank group architectures, tBURST represents the CAS-to-CAS
 173     # delay for bursts to different bank groups (tCCD_S)
 174     tBURST = Param.Latency("Burst duration "
 175                            "(typically burst length / 2 cycles)")
 176
 177     # tBURST_MAX is the column array cycle delay required before next access,
 178     # which could be greater than tBURST when the memory access time is greater
 179     # than tBURST
 180     tBURST_MAX = Param.Latency(Self.tBURST, "Column access delay")
 181
 182     # tBURST_MIN is the minimum delay between bursts, which could be less than
 183     # tBURST when interleaving is supported
 184     tBURST_MIN = Param.Latency(Self.tBURST, "Minimim delay between bursts")
 185
 186     # CAS-to-CAS delay for bursts to the same bank group
 187     # only utilized with bank group architectures; set to 0 for default case
 188     # tBURST is equivalent to tCCD_S; no explicit parameter required
 189     # for CAS-to-CAS delay for bursts to different bank groups
 190     tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
 191
 192     # Write-to-Write delay for bursts to the same bank group
 193     # only utilized with bank group architectures; set to 0 for default case
 194     # This will be used to enable different same bank group delays
 195     # for writes versus reads
 196     tCCD_L_WR = Param.Latency(Self.tCCD_L,
 197         "Same bank group Write to Write delay")
 198
 199     # time taken to complete one refresh cycle (N rows in all banks)
 200     tRFC = Param.Latency("Refresh cycle time")
 201
 202     # refresh command interval, how often a "ref" command needs
 203     # to be sent. It is 7.8 us for a 64ms refresh requirement
 204     tREFI = Param.Latency("Refresh command interval")
 205
 206     # write-to-read, same rank turnaround penalty
 207     tWTR = Param.Latency("Write to read, same rank switching time")
 208
 209     # write-to-read, same rank turnaround penalty for same bank group
 210     tWTR_L = Param.Latency(Self.tWTR, "Write to read, same rank switching "
 211                            "time, same bank group")
 212
 213     # read-to-write, same rank turnaround penalty
 214     tRTW = Param.Latency("Read to write, same rank switching time")
 215
 216     # rank-to-rank bus delay penalty
 217     # this does not correlate to a memory timing parameter and encompasses:
 218     # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
 219     # different rank bus delay
 220     tCS = Param.Latency("Rank to rank switching time")
 221
 222     # minimum precharge to precharge delay time
 223     tPPD = Param.Latency("0ns", "PRE to PRE delay")
 224
 225     # maximum delay between two-cycle ACT command phases
 226     tAAD = Param.Latency(Self.tCK,
 227                          "Maximum delay between two-cycle ACT commands")
 228
 229     two_cycle_activate = Param.Bool(False,
 230                          "Two cycles required to send activate")
 231
 232     # minimum row activate to row activate delay time
 233     tRRD = Param.Latency("ACT to ACT delay")
 234
 235     # only utilized with bank group architectures; set to 0 for default case
 236     tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
 237
 238     # time window in which a maximum number of activates are allowed
 239     # to take place, set to 0 to disable
 240     tXAW = Param.Latency("X activation window")
 241     activation_limit = Param.Unsigned("Max number of activates in window")
 242
 243     # time to exit power-down mode
 244     # Exit power-down to next valid command delay
 245     tXP = Param.Latency("0ns", "Power-up Delay")
 246
 247     # Exit Powerdown to commands requiring a locked DLL
 248     tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
 249
 250     # time to exit self-refresh mode
 251     tXS = Param.Latency("0ns", "Self-refresh exit latency")
 252
 253     # time to exit self-refresh mode with locked DLL
 254     tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
 255
 256     # number of data beats per clock. with DDR, default is 2, one per edge
 257     beats_per_clock = Param.Unsigned(2, "Data beats per clock")
 258
 259     data_clock_sync = Param.Bool(False, "Synchronization commands required")
 260
 261     # Currently rolled into other params
 262     ######################################################################
 263
 264     # tRC  - assumed to be tRAS + tRP
 265
 266     # Power Behaviour and Constraints
 267     # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
 268     # defined as VDD and VDD2. Each current is defined for each voltage domain
 269     # separately. For example, current IDD0 is active-precharge current for
 270     # voltage domain VDD and current IDD02 is active-precharge current for
 271     # voltage domain VDD2.
 272     # By default all currents are set to 0mA. Users who are only interested in
 273     # the performance of DRAMs can leave them at 0.
 274
 275     # Operating 1 Bank Active-Precharge current
 276     IDD0 = Param.Current("0mA", "Active precharge current")
 277
 278     # Operating 1 Bank Active-Precharge current multiple voltage Range
 279     IDD02 = Param.Current("0mA", "Active precharge current VDD2")
 280
 281     # Precharge Power-down Current: Slow exit
 282     IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
 283
 284     # Precharge Power-down Current: Slow exit multiple voltage Range
 285     IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
 286
 287     # Precharge Power-down Current: Fast exit
 288     IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
 289
 290     # Precharge Power-down Current: Fast exit multiple voltage Range
 291     IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
 292
 293     # Precharge Standby current
 294     IDD2N = Param.Current("0mA", "Precharge Standby current")
 295
 296     # Precharge Standby current multiple voltage range
 297     IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
 298
 299     # Active Power-down current: slow exit
 300     IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
 301
 302     # Active Power-down current: slow exit multiple voltage range
 303     IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
 304
 305     # Active Power-down current : fast exit
 306     IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
 307
 308     # Active Power-down current : fast exit multiple voltage range
 309     IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
 310
 311     # Active Standby current
 312     IDD3N = Param.Current("0mA", "Active Standby current")
 313
 314     # Active Standby current multiple voltage range
 315     IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
 316
 317     # Burst Read Operating Current
 318     IDD4R = Param.Current("0mA", "READ current")
 319
 320     # Burst Read Operating Current multiple voltage range
 321     IDD4R2 = Param.Current("0mA", "READ current VDD2")
 322
 323     # Burst Write Operating Current
 324     IDD4W = Param.Current("0mA", "WRITE current")
 325
 326     # Burst Write Operating Current multiple voltage range
 327     IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
 328
 329     # Refresh Current
 330     IDD5 = Param.Current("0mA", "Refresh current")
 331
 332     # Refresh Current multiple voltage range
 333     IDD52 = Param.Current("0mA", "Refresh current VDD2")
 334
 335     # Self-Refresh Current
 336     IDD6 = Param.Current("0mA", "Self-refresh Current")
 337
 338     # Self-Refresh Current multiple voltage range
 339     IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
 340
 341     # Main voltage range of the DRAM
 342     VDD = Param.Voltage("0V", "Main Voltage Range")
 343
 344     # Second voltage range defined by some DRAMs
 345     VDD2 = Param.Voltage("0V", "2nd Voltage Range")
 346
 347 # A single DDR3-1600 x64 channel (one command and address bus), with
 348 # timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
 349 # an 8x8 configuration.
 350 class DDR3_1600_8x8(DRAMCtrl):
 351     # size of device in bytes
 352     device_size = '512MB'
 353
 354     # 8x8 configuration, 8 devices each with an 8-bit interface
 355     device_bus_width = 8
 356
 357     # DDR3 is a BL8 device
 358     burst_length = 8
 359
 360     # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
 361     device_rowbuffer_size = '1kB'
 362
 363     # 8x8 configuration, so 8 devices
 364     devices_per_rank = 8
 365
 366     # Use two ranks
 367     ranks_per_channel = 2
 368
 369     # DDR3 has 8 banks in all configurations
 370     banks_per_rank = 8
 371
 372     # 800 MHz
 373     tCK = '1.25ns'
 374
 375     # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
 376     tBURST = '5ns'
 377
 378     # DDR3-1600 11-11-11
 379     tRCD = '13.75ns'
 380     tCL = '13.75ns'
 381     tRP = '13.75ns'
 382     tRAS = '35ns'
 383     tRRD = '6ns'
 384     tXAW = '30ns'
 385     activation_limit = 4
 386     tRFC = '260ns'
 387
 388     tWR = '15ns'
 389
 390     # Greater of 4 CK or 7.5 ns
 391     tWTR = '7.5ns'
 392
 393     # Greater of 4 CK or 7.5 ns
 394     tRTP = '7.5ns'
 395
 396     # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
 397     tRTW = '2.5ns'
 398
 399     # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
 400     tCS = '2.5ns'
 401
 402     # <=85C, half for >85C
 403     tREFI = '7.8us'
 404
 405     # active powerdown and precharge powerdown exit time
 406     tXP = '6ns'
 407
 408     # self refresh exit time
 409     tXS = '270ns'
 410
 411     # Current values from datasheet Die Rev E,J
 412     IDD0 = '55mA'
 413     IDD2N = '32mA'
 414     IDD3N = '38mA'
 415     IDD4W = '125mA'
 416     IDD4R = '157mA'
 417     IDD5 = '235mA'
 418     IDD3P1 = '38mA'
 419     IDD2P1 = '32mA'
 420     IDD6 = '20mA'
 421     VDD = '1.5V'
 422
 423 # A single HMC-2500 x32 model based on:
 424 # [1] DRAMSpec: a high-level DRAM bank modelling tool
 425 # developed at the University of Kaiserslautern. This high level tool
 426 # uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
 427 # estimate the DRAM bank latency and power numbers.
 428 # [2] High performance AXI-4.0 based interconnect for extensible smart memory
 429 # cubes (E. Azarkhish et. al)
 430 # Assumed for the HMC model is a 30 nm technology node.
 431 # The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
 432 # layers).
 433 # Each layer has 16 vaults and each vault consists of 2 banks per layer.
 434 # In order to be able to use the same controller used for 2D DRAM generations
 435 # for HMC, the following analogy is done:
 436 # Channel (DDR) => Vault (HMC)
 437 # device_size (DDR) => size of a single layer in a vault
 438 # ranks per channel (DDR) => number of layers
 439 # banks per rank (DDR) => banks per layer
 440 # devices per rank (DDR) => devices per layer ( 1 for HMC).
 441 # The parameters for which no input is available are inherited from the DDR3
 442 # configuration.
 443 # This configuration includes the latencies from the DRAM to the logic layer
 444 # of the HMC
 445 class HMC_2500_1x32(DDR3_1600_8x8):
 446     # size of device
 447     # two banks per device with each bank 4MB [2]
 448     device_size = '8MB'
 449
 450     # 1x32 configuration, 1 device with 32 TSVs [2]
 451     device_bus_width = 32
 452
 453     # HMC is a BL8 device [2]
 454     burst_length = 8
 455
 456     # Each device has a page (row buffer) size of 256 bytes [2]
 457     device_rowbuffer_size = '256B'
 458
 459     # 1x32 configuration, so 1 device [2]
 460     devices_per_rank = 1
 461
 462     # 4 layers so 4 ranks [2]
 463     ranks_per_channel = 4
 464
 465     # HMC has 2 banks per layer [2]
 466     # Each layer represents a rank. With 4 layers and 8 banks in total, each
 467     # layer has 2 banks; thus 2 banks per rank.
 468     banks_per_rank = 2
 469
 470     # 1250 MHz [2]
 471     tCK = '0.8ns'
 472
 473     # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
 474     tBURST = '3.2ns'
 475
 476     # Values using DRAMSpec HMC model [1]
 477     tRCD = '10.2ns'
 478     tCL = '9.9ns'
 479     tRP = '7.7ns'
 480     tRAS = '21.6ns'
 481
 482     # tRRD depends on the power supply network for each vendor.
 483     # We assume a tRRD of a double bank approach to be equal to 4 clock
 484     # cycles (Assumption)
 485     tRRD = '3.2ns'
 486
 487     # activation limit is set to 0 since there are only 2 banks per vault
 488     # layer.
 489     activation_limit = 0
 490
 491     # Values using DRAMSpec HMC model [1]
 492     tRFC = '59ns'
 493     tWR = '8ns'
 494     tRTP = '4.9ns'
 495
 496     # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
 497     # 0.8 ns (Assumption)
 498     tCS = '0.8ns'
 499
 500     # Value using DRAMSpec HMC model [1]
 501     tREFI = '3.9us'
 502
 503     # The default page policy in the vault controllers is simple closed page
 504     # [2] nevertheless 'close' policy opens and closes the row multiple times
 505     # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
 506     page_policy = 'close_adaptive'
 507
 508     # RoCoRaBaCh resembles the default address mapping in HMC
 509     addr_mapping = 'RoCoRaBaCh'
 510     min_writes_per_switch = 8
 511
 512     # These parameters do not directly correlate with buffer_size in real
 513     # hardware. Nevertheless, their value has been tuned to achieve a
 514     # bandwidth similar to the cycle-accurate model in [2]
 515     write_buffer_size = 32
 516     read_buffer_size = 32
 517
 518     # The static latency of the vault controllers is estimated to be smaller
 519     # than a full DRAM channel controller
 520     static_backend_latency='4ns'
 521     static_frontend_latency='4ns'
 522
 523 # A single DDR3-2133 x64 channel refining a selected subset of the
 524 # options for the DDR-1600 configuration, based on the same DDR3-1600
 525 # 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
 526 # consistent across the two configurations.
 527 class DDR3_2133_8x8(DDR3_1600_8x8):
 528     # 1066 MHz
 529     tCK = '0.938ns'
 530
 531     # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
 532     tBURST = '3.752ns'
 533
 534     # DDR3-2133 14-14-14
 535     tRCD = '13.09ns'
 536     tCL = '13.09ns'
 537     tRP = '13.09ns'
 538     tRAS = '33ns'
 539     tRRD = '5ns'
 540     tXAW = '25ns'
 541
 542     # Current values from datasheet
 543     IDD0 = '70mA'
 544     IDD2N = '37mA'
 545     IDD3N = '44mA'
 546     IDD4W = '157mA'
 547     IDD4R = '191mA'
 548     IDD5 = '250mA'
 549     IDD3P1 = '44mA'
 550     IDD2P1 = '43mA'
 551     IDD6 ='20mA'
 552     VDD = '1.5V'
 553
 554 # A single DDR4-2400 x64 channel (one command and address bus), with
 555 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
 556 # in an 16x4 configuration.
 557 # Total channel capacity is 32GB
 558 # 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
 559 class DDR4_2400_16x4(DRAMCtrl):
 560     # size of device
 561     device_size = '1GB'
 562
 563     # 16x4 configuration, 16 devices each with a 4-bit interface
 564     device_bus_width = 4
 565
 566     # DDR4 is a BL8 device
 567     burst_length = 8
 568
 569     # Each device has a page (row buffer) size of 512 byte (1K columns x4)
 570     device_rowbuffer_size = '512B'
 571
 572     # 16x4 configuration, so 16 devices
 573     devices_per_rank = 16
 574
 575     # Match our DDR3 configurations which is dual rank
 576     ranks_per_channel = 2
 577
 578     # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
 579     # Set to 4 for x4 case
 580     bank_groups_per_rank = 4
 581
 582     # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
 583     # configurations). Currently we do not capture the additional
 584     # constraints incurred by the bank groups
 585     banks_per_rank = 16
 586
 587     # override the default buffer sizes and go for something larger to
 588     # accommodate the larger bank count
 589     write_buffer_size = 128
 590     read_buffer_size = 64
 591
 592     # 1200 MHz
 593     tCK = '0.833ns'
 594
 595     # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
 596     # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
 597     # With bank group architectures, tBURST represents the CAS-to-CAS
 598     # delay for bursts to different bank groups (tCCD_S)
 599     tBURST = '3.332ns'
 600
 601     # @2400 data rate, tCCD_L is 6 CK
 602     # CAS-to-CAS delay for bursts to the same bank group
 603     # tBURST is equivalent to tCCD_S; no explicit parameter required
 604     # for CAS-to-CAS delay for bursts to different bank groups
 605     tCCD_L = '5ns';
 606
 607     # DDR4-2400 17-17-17
 608     tRCD = '14.16ns'
 609     tCL = '14.16ns'
 610     tRP = '14.16ns'
 611     tRAS = '32ns'
 612
 613     # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
 614     tRRD = '3.332ns'
 615
 616     # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
 617     tRRD_L = '4.9ns';
 618
 619     # tFAW for 512B page is MAX(16 CK, 13ns)
 620     tXAW = '13.328ns'
 621     activation_limit = 4
 622     # tRFC is 350ns
 623     tRFC = '350ns'
 624
 625     tWR = '15ns'
 626
 627     # Here using the average of WTR_S and WTR_L
 628     tWTR = '5ns'
 629
 630     # Greater of 4 CK or 7.5 ns
 631     tRTP = '7.5ns'
 632
 633     # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
 634     tRTW = '1.666ns'
 635
 636     # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
 637     tCS = '1.666ns'
 638
 639     # <=85C, half for >85C
 640     tREFI = '7.8us'
 641
 642     # active powerdown and precharge powerdown exit time
 643     tXP = '6ns'
 644
 645     # self refresh exit time
 646     # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
 647     # tRFC + 10ns = 340ns
 648     tXS = '340ns'
 649
 650     # Current values from datasheet
 651     IDD0 = '43mA'
 652     IDD02 = '3mA'
 653     IDD2N = '34mA'
 654     IDD3N = '38mA'
 655     IDD3N2 = '3mA'
 656     IDD4W = '103mA'
 657     IDD4R = '110mA'
 658     IDD5 = '250mA'
 659     IDD3P1 = '32mA'
 660     IDD2P1 = '25mA'
 661     IDD6 = '30mA'
 662     VDD = '1.2V'
 663     VDD2 = '2.5V'
 664
 665 # A single DDR4-2400 x64 channel (one command and address bus), with
 666 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
 667 # in an 8x8 configuration.
 668 # Total channel capacity is 16GB
 669 # 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
 670 class DDR4_2400_8x8(DDR4_2400_16x4):
 671     # 8x8 configuration, 8 devices each with an 8-bit interface
 672     device_bus_width = 8
 673
 674     # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
 675     device_rowbuffer_size = '1kB'
 676
 677     # 8x8 configuration, so 8 devices
 678     devices_per_rank = 8
 679
 680     # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
 681     tRRD_L = '4.9ns';
 682
 683     tXAW = '21ns'
 684
 685     # Current values from datasheet
 686     IDD0 = '48mA'
 687     IDD3N = '43mA'
 688     IDD4W = '123mA'
 689     IDD4R = '135mA'
 690     IDD3P1 = '37mA'
 691
 692 # A single DDR4-2400 x64 channel (one command and address bus), with
 693 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
 694 # in an 4x16 configuration.
 695 # Total channel capacity is 4GB
 696 # 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
 697 class DDR4_2400_4x16(DDR4_2400_16x4):
 698     # 4x16 configuration, 4 devices each with an 16-bit interface
 699     device_bus_width = 16
 700
 701     # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
 702     device_rowbuffer_size = '2kB'
 703
 704     # 4x16 configuration, so 4 devices
 705     devices_per_rank = 4
 706
 707     # Single rank for x16
 708     ranks_per_channel = 1
 709
 710     # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
 711     # Set to 2 for x16 case
 712     bank_groups_per_rank = 2
 713
 714     # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
 715     # configurations). Currently we do not capture the additional
 716     # constraints incurred by the bank groups
 717     banks_per_rank = 8
 718
 719     # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
 720     tRRD = '5.3ns'
 721
 722     # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
 723     tRRD_L = '6.4ns';
 724
 725     tXAW = '30ns'
 726
 727     # Current values from datasheet
 728     IDD0 = '80mA'
 729     IDD02 = '4mA'
 730     IDD2N = '34mA'
 731     IDD3N = '47mA'
 732     IDD4W = '228mA'
 733     IDD4R = '243mA'
 734     IDD5 = '280mA'
 735     IDD3P1 = '41mA'
 736
 737 # A single LPDDR2-S4 x32 interface (one command/address bus), with
 738 # default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
 739 # in a 1x32 configuration.
 740 class LPDDR2_S4_1066_1x32(DRAMCtrl):
 741     # No DLL in LPDDR2
 742     dll = False
 743
 744     # size of device
 745     device_size = '512MB'
 746
 747     # 1x32 configuration, 1 device with a 32-bit interface
 748     device_bus_width = 32
 749
 750     # LPDDR2_S4 is a BL4 and BL8 device
 751     burst_length = 8
 752
 753     # Each device has a page (row buffer) size of 1KB
 754     # (this depends on the memory density)
 755     device_rowbuffer_size = '1kB'
 756
 757     # 1x32 configuration, so 1 device
 758     devices_per_rank = 1
 759
 760     # Use a single rank
 761     ranks_per_channel = 1
 762
 763     # LPDDR2-S4 has 8 banks in all configurations
 764     banks_per_rank = 8
 765
 766     # 533 MHz
 767     tCK = '1.876ns'
 768
 769     # Fixed at 15 ns
 770     tRCD = '15ns'
 771
 772     # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
 773     tCL = '15ns'
 774
 775     # Pre-charge one bank 15 ns (all banks 18 ns)
 776     tRP = '15ns'
 777
 778     tRAS = '42ns'
 779     tWR = '15ns'
 780
 781     tRTP = '7.5ns'
 782
 783     # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
 784     # Note this is a BL8 DDR device.
 785     # Requests larger than 32 bytes are broken down into multiple requests
 786     # in the controller
 787     tBURST = '7.5ns'
 788
 789     # LPDDR2-S4, 4 Gbit
 790     tRFC = '130ns'
 791     tREFI = '3.9us'
 792
 793     # active powerdown and precharge powerdown exit time
 794     tXP = '7.5ns'
 795
 796     # self refresh exit time
 797     tXS = '140ns'
 798
 799     # Irrespective of speed grade, tWTR is 7.5 ns
 800     tWTR = '7.5ns'
 801
 802     # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
 803     tRTW = '3.75ns'
 804
 805     # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
 806     tCS = '3.75ns'
 807
 808     # Activate to activate irrespective of density and speed grade
 809     tRRD = '10.0ns'
 810
 811     # Irrespective of density, tFAW is 50 ns
 812     tXAW = '50ns'
 813     activation_limit = 4
 814
 815     # Current values from datasheet
 816     IDD0 = '15mA'
 817     IDD02 = '70mA'
 818     IDD2N = '2mA'
 819     IDD2N2 = '30mA'
 820     IDD3N = '2.5mA'
 821     IDD3N2 = '30mA'
 822     IDD4W = '10mA'
 823     IDD4W2 = '190mA'
 824     IDD4R = '3mA'
 825     IDD4R2 = '220mA'
 826     IDD5 = '40mA'
 827     IDD52 = '150mA'
 828     IDD3P1 = '1.2mA'
 829     IDD3P12 = '8mA'
 830     IDD2P1 = '0.6mA'
 831     IDD2P12 = '0.8mA'
 832     IDD6 = '1mA'
 833     IDD62 = '3.2mA'
 834     VDD = '1.8V'
 835     VDD2 = '1.2V'
 836
 837 # A single WideIO x128 interface (one command and address bus), with
 838 # default timings based on an estimated WIO-200 8 Gbit part.
 839 class WideIO_200_1x128(DRAMCtrl):
 840     # No DLL for WideIO
 841     dll = False
 842
 843     # size of device
 844     device_size = '1024MB'
 845
 846     # 1x128 configuration, 1 device with a 128-bit interface
 847     device_bus_width = 128
 848
 849     # This is a BL4 device
 850     burst_length = 4
 851
 852     # Each device has a page (row buffer) size of 4KB
 853     # (this depends on the memory density)
 854     device_rowbuffer_size = '4kB'
 855
 856     # 1x128 configuration, so 1 device
 857     devices_per_rank = 1
 858
 859     # Use one rank for a one-high die stack
 860     ranks_per_channel = 1
 861
 862     # WideIO has 4 banks in all configurations
 863     banks_per_rank = 4
 864
 865     # 200 MHz
 866     tCK = '5ns'
 867
 868     # WIO-200
 869     tRCD = '18ns'
 870     tCL = '18ns'
 871     tRP = '18ns'
 872     tRAS = '42ns'
 873     tWR = '15ns'
 874     # Read to precharge is same as the burst
 875     tRTP = '20ns'
 876
 877     # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
 878     # Note this is a BL4 SDR device.
 879     tBURST = '20ns'
 880
 881     # WIO 8 Gb
 882     tRFC = '210ns'
 883
 884     # WIO 8 Gb, <=85C, half for >85C
 885     tREFI = '3.9us'
 886
 887     # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
 888     tWTR = '15ns'
 889
 890     # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
 891     tRTW = '10ns'
 892
 893     # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
 894     tCS = '10ns'
 895
 896     # Activate to activate irrespective of density and speed grade
 897     tRRD = '10.0ns'
 898
 899     # Two instead of four activation window
 900     tXAW = '50ns'
 901     activation_limit = 2
 902
 903     # The WideIO specification does not provide current information
 904
 905 # A single LPDDR3 x32 interface (one command/address bus), with
 906 # default timings based on a LPDDR3-1600 4 Gbit part (Micron
 907 # EDF8132A1MC) in a 1x32 configuration.
 908 class LPDDR3_1600_1x32(DRAMCtrl):
 909     # No DLL for LPDDR3
 910     dll = False
 911
 912     # size of device
 913     device_size = '512MB'
 914
 915     # 1x32 configuration, 1 device with a 32-bit interface
 916     device_bus_width = 32
 917
 918     # LPDDR3 is a BL8 device
 919     burst_length = 8
 920
 921     # Each device has a page (row buffer) size of 4KB
 922     device_rowbuffer_size = '4kB'
 923
 924     # 1x32 configuration, so 1 device
 925     devices_per_rank = 1
 926
 927     # Technically the datasheet is a dual-rank package, but for
 928     # comparison with the LPDDR2 config we stick to a single rank
 929     ranks_per_channel = 1
 930
 931     # LPDDR3 has 8 banks in all configurations
 932     banks_per_rank = 8
 933
 934     # 800 MHz
 935     tCK = '1.25ns'
 936
 937     tRCD = '18ns'
 938
 939     # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
 940     tCL = '15ns'
 941
 942     tRAS = '42ns'
 943     tWR = '15ns'
 944
 945     # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
 946     tRTP = '7.5ns'
 947
 948     # Pre-charge one bank 18 ns (all banks 21 ns)
 949     tRP = '18ns'
 950
 951     # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
 952     # Note this is a BL8 DDR device.
 953     # Requests larger than 32 bytes are broken down into multiple requests
 954     # in the controller
 955     tBURST = '5ns'
 956
 957     # LPDDR3, 4 Gb
 958     tRFC = '130ns'
 959     tREFI = '3.9us'
 960
 961     # active powerdown and precharge powerdown exit time
 962     tXP = '7.5ns'
 963
 964     # self refresh exit time
 965     tXS = '140ns'
 966
 967     # Irrespective of speed grade, tWTR is 7.5 ns
 968     tWTR = '7.5ns'
 969
 970     # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
 971     tRTW = '2.5ns'
 972
 973     # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
 974     tCS = '2.5ns'
 975
 976     # Activate to activate irrespective of density and speed grade
 977     tRRD = '10.0ns'
 978
 979     # Irrespective of size, tFAW is 50 ns
 980     tXAW = '50ns'
 981     activation_limit = 4
 982
 983     # Current values from datasheet
 984     IDD0 = '8mA'
 985     IDD02 = '60mA'
 986     IDD2N = '0.8mA'
 987     IDD2N2 = '26mA'
 988     IDD3N = '2mA'
 989     IDD3N2 = '34mA'
 990     IDD4W = '2mA'
 991     IDD4W2 = '190mA'
 992     IDD4R = '2mA'
 993     IDD4R2 = '230mA'
 994     IDD5 = '28mA'
 995     IDD52 = '150mA'
 996     IDD3P1 = '1.4mA'
 997     IDD3P12 = '11mA'
 998     IDD2P1 = '0.8mA'
 999     IDD2P12 = '1.8mA'
1000     IDD6 = '0.5mA'
1001     IDD62 = '1.8mA'
1002     VDD = '1.8V'
1003     VDD2 = '1.2V'
1004
1005 # A single GDDR5 x64 interface, with
1006 # default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
1007 # H5GQ1H24AFR) in a 2x32 configuration.
1008 class GDDR5_4000_2x32(DRAMCtrl):
1009     # size of device
1010     device_size = '128MB'
1011
1012     # 2x32 configuration, 1 device with a 32-bit interface
1013     device_bus_width = 32
1014
1015     # GDDR5 is a BL8 device
1016     burst_length = 8
1017
1018     # Each device has a page (row buffer) size of 2Kbits (256Bytes)
1019     device_rowbuffer_size = '256B'
1020
1021     # 2x32 configuration, so 2 devices
1022     devices_per_rank = 2
1023
1024     # assume single rank
1025     ranks_per_channel = 1
1026
1027     # GDDR5 has 4 bank groups
1028     bank_groups_per_rank = 4
1029
1030     # GDDR5 has 16 banks with 4 bank groups
1031     banks_per_rank = 16
1032
1033     # 1000 MHz
1034     tCK = '1ns'
1035
1036     # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
1037     # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
1038     # 8 beats at 4000 MHz = 2 beats at 1000 MHz
1039     # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
1040     # With bank group architectures, tBURST represents the CAS-to-CAS
1041     # delay for bursts to different bank groups (tCCD_S)
1042     tBURST = '2ns'
1043
1044     # @1000MHz data rate, tCCD_L is 3 CK
1045     # CAS-to-CAS delay for bursts to the same bank group
1046     # tBURST is equivalent to tCCD_S; no explicit parameter required
1047     # for CAS-to-CAS delay for bursts to different bank groups
1048     tCCD_L = '3ns';
1049
1050     tRCD = '12ns'
1051
1052     # tCL is not directly found in datasheet and assumed equal tRCD
1053     tCL = '12ns'
1054
1055     tRP = '12ns'
1056     tRAS = '28ns'
1057
1058     # RRD_S (different bank group)
1059     # RRD_S is 5.5 ns in datasheet.
1060     # rounded to the next multiple of tCK
1061     tRRD = '6ns'
1062
1063     # RRD_L (same bank group)
1064     # RRD_L is 5.5 ns in datasheet.
1065     # rounded to the next multiple of tCK
1066     tRRD_L = '6ns'
1067
1068     tXAW = '23ns'
1069
1070     # tXAW < 4 x tRRD.
1071     # Therefore, activation limit is set to 0
1072     activation_limit = 0
1073
1074     tRFC = '65ns'
1075     tWR = '12ns'
1076
1077     # Here using the average of WTR_S and WTR_L
1078     tWTR = '5ns'
1079
1080     # Read-to-Precharge 2 CK
1081     tRTP = '2ns'
1082
1083     # Assume 2 cycles
1084     tRTW = '2ns'
1085
1086 # A single HBM x128 interface (one command and address bus), with
1087 # default timings based on data publically released
1088 # ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
1089 # IDD measurement values, and by extrapolating data from other classes.
1090 # Architecture values based on published HBM spec
1091 # A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
1092 class HBM_1000_4H_1x128(DRAMCtrl):
1093     # HBM gen1 supports up to 8 128-bit physical channels
1094     # Configuration defines a single channel, with the capacity
1095     # set to (full_ stack_capacity / 8) based on 2Gb dies
1096     # To use all 8 channels, set 'channels' parameter to 8 in
1097     # system configuration
1098
1099     # 128-bit interface legacy mode
1100     device_bus_width = 128
1101
1102     # HBM supports BL4 and BL2 (legacy mode only)
1103     burst_length = 4
1104
1105     # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
1106     # with 8 channels, 128MB per channel
1107     device_size = '128MB'
1108
1109     device_rowbuffer_size = '2kB'
1110
1111     # 1x128 configuration
1112     devices_per_rank = 1
1113
1114     # HBM does not have a CS pin; set rank to 1
1115     ranks_per_channel = 1
1116
1117     # HBM has 8 or 16 banks depending on capacity
1118     # 2Gb dies have 8 banks
1119     banks_per_rank = 8
1120
1121     # depending on frequency, bank groups may be required
1122     # will always have 4 bank groups when enabled
1123     # current specifications do not define the minimum frequency for
1124     # bank group architecture
1125     # setting bank_groups_per_rank to 0 to disable until range is defined
1126     bank_groups_per_rank = 0
1127
1128     # 500 MHz for 1Gbps DDR data rate
1129     tCK = '2ns'
1130
1131     # use values from IDD measurement in JEDEC spec
1132     # use tRP value for tRCD and tCL similar to other classes
1133     tRP = '15ns'
1134     tRCD = '15ns'
1135     tCL = '15ns'
1136     tRAS = '33ns'
1137
1138     # BL2 and BL4 supported, default to BL4
1139     # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
1140     tBURST = '4ns'
1141
1142     # value for 2Gb device from JEDEC spec
1143     tRFC = '160ns'
1144
1145     # value for 2Gb device from JEDEC spec
1146     tREFI = '3.9us'
1147
1148     # extrapolate the following from LPDDR configs, using ns values
1149     # to minimize burst length, prefetch differences
1150     tWR = '18ns'
1151     tRTP = '7.5ns'
1152     tWTR = '10ns'
1153
1154     # start with 2 cycles turnaround, similar to other memory classes
1155     # could be more with variations across the stack
1156     tRTW = '4ns'
1157
1158     # single rank device, set to 0
1159     tCS = '0ns'
1160
1161     # from MemCon example, tRRD is 4ns with 2ns tCK
1162     tRRD = '4ns'
1163
1164     # from MemCon example, tFAW is 30ns with 2ns tCK
1165     tXAW = '30ns'
1166     activation_limit = 4
1167
1168     # 4tCK
1169     tXP = '8ns'
1170
1171     # start with tRFC + tXP -> 160ns + 8ns = 168ns
1172     tXS = '168ns'
1173
1174 # A single HBM x64 interface (one command and address bus), with
1175 # default timings based on HBM gen1 and data publically released
1176 # A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1177 # Note: This defines a pseudo-channel with a unique controller
1178 # instantiated per pseudo-channel
1179 # Stay at same IO rate (1Gbps) to maintain timing relationship with
1180 # HBM gen1 class (HBM_1000_4H_x128) where possible
1181 class HBM_1000_4H_1x64(HBM_1000_4H_1x128):
1182     # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1183     # Configuration defines a single pseudo channel, with the capacity
1184     # set to (full_ stack_capacity / 16) based on 8Gb dies
1185     # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1186     # system configuration
1187
1188     # 64-bit pseudo-channle interface
1189     device_bus_width = 64
1190
1191     # HBM pseudo-channel only supports BL4
1192     burst_length = 4
1193
1194     # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1195     # with 16 channels, 256MB per channel
1196     device_size = '256MB'
1197
1198     # page size is halved with pseudo-channel; maintaining the same same number
1199     # of rows per pseudo-channel with 2X banks across 2 channels
1200     device_rowbuffer_size = '1kB'
1201
1202     # HBM has 8 or 16 banks depending on capacity
1203     # Starting with 4Gb dies, 16 banks are defined
1204     banks_per_rank = 16
1205
1206     # reset tRFC for larger, 8Gb device
1207     # use HBM1 4Gb value as a starting point
1208     tRFC = '260ns'
1209
1210     # start with tRFC + tXP -> 160ns + 8ns = 168ns
1211     tXS = '268ns'
1212     # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1213     tCS = '2ns'
1214     tREFI = '3.9us'
1215
1216     # active powerdown and precharge powerdown exit time
1217     tXP = '10ns'
1218
1219     # self refresh exit time
1220     tXS = '65ns'
1221
1222 # A single LPDDR5 x16 interface (one command/address bus)
1223 # for a single x16 channel with default timings based on
1224 # initial JEDEC specification
1225 # Starting with 5.5Gbps data rates and 8Gbit die
1226 # Configuring for 16-bank mode with bank-group architecture
1227 # burst of 32, which means bursts can be interleaved
1228 class LPDDR5_5500_1x16_BG_BL32(DRAMCtrl):
1229
1230     # Increase buffer size to account for more bank resources
1231     read_buffer_size = 64
1232
1233     # Set page policy to better suit DMC Huxley
1234     page_policy = 'close_adaptive'
1235
1236     # 16-bit channel interface
1237     device_bus_width = 16
1238
1239     # LPDDR5 is a BL16 or BL32 device
1240     # With BG mode, BL16 and BL32 are supported
1241     # Use BL32 for higher command bandwidth
1242     burst_length = 32
1243
1244     # size of device in bytes
1245     device_size = '1GB'
1246
1247     # 2kB page with BG mode
1248     device_rowbuffer_size = '2kB'
1249
1250     # Use a 1x16 configuration
1251     devices_per_rank = 1
1252
1253     # Use a single rank
1254     ranks_per_channel = 1
1255
1256     # LPDDR5 supports configurable bank options
1257     # 8B  : BL32, all frequencies
1258     # 16B : BL32 or BL16, <=3.2Gbps
1259     # 16B with Bank Group Arch (4B/BG): BL32 or BL16, >3.2Gbps
1260     # Initial configuration will have 16 banks with Bank Group Arch
1261     # to maximim resources and enable higher data rates
1262     banks_per_rank = 16
1263     bank_groups_per_rank = 4
1264
1265     # 5.5Gb/s DDR with 4:1 WCK:CK ratio for 687.5 MHz CK
1266     tCK = '1.455ns'
1267
1268     # Greater of 2 CK or 18ns
1269     tRCD = '18ns'
1270
1271     # Base RL is 16 CK @ 687.5 MHz = 23.28ns
1272     tCL = '23.280ns'
1273
1274     # Greater of 2 CK or 18ns
1275     tRP = '18ns'
1276
1277     # Greater of 3 CK or 42ns
1278     tRAS = '42ns'
1279
1280     # Greater of 3 CK or 34ns
1281     tWR = '34ns'
1282
1283     # active powerdown and precharge powerdown exit time
1284     # Greater of 3 CK or 7ns
1285     tXP = '7ns'
1286
1287     # self refresh exit time (tRFCab + 7.5ns)
1288     tXS = '217.5ns'
1289
1290     # Greater of 2 CK or 7.5 ns minus 2 CK
1291     tRTP = '4.59ns'
1292
1293     # With BG architecture, burst of 32 transferred in two 16-beat
1294     # sub-bursts, with a 16-beat gap in between.
1295     # Each 16-beat sub-burst is 8 WCK @2.75 GHz or 2 CK @ 687.5 MHz
1296     # tBURST is the delay to transfer the Bstof32 =  6 CK @ 687.5 MHz
1297     tBURST = '8.73ns'
1298     # can interleave a Bstof32 from another bank group at tBURST_MIN
1299     # 16-beats is 8 WCK @2.75 GHz or 2 CK @ 687.5 MHz
1300     tBURST_MIN = '2.91ns'
1301     # tBURST_MAX is the maximum burst delay for same bank group timing
1302     # this is 8 CK @ 687.5 MHz
1303     tBURST_MAX = '11.64ns'
1304
1305     # 8 CK @ 687.5 MHz
1306     tCCD_L = "11.64ns"
1307
1308     # LPDDR5, 8 Gbit/channel for 280ns tRFCab
1309     tRFC = '210ns'
1310     tREFI = '3.9us'
1311
1312     # Greater of 4 CK or 6.25 ns
1313     tWTR = '6.25ns'
1314     # Greater of 4 CK or 12 ns
1315     tWTR_L = '12ns'
1316
1317     # Required RD-to-WR timing is RL+ BL/n + tWCKDQ0/tCK - WL
1318     # tWCKDQ0/tCK will be 1 CK for most cases
1319     # For gem5 RL = WL and BL/n is already accounted for with tBURST
1320     # Result is and additional 1 CK is required
1321     tRTW = '1.455ns'
1322
1323     # Default different rank bus delay to 2 CK, @687.5 MHz = 2.91 ns
1324     tCS = '2.91ns'
1325
1326     # 2 CK
1327     tPPD = '2.91ns'
1328
1329     # Greater of 2 CK or 5 ns
1330     tRRD = '5ns'
1331     tRRD_L = '5ns'
1332
1333     # With Bank Group Arch mode tFAW is 20 ns
1334     tXAW = '20ns'
1335     activation_limit = 4
1336
1337     # at 5Gbps, 4:1 WCK to CK ratio required
1338     # 2 data beats per WCK (DDR) -> 8 per CK
1339     beats_per_clock = 8
1340
1341     # 2 cycles required to send activate command
1342     # 2 command phases can be sent back-to-back or
1343     # with a gap up to tAAD = 8 CK
1344     two_cycle_activate = True
1345     tAAD = '11.640ns'
1346
1347     data_clock_sync = True
1348
1349 # A single LPDDR5 x16 interface (one command/address bus)
1350 # for a single x16 channel with default timings based on
1351 # initial JEDEC specification
1352 # Starting with 5.5Gbps data rates and 8Gbit die
1353 # Configuring for 16-bank mode with bank-group architecture, burst of 16
1354 class LPDDR5_5500_1x16_BG_BL16(LPDDR5_5500_1x16_BG_BL32):
1355
1356     # LPDDR5 is a BL16 or BL32 device
1357     # With BG mode, BL16 and BL32 are supported
1358     # Use BL16 for smaller access granularity
1359     burst_length = 16
1360
1361     # For Bstof16 with BG arch, 2 CK @ 687.5 MHz with 4:1 clock ratio
1362     tBURST = '2.91ns'
1363     tBURST_MIN = '2.91ns'
1364     # For Bstof16 with BG arch, 4 CK @ 687.5 MHz with 4:1 clock ratio
1365     tBURST_MAX = '5.82ns'
1366
1367     # 4 CK @ 687.5 MHz
1368     tCCD_L = "5.82ns"
1369
1370
1371 # A single LPDDR5 x16 interface (one command/address bus)
1372 # for a single x16 channel with default timings based on
1373 # initial JEDEC specification
1374 # Starting with 5.5Gbps data rates and 8Gbit die
1375 # Configuring for 8-bank mode, burst of 32
1376 class LPDDR5_5500_1x16_8B_BL32(LPDDR5_5500_1x16_BG_BL32):
1377
1378     # 4kB page with 8B mode
1379     device_rowbuffer_size = '4kB'
1380
1381     # LPDDR5 supports configurable bank options
1382     # 8B  : BL32, all frequencies
1383     # 16B : BL32 or BL16, <=3.2Gbps
1384     # 16B with Bank Group Arch (4B/BG): BL32 or BL16, >3.2Gbps
1385     # Select 8B
1386     banks_per_rank = 8
1387     bank_groups_per_rank = 0
1388
1389     # For Bstof32 with 8B mode, 4 CK @ 687.5 MHz with 4:1 clock ratio
1390     tBURST = '5.82ns'
1391     tBURST_MIN = '5.82ns'
1392     tBURST_MAX = '5.82ns'
1393
1394     # Greater of 4 CK or 12 ns
1395     tWTR = '12ns'
1396
1397     # Greater of 2 CK or 10 ns
1398     tRRD = '10ns'
1399
1400     # With 8B mode tFAW is 40 ns
1401     tXAW = '40ns'
1402     activation_limit = 4
1403
1404     # Reset BG arch timing for 8B mode
1405     tCCD_L = "0ns"
1406     tRRD_L = "0ns"
1407     tWTR_L = "0ns"
1408
1409 # A single LPDDR5 x16 interface (one command/address bus)
1410 # for a single x16 channel with default timings based on
1411 # initial JEDEC specification
1412 # 6.4Gbps data rates and 8Gbit die
1413 # Configuring for 16-bank mode with bank-group architecture
1414 # burst of 32, which means bursts can be interleaved
1415 class LPDDR5_6400_1x16_BG_BL32(LPDDR5_5500_1x16_BG_BL32):
1416
1417     # 5.5Gb/s DDR with 4:1 WCK:CK ratio for 687.5 MHz CK
1418     tCK = '1.25ns'
1419
1420     # Base RL is 17 CK @ 800 MHz = 21.25ns
1421     tCL = '21.25ns'
1422
1423     # With BG architecture, burst of 32 transferred in two 16-beat
1424     # sub-bursts, with a 16-beat gap in between.
1425     # Each 16-beat sub-burst is 8 WCK @3.2 GHz or 2 CK @ 800 MHz
1426     # tBURST is the delay to transfer the Bstof32 =  6 CK @ 800 MHz
1427     tBURST = '7.5ns'
1428     # can interleave a Bstof32 from another bank group at tBURST_MIN
1429     # 16-beats is 8 WCK @2.3 GHz or 2 CK @ 800 MHz
1430     tBURST_MIN = '2.5ns'
1431     # tBURST_MAX is the maximum burst delay for same bank group timing
1432     # this is 8 CK @ 800 MHz
1433     tBURST_MAX = '10ns'
1434
1435     # 8 CK @ 800 MHz
1436     tCCD_L = "10ns"
1437
1438     # Required RD-to-WR timing is RL+ BL/n + tWCKDQ0/tCK - WL
1439     # tWCKDQ0/tCK will be 1 CK for most cases
1440     # For gem5 RL = WL and BL/n is already accounted for with tBURST
1441     # Result is and additional 1 CK is required
1442     tRTW = '1.25ns'
1443
1444     # Default different rank bus delay to 2 CK, @687.5 MHz = 2.5 ns
1445     tCS = '2.5ns'
1446
1447     # 2 CK
1448     tPPD = '2.5ns'
1449
1450     # 2 command phases can be sent back-to-back or
1451     # with a gap up to tAAD = 8 CK
1452     tAAD = '10ns'
1453
1454 # A single LPDDR5 x16 interface (one command/address bus)
1455 # for a single x16 channel with default timings based on initial
1456 # JEDEC specifcation
1457 # 6.4Gbps data rates and 8Gbit die
1458 # Configuring for 16-bank mode with bank-group architecture, burst of 16
1459 class LPDDR5_6400_1x16_BG_BL16(LPDDR5_6400_1x16_BG_BL32):
1460
1461     # LPDDR5 is a BL16 or BL32 device
1462     # With BG mode, BL16 and BL32 are supported
1463     # Use BL16 for smaller access granularity
1464     burst_length = 16
1465
1466     # For Bstof16 with BG arch, 2 CK @ 800 MHz with 4:1 clock ratio
1467     tBURST = '2.5ns'
1468     tBURST_MIN = '2.5ns'
1469     # For Bstof16 with BG arch, 4 CK @ 800 MHz with 4:1 clock ratio
1470     tBURST_MAX = '5ns'
1471
1472     # 4 CK @ 800 MHz
1473     tCCD_L = "5ns"
1474
1475
1476 # A single LPDDR5 x16 interface (one command/address bus)
1477 # for a single x16 channel with default timings based on
1478 # initial JEDEC specification
1479 # 6.4Gbps data rates and 8Gbit die
1480 # Configuring for 8-bank mode, burst of 32
1481 class LPDDR5_6400_1x16_8B_BL32(LPDDR5_6400_1x16_BG_BL32):
1482
1483     # 4kB page with 8B mode
1484     device_rowbuffer_size = '4kB'
1485
1486     # LPDDR5 supports configurable bank options
1487     # 8B  : BL32, all frequencies
1488     # 16B : BL32 or BL16, <=3.2Gbps
1489     # 16B with Bank Group Arch (4B/BG): BL32 or BL16, >3.2Gbps
1490     # Select 8B
1491     banks_per_rank = 8
1492     bank_groups_per_rank = 0
1493
1494     # For Bstof32 with 8B mode, 4 CK @ 800 MHz with 4:1 clock ratio
1495     tBURST = '5ns'
1496     tBURST_MIN = '5ns'
1497     tBURST_MAX = '5ns'
1498
1499     # Greater of 4 CK or 12 ns
1500     tWTR = '12ns'
1501
1502     # Greater of 2 CK or 10 ns
1503     tRRD = '10ns'
1504
1505     # With 8B mode tFAW is 40 ns
1506     tXAW = '40ns'
1507     activation_limit = 4
1508
1509     # Reset BG arch timing for 8B mode
1510     tCCD_L = "0ns"
1511     tRRD_L = "0ns"
1512     tWTR_L = "0ns"